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4000 series acapella optical modem ic ACS405CS ACS405CS main features general description the ACS405CS is a complete controller, driver and receiver chip-set, supporting full-duplex synchronous transmission up to 8.448/6.312mbps over a single-optical fiber. the designer can share the available bandwidth over 1 to 8 main channels by selecting the appropriate combination on the dr input pins. in addition to the main channels, the ACS405CS provides up to two auxilliary maintenance channel of 64kbps. the internal machine cycle provides for link lengths up to 25/50km. on the electrical side hdb3/ami/nrz/b8zs interfaces are selectable. communicating modems automatically maintain synchronisation with each other, such that the receive phase of one modem is lined-up with the transmit phase of the other, compensating for the propagation delay presented by the link. link lengths from zero to maximum distance are catered for automatically. single fiber full duplex system using ACS405CS chip set with a quad t1/e1 framer ic. * full duplex serial transmission through a single fiber-optic cable without the need for expensive wdm devices. * e2 data-rates of 8.448mbps or 4*e1 at 2.048mbps. t2 data rates of 6.312mbps or 4*t1 at 1.544mbps. * link lengths up to 25km (50km at reduced bandwidth). * single wavelength of light to transmit and receive data. * low power, zero cross talk between rx and tx channels. * incorporates maintenance channel at 64kbps. * bit error rate (ber) of < 10 -10 * typical latency of 0.75ms. * ping pong system supporting bi-directional laser duplex devices or ppleds.
2 ACS405CS issue 4.3 june 1999. the ACS405CS comprises a chip-set of two highly integrated devices, the acs9010 and acs4050. the acs9010 is an analogue device and the acs4050 is predominately a digital device. the acs9010 contains the laser/led driver as well as the pin receiver circuitry. since the device does not transmit and receive concurrently (ping-pong), there is no risk of noise generated by the transmitter interfering with the sensitive receive circuitry. the acs4050 comprises the logic necessary to time compress and decompress the data, plus all the logic associated with window synchronisation and locking. for the purpose of this specification the chip-set will be referred to as the ACS405CS and the individual devices as the acs9010 or acs4050. inter-modem coding the inter-ic coding between communication modems is 8b10b. whilst transparent to the user, 8b10b encoding ensures that there is no dc component in the signal, and provides frequent data transitions, factors which ease the task of data recovery and clock extraction. the coding rules are continuously checked to ensure the integrity of the link, and errors are indicated on the errl and errc pins ( see section headed errc and errl - error detection ). the transmit and receiver functions data presented at the near-end tpos/tneg is time- compressed, encoded in the 8b10b format and transmitted over the link in a high frequency burst. the optical interface is then configured as a receiver ready to accept data from the far-end. the received data is decoded, time decompressed and de-jittered and then presented to the rpos/rneg data output pins. porb the power-on reset (porb) pin resets the device if forced low for 2ms or more. in normal operation porb should be held high. it is recommended that porb is connected to vd+ via a 100k w resistor and to gnd via a 100nf capacitor. porb has a special function when used in conjunction with memory lock (see section headed diagnostic modes ). system clock the system clock on the ACS405CS may be derived from an external source or generated locally using the on-chip crystal oscillator. the oscillator (xto/i) requires the use of a fundamental parallel resonance crystal with appropriate padding capacitors. the input pin, scext should be connected to gnd. the crystal specification should be: calibration tolerance: +/- 20ppm @ 25oc temp. tolerance: +/- 20ppm @ -40 to +85oc temperature range: -40 to +85oc load condition: parallel load 15pf padding capacitor: 18-22pf (tune for desired tolerance) if it is required to drive the device with an externally generated system clock source, then the clock source should be connected to input pin eclk with scext connected to vd+. it is often more convenient to drive boards containing multi ACS405CS chip-sets from a single system clock source. the system clock frequency is determined by the choice of data rates and is tabulated in section headed, data rate selection. for example, for e2 operation, the appropriate frequency is 33.792mhz and for t2 operation, 31.560mhz. the system clock defines the burst frequency at which data is transmitted over the optical link via the optical interface. the receive circuitry within the acs4050 recovers the clock from the received data at the rxdat inputs and produces a clock that is synchronised to the incoming data stream. the system clock must have a maximum tolerance of +/- 50ppm over the desired temperature range. optical operational modes the ACS405CS has four optical operational modes controlled by the pins laser, lasrx and pinrx on the acs9010 device. all of the duplex modes in table 1 may be converted to dual fiber operation simply by interfacing to separate transmitting and receiving devices. mode optical device 1 laser duplex using 4-pin laser. 2 laser duplex using 3-pin laser. 3 led duplex. 4 led (ping-pong). table 1 mode 1 - laser duplex using 4-pin laser in mode 1, the device is configured for use with a laser duplex device containing a 4-pin laser. the diagram below shows the connections to the acs9010 device. the operational control pins found on the acs9010 are configured as follows: acapella optical modem ic ACS405CS
3 ACS405CS issue 4.3 june 1999. laser = va+ lasrx = gnd pinrx = va+ for the bookham bkm-2101-a-02 transceiver module, the following connections should be made: monitor pd p side - pin2 = pmn monitor pd n side - pin3 = lap laser diode n side - pin5 = lan laser diode p side - pin6 = lap receive pd p side - pin9 = pinp receive pd n side - pin 10 = pinn pin 1, 4, 7, 8, 11, 14 should be tied to gnd mode 2 - laser duplex using 3-pin laser in mode 2, the device is configured for use with a laser duplex device containing a 3-pin laser. the diagram below shows the connections to the acs9010 device. the operational control pins found on the acs9010 are configured as follows: laser = va+ lasrx = gnd pinrx = va+ mode 3 - led duplex device in mode 3, the device is configured for use with an led duplex device. the diagram below shows the connections to the acs9010 device. the operational control pins found on the acs9010 are configured as follows: laser = gnd lasrx = gnd pinrx = va+ mode 4 - led ping pong in mode 4, the modem is configured for use with a ping-pong led device (ppled). the diagram below shows the connections to the acs9010 device. ping-pong leds are standard leds which exhibit good photo-detection (high responsivity, low capacitance) characteristics when reverse biased. ping-pong leds are available from several manufacturers as well as from acapella. laser = gnd lasrx = va+ pinrx = gnd single fiber ppled lap lan ping-pong led mode 4 led single fiber mode mode 4 led duplex device containing led and pin. mode 3 duplex device led pin diode lap lan pinp pinn single fiber laser duplex device containing 4-pin laser. va+ = the txvdd power supply to the acs9010. mode 1 duplex device laser pin diode lap lap lan pinp pinn pmn single fiber duplex device laser pin diode lap lan pinp pinn pmn single fiber led duplex device containing 3-pin laser. mode 2
4 ACS405CS issue 4.3 june 1999. i * pin (high) = 2.0 / rtset * tolerance = +/- 20%. i = amps txmn and txflg txmn is used to monitor the current delivered to the led or laser. txmn is a current source that proportionally mirrors the current flow through the led or laser. by placing an appropriate resistor (rtxmn) between txmn and gnd, the voltage developed (referenced to gnd), will be proportional to the transmit current. during the laser setup procedure txmn should be monitored to ensure that the laser manufacturer's maximum current specification is not exceeded (see section headed laser adjustment procedure ). txmn may also be employed during normal operation to continuously check the laser current. the voltage developed across rtxmn is compared within an internally generated reference voltage of 1.25v. in the event that the reference voltage is exceeded, the txflg is set high, otherwise it is set low. the relationship between the transmit current and the txmn current is : i * laser (high) = 100 * txmn * tolerance = +/- 10%. i = amps if rtxmn = 1k w , then txflg = 1 when the laser current exceeds 125ma. laser adjustment procedure the output power from the laser should be measured with a optical power meter during the setup procedure. select one of the laser drive modes in accordance with section headed, operational modes . start with the highest resistance for rtset (at least 50k w is recommended). this defines the monitor-pin reference current. select the laser setup mode on the acs4050 by asserting setb low, this forces the laser into a continuous transmit mode and applies dc-balanced data (equal number of ones and zeros) to the txdat input of the acs9010 device. as rtset is reduced in value, the current to the laser will increase. the current to the laser should be monitored at the txmn in accordance with section headed, txmn and txflag . the laser current will be stable when the laser starts to lase, and produces enough optical power for the pin feedback current to equal the current flowing through rtset.the rtset impedance should be decreased until the desired laser output high-power is achieved. once the setup procedure has been completed, the setb pin should then be set high to control of led current during the transmit cycle, the led drive current is directly proportional to the programmed reference current. to minimise switching delay, a permanent bias current is maintained through the led. the data modulation produces bursts of high light and low light to represent logic high and low levels respectively. the low light level is set by a current equal to 10% of the drive current generated for the high light level. since leds have a linear relationship between current and optical output power, this results in a optical high power of 10 times the optical low power. the optical power is controlled by a variable resistor (rtset) connected between tset and ground (gnd). the lower the value of rtset the greater the current, for this reason the lower limit for rtset should be 1k w , which equates to a nominal peak transmit current of 100ma. a practical maximum for rtset is 50k w . acapella, therefore recommends that rtset should comprise a fixed resistor of 1k w in series with a logarithmic potentiometer of 50k w , thus affording overload protection for the led together with precise control of current. i * led (high) = 100 / rtset i * led (low) = 10 / rtset * where rtset > 1k w , tolerance = +/- 20%. i = amps control of laser current during the transmit cycle, the laser drive current is controlled so as to maintain a constant optical output power from the laser. the monitor-pin resident in the laser converts the incident light power (from the laser itself) to a monitor-current, which is directly compared to a preset programmed current (the current flowing through tset). the laser drive current is automatically adjusted to maintain the original preset light level over the recommended temperature and voltage range. the designer should be aware that whilst the control loop maintains the current generated by the monitor-pin within a tolerance of 2%, there is additional uncertainty attributed to the monitor-pin's temperature coefficient of responsivity. data relating to the laser characteristics should be acquired from the laser supplier. the monitor-pin current is set by a variable resistor (rtset), connected between tset and ground (gnd). acapella recommends that rtset should comprise a logarithmic potentiometer of value 50k w . it is important to ensure that the rtset resistor is inserted and adjusted to its maximum resistance value of 50k w prior to applying power to the acs9010 for the first time and prior to following the procedure detailed in section headed, laser adjustment procedure.
5 ACS405CS issue 4.3 june 1999. return the device to the operation mode. the preset laser power will then be maintained over the recommended temperature and voltage range. receive monitor the acs9010 incorporates a power meter which generates a current source which is proportional to the received optical current. i * rxmn = 6 * i (pin) * tolerance = +/- 20%. i = amps i rxmn flows through a resistor, internal to the acs9010, connected between rxmn and gnd. the internal resistor has a value of 260k w +/- 20 %. rxmn is compared with 1.25v. if rxmn exceeds 1.25v, then output rxflg is set = 1, otherwise rxflg is set = 0. with the internal resistor of 260 kw , the default threshold for the rxflg is a input current of 800na +/- 25%. by adding an external parallel resistor between rxmn and gnd, this threshold may be increased. the voltage on rxmn will modulate with receive data bursts. it will settle to its correct value within 4us following the start of a receive burst, and will collapse to 0v after a burst ends. transmission clock tclk there are two independent transmit clocks on the ACS405CS, tclk1 and tclk2. for the purpose of this specification, these signals will be referred to collectively as tclk. the ACS405CS gives a choice between internally and externally generated transmit clocks. when the ckc pin is held low, tclk is configured as an output producing a clock at the frequency defined by dr(4:1). when the ckc pin is held high, tclk is configured as an input, and will accept an externally produced transmission clock with a tolerance of up to 250ppm with respect to the transmission rate determined by dr(4:1). input data appearing on the tpos/tneg inputs is latched into the device on the falling edge of tclk for both internally and externally generated transmission clocks. receive clock rclk there are two independent receive clocks on the ACS405CS, rclk1 and rclk2. for the purpose of this specification, these signals will be referred to collectively as rclk. the data appearing on rpos/rneg is valid on the rising or falling edge of the rclk clock dependent on the setting of resel (see figure 1. timing diagrams) . to ensure that the average receive frequency is the same as the transmitted frequency, rclk is generated from a digital phase-lock loop (dpll) system (except where master mode has been selected). the dpll makes periodic corrections to the output rclk clock by subtracting or adding a single crystal clock bit-period, so that the average frequency of the rclk clock tracks the average frequency of the transmit clock of the far-end modem (or system master clock). this decompression/de- jittering function is covered in more detail in section headed, jitter characteristics. data coding the main synchronous channels may use any of the following coding methods; nrz, ami, hdb3, b8zs. the desired mode is selected by pol1 and pol2 input pins, as shown in table 2. for non-return-to-zero (nrz) coding, data is applied directly to tpos inputs, and output data appears only on the rpos output pins (except for 8-channel mode, see section headed, multi-channel operation). when using nrz code, unconnected tneg input pins will automatically pull-up to vd+. in addition, the ACS405CS will assert a continuous low on redundant rneg output pins. ami, b8zs and hdb3 coding is normally bipolar. however, it is possible to interface with the ACS405CS using two inputs and outputs rather than a single bipolar interface. data equivalent to positive excursions of the bipolar ami/b8zs/hdb3 signal are applied as a logic high to tpos, while data equivalent to negative excursions are applied as a logic high to tneg. similarly, ami/b8zs/hdb3 positive excursions will appear as a logic high on rpos and negative excursions will appear as a logic high on rneg. it is anticipated that most users of the ACS405CS will interface directly with a e1/t1 framers. all the popular framers provide pos/neg bipolar interfaces which will directly connect to the acs4050. if required, a detailed description of the ami/hdb3 coding rules are available from acapella. data coding pol2 pol1 ami00 hdb3 0 1 b8zs 1 0 nrz 1 1 table 2
6 ACS405CS issue 4.3 june 1999. multi-channel operation there are four choices for multi-channel operation on the ACS405CS, selected by the dr(4:1) pins, namely, 1, 2, 4 or 8 channel operation. 1-channel operation in 1-channel operation tpos1/tneg1 and rpos1/ rneg1 is the only active channel. data appearing on other tpn inputs is ignored. all other rpn outputs are forced low. 2-channel operation in 2-channel operation channel mappings can be seen in table 4. data appearing on all other tpn inputs is ignored. all other rpn outputs are forced low. 4-channel operation in 4-channel operation the mappings can be seen in table 5. data rate selection for the purpose of this specification tpn1 represents the set of signals tpos1 and tneg1, and rpn1 represents the set of signals rpos1 and rneg1. see section headed, data coding for a description of the coding types. the maximum recommended crystal (xtal) is 33.792mhz, this gives a maximum bandwidth of 8.448mhz (e2). this bandwidth can be utilised in various ways, it may be divided up over 1,2,4,8 channels. it may be required to support 2 independent clocks, in which case the available bandwidth is reduced to 4.224mhz. single clock operation is known as mode tx1 and dual clock as tx2. there is a third mode of operation known as ht mode (high tolerance), which is more fully described later. for the purpose of this specification these transmission modes are known collectively as the tmodes. the data rate selection pins dr(4:1) determine the frequency of the tclk clock, the number of channels and the transmission mode (tmode) in accordance with the table 3. asymmetrical data rates it is possible to configure the dr pins setting on each side of the link differently (with input fhold) as long as identical crystal values are observed on the communicating devices. for example, the near-end ACS405CS may be configured to transmit 8 channels at 1mbps and the far-end modem may be configured channel nos. input output 1 tpos1/tneg1 rpos1/rneg1 2 tpos2/tneg2 rpos2/rneg2 table 4 dr pins tclk nos. of tmode 4 3 2 1 freq channels 1 1 1 1 xtal/4 1 tx1 1 1 1 0 xtal/5 1 tx1 1 1 0 1 xtal/16 2 tx2 1 1 0 0 xtal/20 2 tx2 1 0 1 1 xtal/16 1 ht 1 0 1 0 xtal/20 1 ht 1 0 0 1 xtal/16 4 tx1 1 0 0 0 xtal/20 4 tx1 0 1 1 1 xtal/32 4 tx2 0 1 1 0 xtal/64 4 tx2 0 1 0 1 xtal/32 8 tx1 0 1 0 0 xtal/64 8 tx2 0 0 1 1 xtal/128 8 tx2 0 0 1 0 xtal/256 8 tx2 0 0 0 1 xtal/8 1 tx1* 0 0 0 0 xtal/10 1 tx1* * 50 km modes table 3 channel nos. input output 1 tpos1/tneg1 rpos1/rneg1 2 tpos2/tneg2 rpos2/rneg2 3 tpos3/tneg3 rpos3/rneg3 4 tpos4/tneg4 rpos4/rneg4 table 5 to transmit 1 channel at 8mbps. for asymmetrical communication, set fhold = 0, this will lead to the receive circuitry reading the dr pins settings from the far-end ACS405CS rather than locally. it is important that the receive circuitry is aware of the configuration and formatting of the data so that it can correctly interpret it. prior to lock (when dcd = 0), the receive circuitry will default to the local dr pin settings. for symmetrical communication (with input fhold = 1), dr pins setting sent over the link are ignored and the receive circuitry will always read the locally set dr pin values. it is expected that for the vast majority of applications symmetrical communication will be employed. when asymmetrical mode is selected (fhold = 0), the only valid dm settings are the full duplex modes. the other modes of remote-loop-back, local-loop-back, master and slave (as described in the section headed diagnostic modes) are not available.
7 ACS405CS issue 4.3 june 1999. 8-channel operation if one of the 8-channel modes is selected by the dr(4:1) inputs, then the ACS405CS must be configured to expect non-return-to-zero (nrz) transmission data using the pol1/2 settings. the otherwise redundant tneg and rneg pins are then available to carry 4 additional data channels. the mapping of transmission pins for 8-channel nrz operation can be seen in table 6. transmission modes (tmode) there are three transmission modes available on the ACS405CS selected by the dr(4:1) pins, these are tx1, tx2 and ht modes. tx1 mode in tx1 mode all of the data channels (tpn/rpn) are related to the clocks tclk1/rclk1. tx2 mode in tx2 mode there are two system clocks, half the signals are aligned to the clock tclk1/rclk1 and the remaining half are aligned to the clock tclk2/ rclk2. for dual channel operation, channel 1 is aligned to clock tclk1/rclk1 and channel 2 is aligned to clock tclk2/rclk2. for four channel operation, channels 1-2 are aligned to clock tclk1/rclk1 and channels 3-4 are aligned to clock tclk2/rclk2. for eight channel operation, channels 1-4 are aligned to clock tclk1/rclk1 and channels 5-8 are aligned to clock tclk2/rclk2. ht mode acapella recognises that a large number of designers using the ACS405CS modem will be employing the device for single channel t1 or single channel e1 operation. in such cases, the available bandwidth far exceeds the bandwidth required. to exploit this otherwise redundant bandwidth, the ACS405CS incorporates a high tolerant (ht) transmission mode. in ht mode, by virtue of on- chip error-correction, the device is extremely tolerant to data errors. all modes in the ACS405CS generate regular unique synchronisation words (sws) in order to re-enforce 8b10b word boundary synchronisation. this prevents single bit-errors causing an avalanche of errors due to word boundary slippage, often referred to as "error extension". in ht mode, sws are interleaved with the data-words such that alternate words are sws, ensuring that the effect of 8b10b word boundary errors will not propagate beyond one received data word. in ht mode the single data channel is aligned to the tclk1/rclk1 clock. 50km long haul mode some customers will require a modem capable of supporting a longer distance than the standard 25km. to support this acapella have implemented a 50km mode for a single e1 or t1 channel. this is achieved with an xtal of value half of that used for the standard e1 or t1 for 25km modes in combination with the appropriate configuration of the dr(4:1) pins. note: the designer should be aware that the use of lower value crystal will proportionally increase the end-to-end data delay through the system in accordance with the formula found in section headed, data delay (latency). therefore, for the 50km mode the latency will double compared to the standard 25km modes. example data rate selection a set of example configurations follow: e2 selection in order to select one e2 operation then set dr4 = dr3 = dr2 = dr1 = 1, together with a crystal of 33.792mhz as shown in the table 7. t2 selection in order to select one t2 channel then set dr4 = dr3 = dr2 = 1; dr1 = 0, together with a crystal of 31.560mhz as shown in the table 8. dr4 dr3 dr2 dr1 xtal tclk divide (mhz) 1 1 1 1 4 8.448 crystal = 33.792 mhz table 7 channel nos. input output 1 tpos1 rpos1 2 tneg1 rneg1 3 tpos2 rpos2 4 tneg2 rneg2 5 tpos3 rpos3 6 tneg3 rneg3 7 tpos4 rpos4 8 tneg4 rneg4 table 6
8 ACS405CS issue 4.3 june 1999. 1 * t1 channel selection in ht mode in order to set the device for one t1 channels operating in high tolerance mode (ht) then dr4 = dr2 = 1; dr3 = dr = 0, together with a crystal of 30.88mhz as shown in the table 13. 1 * t1 channel selection at 50km in order to double the available transmission distance from 25km to 50km, the value of the crystal must be reduced by half. for a single t1 channel set dr4 = dr3 = dr2 = dr1 = 0, together with a crystal of 15.44mhz as shown in table 14. 4 * e1 channel selection in order to set the device for four e1 channels then dr4 = dr1 = 1; dr3 = dr2 = 0, together with a crystal of 32.768mhz as shown in the table 15. 4 * t1 channel selection in order to set the device for four t1 channels then dr3 = dr2 = dr1 = 0; dr4 = 1, together with a crystal of 30.88mhz a shown in the table 16. 2 * e1 channel selection in order to select two independent e1 channels in tx2 mode then set dr4 = dr3 = dr1 = 1; dr2 = 0, together with a crystal of 32.768mhz as shown in the table 9. 2 * t1 channel selection in order to select two independent e1 channels in tx2 mode then set dr4 = dr3 = 1; dr1 = dr2 = 0, together with a crystal of 30.88mhz as shown in the table 10. 1 * e1 channel selection ht mode in order to select one e1 channel operating in high tolerance (ht) mode then set dr4 = dr2 = dr1 = 1; dr3 = 0, together with a crystal of 32.768mhz as shown in the table 11. 1 * e1 channel selection at 50km in order to double the available transmission distance from 25km to 50km, the value of the crystal must be reduced by half. for a single e1 channel set dr4 = dr3 = dr2 = 0; dr1 = 1, together with a crystal of 16.384mhz as shown in table 12. dr4 dr3 dr2 dr1 xtal tclk divide (mhz) 1 1 0 1 16 2.048 crystal = 32.768 mhz table 9 dr4 dr3 dr2 dr1 xtal tclk divide (mhz) 1 1 0 0 20 1.544 crystal = 30.88 mhz table 10 dr4 dr3 dr2 dr1 xtal tclk divide (mhz) 1 0 1 1 16 2.048 crystal = 32.768 mhz table 11 dr4 dr3 dr2 dr1 xtal tclk divide (mhz) 0 0 0 1 8 2.048 crystal = 16.384 mhz table 12 dr4 dr3 dr2 dr1 xtal tclk divide (mhz) 1 0 1 0 20 1.544 crystal = 30.88 mhz table 13 dr4 dr3 dr2 dr1 xtal tclk divide (mhz) 0 0 0 0 10 1.544 crystal = 15.44 mhz table 14 dr4 dr3 dr2 dr1 xtal tclk divide (mhz) 1 0 0 1 16 2.048 crystal = 32.768 mhz table 15 dr4 dr3 dr2 dr1 xtal tclk divide (mhz) 1 1 1 0 5 6.312 crystal = 31.560 mhz table 8
9 ACS405CS issue 4.3 june 1999. maintenance channel mode with frame = 0 when frame = 0 then maintenance mode is selected. this provides one maintenance channel tmd1/rmd1. tmd2/rmd2 is not available for data transmission. tmd1/rmd1 may be considered as an independent maintenance channel that supports data rates of 64kbps or 32kbps depending on the setting of the dr(4:1) pins. see table 18. input data appearing on the tmd1 input is latched into the device on the falling edge of tmclk and appears at the rmd1 output of the far-end modem on the rising edge of rmclk. the ACS405CS gives a choice between internally and externally generated tmclk clocks. when the ckm pin is held low, tmclk is configured as an output producing a clock at 64khz or 32khz. when the ckm pin is held high, tmclk is configured as an input, and will accept an externally produced transmission clock at 64khz or 32khz with a tolerance of 500ppm. the tmd1/rmd1 is an independent channel and consequently there is not a fixed phase relationship between the maintenance channel and the main tpos/tneg data transmission channels. each dr(4:1) mode is designed to achieve a particular communication frequency by the combination of the xtal value and dc value. table 18 shows the recommended xtal and the divide constant (dc) for each dr(4:1) selection. if the recommended xtals are not employed, then the frequency of the tmclk clock can be calculated from the divide constant. other transmission data rates other standard frequencies may be obtained by setting the appropriate dr(4:1) combination with a 32.768mhz crystal as shown in the table 17. asynchronous communication in order to propagate asynchronous data through the ACS405CS, the device should be configured with ckc = 0 so that the device produces a tclk output clock. the tclk clock asynchronously over- samples the data applied to tpos at the rate defined by dr(4:1). the choice of tclk frequency defines the sample rate of the input data and therefore the sampling-jitter appearing at rpos of the far-end modem. example: 8 - asynchronous 115kbps channels. xtal = 32.768mhz dr4/3/2/1 = 0/1/0/1 ckc = 0 tclk clock = 1.024mhz tpos/tneg data rate = 115kbps over-sample factor = 8.9 sampling jitter (approx.') = 11%. similar considerations apply to the maintenance channel, which may also be used to convey asynchronous data. support channels there are up to two support channels on the ACS405CS: tmd1/rmd1 and tmd2/rmd2. for the purpose of this specification these will be referred to collectively as tmd and rmd. the support channels can be used in one of two ways selected by the input frame. dr4 dr3 dr2 dr1 nos. of xtal tclk chann. divide (khz) 0 1 1 1 4 32 1024 0110 4 64 512 0 1 0 1 8 32 1024 0100 8 64 512 0 0 1 1 8 128 256 0 0 1 0 8 256 128 crystal = 32.768 mhz table 17 dr4 dr3 dr2 dr1 xtal tclk divide (mhz) 1 0 0 0 20 1.544 crystal = 30.88 mhz table 16 dr4 dr3 dr2 dr1 xtal xtal tmclk (mhz) dc (khz) 1 1 1 1 33.792 528 64 1 1 1 0 31.560 493.125 64 1 1 0 1 32.768 512 64 1 1 0 0 30.88 482.5 64 1 0 1 1 32.768 512 64 1 0 1 0 30.88 482.5 64 1 0 0 1 32.768 512 64 1 0 0 0 30.88 482.5 64 0 1 1 1 32.768 512 64 0 1 1 0 32.768 512 64 0 1 0 1 32.768 512 64 0 1 0 0 32.768 512 64 0 0 1 1 32.768 512 64 0 0 1 0 32.768 512 64 0 0 0 1 16.384 512 32 0 0 0 0 15.440 482.5 32 table 18
10 ACS405CS issue 4.3 june 1999. frame channel mode with frame = 1 when frame = 1 the channels tmd/rmd become support channels to the main tpos/tneg data channels and are associated with the tclk and rclk clock rather than the tmclk and rmclk clocks employed in maintenance mode. frame mode is only available for a subset of the possible dr(4:1) settings; these are shown in table 19. where table 19 denotes the number of frame channels available as zero, then the status of the frame input pin will be ignored and the support channels will function in maintenance mode. data appearing on inputs tmd1/2 are latched into the device on the falling edge of tclk for both internally and externally generated transmission clocks. output data appearing on rmd1/2 is valid on the rising or falling edge of the rclk clock depending on the setting of resel (see figure 1. timing diagrams) . for 1-channel operation in either tx1 or ht mode then tmd1/rmd1 will be available for transmission but data appearing on tmd2 will be ignored. for 2-channel operation in tx2 mode then both tmd1/rmd1 and tmd2/rmd2 are available for transmission. tmd1 is associated with channel 1 and is clocked by tclk1/rclk1. tmd2 is associated with channel 2 and is clocked by tclk2/ rclk2. for all other data formats, frame mode is currently unavailable. although, the data applied to the tmd1/2 is clocked by tclk with the same resolution as tclk the number of transitions allowed on these inputs is restricted according to the following rules: tx1 mode a maximum of 2 transitions are permitted on tmd1 for each 512 tclk1 clock period. if two transitions occur sequentially (on two successive tclk cycles) then this may be counted as one transition. tx2 mode a maximum of 2 transitions may occur on both tmd1/2 for each 128 tclk1/2 clock period. if two transitions occur sequentially (on two successive tclk1/2 cycles) then this may be counted as one transition. ht mode a maximum of 2 transitions may occur on tmd1 for each 128 tclk1 clock period. if two transitions occur sequentially (on two successive tclk1 cycles) then this may be counted as one transition. in frame mode, tpos/tneg and the associated tmd data are transmitted over the link in phase and will appear in phase at the rpos/rneg and rmd outputs at the far-end ACS405CS. a typical application of frame mode follows: in an e1 frame, only 30 of the available 32 symbols are available for data transmission, the remaining two symbols are deployed for frame synchronisation and signalling. in a proprietary system, it would be possible to use the tmd1/2 support channels to mark the first bit or first word of each frame, thus freeing up extra bandwidth in the main data channels. diagnostic modes the ACS405CS has eight diagnostic modes controlled by dm(3:1) as shown in table 20. the diagnostic modes apply equally to the tpn/rpn and tmd/rmd channels. full-duplex in the full-duplex configuration, the rclk clock of both devices track the average frequency of the corresponding tclk clock of the opposite end of the link. the receiving digital-phase-lock loop diagnostic mode lock dm3 dm2 dm1 full-duplex drift 0 0 0 full-duplex memory 0 0 1 remote loopback random 0 1 0 full-duplex random 0 1 1 local loopback drift 1 0 0 full-duplex slave active 1 0 1 full-duplex master drift 1 1 0 full-duplex active 1 1 1 table 20 d d d d xtal tmd/tclk nos. of frame r r r r (mhz) transitions mode channels 4 3 2 1 per period available 1 1 1 1 33.792 2/512 1 1 1 1 0 31.560 2/512 1 1 1 0 1 32.768 2/128 2 1 1 0 0 30.88 2/128 2 1 0 1 1 32.768 2/128 1 1 0 1 0 30.88 2/128 1 1 0 0 1 32.768 0 0 1 0 0 0 30.88 0 0 0 1 1 1 32.768 0 0 0 1 1 0 32.768 0 0 0 1 0 1 32.768 0 0 0 1 0 0 32.768 0 0 0 0 1 1 32.768 0 0 0 0 1 0 32.768 0 0 0 0 0 1 16.384 2/512 1 0 0 0 0 15.440 2/512 1 table 19
11 ACS405CS issue 4.3 june 1999. (dpll) system makes periodic adjustments to the rclk clock to ensure that the average frequency is exactly the same as the far-end tclk clock. in summary, each tclk is an independent master clock and each rclk a slave of the far-end tclk clock. the relationship between tmclk and rmclk are treated similarly. full-duplex slave in slave mode, the tclk and rclk clock is derived from the tclk clock of the far-end modem, such that their average frequencies are identical. clearly, it is essential that only one modem within a communicating pair is configured in slave mode. the ckc pin should be forced to gnd, so that tclk is always configured as an output. since only one device in the modem pair may be configured in slave mode, the mode also selects active lock. see section headed, locking modes . the relationship between tmclk and rmclk are treated similarly. the ckm pin should be forced to gnd, so that tmclk is always configured as an output. full-duplex master in master mode, the local rclk clock is internally generated from the local tclk clock. the local tclk clock may be internally or externally generated. master mode is only valid if the far-end device is configured in slave mode or if the far-end tclk clock is derived from the far-end rclk clock. only one modem within a communicating pair may be configured as a master. the relationship between tmclk and rmclk are treated similarly. local loopback in local loopback mode, tpn and tmd data is looped back inside the near-end modem and is output at its own rpn and rmd outputs. data received from the far-end device is ignored, except to maintain lock. if concurrent requests occur for local and remote loopback, local loopback is selected. the local loopback diagnostic mode is used to test data flow up to, and back from, the local ACS405CS and does not test the integrity of the link itself. therefore, local loopback operates independently of synchronisation with a second modem (i.e. dcd may be high or low). remote loopback in remote loopback mode, the near-end modem sends a request to the far-end modem to loopback its received data, thus returning the data so that it appears at the rpn and rmd of the initiating modem. both modems are exercised completely, as well as the lasers/leds and the fiber optic link. the remote loopback test is normally used to check the integrity of the entire link from the near-end (initiating modem). whilst a device is responding to a request for remote loopback from the far-end, requests from the near-end to initiate remote loopback will be ignored. drift lock communicating modems attain a stable state when the transmit window of one modem coincides with the receive window of the other, allowing for delay through the optical link. adjustments to machine cycles are made automatically during operation, to compensate for differences in xtal frequencies which would otherwise cause loss of synchronisation. when both modems are configured in drift lock, synchronisation described above depends on a difference in the xtal or system clock frequencies at each end of the link, and the greater the difference the faster the locking. therefore, if the difference between xtal frequencies is very small (a few ppm), automatic locking may take tens of seconds or even minutes. for this reason, normally only one modem in the communication pair will be configured in drift lock mode. drift lock will not succeed if the two modems are driven by an external xtal clock derived from a single source (i.e. tolerance of 0 ppm). active lock mode active lock mode may be used to accelerate synchronisation of a pair of communicating modems so that they achieve lock in less than 1 second. active lock reduces the machine cycle of the device by 0.5 % ensuring that the receive window moves swiftly through the transmit window of the opposing modem. to effect active lock, one modem should be permanently configured in drift lock and the other in active lock. if this is not possible because the system mandates that all modems are peers ( configured identically ), then the same effect may be realised by temporarily invoking lock for a short time after power-up. this is achieved as follows: connect pins dm1, dm2 and dm3 together attaching the node to an rc arrangement, with the capacitor to vdd and the resistor to gnd, to create a 5 v to 0 v ramp on power-up. the rc time-constant should be ca. 5 seconds. active lock will succeed even when communicating devices are driven from clocks derived from a single source (0 ppm).
12 ACS405CS issue 4.3 june 1999. random lock this mode achieves moderate locking times (typically 2 seconds, worst case 3 seconds) with the advantage that the ACS405CS's are configured as peers. communicating modems may be permanently configured in this mode (i.e. with hard-wired pins). random lock will succeed even when communicating devices are driven from clocks derived from a single source (0 ppm). random lock mode is compatible with drift lock and active lock. memory lock following the assertion of a reset (porb = 0) communicating devices will initiate an arbitration process where within 2 seconds (typically) the communicating modems will achieve synchronisation, one establishing itself as an active-lock modem and the other establishing itself as a drift-lock modem. on subsequent attempts to lock, synchronisation will be achieved within 1 second. it is only necessary to apply porb to one device in the communicating pair to initiate an arbitration process. since memory lock status (active or drift) uses on- chip storage, loss of power to the ic will require a new reset (porb = 0). furthermore, should there be a need to synchronise with a third modem, a new reset will be required. mixing lock modes it is possible to mix all combinations of locking modes once the modems are locked, however, prior to synchronisation two modems configured in active lock will not operate. the effect of mixing locking modes on locking speed can be seen in table 21. errc and errl - error detection these signals can be used to give an indication of the quality of the optical link. even when a dc signal is applied to the data, maintenance and tclk inputs, the ACS405CS modem transmits approximately device a device b locking speed mode mode drift drift drift drift active active drift random random drift memory random active active not allowed active random random active memory random random random random random memory random memory memory active* * memory lock has random lock speed for the first synchronisation (arbitration). table 21 11mbps over the link in each direction. this control data is used to maintain the timing and the relative positioning of transmit and receive windows. the transmit and control data is constantly monitored to make sure it is compatible with the 8b10b format. if a coding error is detected errl will go high and will remain high until reset. errl may be reset by asserting porb, or by removing the fiber optic cable from one side of the link thereby forcing the device temporarily out of lock. errc produces a pulse on detection of each coding error. these pulses may be accumulated by means of an external electronic counter. please note that errl and errc detect coding errors and not data errors, nevertheless because of the complexity of the coding rules employed on the ACS405CS, the absence of detected errors on these pins will give a good indication of a high quality link. laser/led considerations since leds or lasers from different suppliers may emit different wavelengths, it is recommended that the lasers/leds in a communicating pair of modems are obtained from the same supplier. acapella can supply details. power supply decoupling the acs9010 contains a highly sensitive amplifier, capable of responding to extremely low current levels. to exploit this sensitivity it is important to reduce external noise to a low level compared to the input signal from the laser/led. the modem should have an independent power trace to the point where power enters the board. figure 4, shows the recommended power supply decoupling. the laser/led should be sited very close to the pmn, pinp, pinn, lan and lap pins. a generous ground plane should be provided, especially surrounding the sensitive pinp and pinn tracks from the acs9010 pins to the optical component. the modem should be protected from emi/rfi sources in the standard ways. link budgets the link budget is the difference between the power coupled to the fiber via the transmit laser/led and the power required to realise the minimum input- amplifier current via the receive pin/led. the link budget is normally specified in db, and represents the maximum attenuation allowed between communicating lasers/leds. the budget is utilised in terms of the cable length, cable connectors and splices. it usually includes an operating margin to allow for degradation in laser/led performance.
13 ACS405CS issue 4.3 june 1999. the power coupled to the cable is a function of the efficiency of the laser/led, the current applied to the laser/led and the type of the fiber optic cable employed. digital mode the acs4050 may be used without the acs9010 device with custom external circuitry for non-fiber applications. please check with acapella for details. loss ( loss of synchronisation) there are two conditions that will make loss go to logic 1: i) loss of synchronisation - ping-pong windows incorrectly aligned i.e dcd = 0. ii) 64 received symbols break the 8b10b encoding rules in a sequence of 256 symbols. in order to return loss to the logic state 0 the following criteria must be met. i) the devices must be synchronised - ping-pong windows correctly aligned i.e dcd = 1. ii) there are no received symbols in a sequence of 256 symbols which break the 8b10b coding rules. data delay (latency) although the ACS405CS is a full-duplex modem, at the fiber level the device operates in a half-duplex manner. typically, half-duplex systems allow bidirectional transmission by alternating the direction of data flow. this means that data must be stored until the link is configured in the appropriate direction. storage inevitably leads to delay or latency. acapella has designed the ACS405CS to minimise latency by very rapidly switching direction at the fiber level, minimising the need to store data. the latency through the system applies to the main data tpos/tneg channels and the support channels tmd/rmd and is a function of the xtal frequency. for a given implementation, the latency has three components: 1) a constant delay (cd) set by the machine cycle and system clock at a frequency of 32.768mhz then cd = 0.7ms. 2) a transmission rate delay (trd) which is equal to 125 bit periods worst case (de-jittering buffer and internal registers) 3) fiber length dependent delay (fdd) which is equal to 2 * (fiber delay) the latency formula is : (0.7 * 10 -3 * 32.768 * 10 -6 /xtal) + (125 * transmit bit period) + (2 * fiber delay), where the fiber delay is typically 5us per km. example latency calculation latency calculation: fiber length = 10km ( ~ 50us) xtal = 33.792mhz dr mode = 4 * 2.048mbps ( transmit bit period = 488ns) latency = ((0.7 * 10 -3 * 32.768 * 10 -6 /33.792 * 10 -6 ) + (125 * 488* 10 -9 ) + ( 2* 50 * 10 -6 )) = 0.84ms
14 ACS405CS issue 4.3 june 1999. jitter characteristics the transmit path contains a transmit fifo, which acts to attenuate high frequency input jitter components of the order 1khz or greater. the receive path contains a digital phase locked loop (d_pll), which controls the output frequency of the receive clock in order to track the transmit clock frequency at the far end modem. the d_pll also acts to:- 1) maintain the fill level in the receive fifo, to ensure that the data latency stays within the specified limits. 2) ensure that jitter tolerance and jitter attenuation is within itu g.823 and at&t 62411 specifications. 3) accommodate any clock drift that may be present. the performance boundary of the d_pll is 500 ppm. the 500 ppm performance limit includes jitter attenuation and drift accommodation. the oscillator controlled by the digital phase locked loop operates in steps of 8ppm, and therefore has a resolution down to +/- 4ppm. due to the discrete nature of the frequency changes, the period of the receive clock can change by +/- one system clock cycle. in the absence of input jitter, output jitter generation for e1 remote loopback configuration is measured at 0.40uipp over frequency range 20hz to 100khz, and 0.08uipp over frequency range 18khz to 100khz. the e1 jitter transfer plot is shown below, measured worst case, remote loopback. e1 jitter transfer plot with adde d t1 template -70 -60 -50 -40 -30 -20 -10 0 10 1.00e+00 1.00e+01 1.00e+02 1.00e+03 1.00e+04 fr e qu e ncy (hz ) gain (db) pub 62411 l template pub 62411 h template itu g.736 template
15 ACS405CS issue 4.3 june 1999. tclk symbol 1 symbol 2 symbol 3 tpos/tneg tmd rclk rpos/rneg symbol 1 symbol 2 symbol 3 rmd figure 1. timing diagrams tmclk and rmclk clock pulse widths transmit set-up and hold times receive set-up and hold times tmclk/tclk rmclk/rclk the active rmclk edge is defined by input resel. t wl t wh figure 2. use of support signals to identify symbols in e1/e2 frame t sut t ht t sur t hr tmd rmd
16 ACS405CS issue 4.3 june 1999. 90 % 90 % 10 % 10 % figure 3. timing diagrams tclk and rclk clock pulse widths digital outputs rise and fall times transmit set-up and hold times receive set-up and hold times the active rclk edge is defined by input resel. t r t f t wl t wh vd+ vdd gnd va+ vd+ pins are 9, 10, 26, 38, 39, 63, 75 gnd pins are 11, 12, 27, 29, 37, 51, 54, 55, 61,62, 74 rxvdd va+ txvdd va+ rxgnd txgnd acs9010 acs4050 gnd figure 4. power supply 680 w 680 w 680 w rxdat- dvdd va+ gnd pins are 2, 4, 17, 30, 41 vb gnd gnd l = 47 h r < 1 w va+ (vdd)+5v 100 f + 100 nf (gnd) 0v l = 47 h r < 1 w gnd 100nf vb vdd gnd 100nf gnd 100nf gnd 1uf gnd gnd 100nf 100nf gnd 100nf gnd t sut t ht t sur t hr tpos/tneg rpos/rneg rclk tclk
17 ACS405CS issue 4.3 june 1999. laser pin diode single fiber tset txflg coef1 coef2 1 nf ctx1 ctx2 rset lasrx laser pinrx rxvdd txvdd txgnd rxgnd txdat rxdat+ entx enrxb encofb 10nf pinn pinp lap lan pmn 100 nf txdat entx enrxb txmn 5k w xto xti gnd acs4050 figure 5. diagram showing acs9010 and acs4050 configured to drive a laser duplex device 10nf 50 k w rxdat+ rxflg acs9010 1 k w 27 w 100 pf dvdd rxdat- scext eclk 100 nf 1uf va+ va+ va+ va+ rset2 rxmn 1 m w l = 47 h r < 1 w gnd 100nf va+ (vdd)+5v 100 f + 100 nf (gnd) 0v l = 47 h r < 1 w gnd 100nf vb vdd rpos(4:1) rneg(4:1) rclk(2:1) rmd(2:1) rmclk errc errl dcd los iref 51k w 12 12 12 12 vd+ va+ vdd vb 100 nf 100 nf tpos(4:1) tneg(4:1) tclk(2:1) tmd(2:1) tmclk dr(2:1) dm(3:1) pol(2:1) ckc ckm resel setb frame fhold porb 100nf 100k w 680 w 680 w 680 w
18 ACS405CS issue 4.3 june 1999. 1ic 2 gnd 3 rset2 4 gnd 5 rxdat+ 6 laser 7 rset 8 lasrx 9 enrxb 10 res 11 res 12 res 13 pinrx 14 rxflg 15 rxmn 16 rxvdd 17 rxgnd 18 coef1 19 coef2 20 encofb 21 res 22 res ic 44 res 43 dvdd 42 gnd 41 txdat 40 entx 39 tset 38 txflg 37 txmn 36 ctx2 35 res 34 res 33 res 32 ctx1 31 txgnd 30 lan 29 lap 28 txvdd 27 pmn 26 pinn 25 pinp 24 res 23 figure 6. top view of 44 pin tqfp package acapella acs9010 1-fiber modem 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 res = reserved, ic = internally connected 1 rneg1 2 rpos1 3 rneg2 4 rpos2 5 rneg3 6 rpos3 7 rneg4 8 rpos4 9 vd+ 10 vd+ 11 gnd 12 gnd 13 tmclk 14 tclk2 15 tclk1 16 tmd1 17 tmd2 18 tneg1 19 tpos1 20 tneg2 21 tpos2 22 tneg3 23 tpos3 24 tneg4 25 tpos4 26 vd+ 27 gnd 28 txdat 29 gnd 30 eclk 31 enrxb 32 entx 33 ic 34 ic 35 ckc 36 ckm 37 gnd 38 vd+ 39 vd+ 40 resel rmd1 80 rmd2 79 rclk1 78 rclk2 77 rmclk 76 vd+ 75 gnd 74 dr1 73 dr2 72 dr3 71 dr4 70 errc 69 errl 68 ic 67 porb 66 loss 65 dcd 64 vd+ 63 gnd 62 gnd 61 pol1 60 pol2 59 ic 58 scext 57 ic 56 gnd 55 gnd 54 rxdat- 53 rxdat+ 52 gnd 51 iref 50 va+ 49 xin 48 xout 47 dm1 46 dm2 45 dm3 44 frame 43 setb 42 fhold 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 acapella acs4050 1-fiber modem 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 figure 7. top view of 80 pin tqfp package res = reserved, ic = internally connected
19 ACS405CS issue 4.3 june 1999. pin description acs4050 part 2 pin description acs4050 part 1 pin sym io name description 9,10 26,38 39,63 75 vd+ - +ve power supply power supply, 4.75 - 5.25 vo lt s . 49 va+ - +ve power supply power supply for clock recovery pll, 4.75 - 5.25 vo lt s . 11,12 27,29 37,51 54,55 61,62 74 gnd - ground power supply 19 21 23 25 tpos1 tpos2 tpos3 tpos4 i transmit data pos transmit channel 1, corresponds to +ve in bipolar signal. transmit channel 2, corresponds to +ve in bipolar signal. transmit channel 3, corresponds to +ve in bipolar signal. transmit channel 4, corresponds to +ve in bipolar signal. 18 20 22 24 tneg1 tneg2 tneg3 tneg4 i transmit data neg transmit channel 1, corresponds to -ve in bipolar signal. transmit channel 2, corresponds to -ve in bipolar signal. transmit channel 3, corresponds to -ve in bipolar signal. transmit channel 4, corresponds to -ve in bipolar signal. 2 4 6 8 rpos1 rpos2 rpos3 rpos4 o receive data pos receive channel 1, corresponds to +ve in bipolar signal. receive channel 2, corresponds to +ve in bipolar signal. receive channel 3, corresponds to +ve in bipolar signal. receive channel 4, corresponds to +ve in bipolar signal. 1 3 5 7 rneg1 rneg2 rneg3 rneg4 o receive data neg receive channel 1, corresponds to -ve in bipolar signal. receive channel 2, corresponds to -ve in bipolar signal. receive channel 3, corresponds to -ve in bipolar signal. receive channel 4, corresponds to -ve in bipolar signal. 40 resel i receive edge select when resel = 1, rpos/rneg and rmd data is valid on the rising edge of rclk/rmclk. when resel = 0, the data is valid on the falling edge of rclk/rmclk. 48 47 xti/ xto - system clock crystal connect fundamental parallel resonance crystal with appropriate padding capacitor to gnd. 64 dcd o data carrier detect when dcd = 1, then the communicating modems have synchronized, and are communicating. 66 porb i power on reset will initialise the device when porb= 0. porb is normally connected to an rc circuit so that a por is automatically invoked on power-up. porb= 1 for normal operation. pin sym io name description 13 tmclk i/o transmit maintenance clk transmit maintenance clock. samples tmd on falling edge when device is not in valid frame mode. see input 'frame'. 15 14 tclk1 tclk2 i/o transmit clocks transmit clock 1/2, samples tpo s/tn eg data on falling edge. 76 rmclk o receive clock (support channel) support channel receive clock with frame = '0' then nominal frequency = 64 khz 78 77 rclk1 rclk2 o receive clocks receive clock, rpos/rneg data is valid on edge selected by input "resel". 16 17 tmd1 tmd2 i transmit maintenance data nrz maintenance channel. tmd is sampled on falling edge of tmclk clock when frame mode is valid else data is sampled on falling edge of tclk . 80 79 rmd1 rmd2 o receive maintenance data nrz maintenance channel. data is set-up with repect to rclk clock when frame mode is valid else data is set-up with respect to rmclk. data is valid on the clock edge selected by resel. 35 ckc i clock select when ckc = 0, tclk1/2 is configured as an output. when ckc = 1, tclk1/2 is configured as an input 36 ckm i clock select when ckm = 0, tmclk1/2 is configured as an output. when ckm = 1, tmclk1/2 is configured as an input 30 eclk i external clock external system clock input. o nly valid when sc ext = '1'. clock must have at least 40% high and 40% low time. 57 scext i select clock external when scext = '1' , then the system clock will be the external clock applied to input 'eclk'. when scext = '0' , then the system clock will be the crystal clock generated at xti/xto. 43 frame i frame mode when frame = '1' , support channels are configured in frame mode.
20 ACS405CS issue 4.3 june 1999. pin description acs4050 part 3 pin description acs9010 part 1 pin sym io name description 41 fhold i format hold when fhold = '0', the device is configured for asymmetrical data communication.the most common setting for this input is fhold = '1' supporting symmetrical communications. 42 setb i laser set-up setb = 0, to adjust the laser output power. setb = 1, in operational mode. 46 45 44 dm1 dm2 dm3 i diagnostic modes dm(3:1) input select the diagnostic modes such as local-loopback and remote- loopback. 50 iref i current reference a 51k w 1% resistor should be placed between iref and gnd . 53 rxdat- i rxdat -ve input this determines the slicing level for input rxdat+. should be set at dvdd / 2. on the next generation of devices this is likely to be derived from the acs9010 device . backward compatibilty will be maintained. 60 59 pol1 pol2 i polarity defines the polarity of input signal tpos/tneg. nrz,hdb3, b8sz or ami. 65 los o loss of signal when loss = 1, receive data is unreliable. when loss = 0, receive data is reliable. 68 errl o error latch if errors are detected in the 8b10b coding rules errl will be forced high.. errl will be reset low if the device is forced out of synchronisation e.g. porb = 0. 69 errc o error count errc will go high coincident with each error detected in the 8b10b coding rules. errors may be accumulated by means of an external electronic counter. 73 72 71 70 dr1 dr2 dr3 dr4 i data rate select the dr(4:1) input select the data rates and number of channels. see section headed data rate selection pin sym io name description 3 rset2 - pll frequency set tie to dvdd at all times. 6 laser i laser laser = 1, when interfacing to a laser. laser = 0, when interfacing to a led. 7rset- receive bias set internally sets the bias current for the analogue cells. connect a 10nf capacitor between rset and gnd. 8lasrxi lap/lan receive when lasrx = 1, lap and lan are connected to the receiver. required for led ping- pong applications. 13 pinrx i pinp/pinn receive when pinrx = 1, pinp and pinn are connected to the receiver. 14 rxflg o receive power flag when rxflg = 1, receiver power > rxmn threshold. when rxflg = 0, receive power < rxmn threshold. 15 rxmn o receive monitor receive power monitor. 16 rxvdd - receive power supply power supply, 4.75 - 5.25 vo lt s . 17 rxgnd - ground power supply. 18 19 coef1 coef2 - compensation capacitor differential offset compensation capacitor. connect a 1nf capacitor between pins 18,19. 24 25 pinp pinn - pin anode pin cathode connections for pin-diode receiver. 26 pmn - laser mon- pin connection to anode of laser monitor- pin. 27 txvdd - transmit power supply power supply, 4.75 - 5.25 vo lt s . 28 29 lap lan - laser anode laser cathode connections to laser or led. 30 txgnd - ground power supply. 2 4 41 gnd - ground power supply 31 35 ctx1 ctx2 - driver smoothing capacitor when using leds: place a 10 nf capacitor between ctx1 and gnd. place a 10 nf capacitor between ctx2 and gnd. when using lasers: place a 10 nf capacitor between ctx1 and gnd. connect ctx2 directly to gnd.
21 ACS405CS issue 4.3 june 1999. pin description of interface signals between acs9010 and acs4050. pin description acs9010 part 2 single fiber laser link link budget example (rtset set so laser launch current = 25 ma peak) fiber type glass (single mode) fiber size 9 micron minimum transmit couple power to fiber (w) 1000 minimum laser & pin responsivity (a/w) 0.25 minimum ACS405CS sensitivity (na) 1000 minimum input power to ACS405CS amplifier (w) 4 link budget (db) (single mode fiber attenuation = 0.3 db/km) 24 single fiber led link link budget example (rtset set so led launch current = 100 ma peak) fiber type plastic glass glass fiber size 1000 micron 62.5micron 50 micron minimum transmit couple power to fiber (w) 1000 100 50 minimum led responsivity (a/w) 0.01 0.1 0.12 minimum ACS405CS sensitivity (na) 1500 1500 1500 minimum input power to ACS405CS amplifier (w) 100 15 12.5 link budget (db) 10 8.24 6.0 pin sym io name description 36 txmn - transmit power monitor monitors transmit output power. 37 txflg o transmit power flag when txflg = 1, transmit power > txmn threshold. when txflg = 0, transmit power < txmn threshold. 38 tset - transmit power setting a 40k w resistor placed between tset and gnd will set the appropriate transmit power level. 42 dvdd - rxdat slicing level voltage provides the appropriate slicing level for rxdat+. use resistor arrangement seen in fig 5 of this specification. pin sym io name description 32 39 entx o i enable transmit transmit window active (acs4050). enable transmit (acs9010). 31 9 enrxb o i enable receive receive window active (acs4050). enable receive (ac9010). 20 enco fb i enables dc o ffset compensation enables the dc offset compensation - encofb is normally connected to enrxb (acs9010). 28 40 txdat o i transmit burst data. transmit burst data out (acs4050). transmit burst data in (acs9010). 5 52 rxdat+ o i receive burst data positive differential receive burst data out (acs9010). positive differential receive burst data in (acs4050).
22 ACS405CS issue 4.3 june 1999. package information for the tqfp 44 and 80 pin packages thin quad flat pack dime ns ions in mm e1/d1 a a1 a2 e b l a a e/d copl. min tqfp44 max 10.00 1.60 0.05 0.15 1.35 1.45 0.80 0.30 0.45 0.45 0.75 0 o 7 o 12.00 0.10 min tqfp80 max 14.00 1.60 0.05 0.15 1.35 1.45 0.65 0.22 0.38 0.45 0.75 0 o 7 o 16.00 0.10
23 ACS405CS issue 4.3 june 1999. absolute maximum ratings operating conditions static digital input conditions (for specified operating conditions) for ttl logic level input pins: tclk1/2 (as input), tmclk (as input), porb, ckm, ckc, dm1/2/3, pol1/2, setb, frame, fhold, scext, eclk. static digital input conditions (for specified operating conditions) for logic level input pins: rxdat+(acs4050), rxdat-(acs4050). static digital input conditions (for specified operating conditions) for ttl logic level input pins with pull up: tpos1/2/3/4, tneg1/2/3/ 4, tmd1/2, dr1/2/3/4, dm1/2/3, resel. static digital output conditions (for specified operating conditions) for output pins: rpos1/2/3/4, rneg1/2/3/4, rclk1/2, rmclk, rmd1/ 2, dcd, errl, errc,los, enrxb(acs4050), entx(acs4050), txdat(acs4050), rxflg(acs9010), rxdat+(acs9010), txflg(acs9010), tclk1/2 (output), tmclk (output). dynamic characteristics (for specified operating conditions) static digital input conditions (for specified operating conditions) for cmos logic level input pins: entx(acs9010), enrxb(acs9010), txdat(acs9010), laser, lasrx, pinrx, encofb(acs9010). parameter symbol min max units power supply vd+, va+, rxvdd, txvdd vdd -0.3 6.0 v input voltage (non-supply pins) vin gnd- 0.3 vdd+0.3 v input current (except lan, lap, pinn, pinp, pmn) iin - 10.0 ma input current (lan, lap, pinn, pinp, pmn) iina - 1.0 ma storage temperature tstor -50 160 c parame te r symbol min ty p max units power supply vd+,va+, txvdd, rxvdd vdd 4.75 5 5.25 v ambient temperature range ta -40 - 85 c parame te r symbol min ty p max units vin high vih 2.0 - - v vin low vil - - 0.8 v input current iin - - 10 m a parame te r symbol m in ty p max units vin high (rxdat+) - (rxdat-) vihdif 100 - 200 mv vin low (rxdat+) - (rxdat-) vildif -100 - -200 mv input current iin - - 10 m a parame te r symbol min ty p max units vin high vih 2.0 - - v vin low vil - - 0.8 v pull-up resistor pu 18k - 55k w input current iin - - 277 m a parame te r symbol min ty p max units vin high vih 65%vdd --v vin low vil - - 35%vdd v pull-up resistor pu 75k 125k 175k w input current iin - - 100 m a parame te r symbol min ty p max units vo ut l o w iol = 4ma vo l 0 - 0.5 v vout high ioh = 4ma vo h vdd - 0.- 5 - vdd v max load capacitance cl - - 50 pf parame te r symbol min ty p max units c rys tal frequenc y xti/xto xtal 16 32.768 35 mhz external system clk (eclk) high or low time fclp 40 - 60 % tpos/tneg data rate fclf 0 - xtal/4 bps rclk and tclk duty cycle (with tclk= output) twh twl 40 50 60 % fre quency de viation at tclk from s e le c te d v a lue (w it h tc lk = inp ut ) fd -250 - + 250 ppm tpos/tneg to tclk set-up time tsut 20 - - ns tpos/tneg to tc lk hold time tht 10 - - ns rpos/rneg to rclk set-up time tsur 0.4*1/r- clk 0.5*1/r- clk 0.6*1/r- clk ns rpos/rneg to rclk hold time thr 0.4*1/r- clk 0.5*1/r- clk 0.6*1/r- clk ns rmclk and tmclk duty cycle (with tmc lk= output) twh twl 30 50 70 % when frame = '0'; tmd1/2 data rate when frame = '1' ; special data transmission rules apply (see support channels). fclmf 0 - 64k bps fre quency de viation at tmc lk from selected value (with tmclk = input) fd -400 - + 400 ppm tmd1/2 to tmc lk s et- up time tsut 20 - - ns tmd1/2 to tmclk hold time tht 10 - - ns rmd1/2 to rmc lk s et- up time tsur 0.4*1/r- mc lk 0.5*1/r- mc lk 0.6*1/r- mc lk ns rmd1/2 to rmclk hold time thr 0.4*1/r- mc lk 0.5*1/r- mc lk 0.6*1/r- mc lk ns digita l output - fall time 50pf load tf 10 ns digita l output- rise time 50pf load tr 10 ns power c onsumption with laser/led = 50 ma in operational mode. acs9010 acs4050 pc - - - - 150 350 mw
24 ACS405CS issue 4.3 june 1999. matching characteristics (for specified operating conditions) figure 8. shows the relationship between data channels ACS405CS single fiber link tpos1/tneg1 rpos1/rneg1 tpos2/tneg2 rpos2/rneg2 tpos3/tneg3 rpos3/rneg3 tpos4/rneg4 rpos4/rneg4 tclk1 rclk1 tclk2 rclk2 rpos1/rneg1 tpos1/tneg1 rpos2/rneg2 tpos3/tneg3 rpos3/rneg3 tpos4/rneg4 rpos4/rneg4 tpos4/tneg4 rclk1 tclk1 rclk2 tclk2 tmd1 rmd1 tmd2 rmd2 tmclk rmclk rmd1 tmd1 rmd2 tmd2 rmclk tmclk ACS405CS parame te r symbol min ty p max units c rystal tolerance using fundamenal parallel resonance crystals ct -50 - +50 ppm minimum amplifier input current led: laser: irec - - 1500 1000 na maximum amplifier input current (see acapella if this is restrictive) irmax 400 - - m a rtset placed between tset and gnd rtset 1k - 40k w maximum monitor pin current ipin 2.0 ma laser current (laser = 1) txmn = 0.5ma rtset < 40k w ilaser 45 50 55 ma laser c urrent limit (laser = 1) ilaser 100 - - ma led current (laser = 0) rtset = 1k w rtset = 40k w iled 75 2.0 100 2.5 125 3.0 ma led as receiver (ping-pong) reverse bias vr - - 1.4 v led as receiver (ping-pong) capacitance ( vr = 0) cled - - 50 pf led as receiver (ping-pong) leakage ( vr = 1.4) cleak - - 150 na pin diode receiver reverse bias vrb - - 4 v pin diode leakage current vrb = 4.0v pleak - - 100 na dvdd input voltage dvddv 3.0 3.3 3.6 v dvdd input current dvddi - - 500 m a iref resistor rifref 49.5 51 51.5 k w
25 ACS405CS issue 4.3 june 1999. figure 8. pcb schematic for component layout for ACS405CS chipset for typical custom application.
26 ACS405CS issue 4.3 june 1999. acapella - a wholly owned subsidiary of acapella ltd. delta house chilworth research centre southampton s016 7ns united kingdom uk tel. 01703 769 008 uk fax. 01703 768 612 intn'l. tel. +44 (0)1703 769 008 intn'l. fax. +44 (0)1703 768 612 email: sales@acapella.co.uk web: www.acapella.co.uk in the interest of further product development acapella reserve the right to change this specification without further notice. ? copyright, acapella ltd. 1998

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