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1995 data sheet mos integrated circuit description the m pd16435 and 16435a are controllers/drivers for a 119 73-dot lcd, and perform lcd full-dot and character composite display by means of control by a microprocessor that has a 4 or 8-bit data bus. a charge pump type dc/dc converter is also incorporated, enabling 3 or 5 v single power supply drive. the m pd16435 uses an external reference clock. the m pd16435a has the on-chip oscillation circuit (external crystal resonator). features ? can interface to 4 or 8-bit cpu. ? incorporates 119 segment outputs and 73 common outputs. (display duty selectable from 1/35, 1/37, 1/71, 1/73) ?5 7 character font 208 character data configuration character generation rom and 16 character data configuration character generation ram, allowing composite full-dot and character display ? incorporates extended display functions such as magnification, lateral scrolling, blink, reverse, etc. ? operating voltage: 2.7 v to 5.5 v ? on-chip dc/dc converter: selectable between 4 set-up circuit and 2 step-up circuit ? on-chip temperature correction circuit ? master/slave operation capability ? on-chip power-on reset circuit ? on-chip oscillation circuit ( m pd16435a) ? 232-pin tcp (tape carried package) ordering information part number package m pd16435n-001- tcp (tab), standard rom code m pd16435n-001-001 standard quad tcp (conforms to eiaj), standard rom code m pd16435n-001-002 standard dual tcp (output olb: 0.25 mm pitch), standard rom code m pd16435an-001- tcp (tab), standard rom code m pd16435an-001-001 standard quad tcp (conforms to eiaj), standard rom code m pd16435an-001-052 standard dual tcp (output olb: 0.25 mm pitch), standard rom code explanation of part number m pd16435 (a) n-xxx-xxx tcp code rom code the tcp model is a custom model. for details, consult nec sales representative. document no. s10298ej3v0ds00 (3rd edition) date published april 1997 n printed in japan dot matrix lcd controller/driver m pd16435, 16435a
m pd16435, 16435a 2 block diagram com73 73 119 119 7 8 8 8 8 test1 test2 ws cs rs rd wr busy reset sync scr gnd1 gnd2 v cc v dd 3/5 c 1 + c 1 ? c 2 + c 2 ? c 3 + c 3 ? d 0~7 v 5 v 4 v 3 v 2 v 1 v in v in 8 8 5 5 osc1 osc3 com1 seg1 osc seg119 osc2 common driver segment driver scaler timing generator 73-bit shift register 119-bit latch selector cursor blinking control register display ram 119 73 bits scroll ram 13 73 bits cgrom 5 7 208 bits cgram 5 7 16 bits address counter instruction register data register busy flag op-amp parallel i/f 2/ 4 step-up circuit ? + instruction decoder
m pd16435, 16435a 3 pin configuration (chip) dummy22 dummy21 com1 com2 215 214 dummy26 vdd gnd1 cs rs rd wr ws d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 reset scr busy sync test1 test2 3/5 osc 1 osc 2 osc 3 vcc dummy25 c1? c1+ c2? c2+ c3? c3+ v in ( ) v in ( +) gnd2 v1 v2 v3 v4 v5 dummy24 dummy23 seg85 dummy16 dummy17 seg119 com37 dummy20 dummy1 dummy2 com38 com39 258 1 dummy13 seg30 dummy5 dummy14 seg31 seg32 seg83 seg84 dummy15 com73 dummy3 dummy4 seg1 135 80 79 136
m pd16435, 16435a 4 pin descriptions description chip select signal register selection signal (specifies address register when 0, control register when 1). read enable signal. reads write address when scrolling. active edge is falling edge. write enable signal. active edge is falling edge. word length selection signal (4-bit input when 1, 8-bit input when 0). transmit/receive data (3-state bidirectional) upper ? d4 to d7 lower ? d0 to d3 (these pins should be set as unused in case of 4-bit data). in test mode, these pins are output pins. in a 4-bit transfer, storage is performed in the upper (msb) in order from the data transferred first. 0 indicates busy state. 0 ? initialization of all internal registers and commands is performed. output is fixed at v 1 . signal is output to cpu on completion of one-character scroll. synchronization signal input/output pins for master/slave operation. m pd16435: input the 4.19 mhz reference clock to the osc 1 pin externally. leave the osc 2 pin open. (always outputs high level.) m pd16435a: this is the pin to which the 4.19 mhz crystal resonator is connected. input the external clock to osc 1 first. 2 hz external clock input pin. scaled by 2 internally to generate 1 hz, used as blink synchronization signal. common output signals segment output signals 1 ? test mode 0 or open ? normal operating mode output type CCC CCC CCC CCC CCC cmos 3-state nch open-drain CCC cmos nch open-drain CCC CCC analog switch analog switch CCC input/output input input input (schmitt) input (schmitt) input input/output output input output input/output CCC input (schmitt) output output output pin name pin no. cs 255 rs 254 rd 253 wr 252 ws 251 250 d 0 to d 7 to 243 busy 240 reset 242 scr 241 sync 239 osc 1 235 osc 2 234 osc 3 233 com1 to 212 to 176 com73 3 to 38 seg1 to 41 to 70 seg119 81 to 134 137 to 171 test1 238 test2 237
m pd16435, 16435a 5 pin name pin no. v1 221 220 v2 to v5 to 217 v in (C) 224 v in (+) 223 v cc , gnd1 232, 256 v dd , gnd2 257, 222 3/5 236 c1 , c2 , 230 to c3 225 description lcd drive power supply pin internal op-amp output lcd drive power supply pins can be adjusted by addition of external resistor. liquid crystal drive power supply op-amp input pins logic power supply, gnd liquid crystal drive (step-up) power supply, gnd drive voltage selection pin 1 ? v dd = 3 v ( 4 step-up circuit selected) 0 ? v dd = 5 v ( 2 step-up circuit selected) a 1 m f tantalum or ceramic capacitor should be connected externally. input/output output input input CCC CCC input CCC output type CCC CCC CCC CCC CCC CCC CCC reference clock product name reference clock m pd16435 external input m pd16435a on-chip oscillation circuit (external crystal resonator) osc circuit ( m pd16435a) osc 2 osc 1 4.19 mhz
m pd16435, 16435a 6 register address list address register name b3 b2 b1 b0 0 0 0 0 full-dot x address register 0 0 0 1 full-dot y address register 0 0 1 0 full-dot data register 0 0 1 1 character x address register 0 1 0 0 character y address register 0 1 0 1 character data register 0 1 1 0 cgram address register 0 1 1 1 cgram data register 1 0 0 0 extension register 1 0 0 1 extension register x address register 1 0 1 0 extension register y address register 1 0 1 1 scroll register 1 1 0 0 control register register functions (1) address register sets the address of each register, and also sets display control, standby mode, and scaler resetting. msb lsb after powering on : don? care b7 b6 b4 b3 b2 b1 b0 b5 register address (0h to ch) see table below display control 00: display control off (seg n , com n = v 1 ) 01: display control off (seg n , com n = unselected waveform) 10: normal operation 11: normal operation standby mode setting 0: normal operation 1: standby mode blink internal scaler reset and 1/2 scaler reset 0: normal operation 1: reset (blinking starts when it lights.) (used to synchronize time variations and time mark blinking.) note standby mode = dc/dc converter stopped osc 1 input invalid ( pd16435) osc stopped ( pd16435a) seg n , com n = v 1 data write/read prohibited 0 0 0 0 0 0 0 0 note m m
m pd16435, 16435a 7 (2) full-dot x address register (register address = 0000b) performs full-dot display, display screen x (segment) direction address setting. as scrolling is not possible with a full- dot display, addresses are not allocated to the scroll ram area. after powering on: undefined (3) full-dot y address register (register address = 0001b) performs full-dot display, display screen y (common) direction address setting. after powering on: undefined (4) full-dot data register (register address = 0010b) inputs full-dot display data. display data is stored in the display memory with the msb on the left, and display data 1 corresponds to illumination. after powering on: undefined msb lsb : don? care b3 b2 b1 b0 full-dot x address (00h to 0eh) msb lsb : don? care b6 b4 b3 b2 b1 b0 b5 full-dot y address (00h to 48h) msb lsb b7 b6 b4 b3 b2 b1 b0 b5 : don? care msb lsb b7 b6 b4 b3 b2 b1 b5 full-dot x address = 00h to 0dh full-dot x address = 0eh full-dot display data full-dot display data
m pd16435, 16435a 8 full-dot x address and y address allocation (5) character x address register (register address = 0011b) performs character display display, screen x (segment) direction address setting. x addresses include the scroll ram area. after powering on: undefined (6) character y address register (register address = 0100b) performs character display display, screen y (common) direction address setting. after powering on: undefined 00h(1) 00h(1) 01h(2) 0eh(15) 48h(73) 01h(2) x address y address b7 b6 b5 b4 b3 b2 b1 b7 b6 b5 b4 b3 b2 b1 b0 8 bits 7 bits msb lsb : don? care b4 b3 b2 b1 b0 character x address (00h to 15h) msb lsb : don? care b2 b1 b0 character y address (00h to 07h)
m pd16435, 16435a 9 (7) character data register (register address = 0101b) the character indicated in the character code table is displayed at the position indicated by the character x and y address registers. after powering on: undefined character x address and y address allocation msb lsb b7 b6 b4 b3 b2 b1 b0 b5 character code : don? care x address y address 00h(1) 00h(1) 13h(20) 01h(2) 14h (21) 15h (22) 07h(8) 01h(2) 8 bits 1 bit 5 bits 1 bit scroll ram area display ram area
m pd16435, 16435a 10 (8) cgram address register (register address = 0110b) performs address setting when display data is written to cgram. bits b6 to b3 of the cgram address indicate the character code, and bits b2 to b0 indicate the character line. note if auto increment is set with the control register, 06h is followed by 07h. dummy data should be sent when the address is 07h. example: (cgram address with auto increment) --- ? 15h ? 16h ? 17h ? 18h ? --- after powering on: underfined (9) cgram data register (register address = 0111b) cgram display data. the lower 5 bits of the write data are valid. after powering on: undefined msb lsb : don? care b6 b4 b3 b2 b1 b0 b5 line address (00h to 06h) character code (00h to 0fh) note msb lsb : don? care b4 b3 b2 b1 b0 cgram data
m pd16435, 16435a 11 (10) extension register (register address = 1000b) performs magnification, reverse, cursor, and time mark setting. msb lsb : don? care b3 b2 b1 b0 in case of magnification setting 00: standard 01: 2 horizontal 10: 2 vertical 11: 4 magnification ( 2 horizontal & vertical) magnification display is performed at any line position; characters of different sizes cannot be displayed on the same line. line specification magnification display is possible by setting an extension y address after this command, and multiple-line magnification display is possible by setting consecutive extension y address. after powering on 0 0 0 0 extension function setting 00: magnification setting 01: reverse setting 10: cursor setting 11: character blink setting in case of reverse setting 00: reverse cancellation (line specification) 01: reverse (line specification) 10: reverse cancellation (full screen) 11: reverse (full screen) line specification reverse display is possible by setting an extension y address after this command, and multiple-line reverse display is possible by setting consecutive extension y addresses. regarding the reverse display y address direction, a total of 9 dots (7 character part dots + 1 cursor part dot + 1 top space dot) are reversed. in the case of 2 vertical magnification or 4 magnification, a total of 18 dots (14 character part dots + 2 cursor part dots + 2 top space dots) are reversed. in case of cursor setting 00: cursor non-display 01: cursor display (blinking stopped) 10: cursor display (blink operation) 11: don? care blinking display can be performed at any address by specifying an extension x and y address after this command. the specification is for one address only. the address specification should be performed in the order: x address ? y address. in case of character blink setting x0: blinking stopped x1: blink operation blinking can be performed at any address by specifying an extension x and y address after this command. the specification is for one address only. the address specification should be performed in the order: x address ? y address.
m pd16435, 16435a 12 display and ram allocation in case of magnification setting (1) example of 2 horizontal magnification (line 07h specified) note lines 0ah to 15h for which 2 horizontal magnification is specified can be used as scroll ram. 00h(1) 00h(1) 13h(20) 01h(2) 07h(8) 01h(2) (x=00h) (x=09h) 8 bits 1 bit 10 bits 2 bits 1 bit display ram 00h(1) 00h(1) 13h(20) 14h(21) 15h(22) 01h(2) 07h(8) 00h 01h 09h 0ah 15h 01h(2) display area non-display area
m pd16435, 16435a 13 (2) example of 2 vertical magnification (line 00h specified) note if 2 vertical magnification is specified for line 07h, the lower half will be outside the display area. also, if 2 vertical magnification is specified for line 06h, the bottom dot will be a space. 00h(1) 00h(1) 13h(20) 01h(2) 06h(7) 01h(2) 16 bits 2 bits 1 bit 5 bits display ram 00h(1) 00h(1) 13h(20) 14h(21) 15h(22) 01h(2) 07h(8) 06h(7) 01h(2) display area non-display area
m pd16435, 16435a 14 (3) example of 4 magnification (line 00h specified) note lines 0ah to 15h for which 4 magnification is specified can be used as scroll ram. if 4 magnification is specified for line 07h, the lower half will be outside the display area, and if 4 magnification is specified for line 06h, the bottom dot will be a space. 00h(1) 00h(1) 09h(10) 00h 01h 13h 06h(7) 01h(2) 16 bits 2 bits 1 bit 1 bit 2 bits 10 bits display ram 00h(1) 00h(1) 09h(10) 0ah(11) 14h(21) 15h(22) 01h(2) 07h(8) 00h 01h 13h 14h 15h 06h(7) 01h(2) display area non-display area
m pd16435, 16435a 15 (11) extension x address register (register address = 1001b) performs extension display, display screen x (segment) direction address setting. x addresses include the scroll ram area. this register must be executed before the extension y address register. after powering on: undefined (12) extension y address register (register address = 1010b) performs extension display, display screen y (common) direction address setting. this register must be executed after the x address. after powering on: undefined (13) scroll register (register address = 1011b) performs scroll setting. msb lsb : don? care b4 b3 b2 b1 b0 character x address (00h to 15h) msb lsb : don? care b2 b1 b0 character y address (00h to 07h) msb lsb after powering on : don? care b7 b6 b4 b3 b2 b1 b0 b5 scroll direction setting 00: scroll reset 01: right scroll 10: left scroll 11: scrolling stopped scrolling by specification of any line is possible by setting a character y address after this command. scrolling can only be performed for one character-unit line. scroll speed setting (00h to 3fh) this value specifies the number of frames for a one-bit move. if 00h is set, scrolling is stopped. 0 0 0 0 0 0 0 0 note 1 note 2 notes 1 . when scroll reset is executed, the screen leftmost character x address returns to 00h, and scrolling is stopped. 2 . after scrolling has been stopped, character y address setting is necessary when scrolling is restarted. it is not possible to set a different address from the character y address before scrolling was stopped.
m pd16435, 16435a 16 (14) control register (register address = 1100b) performs address increment direction, common output, frame frequency, blinking, and master/slave setting. note cgram is incremented in the y direction even if 00h is set. msb lsb after powering on : don? care b7 b6 b4 b3 b2 b1 b0 b5 address increment direction setting 00: auto increment in x direction (up-count) 01: auto increment in y direction (up-count) 1 : address retention when auto increment is used, the address is automatically up-counted after a full-dot, character, or cgram data write. the character x address is reset to 13h. when address retention is specified, the address is retained after a data write. frame frequency setting 00: 100 hz 01: 75 hz 10: 50 hz 11: don? care lcd drive is performed by frame inversion. blink source setting 0: external clock (osc3) 1: internal scaled block master/slave setting 0: master 1: slave common output setting 00: 35 outputs (1/35 duty, com 2 to com 36 selected) 01: 37 outputs (1/37 duty, com 1 to com 37 selected) 10: 71 outputs (1/71 duty, com 2 to com 72 selected) 11: 73 outputs (1/73 duty, com 1 to com 73 selected) 0 0 0 0 0 0 0 0 note
17 m pd16435, 16435a standard rom code (001) 0000 0001 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 cc ram (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 higher bit 4 bits lower bit 4 bits
18 m pd16435, 16435a absolute maximum ratings (t a = 25 ?c, gnd1 = gnd2 = 0 v) parameter symbol rating unit supply voltage 1 (3/5 = l) v cc1 C0.3 to +7.0 v supply voltage 2 (3/5 = h) v cc2 C0.3 to +4.0 v logic input voltage v in C0.3 to v cc +0.3 v logic output voltage v out1 C0.3 to v cc +0.3 v lcd drive power supply voltage v dd v cc C0.3 to +16.0 v lcd drive power supply input voltage v 2 to v 5 C0.3 to v dd +0.3 v lcd drive power supply output voltage v 1 C0.3 to v dd +0.3 v amplifier input voltage v in (+), v in (C) C0.3 to v dd +0.3 v driver output voltage (segment, common) v out2 C0.3 to v dd +0.3 v storage temperature range t stg. C55 to +150 ?c parameter symbol min. typ. max. unit supply voltage 1 (3/5 = l) v cc1 4.5 5.0 5.5 v supply voltage 2 (3/5 = h) v cc2 2.7 3.0 3.6 v lcd drive supply voltage v dd v cc 8.0 14.5 v logic input voltage v in 0v cc v lcd drive power supply input voltage v 2 to v 5 0v dd v lcd drive power supply output voltage v 1 0v dd v external capacitance c 0 to c 3 1 4.7 m f operating temperature range t a C40 +85 ?c recommended operating ranges
19 m pd16435, 16435a symbol v ih1 v il1 v ih2 v il2 v h i ih1 i ih1 i ih2 i il2 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 i loh i lol r com r seg v dd1 v dd2 min. typ. max. unit 0.7v cc v 0.3v cc v 0.8v cc v 0.2v cc v 0.05v cc 0.2v cc v 1 m a C1 m a 6ma C100 m a 0.9v cc v 0.1v cc v 0.9v cc v 0.1v cc v 0.9v cc v 0.1v dd v 10 m a C10 m a 5k w 10 k w 1.9v cc 2.0v cc v 3.6v cc 4.0v cc v electrical specifications (unless specified otherwise, t a = C40 to +85 ?c, c 0 to c 3 = 1 m f, vcc = 5 v 10% : 3/5 = l or vcc = 2.7 v to 3.6 v : 3/5 = h) test conditions except schmitt inputs except schmitt inputs schmitt inputs schmitt inputs schmitt inputs cs, rs, rd, wr, ws, reset, 3/5, osc 3 , v in (+), v in (C), v in = v cc cs, rs, rd, wr, ws, reset, 3/5, osc 3 , v in (+), v in (C), v in = 0 v test1, test2, v in = v cc test1, test2, v in = 0 v d n , scr, 3/5 = l i oh = C1 ma d n , busy, scr, sync, 3/5 = l i ol = 4 ma d n , sck, 3/5 = h i oh = C0.6 ma d n , busy, scr, sync, 3/5 = h i ol = 2.4 ma v 1 pin i oh = C1 ma v in (+) = v dd , v in (C) = 0 v v 1 pin i ol = C10 m a v in (+) = 0 v, v in (C) = v dd d n , sync, busy v in/out = v cc d n , sync, busy v in/out = 0 v com 1 to com 73 |i o | = 100 m a seg 1 to seg 119 |i o | = 100 m a r b = 10 k w 3/5 = l r b = 10 k w 3/5 = h parameter input voltage high input voltage low input voltage high input voltage low hysteresis voltage input current high input current low input current high input current low output voltage high output voltage low output voltage high output voltage low output voltage high output voltage low leak current high leak current low common output on-resistance segment output on-resistance driver unit supply voltage (step-up voltage) driver unit supply voltage (step-up voltage)
20 m pd16435, 16435a electrical specifications (unless specified otherwise, t a = C40 to +85 ?c, c0 to c3 = 1 m f, vcc = 5 v 10% : 3/5 = l or vcc = 2.7 v to 3.6 v : 3/5 = h) symbol min. typ. max. unit test conditions logic consumption current ( m pd16435) logic consumption current ( m pd16435a) i cc1 i cc2 i cc3 i cc4 i cc1 i cc2 i cc3 i cc4 0.35 1 ma 0.35 1 ma 1.3 2.5 ma 0.75 1.5 ma 0.6 1.5 ma 0.65 1.5 ma 1.5 3 ma 1.05 2 ma parameter v cc = 3.0 v, no load, 3/5=h f osc = 4.19 mhz v cc = 5.0 v, no load, 3/5=l f osc = 4.19 mhz v cc = 3.0 v, 3/5=h r b = 10 k w note f osc = 4.19 mhz v cc = 5.0 v, 3/5=l r b = 10 k w note f osc = 4.19 mhz v cc = 3.0 v, no load, 3/5=h f osc = 4.19 mhz v cc = 5.0 v, no load, 3/5=l f osc = 4.19 mhz v cc = 3.0 v, 3/5=h r b = 10 k w note f osc = 4.19 mhz v cc = 5.0 v, 3/5=l r b = 10 k w note f osc = 4.19 mhz note typ. values are reference values for t a = 25 ?c.
21 m pd16435, 16435a note measurement circuit min. typ. max. unit 150 ns 10 ns 3 9 clk note 48 54 clk note 100 550 m s switching specifications (unless specified otherwise, t a = C40 to +85 ?c, c 0 to c 3 = 1 m f, vcc = 5 v 10%, r l = 5 k w , c l = 150 pf) test conditions rd ? d n rd - ? d n when full-dot data is written when charactor data is written symbol t rdd t rdh t bl t bl t scr note clk = 4/f osc parameter rd data delay time rd data hold time busy low-level time busy low-level time scr high-level time r b v 1 v cc v 2 v 3 v 4 v 5 r b r b r b r b + v in - v in +
22 m pd16435, 16435a symbol f osc t whc t wlc t rdh t rdl t wrh t wrl t wrrd t rdwr t crs t crh t ds t dh min. typ. max. unit 3.77 4.19 4.61 mhz 100 ns 100 ns 200 ns 200 ns 200 ns 200 ns 200 ns 200 ns 0ns 300 ns 0ns 200 ns test conditions m pd16435 only m pd16435 only m pd16435 only wr - ? rd rd - ? wr cs , rs ? wr , rd wr - , rd - ? cs - , rs d n ? wr - wr - ? d n required timing conditions (unless specified otherwise, t a = C40 to +85 ?c, c 0 to c 3 = 1 m f, v cc = 5 v 10%, r l = 5 k w , c l = 150 pf) parameter clock frequency high-level clock pulse width low-level clock pulse width rd high-level width rd low-level width wr high-level width wr low-level width wr C rd time rd C wr time cs, rs setup time cs, rs hold time input data setup time input data hold time switching specifications (unless specified otherwise, t a = C40 to +85 ?c, c 0 to c 3 = 1 m f, vcc = 2.7 to 3.6 v, r l = 5 k w , c l = 150 pf) min. typ. max. unit 500 ns 15 ns 3 9 clk note 48 54 clk note 100 550 m s test conditions rd ? d n rd - ? d n when full-dot data is written when charactor data is written symbol t rdd t rdh t bl t bl t scr parameter rd data delay time rd data hold time busy low-level time busy low-level time scr high-level time note clk = 4/f osc
23 m pd16435, 16435a required timing conditions (unless specified otherwise, t a = C40 to +85 ?c, c 0 to c 3 = 1 m f, v cc = 2.7 to 3.6 v, r l = 5 k w , c l = 150 pf) parameter clock frequency high-level clock pulse width low-level clock pulse width rd high-level width rd low-level width wr high-level width wr low-level width wr C rd time rd C wr time cs, rs setup time cs, rs hold time input data setup time input data hold time symbol f osc t whc t wlc t rdh t rdl t wrh t wrl t wrrd t rdwr t crs t crh t ds t dh min. typ. max. unit 3.77 4.19 4.61 mhz 100 ns 100 ns 400 ns 400 ns 400 ns 400 ns 400 ns 400 ns 0ns 600 ns 0ns 400 ns test conditions m pd16435 only m pd16435 only m pd16435 only wr - ? rd rd - ? wr cs , rs ? wr , rd wr - , rd - ? cs - , rs d n ? wr - wr - ? d n
24 m pd16435, 16435a ac timing test voltage ac characteristics waveform osc read timing write timing v ih v il v oh v ol input output t whc t wlc i/f osc osc1 t crs t rdl t rdh t rdwr t crh t rdh t rdd cs, rs rd wr d n t crs t wrl t wrh t wrrd t crh t dh t ds cs, rs wr rd d n
25 m pd16435, 16435a busy scr t bl busy t scr scr
26 m pd16435, 16435a example temperature correction circuit connection v 2 v 3 v 4 v 5 v 1 v in - v in + v cc r 1 r t r p + - r b r b r b r b r b r t : thermistor
27 m pd16435, 16435a standard tcp package drawings ( m pd16435n-001-001, m pd16435an-001-001) 8.33 137 171 134 7.50 81 70 41 3 257 232 217 212 0.15 (0.30) p0.28 ?0.01x57 = 15.96 ?0.025 w0.12 ?0.02 p0.40 ?0.01x60 = 24.00 ?0.04 11.50 12.70 12.70 13.475 16.30 13.475 11.50 4.75 ?0.03 0.3 ?0.3 w0.12 ?0.02 11.50 11.50 12.70 13.475 0.142 ?0.03 12.70 13.475 31.82 +0.04 - 0.07 p0.28 ?0.01x57 = 15.96 ?0.025 p0.40 ?0.01x60 = 24.00 ?0.04 1.00 2.25 2.25 1.42 ?0.03 2.25 2.25 18.00 6.00 4.00 9.50 11.00 13.475 13.475 30 1.00 cu f 1.00 18.00 13.475 13.475 14.50 3.50 11.50 p0.40 12.70 13.475 90 12.70 13.475 p0.40 11.50 0.50 0.65 0.40?.015 0.60?.015 detail of test pad and alignment mark from pattern center from pattern center 12.1 +0 - 4.6 coating area 12.93 +0 - 4.6 coating area max. 0.9
28 m pd16435, 16435a dummy seg31 d u m m y seg30 seg29 seg28 dummy seg27 com50 com51 com48 com49 dummy com47 d u m m y s e g 3 3 s e g 3 2 s e g 3 4 s e g 8 6 s e g 8 4 s e g 8 8 d u m m y s e g 8 5 c o m 4 6 c o m 3 8 g n d 0 1 d u m m y v d d c s d u m m y v 0 3 v 0 5 d u m m y v 0 4 c o m 0 1 c o m 0 9 s e g 8 7 s e g 8 9 s e g 3 6 s e g 3 5 dummy seg91 seg93 dummy com13 com11 dummy com10 com12 com14 seg94 seg92 seg90
29 m pd16435, 16435a standard tcp package drawings ( m pd16435n-001-002) 8.33 137 171 134 7.50 81 70 41 3 257 232 217 212 material detail of alignment mark base hole 3.50 17.50 14.7 ?0.3 10.00 p0.10 p0.1044 10.00 14.7 ?0.3 (30.00) 12.1 +0 - 4.6 coating area p0.70 ?0.01x41 = 28.70 ?0.045 w0.35 ?0.02 31.00 19.00 base film adhesive copper foil plating solder resist : upilex-s : epoxy : electrolysis c u : s n : epoxy t=75 m t=12 m t=18 m t=min 0.25 m t=25 m this figure is shown by copper side over polyimide all tolerances unless otherwise specified 0.05 mm. coner radius is 0.3 mm max. ii sprocket holes (52.25 mm) for 1 pattern 2- f 1.30 2-r1.15 ?0.3 sr 2- f 1.10 cu 2- f 1.90 cu winding way output leads unwinding direction face(copper) 3.00 (1.50) 0.95 2.00 6.00 4.65 31.82 +0.04 - 0.07 9.00 5.05 ?0.3 (4.20) (12.50) (9.25) 13.00 11.10 n 1.42 ?0.03 10.90 (0.70) p0.1003 1.175 ?0.01 24.8 ?0.3 24.8 ?0.3 1.175 ?0.01 max 0.9 25.55 25.55 (50.25) p0.25 ?0.01x195 = 48.75 ?0.075 w0.125 ?0.015 4.60 p0.10x65 4.60 p0.10x71 p0.0964 p0.1013 n 4.75 ?0.03 p0.1 p0.10 10.00 4.00 8.465 +0 - 2.3 4.465 +0 - 2.3 coating area 4.75 10.90 7.00 0.3 ?0.3 0.70 (3.80) 6.00 2.50 (0.70) f1.00 1.00 p0.1005 cu m m m m m p0.1060
30 m pd16435, 16435a from p.c. 25.55 p0.25 0.40 0.30 1.175 ?0.01 0.60 ?0.015 0.40 ?0.015 0.125 1.50 0.50 0.20 0.10 0.50 0.10 (1.20) 0.10 (1.40) 1.40 10.90 from p.c. 11.10 from p.c. detail of test pad and alignment mark dummy v dd gnd1 cs rs rd wr ws d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 reset scr busy sync test1 test2 3/5 osc 1 osc 2 osc 3 v cc c1 - c1+ c2 - c2+ c3 - c3+ v in ( - ) v in (+) gnd2 v1 v2 v3 v4 v5 dummy nc nc com38 com39 com40 com41 com42 com73 seg1 seg119 com37 com5 com4 com3 com2 com1 nc nc
31 m pd16435, 16435a 8.33 137 171 134 7.50 81 70 41 3 257 232 217 212 material detail of alignment mark base hole 3.50 17.50 14.7 ?0.3 10.00 p0.10 p0.1044 10.00 14.7 ?0.3 (30.00) 12.1 +0 - 4.6 coating area p0.70 ?0.01x41 = 28.70 ?0.045 w0.35 ?0.02 31.00 19.00 base film adhesive copper foil plating solder resist : upilex-s : epoxy : electrolysis c u : s n : epoxy t=75 m t=12 m t=18 m t=min 0.25 m t=25 m this figure is shown by copper side over polyimide all tolerances unless otherwise specified 0.05 mm. coner radius is 0.3 mm max. ii sprocket holes (52.25 mm) for 1 pattern 2- f 1.30 2-r1.15 ?0.3 sr 2- f 1.10 cu 2- f 1.90 cu winding way output leads unwinding direction face(copper) 3.00 (1.50) 0.95 2.00 6.00 4.65 31.82 +0.04 - 0.07 9.00 5.05 ?0.3 (4.20) (12.50) (9.25) 13.00 11.10 n 1.42 ?0.03 10.90 (0.70) p0.1003 1.175 ?0.01 24.8 ?0.3 24.8 ?0.3 1.175 ?0.01 max 0.9 25.55 25.55 (50.25) p0.25 ?0.01x195 = 48.75 ?0.075 w0.125 ?0.015 4.60 p0.10x65 4.60 p0.10x71 p0.0964 p0.1013 n 4.75 ?0.03 p0.1 p0.10 10.00 4.00 8.465 +0 - 2.3 4.465 +0 - 2.3 coating area 4.75 10.90 7.00 0.3 ?0.3 0.70 (3.80) 6.00 2.50 (0.70) f1.00 1.00 p0.1005 cu m m m m m p0.1060 standard tcp package drawings ( m pd16435an-001-052)
32 m pd16435, 16435a from p.c. 25.55 p0.25 0.40 0.30 1.175 ?0.01 0.60 ?0.015 0.40 ?0.015 0.125 1.50 0.50 0.20 0.10 0.50 0.10 (1.20) 0.10 (1.40) 1.40 10.90 from p.c. 11.10 from p.c. detail of test pad and alignment mark dummy v dd gnd1 cs rs rd wr ws d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 reset scr busy sync test1 test2 3/5 osc 1 osc 2 osc 3 v cc c1 - c1+ c2 - c2+ c3 - c3+ v in ( - ) v in (+) gnd2 v1 v2 v3 v4 v5 dummy nc nc com38 com39 com40 com41 com42 com73 seg1 seg119 com37 com5 com4 com3 com2 com1 nc nc
33 m pd16435, 16435a reference documents nec semiconductor device reliability/quality control system (iei-1212) semiconductor device mounting technology manual (c10535e)
34 m pd16435, 16435a [memo]
35 m pd16435, 16435a [memo]
32 m pd16435, 16435a no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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