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xicor, inc. 1994, 1995, 1996, 1998 patents pending 9900 - 3003 5 1/11/00 cm 1 characteristics subject to change without notice preliminary information 64k x46402 functional diagram command decode and control logic hv generation timing and control x decoder y decoder data register write control wp scl sda vcc v2f ail (vcc) control signal v2mon reset password logic eeprom array (64kbits) write password area (64, 128, 256, 512, 2k, 4k, all, none) (bytes) power on and generation v 2trip + - reset low voltage v trip + - reset & watchdog timebase control watchdog timer reset otp array 1 passwords no password area otp array 2 dual voltage cpu supervisor with 64k password protected eeprom features ? dual voltage detection and reset assertion low vcc monitor low v2mon monitor low vcc block of eeprom writes reset signal valid down to vcc=1v ? selectable watchdog timer 150ms, 450ms, 1s, 5s, 10s, 20s, 1min, off ? volatile flag shows watchdog/low voltage reset ? 64kbit 2-wire serial eeprom 1mhz serial interface speed 64-byte page write mode ? two 64-byte otp memory blocks requires 64-bit otp password to write ? adjustable size password protected array 64 bit read and write array passwords non-password protected array area ? 8 count tamper counter for invalid passwords ? operates at 2.5-3.7v ? 8l tssop package description the x46402 combines several functions into one device. the ?rst is a dual voltage cpu supervisor plus 64kbit serial eeprom memory with password protected write and read operations. the size of the password protected area is selectable by 3 control bits. a write protect (wp) pin in conjunction with a wpen bit provides hardware otp control of the con?guration of the array. password protected areas require 64 bit read or write passwords prior to access. the eighth illegal password entry (regardless of the number of correct entries) sets an otp tamper bit. this bit is one of the 32 bits in the device id. a secondary voltage monitor circuit activates a v2f ail pin when the secondary supply voltage drops below a v2trip voltage. this circuit is primarily intended to detect the immediate loss of the battery supply. a low vcc voltage detect circuit activates a reset pin when vcc drops below a v trip voltage. this signal also blocks read or write operations. a watchdog timer with the time period controlled by three bits provides several possible time out periods from 150ms to 1 minute.
x46402 preliminary information 2 package/pinouts pin names pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with other open drain or open collector out- puts. an open drain requires the use of a pull-up resistor. write protect (wp) the wp pin works in conjunction with a nonvolatile wpen bit to lock the setting of the watchdog timer control and the memory write protect bits. reset output (reset ) reset is an active low, open drain output which goes active whenever vcc falls below the minimum vtrip sense level. it will remain active until vcc rises above the mini- mum vtrip sense level for 150ms. reset goes active if the watchdog timer is enabled and there is no start bit before the end of the selectable watchdog time-out period. a serial start bit will reset the watchdog timer. reset also goes active on power up at 1v and remains active for 150ms after the power supply stabilizes. v2 voltage fail output (v2fail ) v2f ail is an active low, open drain output which goes active whenever v2mon falls below the minimum v2trip sense level. it will remain active until v2mon rises above the minimum v2mon sense level. device operation power on reset application of power to the x46402 activates a power on reset circuit. this circuit goes active at 1v and pulls the reset pin active. this signal prevents the system micro- processor from starting to operate with insuf?cient volt- age or prior to stabilization of the oscillator. when vcc exceeds the device v trip value for 200ms (nominal) the circuit releases reset allowing the processor to begin executing code. low voltage monitoring during operation, the x46402 monitors the v cc and v2mon levels and compares these with internal, preset voltages. when the internal low voltage detect circuitry senses that v2mon is low, the v2f ail pin goes active. typically this would be used by the processor as an interrupt to stop the execution of the code or to do housekeeping in prep- aration for an impending power failure. when the internal low voltage detect circuitry senses that vcc is low, the following happens: the reset pin goes active. the flag bit in the control register is set to zero. communication to the device is interrupted and any command is aborted. if a serial nonvolatile store is in progress when power fails, the circuitry does not stop the nonvolatile store operation, but attempts to com- plete the operation. the reset and v2f ail signals remain active until vcc voltage drops below 1v. reset remains active until vcc returns and exceeds v trip for 200ms. v2f ail remains active until immediately after v2mon returns and exceeds its minimum voltage. watchdog timer the watchdog timer circuit monitors the microprocessor activity by monitoring the start bit. the microprocessor must send a start bit periodically to prevent a reset sig- nal. the start bit must occur prior to the expiration of the watchdog time-out period. the state of three nonvolatile control bits in the control register determines the watch- dog timer period. the microprocessor can change these watchdog bits, or they may be locked by tying the wp pin high and setting the wpen bit high. vss ground sda serial data vcc power scl serial clock wp write protect v2mon voltage monitor input reset low voltage detect output v2fail v2 voltage fail output wp v cc v2f ail scl v ss v2mon sda reset 3 2 4 1 6 7 5 8 8l tssop
x46402 preliminary information 3 architecture data memory this 64kbit memory array can be partitioned into pass- word protected or non-password protected areas. when password protected, the contents are readable after sending a memory read password. the contents of a password protected portion of the memory array are writeable with a memory write password. this array is re-writable up to the limit of the eeprom endurance. otp the second section of memory consists of two 64-byte arrays, each writable only once. these arrays are always password protected. reading from either of these arrays requires the use of an otp read password. both arrays can be read with a single operation. writing either array requires an otp write password. writing more than 64 bytes to each array results in the data wrapping around and over-writing previous values. control register a password protected read or write array command at address ffffh reads or writes the control register. since the control register contains information relating to the password protection, it is necessary to use the array passwords to access the control register. the control register contains bits that control the watch- dog timer and the hardware write protect features and is formatted as follows: write protect enable bit (wpen) the wp pin, in conjuction with a wpen bit programmed high, provides hardware write protection. this prevents changes to the control register contents even with a valid password. when either the wp pin or wpen bit is low, a 64 bit array write array password is required to change the contents of the control register. when both the wp pin and the wpen bit are high, the control register cannot be written. flag bit the ?ag bit is a volatile bit. it can be used to determine if a reset condition was due to a power failure or watchdog reset condition. if power fails (i.e. the internal low voltage detect signal goes active), the bit is set to 0. this bit is also set or reset by a control register write operation. a watchdog reset does not change the state of the ?ag bit. watchdog timer control the watchdog time-out period is controlled by the bits wd2, wd1, and wd0. see the following table. array address otp array 1 0000h - 003fh otp array 2 0040h - 007fh v2f ail reset vss v2mon scl wp sda vcc volt reg vcc scl sda intr reset c otp mode enabled recommended connection pin1 7 6543210 wpen flb wd2 wd1 wd0 bl2 bl1 bl0 table 1. watchdog time control bits control register bits watchdog time-out (typical) wd2 wd1 wd0 0 0 0 1 second 0 0 1 450 milliseconds 0 1 0 150 milliseconds 0 1 1 disabled 1 0 0 1 minute 1 0 1 20 seconds 1 1 0 10 seconds 1 1 1 5 seconds
x46402 preliminary information 4 password protection configuration portions of the memory array may be locked. this area of memory is password protected and is de?ned by the bits bl2, bl1 and bl0. for these protected areas it is necessary to use a read password to output data and an array write password to write data. this block lock area is re-writable, by issuing the correct password. serial memory operation there are four primary modes of operation for the x46402; protected read and write of the memory and otp arrays and unprotected read and write of non- password protected areas of the memory array. pro- tected operations must be performed with one of four 8- byte passwords. the basic method of communication for the password protected areas of the device is established by generat- ing a start condition, then transmitting a command, fol- lowed by the correct password. all parts will be shipped from the factory with all passwords equal to 0. the user must perform ack polling to determine the validity of the password, before starting a data transfer (see acknowl- edge polling.) only after the correct password is accepted and a ack polling has been performed, can the data transfer occur. non-password protected areas of the memory array are accessed in the same manner as access to password protected areas, except the password and the password acknowledge polling sequences are not required. data is transferred in 8-bit segments, with each transfer being followed by an ack, generated by the receiving device. if the x46402 is in a nonvolatile write cycle a no ack (sda=high) response will be issued in response to loading of the command byte. if a stop is issued prior to the start of a nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. the basic sequence is illustrated in figure 1. after each transaction is completed, the x46402 will reset and enter into a standby mode. this will also be the response if an unsuccessful attempt is made to access a protected array. password protection the x46402 requires a 64 bit write password to change the contents of the control register or to write to a block protected memory area. the x46402 also requires a 64 bit read password to output the contents of the block pro- tected array or the control register. the block protection is controlled by the [bl2:bl0] bits and allows the options described in table 2. if an area is block protected, it needs a password prior to each read or write to the area. the passwords cannot be read, even after the device receives the correct password. figure 1. x46402 device operation (password protected areas) table 2. password protected block size select bl2 bl1 bl0 password protected addresses (use password command) non-password protected addresses (use password or no-password commands) 000 none 0000h - 1fffh 001 0000h - 003fh 0040h - 1fffh 010 0000h - 007fh 0080h - 1fffh 011 0000h - 00ffh 0100h - 1fffh 100 0000h - 01ffh 0200h - 1fffh 101 0000h - 07ffh 0800h - 1fffh 110 0000h - 0fffh 1000h - 1fffh 111 0000h - 1fffh none load command byte load 2 byte address load 8-byte password verify password acceptance by use of password ack polling read/write data bytes twc or data ack polling
x46402 preliminary information 5 figure 2. set v trip level sequence (v cc 3 v trip ) figure 3. set v2 trip level sequence (v cc 3 v2 trip ) figure 4. reset v trip level sequence (vcc > 3v, wel is set.) 012 3 4567 scl sda d8h 012 3 4567 00h reset v p = 15v 012 3 4567 01h v trip v cc 01h sets vcc 012 3 4567 scl sda d8h 012 3 4567 00h reset v p = 15v 012 3 4567 0dh v2 trip v2mon 0dh sets v2mon sda d8h 00h 012 3 4567 scl 012 3 4567 reset v p = 15v 012 3 4567 v trip v cc 03h 03h resets vcc
x46402 preliminary information 6 figure 5. reset v2 trip level sequence (vcc > 3v, wel is set.) sda d8h 00h 012 3 4567 scl 012 3 4567 reset v p = 15v 012 3 4567 v2 trip v2mon 0fh 0fh resets v2mon v cc and v2mon threshold reset procedure the x46402 is shipped with standard v trip, and v2 trip voltages. these values will not change over normal oper- ating and storage conditions. however, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the x46402 trip points may be adjusted. the procedure is described below, and uses the application of a high volt- age control signal. setting the v trip voltage this procedure is used to set the v trip ,v2 trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure will directly make the change. if the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. to set the new voltages, apply the desired v trip thresh- old voltage to the vcc pin, the v2 trip voltage to the v2mon pin, then tie the reset pin to the programming voltage v p . then, write data 01h or 0dh address 00h to program v trip , v2 trip respectively. the stop bit following a valid write operation initiates the programming sequence. bring reset low to complete the operation. note: this operation also writes 01h, or 0dh to address 00h. resetting the v trip voltage this procedure is used to set the v trip , the v2 trip to a native voltage level. for example, if the current v trip is 4.4v and the new v trip must be 4.0v, then the v trip must be reset. when the threshold is reset, the new level is something less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the new v trip , v2 trip voltage, apply the desired v trip or v2 trip threshold voltage to the vcc or v2mon pin, respectively, and tie the reset pin to the program- ming voltage v p . then write 03h or 0fh to address 00h. the stop bit of a valid write operation initiates the pro- gramming sequence. bring reset low to complete the operation. note: this operation also writes 03h or 0fh to address 00h of the eeprom array. figure 6. sample v trip reset circuit 5 4 7 1 8 2 6 3 x46402 v trip adj. v p reset 4.7k sda scl c adjust run v2fail v2 trip adj.
x46402 preliminary information 7 v trip /v2 trip programming apply 5v to vcc or v2mon decrement vcc reset goes active? measured v(2) trip - desired v(2) trip done execute sequence reset v trip /v2 trip set vcc = vcc applied = desired v trip or execute sequence set v trip, v2 trip new vcc or v2mon applied = old vcc v2mon applied + error (<50mv step) execute sequence reset v2 trip , v trip new vcc/v2mon applied = old vcc applied - error error < 0 error = 0 yes no error > 0 set v2mon = v2mon applied = desired v2 trip, vcc>=v2trip or v2mon or v2fail pin recyle vcc power
x46402 preliminary information 8 figure 7. x46402 device operation (non-password protected areas) tamper counter the x46402 contains a tamper counter. the entry of an invalid password increments the counter. this operation requires an internal nonvolatile cycle, requiring up to 10 ms to complete. to minimize the possibility of of an unau- thorized person monitoring the device current to detect the enry of the correct password, an internal high voltage cycle is initiated even when the counter does not incre- ment. as such, each password entry requires up to 10ms to acknowledge, so a long period of time would be required to correctly guess the password. on the eighth incorrect password entry, a one-time pro- grammable tamper bit is set in the device id area. the tamper counter increments with each incorrect pass- word attempt and cannot be reset, except by the reset device command. when the tamper counter over?ows, the device is locked. in the locked condition, none of the password commands respond except reset device. no- password commands are always available. the locked condition is determined by reading the device id and reading bit 32. the device is reset by the master reset or reset device commands. device protocol the x46402 supports a bidirectional bus oriented proto- col. the protocol de?nes any device that sends data onto the bus as a transmitter and the receiving device as a receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the x46402 will be considered a slave in all applications. after each byte written to or read from the x46402, the address pointer is incremented by 1. this allows the user to read from the entire device after sending only a single address. it also allows an entire page to be written in one operation. an exception to this address incrementation occurs during a read. after reading address 1fffh the device goes into an idle mode, so additional reads return all 1s. clock and data conventions data states on the sda line can change only during scl low. sda changes during scl high are reserved for indicating start and stop conditions. refer to figure 8 and figure 9. start condition all commands are preceeded by the start condition, which is a high to low transition of sda when scl is high. the x46402 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition is met. a start may be issued to terminate the input of a control byte or the input data to be written. this will reset the device and leave it ready to begin a new read or write command. a start bit generated while the part is output- ting data is accepted as a start as long as the device is not outputting a zero. stop condition all communications are be terminated by a stop condi- tion. the stop condition is a low to high transition of sda when scl is high. the stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. as with starts, stops are recognized while the device outputs data, as long as the data output is not a zero. figure 8. data validity load command byte load 2 byte address read/write data bytes twc or data ack polling scl sda data data change stable
x46402 preliminary information 9 figure 9. definition of start and stop conditions acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. the x46402 will respond with an acknowledge after rec- ognition of a start condition and its slave address. if both the device and a write condition have been selected, the x46402 will respond with an acknowledge after the receipt of each subsequent eight-bit word. read device id command a special, non-password protected command reads the device id. the device id is a 32 bit identi?cation code that can be generic or tailored to the needs of an individ- ual company. the last of the 32 bits indicates whether the device has been tampered with by an unauthorized user attempting to enter invalid passwords. reset device command the reset device command resets the tamper bit, clears the tamper counter and removes the tamper lock (allowing the device to accept commands). however, the reset device command does not clear any memory array area. scl sda start condition stop condition table 3. x46402 instruction set notes: illegal command codes will be disregarded. the part will respond with a no-ack to the illegal byte and then return to the sta ndby mode. 1st byte after start 1st byte after password 2nd byte after password command description password used 1000 0000 high address low address password memory array read memory read 1000 1000 high address low address otp read otp read 1001 0000 high address low address password memory array write memory write 1001 1000 high address low address otp write otp write 1010 0000 0000 0000 0000 0000 change memory read password memory read 1010 1000 0000 0000 0000 0000 change otp read password otp read 1011 0000 0000 0000 0000 0000 change memory write password memory write 1011 1000 0000 0000 0000 0000 change otp write password otp write 1100 0000 0000 0000 0000 0000 change reset password reset 1100 1000 high address low address no-password memory array read none 1101 1000 high address low address no-password memory array write none 1110 1000 not used not used reset device command (resets tamper bit) reset 1111 0000 not used not used ack polling command (ends password operation) none all the rest reserved
x46402 preliminary information 10 program operations password protected array programming the password protected memory array write or otp write requires issuing an 8-bit password write command followed by the password, password ack command, the address and then the data bytes transferred as illustrated in figure 10. up to 64 bytes (or more) may be trans- ferred. sending more than 64 bytes results in data wrap- ping and over-writing previous data. after the last byte to be transferred is acknowledged, a stop condition is issued which starts the nonvolatile write cycle. non-password protected array programming the non-password protected memory array program mode requires issuing the 8-bit no-password write com- mand followed by the address and then the data bytes transferred as illustrated in figure 11. up to 64 bytes (or more) may be transferred. sending more than 64 bytes results in data wrapping and over-writing previous data. after the last byte to be transferred is acknowledged a stop condition is issued which starts the nonvolatile write cycle. figure 10. password protected array programming (memory and otp arrays) figure 11. non-password protected array programming (memory array only) data 63 ack ack s start command ack ack ack ack ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 write password 7 write password 0 ack data 0 s sda wait t wc data ack polling . . . wait t wc or stop ack polling ack s ack polling repeated command command nack if ack, then password matches start password start command ack s sda ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ack data 0 data 63 ack ack s wait t wc data ack stop . . . polling no password
x46402 preliminary information 11 ack polling once a stop condition is issued to indicate the end of the hosts write sequence, the x46402 initiates the internal nonvolatile write cycle. in order to take advantage of the typical 5ms write cycle, ack polling can begin immedi- ately. this involves issuing the start condition followed by the new command code of 8 bits (1st byte of the protocol.) if the x46402 is still busy with the nonvolatile write opera- tion, it will issue a no-ack in response. if the nonvolatile write operation has completed, an ack will be returned and the host can then proceed with the rest of the proto- col. see figure 12. after the password sequence, there is always a nonvolatile write cycle. this is done to discourage random guesses of the password if the device is being tampered with. in order to continue the transaction, the x46402 requires the mas- ter to perform an ack polling with the speci?c code of f0h. as with regular acknowledge polling the user can either time out for 10ms, and then issue the ack polling once, or continuously loop as described in the ?ow. if the password that was inserted was correct, then an ack will be returned once the nonvolatile cycle is over, in response to the ack polling cycle immediately following it. if the password that was inserted was incorrect, then a no ack will be returned even if the nonvolatile cycle is over. therefore, the user cannot be certain that the password is incorrect until the 10ms write cycle time has elapsed. data ack polling sequence ack returned ? issue new command code write sequence completed enter ack polling issue start no yes proceed password ack polling sequence ack returned ? issue password ack command password load completed enter ack polling issue start no yes proceed
x46402 preliminary information 12 figure 12. acknowledge polling 8th clk. of 8th pwd. byte ack clk 8th clk ack clk ack start condition 8th bit ack or no ack scl sda password protected read operations password protected read operations are initiated in the same manner as password protected write operations but with a different command code. password random read (data array, otp arrays) data from a password protected array can be randomly read after sending a single password. to do this, the mas- ter issues a start bit, sends a password read instruction and read password, performs password ack polling, then issues the desired 2 byte address. the host receives the ?rst byte from the x46402 and sends a nack, followed by a repeated start bit. a new 8-bit address speci?es the next byte to read. this process can continue inde?nitely as long as the each byte read out of the x46402 is nacked and followed by a repeated start. the address automatically increments after each read operation. as such, a special case arises. a random read of address 00ffh automatically increments to 0100h after reading the byte. consider the following example. example: a system needs data from password protected locations 0020h and 0150h and the designer does not wish to send the password twice. after receiving data from 0020h, the host sends a nack and a repeated start, followed by address byte ffh. the data read from location 0ffh is ignored, but the operation has adjusted the address pointer to 100h. another nack and repeated start followed by the address 50h allows the contents of 150h to be read by the host. a random read of either of the otp arrays can access all locations of both arrays without another password com- mand sequence. a password random read operation will also return valid data if accessing a non-password protected area of the array. see figure 13. password sequential read the host can read sequentially within an array after the password acceptance sequence. the data output is sequential, with the data from address n followed by the data from n+1. the address counter for read operations increments all address bits, allowing the entire memory array contents to be serially read during one operation. at the end of the address space (address 1fffh for the memory array, 7fh for the otp array) the device goes into an idle state and data output is all 1s. to continue reading at another address requires a new read opera- tion. refer to figure 14 for the address, acknowledge and data transfer sequence. an acknowledge must follow each 8-bit data transfer. after the last bit has been read, the host sends a stop condition with or without a preced- ing acknowledge. after sending a password read command and the cor- rect password, the entire array, including non-password protected areas will be read with a sequential read com- mand. after sending a password array read command and cor- rect password, the entire array, including non-password protected areas are read by a sequential read command. non-password read operations non-password protected read operations are initiated in the same manner as non-password protected write oper- ations but with a different command code. no-password random read the master issues the start condition, then a no-password read instruction, then issues the word address. once the ?rst byte has been read, another start can be issued fol- lowed by a new 8-bit address. a no-password random read operation is not allowed to a password protected area. in a no-password random read from address 00ffh, the address pointer changes to 100h after output- ting the data byte and operates in the same manner as the password protected operation. see figure 15.
x46402 preliminary information 13 no-password sequential read the host can read sequentially within the un-protected area of the array after receiving the no-password com- mand and an address within the unprotected address space. the data output is sequential, with the data from address n followed by the data from n+1. the address counter for read operations increments all address bits, allowing the entire un-protected memory array contents to be serially read during one operation. at the end of the address space (address 1fffh) the device goes into an idle state and a new read sequence must be initiated to continue reading at another address. refer to figure 16 for the address, acknowledge and data transfer sequence. an acknowledge must follow each 8-bit data transfer. after the last bit has been read, the host sends a stop condition with or without a preceding acknowledge. combined random/sequential operations a random read and sequential read can be combined, however there are some limitations. both password pro- tected or non-password operations operate in the same way. after sending a random read command and reading the ?rst byte, continued clocks will return successive addresses. however, after more than one byte of data is returned, it is not possible to initiate a new random read, without issuing a stop and starting a new command. this also allows multiple random read operations and a sequential read operation, as long as the last operation is sequential. note: a read operation that includes a random read of the last byte in the memory or otp arrays cannot include a sequential read operation. figure 13. password protected random read figure 14. password protected sequential read s ack stop a7 a6 a5 a4 a3 a2 a1 a0 data 0 s start start command ack ack ack ack read password 7 read password 0 s sda ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 0 wait t wc or start ack polling ack s ack polling repeated command command nack if ack, then password matches password data x ack s start command ack ack ack ack read password 7 read password 0 s sda ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ack data 0 if ack, then wait t wc or start ack polling ack s ack polling repeated command command nack password matches stop password
x46402 preliminary information 14 figure 15. non-password protected random read figure 16. non-password protected sequential read figure 17. change passwords s ack stop a7 a6 a5 a4 a3 a2 a1 a0 data 0 s start start command ack s sda ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 0 no-password data x ack s start command ack s sda ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ack data 0 stop no-password start command ack ack ack ack old password 7 old password 0 s sda ack ack ack new password 7 password 0 ack ack ack/noack new password 7 new password 0 ack s stop if ack, then ack two bytes of 0 wait t wc or start ack polling ack s ack polling repeated command command nack password matches if immediate ack, then new password error data ack polling if immediate nack, then new password ok followed by ack after ~5ms * * ack for correct password, no ack for incorrect password new
x46402 preliminary information 15 note on read/write operations password protected (none of the array to all of the array) non- password protected (all of the array to none of the array) 0000h 1fffh password sequential read operation no-password sequential read operation notes: using a password read or a password write to a non-password protected area is acceptable, because the pass- word is received and accepted prior to an address transmission. it is assumed that access to non-password pro- tected areas is uncontrolled, so either method should work. using a no-password read or a no-password write on a password protected area would not work. trying to access a password protected area without the password match causes the device to return a nack after the address. a password sequential read that starts in the password protected area can continue into and through the non-pass- word protected area. it will not wrap back to address 0. a no-password sequential read can only start in the non-password protected area and cannot wrap back into the protected area. change password command when changing a password, the change password com- mand is sent to the device. the old password follows. when the old password is accepted (as indicated by the ack polling command sequence), the new password is sent to the device twice, following two bytes of zero. a stop bit initiates the store of the new password. to be suc- cessful in the password change operation the ?rst and second transmission of the new password must match and there must be exactly 16 password bytes. if this is not the case, the operation is aborted and the password remains unchanged. passwords the sequence in figure 17 shows how to change (pro- gram) the passwords. the programming of passwords is done twice prior to the nonvolatile write cycle in order to verify that the new password is consistent. after the eight bytes are entered in the second pass, a comparison takes place. a mismatch will cause the part to ignore the change command and enter into the standby mode. there are two ways to determine whether the operation was completed successfully. the data ack polling method can determine if a password has been loaded correctly, however the data ack command must be issued less than 2ms after the stop bit. after this time, it cannot be determined if the password has been loaded correctly, without trying the new password. to determine if the new password has been loaded correctly the data ack polling command is issued immediately following the stop bit. if it returns an ack, then the two passes of the new password entry do not match. if it returns a no ack then the passwords match and a high voltage cycle is in progress. the high voltage cycle is complete when a sub- sequent data ack command returns an ack.
x46402 preliminary information 16 d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 1ma f scl = 1mhz, reset = v2fail = v cc w/ pull up resistor v 2mon = v cc i cc2 (3) v cc supply current (write) 3ma f scl = 1mhz, reset = v2fail = v cc w/ pull up resistor rst = v ss i sb1 (1) v cc supply current (standby) 50 a v il = v cc x 0.1, v ih = v cc x 0.9 f scl = 1mhz, f sda = 400 khz i sb2 (1) v cc supply current (standby) 1a v sda = v scl = v 2mon = v cc other = gnd or v cc C0.3v i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v il1 (2) input low voltage C0.5 v cc x 0.3 v v cc = 3.0v v ih1 (2) input high voltage v cc x 0.7 v cc + 0.5 v v cc = 3.0v v il2 (2) input low voltage C0.5 v cc x 0.1 v v cc = 3.0v v ih2 (2) input high voltage v cc x 0.9 v cc + 0.5 v v cc = 3.0v v ol output low voltage 0.4 v i ol = 3ma an easier way to determine that the password has been changed correctly is to read the ack bit following the second writing of the new password. if the device returns an ack, the password is good. a no ack indicates something went wrong. if there was an error, the pass- word remains unchanged. there is no way to read any of the passwords. absolute maximum ratings* temperature under bias . . . . . . . . . . . . C65c to +135c storage temperature . . . . . . . . . . . . . . . C65c to +150c voltage on any pin with respect to v ss . . . . .C1v to +7v d.c. output current . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma lead temperature (soldering, 10 seconds) . . . . . .300c *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommended operating conditions temp min. max. commercial 0c +70c extended C20c +85c device supply voltage limits x46402 2.5v to 3.7v
x46402 preliminary information 17 table 4. capacitance (t a = +25c, f = 1mhz, v cc = 3v) notes: (1) must perform a stop command after a read command prior to measurement (2) v il min. and v ih max. are for reference only and are not tested. (3) this parameter is periodically sampled and not 100% tested. symbol test max. units conditions c out (3) output capacitance (sda) 8pf v i/o = 0v c in (3) input capacitance (wp, scl, v 2mon ) 6pf v in = 0v equivalent a.c. load circuit a.c. test conditions 3v 1.3k w output 100pf input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 output load 100pf ac characteristics ac specifications (over the recommended operating conditions) symbol parameter min typ (1) max units f scl scl clock frequency 0 1000 khz t in pulse width of spikes which must be suppressed by the input filter 10 ns t aa scl low to sda data out valid 0.05 0.55 m s t buf time the bus must be free before a new transmit can start 0.5 m s t low clock low time 0.6 m s t high clock high time 0.4 m s t su:sta start condition setup time 0.25 m s t hd:sta start condition hold time 0.25 m s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 m s t su:sto stop condition setup time 0.25 m s t dh data output hold time 0 100 ns t r sda and scl rise time (10% to 90% of vcc) 10 100 ns t f sda and scl fall time 10 100 ns
x46402 preliminary information 18 reset ac specifications nonvolatile write cycle timing notes: 1. t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. timing diagrams bus timing write cycle timing symbol parameter min. typ.(1) max. units t wc (1) write cycle time 5 10 ms t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r scl sda t wc 8th bit of last byte ack stop condition start condition
x46402 preliminary information 19 guidelines for calculating typical values of bus pull up resistors power-up and power-down timing reset output timing v2fail output timing 50 40 30 20 10 bus capacitance in pf pull up resistance in k w r min r pmax 2 4 6 8 10 for v ih = 0.9v cc r min v ccmax 0.4 C i olmin ---------------------------------------- 1100 w = = v ih vcc 1 e t rmax C r pmax c bus ------------------------------------ C ? ? ? ? ?? = r pmax t r 2.3 c bus () ------------------------------ = t rmax = maximum allowable sda rise time 100ns max rise time vcc t purst t purst t rv t fv t dvc reset 0 volts v trip v trip v2mon v2fail t rb t fb t dvb 0 volts v2 v2 trip trip
x46402 preliminary information 20 notes: (5) this parameter is periodically sampled and not 100% tested. (6) typical values not tested. start bit vs. reset timing symbol parameter min. typ. max. units v trip reset trip point voltage 2.4 C 3.5 v v 2trip v2fail trip point voltage 1.7 C 3.5 v v th v trip hysteresis (high to low vs. low to high v trip voltage) 40 mv v 2ta v 2trip hysteresis (high to low vs. low to high v trip voltage) 40 mv t purst power-up reset timeout 75 150 225 ms t dvc (5) detect v cc low voltage to reset output (vcc = 2.3v) 65 m s t dvb (5) detect v 2mon low voltage to reset output (vcc = 2.5-3.7v) 100 m s t fv (5) v cc fall time 100 m s t rv (5) v cc rise time 100 m s t fb (5) v 2mon fall time 500 n s t rb (5) v 2mon rise time 500 n s v rvalid reset valid v cc 1v sda t wdr reset t wdo t rst t wdo t rst scl t su:sta t su:sto
x46402 preliminary information 21 reset output timing symbol parameter min. typ. max. units t wdo watchdog timeout period, wd2 = 0, wd1 = 1, wd0 = 0 wd2 = 0, wd1 = 0, wd0 = 1 wd2 = 0, wd1 = 0, wd0 = 0 wd2 = 1, wd1 = 1, wd0 = 1 wd2 = 1, wd1 = 1, wd0 = 0 wd2 = 1, wd1 = 0, wd0 = 1 wd2 = 1, wd1 = 0, wd0 = 0 75 225 0.5 2.5 5 10 30 150 450 1 5 10 20 60 225 675 1.5 7.5 15 30 90 ms ms sec sec sec sec sec t wdr sda low duration (reset the watchdog) 400 ns t rst reset timeout 75 150 225 ms
x46402 preliminary information 22 note: all dimensions in inches (in p arentheses in millimeters) 8-lead plastic, tssop, package type v see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 C 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x46402 preliminary information 23 ordering information notes: tolerance for vtrip and v2trip are +/-5% part mark convention v cc range v trip v 2trip package operating temperature range part number 2.5C3.7v 3.1 2.6 8l tssop 0cC70c x46402v8-3.1 -20cC85c x46402v8e-3.1 2.5C3.7v 3.1 1.7 8l tssop 0cC70c x46402v8-3.1a -20cC85c x46402v8e-3.1a 2.5C3.7v 2.9 2.3 8l tssop 0cC70c x46402v8-2.9 -20cC85c x46402v8e-2.9 8-lead tssop eyww xxxx xx 4642 ar = v trip v2 trip temp 4642 as = 4642 at = 4642 au = 4642 av = 4642 aw = 2.6 2.6 1.7 1.7 2.3 2.3 0 to 70 c -20 to 85c 0 to 70 c -20 to 85c 0 to 70 c -20 to 85c 3.1 3.1 3.1 3.1 2.9 2.9 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?cation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the f reedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?tness for any purpose. xicor, inc. reserves the right to discontinue production and change speci?cations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874 , 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) su pport or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?cant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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