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version 4.2 april 2000 1/43 STV6886 low-cost i 2 c controlled deflection processor for multisync monitor features general n sync processor (separate or composite) n 12v supply voltage n 8v reference voltage n hor. lock/unlock output n hor. & vert. lock/unlock indication n read/write i 2 c interface n horizontal and vertical moire n b+ regulator - internal pwm generator for b+ current mode step-up converter - switchable to step-down converter -i 2 c-adjustable b+ reference voltage - output pulses synchronized on horizontal frequency - internal maximum current limitation. horizontal n self-adaptative n dual pll concept n 80khz maximum frequency n x-ray protection input n i 2 c controls: horizontal duty-cycle, h-position, horizontal size amplitude vertical n vertical ramp generator n 50 to 120 hz agc loop n geometry tracking with vpos & vamp n i 2 c controls:vamp, vpos, s-corr, c-corr n vertical breathing compensation i 2 c geometry corrections n vertical parabola generator (pin cushion - e/w, keystone, corner correction) n horizontal dynamic phase (side pin balance & parallelogram) n horizontal and vertical dynamic focus (horizontal focus amplitude, horizontal focus symmetry, vertical focus amplitude) description the STV6886 is a monolithic integrated circuit as- sembled in a 32-pin shrink dual-in-line plastic package. this ic controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. the internal sync processor, combined with the powerful geometry correction block, makes the STV6886 suitable for very high performance mon- itors, using few external components. combined with other st components dedicated for crt monitors (microcontroller, video preampli- fier, video amplifier, osd controller) the STV6886 allows fully i 2 c bus-controlled computer display monitors to be built with a reduced number of ex- ternal components. pin connections shrink32 (plastic package) order code: STV6886 h/hvin vsyncin hmoire/hlock pll2c c0 r0 pll1f hposition hfocuscap focus-out hgnd hfly href comp regin i sense 5v sda scl v cc bout gnd hout xray ewout vout vcap v ref vagccap vgnd vbreath b + gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1
table of contents 2 2/43 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . .................................. 3 quick reference data . . . . . . . . . . . ............................................ 4 block diagram . . . . . . . . . ................................. .................... 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal data . . . . . . . . . . . . . . . . . . . ............................................ 6 supply and reference voltages ..................................................... 6 i2c read/write . . . . . . . . . . . . . . . . . . . . . . ......................................... 7 sync processor . . . . . . . . . . . . ........................................... ..... 7 horizontal section . . . . . . . . . . . . . ............................................ 8 vertical section . . . . . ...................................................... 10 dynamic focus section . . . . . . ........................................... .... 11 geometry control section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 moire cancellation section . . . . . . . . . . . . . . . ................................. 13 b+ section . ............................. ................................ .... 14 typical output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 16 i2c bus address table . . . . . . . ........................................... .... 20 operating description . . . . . . ............................................... 23 1 general considerations . . . . . ......................................... 23 1.1 power supply . . . . . . . ............................................... 23 1.2 i 2 c control . . . . . . . . . . . . . . . . . . . . . . . ................................. 23 1.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 23 1.4 read mode ....................................................... 23 1.5 sync processor . . . . . ........................................... .... 23 1.6 sync identification status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.7 ic status . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 24 1.8 sync inputs . . . .................................................... 24 1.9 sync processor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2 horizontal part . . . . . . . . . . . . . . . . . . . . . . . . .............................. 24 2.1 internal input conditions . . ........................................... 24 2.2 pll1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 25 2.3 pll2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 26 2.4 output section . . . . . . . . . . . . . ........................................ 27 2.5 x-ray protection . . . . . . . . . . . . . . . . . .................................. 27 2.6 horizontal and vertical dynamic focus . . . . . . . . . . . . . . . . . . . . . . . ........... 27 2.7 horizontal moir output . . . . . . . . . . . . .................................. 29 3 vertical part . . . . . . . . . . ........................................... .... 29 3.1 function . . . . . . .................................................... 29 3.2 i2c control adjustments . . . . . . . . . .................................... 29 3.3 vertical moir . . . . . . . ............................................... 29 3.4 basic equations .................................................... 30 3.5 geometric corrections . . . . ........................................... 30 3.6 e/w ............................................................. 31 3.7 dynamic horizontal phase control . . . . . ................................ 32 4 dc/dc converter part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 step-up configuration . . . . . . . . . . . . . .................................. 32 4.2 step-down configuration . . . . . . . . . . . .................................. 32 4.3 step-up and step-down configuration comparison . . . . . . . . . . . . . . . . . . . . . . . . 32 internal schematics . . . ................................. ................... 34 package mechanical data . . . ........................................... .... 41
STV6886 3/43 pin connections pin name function 1 h/hvin ttl-compatible horizontal sync input (separate or composite) 2 vsyncin ttl-compatible vertical sync input (for separated h&v) 3 hmoire/ hlock horizontal moir output (to be connected to pll2c through a resistor divider), hlock output 4 pll2c second pll loop filter 5 c0 horizontal oscillator capacitor 6 r0 horizontal oscillator resistor 7 pll1f first pll loop filter 8 hpositio n horizontal position filter (capacitor to be connected to hgnd) 9 hfocus- cap horizontal dynamic focus oscillator capacitor 10 focus out mixed horizontal and vertical dynamic focus output 11 hgnd horizontal section ground 12 hfly horizontal flyback input (positive polarity) 13 href horizontal section reference voltage (to be filtered) 14 comp b+ error amplifier output for frequency compensation and gain setting 15 regin feedback input of b+ control loop 16 i sense sensing of external b+ switching transistor current, or switch for step-down converter 17 b+gnd ground (related to b+ reference) 18 vbreath v breathing input control (compensation of vertical amplitude against ehv variation) 19 vgnd vertical section ground 20 vagccap memory capacitor for automatic gain control in vertical ramp generator 21 v ref vertical section reference voltage (to be filtered to pin 19) 22 vcap vertical sawtooth generator capacitor 23 vout vertical ramp output (with frequency-independent amplitude and s or c corrections if any). it includes vertical position and vertical moir voltages. 24 ewout pin cushion (e/w) correction parabola output 25 xray x-ray protection input (with internal latch) 26 hout horizontal drive output (npn open collector) 27 gnd general ground 28 bout b+ pwm regulator output (npn open collector) 29 v cc supply voltage(12v typ) (referenced to pin 27) 30 scl i 2 c clock input 31 sda i 2 c data input 32 5v 5v supply voltage
STV6886 4/43 quick reference data parameter value unit any polarity on h sync & v sync inputs yes ttl or composite syncs yes sync on green no horizontal frequency 15 to 80 khz horizontal autosync range (for given r0 and c0. can be easily increased by application) 1 to 3.5 f0 control of free-running frequency no frequency generator for burn-in no control of h-position through i 2 cyes control for h-duty cycle through i 2 c30to65% pll1 inhibition possibility no output for horizontal lock/unlock yes dual polarity h-drive outputs no vertical frequency 35 to 150 hz vertical autosync range (for 150nf on pin 22 and 470nf on pin 20) 50 to 120 hz vertical s-correction (adapted to normal or super flat tube), controlled through i 2 cyes vertical c-correction, controlled through i 2 cyes control of vertical amplitude through i 2 cyes control of vertical position through i 2 cyes input for vertical amplitude compensation versus ehv yes e/w correction output (also known as pin cushion output) yes horizontal size adjustment through i 2 c control of e/w output dc level yes control of e/w (pincushion) adjustment through i 2 cyes control of keystone (trapezo?d) adjustment through i 2 cyes control of corner adjustment through i 2 cyes fully integrated dynamic horizontal phase control yes control of side pin balance through i 2 cyes control of parallelogram through i 2 cyes h/v composite dynamic focus output yes control of horizontal dynamic focus amplitude through i 2 cyes control of horizontal dynamic focus symmetry through i 2 cyes control of vertical dynamic focus amplitude through i 2 cyes tracking of geometric corrections and of vertical focus with vertical amplitude and position yes control of horizontal and vertical moir cancellations through i 2 cyes optimisation of hmoir frequency through i 2 cyes b+ regulation, adjustable through i 2 cyes stand-by function, disabling h and v scanning and b+ yes x-ray protection, disabling h scanning and b+ yes blanking outputs no fast i 2 c read/write 400 khz i 2 c indication of the presence of syncs (biased from 5v alone) yes i 2 c indication of the polarity and type of syncs yes i 2 c indication of lock/unlock, for both horizontal and vertical sections yes
STV6886 5/43 block diagram hsize 7 bits pll1f position r0 c0 hfly pll2c hout 7 8 6 5 12 4 26 phase/frequency comparator h-phase(7bits) vco phase comparator phase shifter h-duty (7bits) hout buffer safety processor controller spin bal 7bits x 2 x key bal 7bits b+ lock/unlock identification sync processor sync input select (1bit) vsync hfly horizontalmoire generator 7 bits+on/off +frequency geometry tracking vdfamp 7bits internal reference (7bits) 5v amp symmetry 2x7bits x 2 x 2 corner 7bits e/wpcc 7bits keyst. 7 bits x dc verticalmoire cancel 7bits+on/off STV6886 vsync vpos 7bits vamp 7bits 7 bits 7 bits vertical oscillator ramp generator s and c correction i 2 c interface h ref v ref 11 19 17 29 25 28 16 14 15 hgnd vgnd vcc xray +out isense comp regin gnd 10 9 24 focus hfocus- ewout 23 18 20 22 v out vbreath v agccap v cap 21 13 32 27 30 31 1 2 3 h/hvin v syncin hmoire /hlock sda scl gnd 5v href vref cap x 4 x 2 +
STV6886 6/43 absolute maximum ratings thermal data supply and reference voltages electrical characteristics (v cc = 12v, t amb =25 c unless otherwise indicated) symbol parameter value unit v cc supply voltage (pin 29) 13.5 v v dd supply voltage (pin 32) 5.7 v v in max voltage on pin 4 pin 9 pin 5 pins 6, 7, 8, 14, 15, 16, 20, 22 pins 3, 10, 18, 23, 24, 25, 26, 28 pins 1, 2 pins 30, 31 4.0 5.5 6.4 8.0 v cc v dd 5 v v v v v v v vesd esd susceptibility human body model, 100pf discharge through 1.5k w eiaj norm, 200pf discharge through 0 w 2 300 kv v t stg storage temperature -40, +150 c t j junction temperature +150 c t oper operating temperature 0, +70 c symbol parameter value unit r th(j-a) max. junction-ambient thermal resistance 65 c/w symbol parameter test conditions min. typ. max. units v cc supply voltage pin 29 10.8 12 13.2 v v dd supply voltage pin 32 4.5 5 5.5 v i cc supply current pin 29 50 ma i dd supply current pin 32 5 ma v ref-h horizontal reference voltage pin 13, i = -2ma 7.6 8.2 8.8 v v ref-v vertical reference voltage pin 21, i = -2ma 7.6 8.2 8.8 v i ref-h max. sourced current on v ref-h pin 13 5 ma i ref-v max. sourced current on v ref-v pin 21 5 ma
STV6886 7/43 i 2 c read/write electrical characteristics (v dd = 5v, t amb =25 c) note: 1 see also i 2 c bus address table. sync processor operating conditions (v dd = 5v, v cc = 12v, t amb =25 c) electrical characteristics (v dd = 5v, v cc = 12v, t amb =25 c) note: 2 t h is the horizontal period. symbol parameter test conditions min. typ. max. units i 2 c processor (1) fscl maximum clock frequency pin 30 400 khz tlow low period of the scl clock pin 30 1.3 m s thigh high period of the scl clock pin 30 0.6 m s vinth sda and scl input threshold pins 30, 31 2.2 v vack acknowledged output voltage on sda input with 3ma pin 31 0.4 v i 2 c leak leakage current into sda and scl with no logic supply v dd =0 pins 30, 31 = 5 v 20 m a symbol parameter test conditions min. typ. max. units hsvr voltage on h/hvin input pin 1 0 5 v mind minimum horizontal input pulses dura- tion pin 1 0.7 m s mduty maximum horizontal input signal duty cycle pin 1 25 % vsvr voltage on vsyncin pin 2 0 5 v vsw minimum vertical sync pulse width pin 2 5 m s vsmd maximum vertical sync input duty cycle pin 2 15 % vextm maximum vertical sync width on ttl h/ vcomposite pin 1 750 m s symbol parameter test conditions min. typ. max. units vinth horizontal and vertical input logic level (pins 1, 2) high level low level 2.2 0.8 v v rin horizontal and vertical pull-up resistor pins 1, 2 250 k w voutt extracted vsync integration time (% of t h ) on h/vcomposite (2) c0 = 820pf 26 35 %
STV6886 8/43 horizontal section operating conditions electrical characteristics (v cc = 12v, t amb =25 c) symbol parameter test conditions min. typ. max. units vco i 0max max current from pin 6 pin 6 1.5 ma f(max.) maximum oscillator frequency 80 khz output section i12m maximum input peak current pin 12 5 ma hoi horizontal drive output maximum cur- rent pin 26, sunk current 30 ma symbol parameter test conditions min. typ. max. units 1st pll section hpoit delay time for detecting polarity change (3) pin 1 0.75 ms vvco vco control voltage (pin 7) v ref-h = 8.2v f h =f 0 f h= f h (max.) 1.4 4.9 v v vcog vco gain (pin 7) r 0 = 6.49k w , c 0 = 820pf tbd 15.9 tbd khz/v hph horizontal phase adjustment (4) % of horizontal period 10 % vbmi vbtyp vbmax horizontal phase setting value (pin 8) (4) minimum value typical value maximum value sub-address 01 byte x1111111 byte x1000000 byte x0000000 2.9 3.5 4.2 v v v ipii1u ipii1l pll1 filter charge current pll1 unlocked pll1 locked 140 1 m a ma f o free running frequency r 0 = 6.49k w ,c 0 = 820pf tbd 22.8 tbd khz dfo/dt free running frequency thermal drift (5) not including external componant drift -150 ppm/c cr pll1 capture range fh(min.) fh(max.) (6) f o +0.5 3.5f o khz khz hunlock dc level pin 3 when pll1 is unlocked (7) sub-address 02 1xxx xxxx 0000 0000 0111 1111 6 0.3 2.75 3 v v v
STV6886 9/43 note: 3 this delay is necessary to avoid a wrong detection of polarity change in the case of a composite sync. 4 see figure 10 for explanation of reference phase. 5 these parameters are not tested on each unit. they are measured during our internal qualification. 6 a larger range may be obtained by application. 7 when at 0xxx xxxx, (hmoir/hlock not selected), pin 3 is a dac with 0.3...2.75v range. when at 1xxx xxxx (hmoir/hlock selected) and pll1 is locked, pin 3 provides the waveform for hmoir. see also moir section. 8 hjit = 10 6 x(standard deviation/horizontal period). 9 duty cycle is the ratio between the output transistor off time and the period. the scanning transistor is controlled off when the output transistor is off. 10 initial condition for safe start up. 2nd pll section and horizontal output section fbth flyback input threshold voltage (pin 12) 0.65 0.75 v hjit horizontal jitter (8) at 31.4khz 70 ppm hdmin hdmax horizontal drive output duty-cycle (pin 26) (9) sub-address 00 byte x1111111 byte x0000000 (10) 30 65 % % xrayth x-ray protection input threshold volt- age, pin 25, (see fig. 14) 7.6 8.2 8.8 v vphi2 internal clamping levels on 2nd pll loop filter (pin 4) low level high level 1.6 4.2 v v vscinh inhibition threshold (the condition v cc < vscinh will stop h-out, v-out, b-out and reset x-ray) pin 29 7.5 v hdvd horizontal drive output (low level) pin 26, i out = 30ma 0.4 v symbol parameter test conditions min. typ. max. units
STV6886 10/43 vertical section operating conditions electrical characteristics (v cc = 12v, t amb =25 c) note: 11 these parameters are not tested on each unit. they are measured during our internal qualification procedure. note: 12 set register 07 at byte 0xxxxxxx (s correction inhibited) and register 08 at byte 0xxxxxxx (c correction inhibited), to obtain a vertical sawtooth with linear shape. note: 13 this is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on pin22 and pin 20, and with a constant ramp amplitude. note: 14 when not used, the dc breathing control pin must be connected to 12v. symbol parameter test conditions min. typ. max. units r load minimum load for less than 1% vertical amplitude drift pin 20 65 m w symbol parameter test conditions min. typ. max. units vrb voltage at ramp bottom point pin 22 2.1 v vrt voltage at ramp top point (with sync) pin 22 5.1 v vrtf voltage at ramp top point (without sync) pin 22 vrt- 0.1 v vstd vertical sawtooth discharge time pin 22, c 22 = 150nf 70 m s vfrf vertical free running frequency (12) pin 22, c 22 = 150nf 100 hz asfr auto-sync frequency (13) c 22 = 150nf 5% 50 120 hz rafd ramp amplitude drift versus frequency at maximum vertical amplitude (11) c 22 = 150nf 50hz< f < 120hz 200 ppm/ hz rlin ramp linearity on pin 22 (12) 2.5v < v 27 < 4.5v 0.5 % vpos vertical position adjustment voltage (pin 23 - vout mean value) sub address 06 byte 00000000 byte 01000000 byte 01111111 tbd 3.2 3.6 4.0 tbd v v v vor vertical output voltage (peak-to-peak on pin 23) sub address 05 byte 10000000 byte 11000000 byte 11111111 tbd 2.15 3.0 3.9 tbd v v v voi vertical output maximum current (pin 23) 5ma dvs max vertical s-correction amplitude (tv is the vertical period) (0xxxxxxx inhibits s-corr 11111111 gives max s-corr) sub address 07 byte 11111111 d v/v pp at tv/4 d v/v pp at 3tv/4 -3.5 +3.5 % % ccorr vertical c-corr amplitude (0xxxxxxx inhibits c-corr) sub address 08 d v/v pp at tv/2 byte 10000000 byte 11000000 byte 11111111 -3 0 +3 % % % brrang dc breathing control range (14) v 18 112v bradj vertical output variation versus dc breathing control (pin 23) v 18 >v ref-v 1v STV6886 11/43 dynamic focus section electrical characteristics (v cc = 12v, t amb =25 c) note: 15 s and c correction are inhibited to obtain a linear vertical sawtooth. symbol parameter test conditions min. typ. max. units horizontal dynamic focus function (seefigure 15 on page 28) hdfst horizontal dynamic focus sawtooth minimum level maximum level pin 9, capacitor on hfo- cuscap and c0 = 820pf, t h =20 m s 2.2 4.9 v v hdfdis horizontal dynamic focus sawtooth discharge width triggered by hdfstart 400 ns hdfstart internal phase advance versus hfly middle (independent of frequency) 1 m s hdfdc bottom dc output level r load = 10k w , pin 10 2.1 v tdfhd dc output voltage thermal drift (11) 200 ppm/c hdfamp horizontal dynamic focus amplitude max byte typ byte max byte sub-address 03, pin 10, fh = 50khz, symmetric wave form x1111111 x1000000 x0000000 1 1.5 3.5 v pp v pp v pp hdfkeyst horizontal dynamic focussymmetry (for time reference, see figure 15) max phase advance max phase delay subaddress 04 x1111111 (decimal 127) x0000000 (decimal 0) 16 16 % % vertical dynamic focus function (see figu re 1) ampvdf vertical dynamic focus parabola (added to horizontal) amplitude with vamp and vpos typical sub-address 0f min byte x0000000 typ byte x1000000 max byte x1111111 0 0.5 1 v pp v pp v pp vdfamp parabola amplitude function of vamp (tracking between vamp and vdf) with vpos typ. (see figure 1 on page 15, and (15) ) sub-address 05 byte x0000000 byte x1000000 byte x1111111 0.6 1 1.5 v pp v pp v pp vhdfkeyt parabola asymmetry function of vpos control (tracking between vpos and vdf) with vamp max. b/a ratio a/b ratio sub-address 06 byte x0000000 byte x1111111 0.52 0.52
STV6886 12/43 geometry control section electrical characteristics (v cc = 12v, t amb =25 c) symbol parameter test conditions min. typ. max. units symmetric control through e/w output (see figure 2 on page 15 and figure 4 on page 15) vewm maximum e/w output voltage pin 24 6.5 v vewm minimum e/w output voltage pin 24 1.8 v ew dc for control of horizontal size. dc output voltage with: -e/w corner inhibited -keystone inhibited pin 24, see figure 2 subaddress 11 byte x0000000 byte x1000000 byte x1111111 2 3.25 4.2 v v v tdew dc dc output voltage thermal drift see (16) 100 ppm/c ewpara parabola amplitude with: -vamp max, -vpos typ., -keystone and corner inhibited subaddress 0a byte 11111111 byte 11000000 byte 10000000 1.4 0.7 0 v pp v pp v pp ewtrack parabola amplitude function of vamp control (tracking between vamp & e/w): -vpos typ. -e/w amplitude, corner & keystone in- hibited (17) subaddress 05 byte 10000000 byte 11000000 byte 11111111 0.2 0.4 0.7 v pp v pp v pp keyadj keystone adjustment capability with: - vpos typ. -e/w inhibited, -corner inhibited -vert. amplitude max (see (17) and figure 4) subaddress 09 byte 10000000 byte 11111111 0.4 0.4 v pp v pp ew corner corner adjustment capability with: -vpos typ, -e/w inhibited -keystone inhibited -vertical amplitude max. subaddress 10 byte 11111111 byte 11000000 byte 10000000 + 1.25 0 - 1.25 v pp v pp v pp keytrack intrinsic keystone function of vpos control (tracking between vpos & e/w): - e/w amplitude -vertical amplitude max -corner inhibited b/a ratio a/b ratio subaddress 06 byte 00000000 byte 01111111 0.52 0.52
STV6886 13/43 note: 16 these parameters are not tested on each unit. they are measured during our internal qualification procedure. note: 17 with register 07 at byte 0xxxxxxx (s correction inhibited) and register 08 at byte 0xxxxxxx (c correction inhibited), the sawtooth has a linear shape. moire cancellation section electrical characteristics ( v cc = 12v, t amb =25 c) note: 18 t h is the horizontal period. asymmetric control through internal dynamic horizontal phase modulation (see figure 3) spbpara side pin balance parabola amplitude (figure 3) with : -vamp max., -vpos typ. -parallelogram inhibited (17 & 18) subaddress 0d byte 11111111 byte 10000000 +2.8 -2.8 %t h %t h spbtrack side pin balance parabola amplitude function of vamp control (tracking be- tween vamp and spb) with: -spb max., -vpos typ. -parallelogram inhibited (17 & 18) subaddress 05 byte 10000000 byte 11000000 byte 11111111 1 1.8 2.8 %t h %t h %t h paradj parallelogram adjustment capability with: -vamp max., -vpos typ. -spb inhibited (17 & 18) subaddress 0e byte 11111111 byte 11000000 +2.8 -2.8 %t h %t h partrack intrinsic parallelogram function of vpos control (tracking between vpos and dhpc) with : -vamp max., -spb max. -parallelogram inhibited (17 & 18) b/a ratio a/b ratio subaddress 06 byte x0000000 byte x1111111 0.52 0.52 symbol parameter test conditions min. typ. max. units horizontal and vertical moire r moire minimum output resistor to gnd pin 3 4.7 k w dacout dc voltage pin 3 dac configuration r moire =4.7k w sub-address 02 byte 00000000 byte 01000000 byte 01111111 0.3 1.1 2.75 3 v v v hmoire moir pulse (see also hunlock in 1st pll section) h frequency: locked r moire =4.7k w sub-address 02 byte 10000000 byte 11000000 byte 11111111 0 0.8 2.2 v pp v pp v pp t hmoire preferred scanning/eht structure sub-address ii: 0xxx xxxx 1xxx xxxx separate combined vmoire vertical moir (measured on vout: pin 23) sub-address 0c byte 11111111 3 mv symbol parameter test conditions min. typ. max. units
STV6886 14/43 b+ section operating conditions electrical characteristics (v cc = 12v, t amb =25 c) note: 19 these parameters are not tested on each unit. they are measured during our internal qualification procedure which includes characterization on batches coming from corners of our process and also temperature characterization. note: 20 to make soft start possible, 0.5ma are sunk when b+ is disabled. note: 21 the external power transistor is off during 400ns of the hfocuscap discharge symbol parameter test conditions min. typ. max. units feedres minimum feedback resistor resistor between pins 15 and 14 5k w symbol parameter test conditions min. typ. max. units olg error amplifier open loop gain at low frequency (19) 85 db ugbw unity gain bandwidth see (19) 6mhz iri feedback input bias current current sourced by pin 15 (pnp base) 0.2 m a eaoi error amplifier output current current sourced by pin 14 current sunk by pin 14 (20) 2 1.4 ma ma csg current sense input voltage gain pin 16 3 mceth max current sense input threshold volt- age pin 16 1.3 v isi current sense input bias current current sunk by pin 16 (pnp base) 1 m a tonmax maximum on time of the external power transistor % of horizontal period, f o = 27khz) (21) 100 % b+osv b+output saturation voltage v 28 with i 28 = 10ma 0.25 v iv ref internal reference voltage on error amp (+) input subaddress ob: byte 1000000 5v v refadj internal reference voltage adjustment range byte 01111111 byte 00000000 +20 -20 % % pwmsel threshold for step-up/step-down selec- tion (step-up configuration if v 16 < pwm- sel) pin 16 6 v t fb+ fall time pin 28 100 ns
STV6886 15/43 figure 1. vertical dynamic focus function figure 2. e/w output figure 3. dynamic horizontal phase control figure 4. keystone effect on e/w output (pcc inhibited)
STV6886 16/43 typical output waveforms function sub address pin byte specification effect on screen vertical size 05 23 10000000 11111111 vertical position dc control 06 23 00000000 v outdc = 3.2v 01000000 v outdc = 3.6v 01111111 v outdc = 4.0v vertical s linearity 07 23 0xxxxxxx: inhibited 11111111 2.15v v outdc v outdc 3.9v = d v v pp 3.5% d v v pp
STV6886 17/43 vertical c linearity 08 23 0xxxxxxx : inhibited 10000000 11111111 horizontal size 11 24 x1111111 x0000000 horizontal dynamic focus with: amplitude 03 10 x000 0000 e x111 1111 --- horizontal dynamic focus with: symmetry 04 10 x000 0000 e x111 1111 --- function sub address pin byte specification effect on screen d v v pp dv v pp =-3% v pp dv v pp =+3% 4.2v 2v
STV6886 18/43 keystone (trapezoid) control 09 24 (e/w + corner inhibited) 10000000 11111111 e/w (pin cushion) control 0a 24 (keystone + corner inhibited) 10000000 11111111 corner control 10 24 (keystone+ e/w inhibited) 11111111 10000000 parallel- ogram control 0e (spb inhibited) 10000000 11111111 function sub address pin byte specification effect on screen 0.4v ew dc 0.4v ew dc ew dc 0v ew dc 1.4v 1.25v ew dc ew dc 1.25v internal 2.8% t h 2.8% t h
STV6886 19/43 side pin balance control 0d (parallelogram inhibited) 10000000 11111111 vertical dynamic focus with horizontal 0f 10 x111 1111 x000 0000 function sub address pin byte specification effect on screen 2.8% t h 2.8% t h t v 2.1v t v 2.1v 0v
STV6886 20/43 i 2 c bus address table slave address (8c): write mode sub address definition slave address (8d): read mode: no sub address needed. d8 d7 d6 d5 d4 d3 d2 d1 0 0 0 0 0 0 0 0 0 horizontal drive selection/horizontal duty cycle 1 0 0 0 0 0 0 0 1 x-ray reset/horizontal position 2 0 0 0 0 0 0 1 0 horizontal moir/h lock 3 0 0 0 0 0 0 1 1 sync. priority/horizontal focus amplitude 4 0 0 0 0 0 1 0 0 refresh/horizontal focus symmetry 5 0 0 0 0 0 1 0 1 vertical ramp amplitude 6 0 0 0 0 0 1 1 0 vertical position adjustment 7 0 0 0 0 0 1 1 1 s correction 8 0 0 0 0 1 0 0 0 c correction 9 0 0 0 0 1 0 0 1 e/w keystone a 0 0 0 0 1 0 1 0 e/w amplitude b 0 0 0 0 1 0 1 1 b+ reference adjustment c 0 0 0 0 1 0 0 0 vertical moir d 0 0 0 0 1 0 0 1 side pin balance e 0 0 0 0 1 0 1 0 parallelogram f 0 0 0 0 1 0 1 1 vertical dynamic focus amplitude 10 0 0 0 1 0 0 0 0 e/w corner 11 0 0 0 1 0 0 0 1 h. moir frequency/horizontal size amplitude
STV6886 21/43 i 2 c bus address table (continued) d8 d7 d6 d5 d4 d3 d2 d1 write mode 00 hdrive 0, off [1], on horizontal duty cycle [0] [0] [0] [0] [0] [0] [0] 01 xray 1, reset [0] horizontal phase adjustment [1] [0] [0] [0] [0] [0] [0] 02 hmoir/hlock 1, on [0], off horizontal moir amplitude [0] [0] [0] [0] [0] [0] [0] 03 sync 0, comp [1], sep horizontal focus amplitude [1] [0] [0] [0] [0] [0] [0] 04 detect refresh [0], off horizontal focus symmetry [1] [0] [0] [0] [0] [0] [0] 05 vramp 0, off [1], on vertical ramp amplitu de adjustment [1] [0] [0] [0] [0] [0] [0] 06 test v 1, on [0], off vertical position adjustment [1] [0] [0] [0] [0] [0] [0] 07 s select 1, on [0] s correction [1] [0] [0] [0] [0] [0] [0] 08 c select 1, on [0] c correction [1] [0] [0] [0] [0] [0] [0] 09 e/w key 0, off [1] e/w keystone [1] [0] [0] [0] [0] [0] [0] 0a e/w sel 0, off [1] e/w amplitude [1] [0] [0] [0] [0] [0] [0] 0b test h 1, on [0], off b + reference adjustment [1] [0] [0] [0] [0] [0] [0] 0c v. moir 1, on [0] vertical moir amplitude [0] [0] [0] [0] [0] [0] [0] 0d spb sel 0, off [1] side pin balance [1] [0] [0] [0] [0] [0] [0] 0e parallelo 0, off [1] parallelogram [1] [0] [0] [0] [0] [0] [0]
STV6886 22/43 [x] at power-on reset value data is transferred with vertical sawtooth retrace. we recommend setting the unspecified bits to [0] in order to ensure compatibility with future devices. 0f eq. pulse 1, ignore t h /2 [0], accept all vertical dynamic focus amplitude [1] [0] [0] [0] [0] [0] [0] 10 corner sel 1, on [0], off e/w corner [1] [0] [0] [0] [0] [0] [0] 11 h. moir suited to 1 combined [0] separate scanning/eht horizontal size amplitude [1] [0] [0] [0] [0] [0] [0] read mode hlock 0, on [1], no vlock 0, on [1], no xray 1, on [0], off polarity detection sync detection h/v pol [1], negative v pol [1], negative vext det [0], no det h/v det [0], no det vdet [0], no det d8 d7 d6 d5 d4 d3 d2 d1
STV6886 23/43 operating description 1 general considerations 1.1 power supply the typical values of the power supply voltages v cc and v dd are 12 v and 5 v respectively. opti- mum operation is obtained for v cc between 10.8 and 13.2 v and v dd between 4.5 and 5.5 v. in order to avoid erratic operation of the circuit dur- ing the transient phase of vcc switching on, or off, the value of v cc is monitored: if v cc is less than 7.5 v typ., the outputs of the circuit are inhibited. similarly, before v dd reaches 4 v, all the i 2 c reg- ister are reset to their default value (see i 2 cbus address table). in order to have very good power supply rejection, the circuit is internally supplied by several voltage references (typ. value: 8.2 v). two of these volt- age references are externally accessible, one for the vertical and one for the horizontal part. they can be used to bias external circuitry (if i load is less than 5 ma). it is necessary to filter the voltage references by external capacitors connected to the respective grounds, in order to minimize the noise and consequently the ajittero on vertical and hori- zontal output signals. 1.2 i 2 c control STV6886 belongs to the i 2 c-controlled device family. instead of being controlled by dc voltages on dedicated control pins, each adjustment can be done via the i 2 c interface. the i 2 c bus is a serial bus with a clock and a data input. the general function and the bus protocol are specified in the philips-bus data sheets. the inputs (data and clock) are comparators with a 2.2 v threshold at 5 v supply. spikes of up to 50 ns are filtered by an integrator and the maximum clock speed is limited to 400 khz. the data line (sda) can receive or transmit data. in read-mode the ic sends reply information (1 byte) to the micro-processor. the bus protocol prescribes a full-byte transmis- sion in all cases. the first byte after the start con- dition is used to transmit the ic-address (hexa 8c for write, 8d for read). 1.3 write mode in write mode the second byte is the subaddress of the selected function to adjust (or controls to af- fect) and the third byte the corresponding data byte. it is possible to send more than one data byte to the ic. if after the third byte no stop or start con- dition is detected, the circuit increments automati- cally by one the momentary subaddress in the subaddress counter (auto-increment mode). so it is possible to transmit immediately the following data bytes without sending the ic address or sub- address. this can be useful to reinitialize all the controls very quickly (flash manner). this proce- dure can be finished by a stop condition. the circuit has 18 adjustment capabilities: 3 for the horizontal part, 4 for the vertical, 3 for the e/w cor- rection, 2 for the dynamic horizontal phase control, 2 for the vertical and horizontal moir options, 3 for the horizontal and the vertical dynamic focus and 1 for the b+ reference adjustment. 18 bits are also dedicated to several controls (on/ off, horizontal forced frequency, sync priority, detection refresh and xray reset). 1.4 read mode during the read mode the second byte transmits the reply information. the reply byte contains the horizontal and vertical lock/unlock status, the xray activation status, and the horizontal and vertical polarity detection. it also contains the sync detection status which is used by the mcu to assign the sync priority. a stop condition always stops all the activities of the bus decoder and switches to high impedance both the data and clock line (sda and scl). see i 2 c bus address table. 1.5 sync processor the internal sync processor allows the STV6886 to accept: separated horizontal & vertical ttl-compatible sync signal composite horizontal & vertical ttl-compatible sync signal 1.6 sync identification status the mcu can read (address read mode: 8d) the status register via the i 2 c bus, and then select the sync priority depending on this status. among other data this register indicates the pres- ence of sync pulses on h/hvin, vsyncin and (when 12 v is supplied) whether a vext has been extracted from h/hvin. both horizontal and verti- cal sync are detected even if only 5 v is supplied.
STV6886 24/43 in order to choose the right sync priority the mcu may proceed as follows (see i 2 c bus address ta- ble): refresh the status register, wait at least for 20ms (max. vertical period), read the status register. sync priority choice should be : of course, when the choice is made, we can re- fresh the sync detections and verify that the ex- tracted vsync is present and that no sync type change has occurred. the sync processor also gives sync polarity information. 1.7 ic status the ic can inform the mcu about the 1st horizon- tal pll and vertical section status (locked or not) and about the xray protection (activated or not).resetting the xray internal latch can be done either by decreasing the v cc supply or di- rectly resetting it via the i 2 c interface. 1.8 sync inputs both h/hvin and vsyncin inputs are ttl com- patible triggers with hysteresis to avoid erratic de- tection. both inputs include a pull up resistor con- nected to v dd . 1.9 sync processor output the sync processor indicates on bit d8 of the sta- tus register whether 1st pll is locked to an incom- ing horizontal sync. its level goes to low when locked. this information is also available on pin 3 if sub-address 02 d8 is equal to 1. when pll1 is un- locked, pin 3 output voltage becomes higher than 6v. when it is locked, the hmoir waveform is available on pin 3 (max voltage: 3v). 2 horizontal part 2.1 internal input conditions a digital signal (horizontal sync pulse or ttl com- posite) is sent by the sync processor to the hori- zontal input. it may be positive or negative (see figure 5). using internal integration, both signals are recog- nized if z/t < 25%. synchronization takes place on the leading edge of the internal sync signal. the minimum value of z is 0.7 m s. another integration is able to extract the vertical pulse from composite sync if the duty cycle is high- er than 25% (typically d = 35%), (see figure 6). figure 5. figure 6. the last feature performed is the removal of these equalization pulses which fall in the middle of a line, to avoid parasitic pulses on the phase compa- rator (which would be disturbed by missing or ex- traneous pulses). this last feature is switched on/ off by sub-address 0f d8. by default [0], equaliza- tion pulses will not be removed. vextd et h/v det v det sync priority subaddress 03 (d8) comment sync type no yes yes 1 separated h&v yes yes no 0 composite ttl h&v d csync integ. vsyn
STV6886 25/43 2.2 pll1 the pll1 consists of a phase comparator, an ex- ternal filter and a voltage-controlled oscillator (vco).the phase comparator is a aphase/frequen- cyo type designed in cmos technology. this kind of phase detector avoids locking on wrong fre- quencies. it is followed by a acharge pumpo, com- posed of two current sources : sunk and sourced (typically i =1 ma when locked and i = 140 m a when unlocked). this difference between lock/un- lock allows smooth catching of the horizontal fre- quency by pll1. this effect is reinforced by an in- ternal original slow down system when pll1 is locked, avoiding the horizontal frequency chang- ing too quickly. the dynamic behavior of pll1 is fixed by an external filter which integrates the cur- rent of the charge pump. a acrco filter is generally used (see figure 7 on page 25). figure 7. the pll1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong pulses on phase compa- rator. inhibition is obtained by stopping high and low signals at the input of the charge pump block (see figure 8 on page 25). figure 8. figure 9. pll1f 7 1.8k w 10nf extracted lock/unlock status vsync pll inhibition hposition phase adjust low high lockdet comp1 charge pump pll1f r0 c0 765 vco osc i 2 c hpos adj. extracted vsync 1 input interface h/hvin rs flip flop c0 5 1.6v 6.4v 4i 0 i 0 2 (1.4v STV6886 26/43 the vco uses an external rc network. it delivers a linear sawtooth obtained by the charge and the discharge of the capacitor, with a current propor- tional to the current in the resistor. the typical thresholds of the sawtooth are 1.6 v and 6.4 v. the control voltage of the vco is between 1.4 v and 4.9 v (see figure 9). the theoretical frequen- cy range of this vco is in the ratio of 1 to 3.5. the effective frequency range has to be smaller due to clamp intervention on the filter lowest value. the sync frequency must always be higher than the free running frequency. for example, when us- ing a sync range between 25 khz and 80 khz, the suggested free running frequency is 22 khz. pll1 ensures the coincidence between the lead- ing edge of the sync signal and a phase reference ref1 obtained by comparison between the saw- tooth of the vco and an internal dc voltage vb. vb is i 2 c adjustable between 2.9 v and 4.2 v (cor- responding to 10 %) (see figure 10). the STV6886 also includes a lock/unlock identifi- cation block which senses in real time whether pll1 is locked or not on the incoming horizontal sync signal. this information is available through i 2 c, and also on pin 3 if hlock/unlock option has been set through subaddress 02,d8. figure 10. pll1 timing diagram 2.3 pll2 pll2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the vco, taking into account the saturation time ts (see figure 11 on page 26) figure 11. pll2 timing diagram the phase comparator of pll2 is followed by a charge pump (typical output current: 0.5 ma). the flyback input consists of an npn transistor. the input current must be limited to less than 5 ma (see figure 12). figure 12. flyback input electrical diagram the duty cycle is adjustable through i 2 c from 30 % to 65 %. for a safe start-up operation, the initial duty cycle (after power-on reset) is 65% in order to avoid having too long a conduction period of the horizontal scanning transistor. the maximum storage time (ts max.) is (0.44t h - t fly /2). typically, t fly /t h is around 20 %, at maximum frequency, which means that ts max is around 34 % of t h . the pll1 ensures the exact coincidence between the signal phase ref and hsync. a 10% t h phase adjustment is possible around the 3.5v point. phase ref1 is obtained by comparison between the sawtooth and a dc voltage adjustable between 2.9 v and 4.2 v. ho sc sawtooth 7/8 th 1/8 th 6.4v ref. for h position vb (2.9v STV6886 27/43 2.4 output section the h-drive signal is sent to the output through a shaping stage which also controls the h-drive duty cycle (i 2 c adjustable) (see figure 11). in order to secure the scanning power part operation, the out- put is inhibited in the following cases: when v cc or v dd are too low when the xray protection is activated during the horizontal flyback when the hdrive i 2 c bit control is off. the output stage consists of a npn bipolar tran- sistor. only the collector is accessible (see figure 13). figure 13. this output stage is intended for areverseo base control, where setting the output npn in off-state will control the power scanning transistor in off- state. the maximum output current is 30ma, and the corresponding voltage drop of the output v cesat is 0.4v max. obviously the power scanning transistor cannot be directly driven by the integrated circuit. an inter- face has to be added between the circuit and the power transistor either of bipolar or mos type. 2.5 x-ray protection the x-ray protection is activated by application of a high level on the x-ray input (more than 8.2v on pin 25). it inhibits the h-drive and b+ outputs. this activation is internally delayed by 2 lines to avoid erratic detection when short parasitics are present . this protection is latched; it may be reset either by v cc switch-off or by i 2 c (see figure 14 on page 28). 2.6 horizontal and vertical dynamic focus for dynamic focus adjustment, the STV6886 deliv- ers the sum of two signals on pin 10: a parabolic waveform at horizontal frequency, a parabolic waveform at vertical frequency. the horizontal parabola comes from a sawtooth in phase advance with flyback pulse middle. the phase advance versus horizontal flyback middle is kept constant versus frequency (about 1 m s). sym- metry and amplitude are i 2 c adjustable (see figure 15 on page 28). the vertical parabola is tracked with vpos and vamp. its amplitude can be adjusted. it is also af- fected by s and c corrections. this positive signal once amplified is to be sent to the crt focusing grids. because the dc/dc converter is triggered by the hfocus sawtooth, it is recommended to connect a capacitor to pin 9, even if hfocus is not needed. the capacitor value is critical only if focus is used.
STV6886 28/43 figure 14. safety functions block diagram figure 15. phase of hfocus parabola 127 64 45 0 0.16t h 0.16t h 0.475t h 127 64 45 0 i 2 c code (decimal) 0.6 m s 0.6 m s 0.4 m s 1 m s flyback pulse h focus sawtooth h focus parabola
STV6886 29/43 2.7 horizontal moir output the horizontal moir output is intended to correct a beat between the horizontal video pixel period and the crt pixel width. the moir signal is a combination of the horizontal and vertical frequency signals. to achieve a moir cancellation, the moir output has to be connected so as to modulate the hori- zontal position. we recommend introducing this ahorizontal controlled jittero on the ground side of pll2 capacitor where this acontrolled jittero will di- rectly affect the horizontal position. the amplitude of the signal is i 2 c adjustable. the h-moir frequency can be chosen via the i 2 c. if h scanning and eht are separated, bit d8 in subaddress 11 should be set to 0. if h scanning and eht are combined, setting this bit to 1 will pro- vide a better screen aspect. the h-moir output is combined with the pll1 horizontal unlock output. if hmoir/hlock is selected (bit 02d8 to 1): when pll1 is unlocked, pin 3 output voltage goes above 6v. when pll1 is locked, the hmoir signal (up to 2.2v peak) is present on pin 3. if hmoir/hlock is not selected, pin 3 can be used as a 0....2.5v dac. 3 vertical part 3.1 function when the synchronization pulse is not present, an internal current source sets the free-running fre- quency. for an external capacitor c osc = 150nf, the typical free running frequency is 100hz. the typical free running frequency can be calculat- ed by: fo(hz) = 1.5 . 10 -5 . a negative or positive ttl level pulse applied on pin 2 (vsync) as well as a ttl composite sync on pin 1 can synchronize the ramp in the range [fmin, fmax] (see figure 16 on page 30). this fre- quency range depends on the external capacitor connected on pin 22. a 150nf ( 5%) capacitor is recommended for 50hz to 120hz applications. if a synchronization pulse is applied, the internal oscillator is synchronized immediately but with wrong amplitude. an internal correction then ad- justs it in less than half a second. the top value of the ramp (pin 22) is sampled on the agc capaci- tor (pin 20) at each clock pulse and a transcon- ductance amplifier modifies the charge current of the capacitor so as to adjust the amplitude to the right value. the read status register provides the vertical lock-unlock and the vertical sync polarity informa- tion. we recommend to use an agc capacitor with low leakage current. a value lower than 100na is man- datory. a good stability of the internal closed loop is reached with a 470nf 5% capacitor value on pin 20 (vagc). 3.2 i 2 c control adjustments s and c correction shapes can then be added to this ramp. these frequency-independent s and c corrections are generated internally. their ampli- tudes are adjustable by their respective i 2 c regis- ters. they can also be inhibited by their select bits. finally, the amplitude of this s and c corrected ramp can be adjusted by the vertical ramp ampli- tude control register. the adjusted ramp is available on pin 23 (v out )to drive an external power stage. the gain of this stage can be adjusted ( 25%) de- pending on its register value. the mean value of this ramp is driven by its own i 2 c register (vertical position). its value is vpos = 7/16 . v ref-v 400mv. usually v out is sent through a resistive divider to the inverting input of the booster. since vpos de- rives from v ref-v , the bias voltage sent to the non- inverting input of the booster should also derive from v ref-v to optimize the accuracy (see appli- cation diagram). 3.3 vertical moir by using the vertical moir, vpos can be modulat- ed from frame to frame. this function is intended to cancel the fringes which appear when the line to line interval is very close to the crt vertical pitch. the amplitude of the modulation is controlled by register vmoire on sub-address 0c and can be switched-off via the control bit d8. 1 c osc
STV6886 30/43 figure 16. agc loop block diagram 3.4 basic equations in first approximation, the amplitude of the ramp on pin 23 (vout) is: v out - vpos = (v osc -v dcmid ) . (1 + 0.3 (v amp )) where: v dcmid = 7/16 v ref (middle value of the ramp on pin 22, typically 3.6v) v osc =v 22 (ramp with fixed amplitude) v amp = -1 for minimum vertical amplitude regis- ter value and +1 for maximum vpos is calculated by: vpos = v dcmid + 0.4 v p where v p = -1 for minimum vertical position reg- ister value and +1 for maximum. the current available on pin 22 is: i osc = . v ref xc osc xf where c osc = capacitor connected on pin 22 and f = synchronization frequency. 3.5 geometric corrections the principle is represented in figure 17 on page 31. starting from the vertical ramp, a parabola-shaped current is generated for e/w correction (also known as pin cushion correction), dynamic hori- zontal phase control correction, and vertical dy- namic focus correction. the parabola generator is made by an analog mul- tiplier, the output current of which is equal to: di = k . (v out -v dcmid ) 2 where v out is the vertical output ramp (typically between 2 and 5v) and v dcmid is 3.6v (for v ref-v = 8.2v). the vout sawtooth is typical- ly centered on 3.6v. by changing the vertical posi- tion, the sawtooth shifts by 0.4v. to provide good screen geometry for any end- user adjustment, the STV6886 has the ageometry trackingo feature which automatically adapts the parabola shape, depending on the vertical position and size. 3 8
STV6886 31/43 due to the large output stage voltage range (e/w pin cushion, keystone, e/w corner), the combi- nation of the tracking function, maximum vertical amplitude, maximum or minimum vertical position and maximum gain on the dac control may lead to output stage saturation. this must be avoided by limiting the output voltage with appropriate i 2 c register values. for the e/w part and the dynamic horizontal phase control part, a sawtooth-shaped differential current in the following form is generated: d i' = k' . ( v out - v dcmid ) then d i and d i' are added and converted into volt- age for the e/w part. each of the three e/w components or the two dy- namic horizontal phase control components may be inhibited by their own i 2 c select bit. the e/w parabola is available on pin 24 via an emitter follower output stage which has to be bi- ased by an external resistor (10 k w to ground). be- ing stable in temperature, the device can be dc coupled with external circuitry (mandatory to ob- tain h size control). the vertical dynamic focus is combined with the horizontal focus on pin 10. the dynamic horizontal phase control drives inter- nally the h-position, moving the hfly position on the horizontal sawtooth in the range of 2.8 %t h both for side pin balance and parallelogram. figure 17. geometric corrections principle 3.6 e/w ewout = ew dc +k1 ( v out - v dcmid )+ k2 ( v out - v dcmid ) 2 +k3 ( v out - v dcmid ) 4 k1 is adjustable by the keystone i 2 c register. k2 is adjustable by the e/w amplitude i 2 c register. k3 is adjustable by the e/w corner i 2 c register.
STV6886 32/43 3.7 dynamic horizontal phase control i out =k4(v out - v dcmid ) + k5 (v out - v dcmid ) 2 k4 is adjustable by the parallelogram i 2 c register. k5 is adjustable by the side pin balance i 2 c regis- ter. 4 dc/dc converter part this unit controls the switch-mode dc/dc con- verter. it converts a dc constant voltage into the b+ voltage (roughly proportional to the horizontal frequency) necessary for the horizontal scanning. this dc/dc converter can be configured either in step-up or step-down mode. in both cases it oper- ates very similarly to the well known uc3842. 4.1 step-up configuration operating description the power mos is switched on during the fly- back (at the beginning of the positive slope of the horizontal focus sawtooth). the power mos is switched off when its cur- rent reaches a predetermined value. for this pur- pose, a sense resistor is inserted in its source. the voltage on this resistor is sent to pin16 (i sense ). the feedback (coming either from the ehv or from the flyback) is divided to a voltage close to 5.0v and compared to the internal 5.0v refer- ence (i vref ). the difference is amplified by an error amplifier, the output of which controls the power mos switch-off current. main features switching synchronized on the horizontal fre- quency, b+ voltage always higher than the dc source, current limited on a pulse-by-pulse basis. the dc/dc converter is disabled: when v cc or v dd are too low, when x-ray protection is latched, directly through i 2 c bus. when disabled, bout is driven to gnd by a 0.5ma current source. this feature allows to im- plement externally a soft start circuit. 4.2 step-down configuration in step-down configuration, the i sense information is not used any more and therefore not sent to the pin16. this configuration is selected by connect- ing this pin16 to a dc voltage higher than 6v (for example v ref-v ). instead of i sense waveform the h-focus saw- tooth is used for comparison with the amplified er- ror voltage. for that reason, the step-down config- uration can operate only if the h-focus capacitor is connected. operating description the power mos is switched on as for the step- up configuration. the feedback to the error amplifier is done as for the step-up configuration. the power mos is switched off when the hfo- cuscap voltage gets higher than the error am- plifier output voltage. main features switching synchronized on the horizontal fre- quency, b+ voltage always lower than the dc source, no current limitation. 4.3 step-up and step-down configuration comparison in step-down configuration the control signal is in- verted compared with the step-up mode.this, for the following reason: in step-up mode, the switch is a n-channel mos referenced to ground and made conductive by a high level on its gate. in step-down, a high-side switch is necessary. it can be either a p- or a n-channel mos. ? for a p-channel mos, the gate is controlled directly from pin 28 through a capacitor (this allows to spare a transformer). in this case, a negative-going pulse is needed to make the mos conductive. therefore it is necessary to invert the control signal. ? for a n-channel mos, a transformer is needed to control the gate. the polarity of the transformer can be easily adapted to the negative-going control pulse.
STV6886 33/43 figure 18. dc/dc converter (represented: step-up configuration) b + inhibit. dac 7bits i adjust 8.2v horizontal dynamic focus sawtooth + - c1 + - c2 + - c3 + - c4 6v 1.3v 1.3v 1/3 + - 85 db a 5v 20% regin comp i sense STV6886 16 14 15 28 1m w 22k w ehv feedback v b+ l command step-up/down down up s r q down up bout 12v hdf discharge 400ns 10nf
STV6886 34/43 internal schematics figure 19. figure 20. figure 21. figure 22. figure 23. figure 24. pins 1-2 h/hvin vsyncin 5v 20 k w 200 w hmoire/hlock 3 12v pll2 4 12v 13 href 12v href 13 5 co r0 6 12v href 13 13 href pll1f 7
STV6886 35/43 figure 25. figure 26. figure 27. figure 28. figure 29. figure 30. href 12v hposition 8 href 12v 13 hfocus cap 9 hfocus 10 12v 12v 12v hfly 12 13 href comp 14 regin 15 12v
STV6886 36/43 figure 31. figure 32. figure 33. figure 34. figure 35. figure 36. i sense 16 12v 12v breath 18 vagccap 12v 20 vcap 22 12v vout 23 12v ewout 24 12v
STV6886 37/43 figure 37. figure 38. figure 39. 12v xray 25 v12 hout-bout pins 26-28 pins 30-31 sda-scl
STV6886 38/43 figure 40. demonstration board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 h/hv in vsyn cin hmoire/ hlock pll2c c0 r0 pll1f h hfocus- cap focus out hgnd hfly hr ef comp regin i sense +5v sda scl v cc b+out gnd hout xray ewout vout v cap v ref vagccap vgnd bre ath b+gnd position tp1 j11 tp13 tp17 j1 2 tp16 tp10 c7 22nf c28 820pf 5% r23 6.49k w 1% c1 3 10nf c31 4.7 m f r36 1 .8k w c1 7 1 m f c34 820pf 5% hr ef c3 3 10 0nf c27 47 m f c46 1nf r50 1m w c51 100nf jp1 r57 82 k w r51 1k w i sense gnd b+out regin c47 1 00pf r58 10 w +12v c6 0 10 0nf r77 15k w r74 10k w r73 1m w r75 10k w tp8 eht comp r76 47k w p1 10k w c on4 j19 1 2 3 4 dyn focus r24 10k w l 47m h r25 1k w j9 hfly j8 c22 33pf r8 10k w hou t c25 33pf r1 0 10k w r35 10k w +12v pc2 47k w cc4 47pf +12v cc1 100nf cc 2 10 m f +12v cc3 47pf pc1 47k w -12v 1 234 5678 9 10 11 12 13 14 15 16 v cc tb1 tb2 cdb ib qb qb ib ta1 ta2 cda ia ia qa qa gnd icc1 mc1 4528 c50 10 m f l3 22 m h q4 bc557 q5 bc547 c2 10 0nf c3 47 m f 470nf c15 c12 150nf +12v r52 3 .9k w r45 33 k w r7 10 k w c49 100nf hout c48 10 m f r53 1k w +12 v r56 560k w d2 1n4148 +12v c5 100 m f c6 100nf c30 100 m f c32 100nf l1 22 m h +5v j16 j15 +5v r39 4.7k w r29 4.7k w r42 100 w j14 12 34 c39 22pf c40 22pf r41 100 w scl sda c38 33pf c45 10 m f r49 22k w +5v ic3-stv9422 tilt j13 r43 10k w c42 1 m f r30 10k w +5v c4 3 47 m f c37 33pf x1 8mhz 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 18 19 20 21 22 23 24 pwm4 pwm5 scl sda rst gnd r g b test pwm6 pwm7 pwm3 pwm2 xtalin xtalout ckout pxck v dd hsync vsync fblk pwm1 pwm0 e/w power stage r38 2.2 w 3w j1 e/w r19 270k w c11 220pf q3 tip122 r18 10k w r33 4 .7k w r9 47 0 w r3 4 1k w q1 bc557 q2 bc557 r37 27k w r15 1k w r17 43k w c36 1 m f +12v j2 j3 j6 1 2 3 j18 vyoke r11 220 w 0.5w r4 1 w 0.5w r5 5.6 w +12v -12 v tp3 tp4 tp6 tp7 c9 100nf c14 470 m f c10 100 m f 35v d1 1n400 1 -12v c10 470 m f c8 100nf c1 2 20nf r3 1.5 w c4 100nf r2 5.6 w ic1 tda817 2 r40 36k w r1 12k w c41 470pf vertic al deflec tion stage j17 hou t c 16 (*) STV6886 ic4
STV6886 39/43 figure 41.
STV6886 40/43 figure 42.
STV6886 41/43 package mechanical data
STV6886 42/43 package mechanical data 32 pins - plastic shrink dimensions millimeters inches min. typ. max. min. typ. max. a 3.556 3.759 5.080 0.140 0.148 0.200 a1 0.508 0.020 a2 3.048 3.556 4.572 0.120 0.140 0.180 b 0.356 0.457 0.584 0.014 0.018 0.023 b1 0.762 1.016 1.397 0.030 0.040 0.055 c .203 0.254 0.356 0.008 0.010 0.014 d 27.43 27.94 28.45 1.080 1.100 1.120 e 9.906 10.41 11.05 0.390 0.410 0.435 e1 7.620 8.890 9.398 0.300 0.350 0.370 e 1.778 0.070 ea 10.16 0.400 eb 12.70 0.500 l 2.540 3.048 3.810 0.100 0.120 0.150 ea eb e1 e d 32 17 16 1 stand-off e b1 b a2 a1 a l c
STV6886 43/43 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this public ation are subject to change witho ut notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics. ? 2000 stmicroelectronics - all rights reserved purchase of i 2 c components of stmicroelectronics, conveys a license under the philip s i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philip s. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www .st.com

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