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1 features ? full compliance with usb spec rev 1.1 four downstream ports full-speed and low-speed data transfers bus-powered controller bus-powered or self-powered hub operation port overcurrent monitoring port power switching 5v operation with on-chip 3.3v regulator 24-pin soic description the at43301 is a 5-port usb hub chip supporting one upstream and four down- stream ports. the at43301 connects to an upstream hub or host/root hub via port0, while the other ports connect to external downstream usb devices. the hub re-trans- mits the usb differential signal between port0 and ports[1:4] in both directions. the at43301 is designed for very low-cost bus-powered or self-powered hub applications and comes in a 24-pin soic package. the at43301 supports the 12 mb/s full speed as well as 1.5 mb/s slow speed usb transactions. to reduce emi, the at43301?s oscillator frequency is 6 mhz even though some internal circuitry operates at 48 mhz. low-cost usb hub controller at43301 rev. 1137c ? 08/99 pin configurations top view 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vcc vss cext1 osc1 osc2 lft stat pwr ovc lpstat test self/bus nc dp4 dm4 dp3 dm3 dp2 dm2 dp1 dm1 dp0 dm0 vss
at43301 2 the at43301 consists of a serial interface engine, a hub repeater, and a hub controller. the serial interface engine ? s tasks are: manage the usb communication protocol usb signaling detection/generation clock/data separation, data encoding/decoding, crc generation/checking data serialization/deserialization the hub repeater is responsible for: providing upstream connectivity between the selected device and the host managing connectivity setup and tear-down handling bus fault detection and recovery detecting connect/disconnect on each port the hub controller is responsible for: hub enumeration providing configuration information to the host providing status of each port to the host controlling each port per host command managing port power supply block diagram figure 1. note: this document assumes that the reader is familiar with the universal serial bus and therefore only describes the unique features of the at43301 chip. for detailed information about the usb and its operation, the reader should refer to the universal serial bus specification version 1.1, september 23, 1998. hub controller serial interface engine hub repeater endpoint 0 endpoint 1 port 1 port 2 port 3 port 4 to downstream devices upstream port port 0
at43301 3 pin assignment type: i= input is = input, schmitt trigger o= output od = output, open drain b = bi-directional v = power supply, ground table 1. pin assignment in numerical order pin# signal type 1vcc v 2 vss v 3 cext1 o 4osc1 i 5osc2 o 6lft i 7stat od 8pwr od 9ovc is 10 lpstat is 11 test i 12 self/bus is 13 vss v 14 dm0 b 15 dp0 b 16 dm1 b 17 dp1 b 18 dm2 b 19 dp2 b 20 dm3 b 21 dp3 b 22 dm4 b 23 dp4 b 24 nc - table 2. pin assignment in alphabetical order pin# signal type 3 cext1 o 14 dm0 b 16 dm1 b 18 dm2 b 20 dm3 b 22 dm4 b 15 dp0 b 17 dp1 b 19 dp2 b 21 dp3 b 23 dp4 b 6lft i 10 lpstat is 24 nc - 4osc1 i 5osc2 o 9ovc is 8pwr od 12 self/bus is 7stat od 11 test i 1vcc v 2 vss v 13 vss v
at43301 4 functional description summary the atmel at43301 usb hub controller chip contains vari- ous features that makes it the ideal solution for very low- cost usb hubs. these features are: on-chip regulator, low- frequency oscillator, bus or self-powered operation, ganged port power switching and global overcurrent pro- tection. such a hub can be a stand-alone hub used with portable computers to allow convenient connectivity to standard desktop peripheral devices. alternatively, the hub can be added to an existing non-usb peripheral such a keyboard. the at43301 provides 4 downstream usb ports and can operate in a self-powered or bus-powered mode. usb ports the at43301 ? s upstream port, port0, is a full speed port. a 1.5 k ? pull-up resistor to the 3.3v regulator output, cext, is required for proper operation. the downstream ports support both full-speed as well as low-speed devices. 15 k ? pull down resistors are required at their inputs. full speed signal requirements demand controlled rise/fall times and impedance matching of the usb ports. to meet these requirements, 22 ? resistors must be inserted in series between the usb data pins and the usb connectors. table 3. signal descriptions cext1 o external capacitor. for proper operation of the on-chip regulator, a 0.27 f capacitor must be connected to cext1. dp0 b upstream plus usb i/o. this pin should be connected to the cext1 pin through an external 1.5 k ? pull-up resistor. dp0 and dm0 form the differential signal pin pairs connected to the usb host controller or an upstream hub. dm0 b upstream minus usb i/o. dp[1:4] b port plus usb i/o. this pin should be connected to vss through an external 15 k ? resistor. dp[1:4] and dm[1:4] are the differential signal pin pairs to connect downstream usb devices. dm[1:4] b port minus usb i/o. this pin should be connected to vss through an external 15 k ? resistor. lft i pll filter. for proper operation of the pll, this pin should be connected through a 2.2 nf capacitor in parallel with a 100 ? resistor in series with a 10 nf capacitor to ground (vss). lpstat i local power status. schmitt trigger input pin that is used in the self-powered mode to indicate the condition of the local power supply. this pin should be connected to the local power supply through a 100 k ? resistor. osc1 i oscillator input. input to the inverting 6 mhz oscillator amplifier. osc2 o oscillator output. output of the inverting oscillator amplifier. ovc i port overcurrent. this is the schmitt trigger input signal used to indicate to the at43301 that there is a power supply problem with the ports. if ovc is asserted, the at43301 will de-assert pwr and report the status to the usb host. pwr o power switch. this is an output signal to enable or disable the external port power switch for the port power supply. pwr is de-asserted when an overcurrent is detected at ovc. self/bus i power mode. schmitt trigger input pin to set power mode of hub. if high, the at43301 works in the self-powered mode. if low, the bus-powered mode. stat o status. output pin which is asserted by the at43301 whenever it is enumerated. stat is de-asserted when the hub enters the suspend state. an led in series with a resistor can be connected to this pin to provide visual feedback to the user. test i test. this pin has an internal pull up and should be left unconnected in the normal operating mode. vcc v 5v power supply from the usb. vss v ground. nc - no connect. this pin should be left unconnected.
at43301 5 hub repeater the hub repeater is responsible for port connectivity setup and teardown. it also supports exception handling such as bus fault detection and recovery, and connect/disconnect detection. port0 is the root port and is connected to the root hub or an upstream hub. when a packet is received at port0, the at43301 propagates it to all the enabled down- stream ports. conversely, a packet from a downstream port is transmitted from port0. the at43301 supports downstream port data signaling at both 1.5 mb/s and 12 mb/s. devices attached to the down- stream ports are determined to be either full speed or low speed depending which data line (dp or dm) is pulled high. if a port is enumerated as low speed, its output buffers operate at a slew rate of 75-300 ns, and the at43301 will not propagate any traffic to that port unless it is prefaced with a preamble pid. low speed data following the pream- ble pid is propagated to both low- and full-speed devices. the at43301 will enable low-speed drivers within four full- speed bit times of the last bit of a preamble pid, and will disable them at the end of an eop. the upstream traffic from all ports is propagated by port0 using the full speed 4- 20ns slew rate drivers. all the at43301 ports independently drive and monitor their dp and dm pins so that they are able to detect and generate the ? j ? , ? k ? , and se0 bus signaling states. each hub port has single-ended and differential receivers on its dp and dm lines. the ports ? i/o buffers comply with the voltage levels and drive requirements as specified in the usb specifications rev 1.0. the hub repeater implements a frame timer which is timed by the 12 mhz usb clock and gets reset every time an sof token is received from the host. serial interface engine the serial interface engine handles the usb communica- tion protocol. it performs the usb clock/data separation, the nrzi data encoding/decoding, bit stuffing, crc gener- ation and checking, usb packet id decoding and genera- tion, and data serialization and de-serialization. the on- chip phase locked loop generates the high frequency clock for the clock/data separation circuit. power management a hub is allowed to draw up to 500 ma of power from the host or upstream hub. the at43301 ? s itself and its external circuitry typically consume about 24 ma. therefore, in the bus-powered mode, 100 ma is available for each of the hub ? s downstream devices. in the self-powered mode, an external power supply is required which must be capable of supplying 500 ma per port. the power supplied to the ports is monitored and controlled by the at43301. the at43301 reports overcurrent on a global basis. the overcurrent signal, which needs to be detected by an exter- nal device, is read through the ovc pin. a logic low at ovc is interpreted as an overcurrent condition. this could be caused by an overload, or a short circuit, and causes the at43301 to set the over-current indicator bit of the hub status field, whubstatus, as well as the over-current indi- cator change bit of the hub change field, whubchange. at the same time, power to the ports is switched off by de- asserting pwr . an external device is needed to perform the actual switch- ing of the ports ? power under control of the at43301. the signal to control the external switch is the pwr pin which is an open drain signal and requires an external pull-up resis- tor. 47 k ? is a typical value for this resistor. any type of suitable switch or device is acceptable. however, the switch should have a low-voltage drop across it even when the port absorbs full power. in its simplest form, this switch can be a high side mosfet switch. the advantage of using a mosfet switch is its very low-voltage drop. the power control pin, pwr , is asserted only when a set- portfeature[port-power] request is received from the host. pwr is de-asserted under the following conditions: 1. power up 2. reset and initialization 3. overcurrent condition 4. requested by the host though a clearportfea- ture[port_power] for all the ports self-powered mode in the self-powered mode, power to the downstream ports must be supplied by an external power supply. this power supply must be capable of supplying 500 ma per port or 2a total with good voltage tolerance and regulation. at full hub operating power, that is all downstream ports drawing 500 ma each, the minimum voltage at the downstream port connector must be 4.75v. the usb specification requires that the voltage drop at the power switch and board traces be no more than 100 mv. a good conservative maximum drop at the power switch itself should be no more than 75 mv. careful design and selec- tion of the power switch and pc board layout is required to meet the specifications. when using a mosfet switch, its resistance must be 40 m ? or less under worst case condi- tions. a suitable mosfet switch for an at43301 based hub is an integrated highside mosfet switch such as the micrel mic2505.
at43301 6 bus-powered mode in the bus-powered mode all the power for the hub itself as well as the downstream ports is supplied by the root hub or upstream hub through the usb. only 100 ma is available for each of the hub ? s downstream devices and therefore only low-power devices are supported. the power switch works exactly like the self-powered mode, except that the allowable switch resistance is higher: 140 m ? or less under the worst case condition. an exam- ple of a suitable high side switch for a bus-powered hub is the micrel mic2525. the diagrams of figure 2 and figure 3 show examples of the power supply and power management scheme in the self-powered mode and bus-powered mode using an inte- grated switch with built-in overcurrent protection. figure 2. bus-powered hub figure 3. self-powered hub bus_power gnd gnd vcc at43301 pwr ovc u1 ctl flg in out switch u2 port_power gnd port_power gnd port_power gnd port_power gnd to downstream devices bus_power gnd gnd vcc at43301 pwr ovc u1 ctl flg in out switch u2 port_power gnd port_power gnd port_power gnd port_power gnd to downstream devices power supply 5v out gnd ps5
at43301 7 hub controller the hub controller of the at43301 provides the mecha- nism for the host to enumerate the hub and the at43301 to provide the host with its configuration information. it also provides a mechanism for the host to monitor and control the downstream ports. the hub controller supports two endpoints, endpoint0 and endpoint1. the hub controller maintains a status register, controller status register, which reflects the at43301 ? s current set- tings. at power up, all bits in this register will be set to 0 ? s. endpoint 0 endpoint 0 is the at43301 ? s default endpoint used for enu- meration of the hub and exchange of configuration informa- tion and requests between the host and the at43301. endpoint 0 supports control transfers. the hub controller supports the following descriptors through endpoint 0: device descriptor, configuration descriptor, interface descriptor, endpoint descriptor, and hub descriptor. these descriptors are described in detail elsewhere in this document. standard usb device requests and class-specific hub requests are also sup- ported through endpoint 0. there is no endpoint descriptor for endpoint0. endpoint 1 endpoint1 is used by the hub controller to send status change information to the host. this endpoint supports interrupt transfers. the hub controller samples the changes at the end of every frame at time marker eof2 in preparation for a potential data transfer in the subsequent frame. the sam- pled information is stored in a byte wide register, the status change register, using a bitmap scheme. each bit in the status change register corresponds to one port as shown below: table 4. controller status register bit function value description 0 hub configuration status 0 1 set to 0 or 1 by a set_configuration request hub is not currently configured hub is currently configured 1 hub remote wakeup status 0 1 set to 0 or 1 by clearfeature or setfeature request. default value is 0. hub is currently not enabled to request remote wakeup hub is currently enabled to request remote wakeup 2 endpoint0 stall status 0 1 endpoint0 is not stalled endpoint0 is stalled 3 endpoint1 stall status 0 1 endpoint1 is not stalled endpoint1 is stalled table 5. status change register bit function value meaning 0 hub status change 0 1 no change in status change in status detected 1 port1 status change 0 1 no change in status change in status detected 2 port2 status change 0 1 no change in status change in status detected 3 port3 status change 0 1 no change in status change in status detected 4 port4 status change 0 1 no change in status change in status detected 5-7 reserved 000 default values
at43301 8 an in token packet from the host to endpoint 1 indicates a request for port change status. if the hub has not detected any change on its ports, or any changes in itself, then all bits in this register will be 0 and the hub controller will return a nak to requests on endpoint1. if any of bits 0-4 is 1, the hub controller will transfer the whole byte. the hub controller will continue to report a status change when polled until that particular change has been removed by a clearportfeature request from the host. no status change will be reported by endpoint 1 until the at43301 has been enumerated and configured by the host. oscillator and phase-locked-loop all the clock signals required to run the at43301 are derived from an on-chip oscillator. to reduce emi and power dissipation in the system, the at43301 is designed to operate with a 6 mhz crystal. an on-chip pll generates the high frequency for the clock/data separator of the serial interface engine. in the suspended state, the oscillator cir- cuitry is turned off. to assure quick startup, a crystal with a high q, or low esr, should be used. to meet the usb hub frequency accuracy and stability requirements for hubs, the crystal should have an accuracy and stability of better than 100 ppm. even though the oscillator circuit would work with a ceramic resonator, its use is not recommended because a resonator would not have the frequency accuracy and stability. a 6 mhz series resonance quartz crystal with a load capac- itance of approximately 10 pf is recommended. the oscil- lator is a special low-power design and in most cases no external capacitors and resistors are necessary. if the crys- tal used cannot tolerate the drive levels of the oscillator, a series resistor between osc2 and the crystal pin is recom- mended. status pin the status pin, stat , is provided to allow feedback to the user. if an led and a series resistor is connected between stat and vcc, the led will light when the hub is enumer- ated. during an overcurrent condition, the led will blink. it will continue to blink until the host turns off the power to the ports or until the hub is re-enumerated. figure 4. external oscillator and pll circuit the clock can also be externally sourced. in this case, con- nect the clock source to the osc1 pin, while leaving osc2 pin floating. the switching level at the osc1 pin can be as low as 0.47v (see ? electrical specification ? on page 9) and a cmos device is required to drive this pin to maintain good noise margins at the low switching level. for proper operation of the pll, an external rc filter con- sisting of a series rc network of 100 ? and 10 nf in parallel with a 2 nf capacitor must be connected from the lft pin to v ss . power supply the at43301 is powered from the usb bus, but has an internal voltage regulator to supply the 3.3v operating power to its circuitry. for proper operation, an external high quality, low esr, 0.27 f, or larger, capacitor should be connected to the output of the regulator, cext1 and ground. the cext1 pin can also be used to supply the voltage to the 1.5 k ? pull up resistor at port 0 ? s dp pin. to provide the best operating condition for the at43301, careful consideration of the power supply connections are recommended. use short, low impedance connections to all power supply lines: v cc and v ss . use sufficient decou- pling capacitance to reduce noise: 0.1 f of high quality ceramic capacitor soldered as close as possible to the vcc and vss package pins are recommended. at43301 osc1 osc2 lft y1 6.000 mhz r1 100 c1 10nf c2 2nf u1
at43301 9 electrical specification *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics the values shown in this table are valid for t a = 0 c to 85 c, v cc = 4.4v to 5.25v, unless otherwise noted. absolute maximum ratings* symbol parameter condition min max unit v cc5 5v power supply 5.5 v v i dc input voltage -0.3v v cext + 0.3 4.6 max v v o dc output voltage -0.3 v cext + 0.3 4.6 max v t o operating temperature -40 +125 c t s storage temperature -65 +150 c table 6. power supply symbol parameter condition min max unit v cc 5v power supply 4.4 5.25 v i cc 5v supply current 24 ma i ccs suspended device current 150 a table 7. usb signals: dpx, dmx symbol parameter condition min max unit v ih input level high (driven) 2.0 v v ihz input level high (floating) 2.7 3.6 v v il input level low 0.8 v v di differential input sensitivity dpx and dmx 0.2 v v cm differential common mode range 0.8 2.5 v v ol1 static output low r l of 1.5 k ? to 3.6v 0.3 v v oh1 static output high r l of 15 k ? to gnd 2.8 3.6 v v crs output signal crossover 1.3 2.0 v c in input capacitance 20 pf
at43301 10 note: osc2 must not be used to drive other circuitry. ac characteristics note: 1. with external 22 ? series resistor. table 8. pwr , stat , ovc symbol parameter condition min max unit v ol2 output low level, pwr , stat i ol = 4 ma 0.5 v c out output capacitance 1 mhz 10 pf v il3 input low level 0.3v cext v v ih3 input high level 0.7v cext v c out output capacitance 1 mhz 10 pf v oh2 output high level, pwr i oh = 4 ma v cext - 0.5 v table 9. oscillator signals: osc1, osc2 symbol parameter condition min max unit v lh osc1 switching level 0.47 1.20 v v hl osc1 switching level 0.67 1.44 v c x1 input capacitance, osc1 17 pf c x2 output capacitance, osc2 17 pf c 12 osc1/2 capacitance 1pf tsu start-up time 6 mhz, fundamental 2 ms d l drive level v cc = 3.3v, 6 mhz crystal, 100 ? equiv series resistor 150 w table 10. dpx, dmx driver characteristics, full speed operation symbol parameter condition min max unit t r rise time c l = 50 pf 4 20 ns t f fall time c l = 50 pf 4 20 ns t rfm t r /t f matching 90 110 % z drv driver output resistance (1) steady state drive 28 44 ?
at43301 11 note: 1. with 6.000 mhz, 100 ppm crystal. table 11. dpx, dmx source timings, full speed operation symbol parameter condition min max unit t drate full speed data rate (1) average bit rate 11.97 12.03 mb/s t frame frame interval (1) 0.9995 1.0005 ms t rfi consecutive frame interval jitter (1) no clock adjustment 42.0 ns t rfiadj consecutive frame interval jitter (1) with clock adjustment 126.0 ns t dj1 t dj2 source diff driver jitter to next transition for paired transitions -3.5 -4.0 3.5 4.0 ns ns t fdeop source jitter for differential transition to seo transitions -2.0 5.0 ns t jr1 t jr2 recvr data jitter tolerance to next transition for paired transitions -18.5 -9.0 18.5 9.0 ns ns t feopt source seo interval of eop 160.0 175.0 ns t feopr receiver seo interval of eop 82.0 ns t fst width of seo interval during differential transition 14.0 ns table 12. dpx, dmx driver characteristics, low-speed operation symbol parameter condition min max unit t r rise time c l = 200 - 600 pf 75.0 300.0 ns t f fall time c l = 200 - 600 pf 75.0 300.0 ns t rfm t r /t f matching 80.0 125.0 % table 13. dpx, dmx hub timings, high-speed operation symbol parameter condition min max unit t hdd2 hub differential data delay without cable 44.0 ns t hdj1 t hdj2 hub diff driver jitter to next transition for paired transitions -3.0 -1.0 3.0 1.0 ns ns t fsop data bit width distortion after sop -5.0 5.0 ns t feopd hub eop delay relative to t hdd 015.0ns t fhesk hub eop output width skew -15.0 15.0 ns
at43301 12 table 14. dpx, dmx hub timings, low-speed operation symbol parameter condition min max unit t lhdd hub differential data delay 300.0 ns t lhdj1 t lhdj2 t luhj1 t luhj2 downstr hub diff driver jitter to next transition, downst for paired transitions, downst to next transition, upstr for paired transitions, upstr -45.0 -15.0 -45.0 -45.0 45.0 15.0 45.0 45.0 ns ns ns ns t sop data bit width distortion after sop -60.0 60.0 ns t leopd hub eop delay relative to t hdd 0 200.0 ns t lhesk hub eop output width skew -300.0 300.0 ns table 15. hub event timings symbol parameter condition min max unit t dcnn time to detect a downstream port connect event awake hub suspended hub 2.5 2.5 2000.0 12000.0 s s t ddis time to detect a disconnect event on downstream port awake hub suspended hub 2.5 2.5 2.5 10000.0 s s t ursm time from detecting downstream resume to rebroadcast 100.0 s t drst duration of driving reset to a downstream device only for a setportfeature (port_reset) request 10.0 20.0 ms t urlk time to detect a long k from upstream 2.5 100.0 s t urlseo time to detect a long seo from upstream 2.5 10000.0 s t urpseo duration of repeating seo upstream 23 fs bit time
at43301 13 timing waveforms figure 5. data signal rise and fall time figure 6. full-speed load figure 7. low-speed downstream port load figure 8. differential data jitter v crs rise time fall time differential data lines 10% 90% 90% 10% t r t f txd+ txd- r s c l r s c l c l = 50pf txd+ txd- r s c l r s c l c l = 200pf to 600pf 3.6v 1.5k ? t period crossover points differential data lines consecutive transitions n*t period +t xjr1 paired transitions n*t period +t xjr2
at43301 14 figure 9. differential-to-eop transition skew and eop width figure 10. receiver jitter tolerance figure 11. hub differential delay, differential jitter, and sop distortion t period crossover point extended differential data lines diff. data-to- se0 skew n*t period +t deop source eop width: t feopt t leopt receiver eop width: t feopr, t leopr t period differential data lines consecutive transitions n*t period +t jr1 t jr t jr1 t jr2 consecutive transitions n*t period +t jr1 crossover point differential data lines a. downstream hub delay with cable 50% point of initial swing upstream end of cable hub delay downstream t hdd1 crossover point downstream port crossover point hub delay upstream t hdd2 upstream port v ss v ss v ss v ss b. upstream hub delay without cable crossover point downstream port crossover point hub delay upstream t hdd1, t hdd2 upstream port or end of cable v ss v ss c. upstream hub delay with or without cable
at43301 15 hub differential jitter: t hdj1 = t hddx (j) - t hddx (k) or t hddx (k) - t hddx (j) consecutive transitions t hdj2 = t hddx (j) - t hddx (j) or t hddx (k) - t hddx (k) paired transitions bit after sop width distortion (same as data jitter for sop and next j transition): t sop = t hddx (nextj) - t hddx (sop) low-speed timings are determined in the same way for: t lhdd , t ldhj1 , t ldjh2 , t luhj1 , t lujh2 , and t lsop figure 12. hub eop delay and eop skew eop delay: t eopd = t eop - t hddx eop skew: t hesk = t eop + -t eop- low-speed timings are determined in the same way for: t leopd and t lhesk crossover point extended downstream port a. downstream eop delay with cable 50% point of initial swing upstream end of cable upstream port v ss v ss v ss v ss b. downstream eop delay without cable downstream port upstream port or end of cable v ss v ss c. upstream eop delay with or without cable t eop- t eop+ crossover point extended downstream port t eop- t eop+ crossover point extended crossover point extended t eop- t eop+ crossover point extended
at43301 16 schematic diagrams the following pages shows schematic diagrams of an at43301 based bus-powered hub and self-powered hub. figure 13. bus-powered hub vbus dm1 dp1 dm2 dp2 dm3 dp3 dm4 dp4 pwr ovc vbus y1 6.000mhz r1 22 r2 22 r4 100 c2 0.01uf c3 2.2nf r3 1.5k l1 fb r7 22 r8 22 r9 22 r10 22 r11 22 r12 22 r13 22 r14 22 r5 470 d1 led + c12 4.7uf rp1 15k 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 c1 0.27uf usb-b jp1 4 3 2 1 5 6 r16 47k u1 at43301 14 15 16 17 18 19 20 21 22 23 13 2 4 5 1 3 6 8 9 10 11 7 12 24 dm0 dp0 dm1 dp1 dm2 dp2 dm3 dp3 dm4 dp4 vss vss osc1 osc2 vcc cext lft pwr ovc lpstat test stat self/bus nc d2 1n4148 l11 fb
at43301 17 figure 14. bus-powered hub vbus vbus pwr ovc dp1 dm2 dm4 dm1 dp2 dm3 dp3 dp4 + c8 47uf + c9 47uf + c10 47uf + c11 47uf u2 mic2525-2 1 2 3 7 8 5 6 4 en flg gnd in out nc out nc jp3 usb-2a 1 2 3 4 5 6 7 8 9 10 11 12 l13 fb l4 fb c5 0.1uf l2 fb c4 0.1uf l12 fb l3 fb c6 0.1uf jp2 usb-2a 1 2 3 4 5 6 7 8 9 10 11 12 c7 0.1uf l15 fb l5 fb l14 fb
at43301 18 figure 15. self-powered hub vbus vlocal dm1 dp1 dm2 dp2 dm3 dp3 dm4 dp4 pwr ovr y1 6.000mhz r1 22 r2 22 r4 100 c2 0.01uf c3 2.2nf r3 1.5k l1 fb c1 0.27uf r7 22 r8 22 r9 22 r10 22 r11 22 r12 22 r13 22 r14 22 r6 47k d1 led usb-b jp1 4 3 2 1 5 6 rp1 15k 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 r16 47k q1 2n4401 u1 at43301 14 15 16 17 18 19 20 21 22 23 13 2 4 5 1 3 6 8 9 10 11 7 12 24 dm0 dp0 dm1 dp1 dm2 dp2 dm3 dp3 dm4 dp4 vss vss osc1 osc2 vcc cext lft pwr ovc lpstat test stat self/bus nc r35 470 r5 470 l11 fb
at43301 19 figure 16. self-powered hub vlocal pwr ovc dp4 dm3 dp1 dp3 dm1 dm2 dp2 dm4 + c8 100 uf + c9 100 uf + c10 100 uf + c11 100 uf u2 mic2505-2 1 2 3 5 6 7 8 4 ctl flg gnd in out in out gate j1 con2 1 2 + 4.7 uf c15 0.1 uf c14 jp2 usb-2a 1 2 3 4 5 6 7 8 9 10 11 12 l5 fb c4 0.1uf l3 fb l12 fb c6 0.1uf l2 fb l15 fb l14 fb c7 0.1uf l13 fb jp3 usb-2a 1 2 3 4 5 6 7 8 9 10 11 12 c5 0.1uf l4 fb
at43301 20 packaging information .020(.508) .013(.330) .299(7.60) .291(7.39) .420(10.7) .393(9.98) .105(2.67) .092(2.34) .050(1.27) bsc .616(15.6) .598(15.2) .012(.305) .003(.076) .013(.330) .009(.229) .050(1.27) .015(.381) 8 0 ref pin 1 id 24s, 24-lead, 0.300" wide plastic gull wing small outline package (soic) dimensions in inches and (millimeters)
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