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asahi kasei [AK5365] ms0164-e-01 2002/08 - 1 - general description AK5365 is a high-performance 24-bit, 96khz sampling adc for consumer audio and digital recording applications. thanks to akm?s enhanced dual-bit modulator architecture, this analog-to-digital converter has an impressive dynamic range of 103db with a high level of integration. the AK5365 has a 5-channel stereo input selector, an input programmable gain amplifier with an alc function. all this integration with high-performance makes the AK5365 well suited for cd and dvd recording systems. features 1. 24bit stereo adc ? 5ch stereo inputs selector ? input pga from +12db to 0db, 0.5db step ? auto level control (alc) circuit ? digital hpf for offset cancellation (fc=1.0hz@fs=48khz) ? digital attenuator ? soft mute ? single-end inputs ? s/(n+d) : 94db ? dr, s/n : 103db ? audio i/f format : 24bit msb justified, i 2 s 2. 3-wire serial p interface / i 2 c-bus 3. master / slave mode 4. master clock : 256fs/384fs/512fs 5. sampling rate : 32khz to 96khz 6. power supply ? avdd: 4.75 5.25v (typ. 5.0v) ? dvdd: 3.0 5.25v (typ. 3.3v) 7. power supply current : 27ma 8. ta = -40 85 c 9. package : 44pin lqfp 24-bit 96khz ? adc with selector/pg a/alc AK5365
asahi kasei [AK5365] ms0164-e-01 2002/08 - 2 - ? block diagram lin1 lin2 lin3 lin4 lin5 rin1 rin2 rin3 rin4 rin5 adc hpf audio i/f controller ipgal ropin rout ipgar control register i/f csn cad1 cclk scl cdti sda lrck bick mclk sdto avss avdd dvss dvdd lopin m/s sel2 sel1 sel0 pdn lout alc ipga ipga datt ctrl (alc) (alc) smute pre-amp pre-amp vcom block diagram
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 3 - ? ordering guide AK5365vq ? 40 +85 c 44pin lqfp (0.8mm pitch) akd5365 evaluation board for AK5365 ? pin layout lin5 rin5 44 43 1 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 2 3 4 5 6 7 8 9 10 11 AK5365vq top view test1 lin4 test2 lin3 test3 lin2 test4 lin1 lopin lout ipgal ipgar rout ropin avdd avss vcom dvss dvdd sdto bick lrck mclk pdn alc smute sel0 sel1 sel2 cdti/sda cclk/scl csn/cad1 test8 rin4 test7 rin3 test6 rin2 test5 rin1 m/s ctrl
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 4 - pin/function no. pin name i/o function 1 lin5 i lch analog input 5 pin 2 test1 i test 1 pin (connected to avss) 3 lin4 i lch analog input 4 pin 4 test2 i test 2 pin (connected to avss) 5 lin3 i lch analog input 3 pin 6 test3 i test 3 pin (connected to avss) 7 lin2 i lch analog input 2 pin 8 test4 i test 4 pin (connected to avss) 9 lin1 i lch analog input 1 pin 10 lopin i lch feed back resistor input pin 11 lout o lch feed back resistor output pin 12 ipgal i lch ipga input pin 13 ipgar i rch ipga input pin 14 rout o rch feed back resistor output pin 15 ropin i rch feed back resistor input pin 16 avdd - analog power supply pin, 4.75 5.25v 17 avss - analog ground pin 18 vcom o common voltage output pin, avdd/2 bias voltage of adc input. 19 dvss - digital ground pin 20 dvdd - digital power supply pin, 3.0 5.25v 21 sdto o audio serial data output pin 22 bick i/o audio serial data clock pin note: all digital input pins except pull-down pins should not be left floating. note: test1, test2, test3 and test4 pins should be connected to avss.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 5 - no. pin name i/o function 23 lrck i/o output channel clock pin 24 mclk i master clock input pin 25 pdn i power-down mode pin ?h?: power up, ?l?: power down reset and initializes the control register. 26 alc i alc enable pin (internal pull-down pin, typ. 100k ? ) ?h? : alc enable, ?l? : alc disable 27 smute i soft mute pin (internal pull-down pin, typ. 100k ? ) ?h? : soft mute, ?l? : normal operation 28 sel0 i input selector 0 pin 29 sel1 i input selector 1 pin 30 sel2 i input selector 2 pin cdti i control data input pin in 3-wire control (ctrl pin = ?l?) 31 sda i/o control data input / output pin in i 2 c control (ctrl pin = ?h?) cclk i control data clock pin in 3-wire control (ctrl pin = ?l?) 32 scl i control data clock pin in i 2 c control (ctrl pin = ?h?) csn i chip select pin in 3-wire control (ctrl pin = ?l?) 33 cad1 i chip address 1 select pin in i 2 c control (ctrl pin = ?h?) 34 ctrl i control mode pin ?h? : i 2 c control & i 2 s compatible, ?l? : 3-wire control 35 m/s i master / slave mode pin ?h? : master mode, ?l? : slave mode 36 rin1 i rch analog input 1 pin 37 test5 i test 5 pin (connected to avss) 38 rin2 i rch analog input 2 pin 39 test6 i test 6 pin (connected to avss) 40 rin3 i rch analog input 3 pin 41 test7 i test 7 pin (connected to avss) 42 rin4 i rch analog input 4 pin 43 test8 i test 8 pin (connected to avss) 44 rin5 i rch analog input 5 pin note: all digital input pins except pull-down pins should not be left floating. note: test5, test6, test7 and test8 pins should be connected to avss.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 6 - absolute maximum ratings (avss, dvss=0v; note 1) parameter symbol min max units power supplies: analog digital |avss ? dvss| (note 2) avdd dvdd ? gnd ? 0.3 ? 0.3 - 6.0 6.0 0.3 v v v input current, any pin except supplies iin - 10 ma analog input voltage (vref, lin1-5, rin1-5, lopin, ropin, ipgal, ipgar pins) vina ? 0.3 avdd+0.3 v digital input voltage (all digital input pins) vind ? 0.3 dvdd+0.3 v ambient temperature (powered applied) ta ? 40 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. avss and dvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 1) parameter symbol min typ max units power supplies (note 3) analog digital avdd dvdd 4.75 3.0 5.0 3.3 5.25 avdd v v note 1. all voltages with respect to ground. note 3. the power up sequence between avdd and dvdd is not critical. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 7 - analog characteristics (ta=25 c; avdd=5.0v, dvdd=3.3v; avss=dvss=0v; fs=48khz, 96khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at fs=48khz, 40hz 40khz at fs=96khz; unless otherwise specified) parameter min typ max units pre-amp characteristics: feedback resistance 10 50 k ? s/(n+d) (note 4) - 100 db s/n (a-weighted) - 108 db load resistance (note 5) 6.3 k ? load capacitance 20 pf input pga characteristics: input voltage (note 6) 0.9 1 1.1 vrms input resistance (note 7) 6.3 10 15 k ? step size 0.2 0.5 0.8 db gain control range alc = off alc = on 0 ? 9.5 +12 +12 db db adc analog input characteristics: ipga=0db, alc = off (note 8) resolution 24 bits s/(n+d) ( ? 0.5dbfs) fs=48khz fs=96khz 84 82 94 92 db db dr ( ? 60dbfs) fs=48khz, a-weighted fs=96khz 96 89 103 99 db db s/n fs=48khz, a-weighted fs=96khz 96 89 103 99 db db interchannel isolation (note 9) 90 110 db interchannel gain mismatch 0.2 0.5 db gain drift 100 - ppm/ c power supply rejection (note 10) 50 - db power supplies power supply current normal operation (pdn pin = ?h?) avdd dvdd (fs=48khz) (fs=96khz) power-down mode (pdn pin = ?l?) (note 11) avdd dvdd 23 4 8 10 10 35 8 16 100 100 ma ma ma a a note 4. this value is measured at lout and rout pins using the circuit as shown in figure 24. the input signal voltage is 2vrms. note 5. this value is the input impedance of an external device that the lout and rout pins can drive, when a device is connected with lout and rout pin externally. the feedback resistor (min. 10k ? ) that it is usually connected with the lout/rout pins, and the value of input impedance (min. 6.3k ? ) of the ipgal/r pins are not included. note 6. full scale (0db) of the input voltage at alc=off and ipga=0db. input voltage to ipgal and ipgar pins is proportional to avdd voltage. vin = 0.2 x avdd (vrms). note 7. this value is input impedance of the ipgal and ipgar pins. note 8. this value is measured via the following path. pre-amp ipga (gain : 0db) adc. the measurement circuit is figure 24. note 9. this value is the interchannel isolation between all the channels of the lin1-5 and rin1-5 when the applied input signal causes the pre-amp output to equal ipga input. note 10. psr is applied to avdd and dvdd with 1khz, 50mvpp. note 11. all digital input pins are held dvdd or dvss.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 8 - filter characteristics (fs=48khz) (ta= ? 40 85 c; avdd=4.75 5.25v; dvdd=3.0 5.25v; fs=48khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 12) ? 0.005db ? 0.02db ? 0.06db ? 6.0db pb 0 - - - 21.768 22.0 24.0 21.5 - - - khz khz khz khz stopband sb 26.5 khz passband ripple pr 0.005 db stopband attenuation sa 80 db group delay (note 13) gd 29.6 1/fs group delay distortion ? gd 0 s adc digital filter (hpf): frequency response (note 12) ? 3db ? 0.5db ? 0.1db fr 1.0 2.9 6.5 hz hz hz note 12. the passband and stopband frequencies scale with fs. for example, 21.768khz at ? 0.02db is 0.454 x fs. note 13. the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the setting of 24bit data both channels to the adc output register for adc. filter characteristics (fs=96khz) (ta= ? 40 85 c; avdd=4.75 5.25v; dvdd=3.0 5.25v; fs=96khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 14) ? 0.005db ? 0.02db ? 0.06db ? 6.0db pb 0 - - - 43.536 44.0 48.0 43.0 - - - khz khz khz khz stopband sb 53.0 khz passband ripple pr 0.005 db stopband attenuation sa 80 db group delay (note 15) gd 29.6 1/fs group delay distortion ? gd 0 s adc digital filter (hpf): frequency response (note 14) ? 3db ? 0.5db ? 0.1db fr 2 5.8 13 hz hz hz note 14. the passband and stopband frequencies scale with fs. for example, 43.536khz at ? 0.02db is 0.454 x fs. note 15. the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the setting of 24bit data both channels to the adc output register for adc.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 9 - dc characteristics (ta= ? 40 85 c; avdd=4.75 5.25v; dvdd=3.0 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd - - - - 30%dvdd v v high-level output voltage (iout= ? 400 a) low-level output voltage (except sda pin : iout=400 a) (sda pin : iout=3ma) voh vol vol dvdd-0.5 - - - - - - 0.5 0.4 v v v input leakage current iin - - 10 a switching characteristics (ta= ? 40 85 c; avdd=4.75 5.25v; dvdd=3.0 5.25v; c l =20pf) parameter symbol min typ max units master clock timing frequency pulse width low pulse width high fclk tclkl tclkh 8.192 0.4/fclk 0.4/fclk 24.576 mhz ns ns lrck frequency normal speed mode double speed mode fsn fsd 32 48 48 96 khz khz duty cycle slave mode master mode 45 50 55 % % audio interface timing slave mode bick period bick pulse width low pulse width high lrck edge to bick ? ? (note 16) bick ? ? to lrck edge (note 16) lrck to sdto (msb) (except i 2 s mode) bick ? ? to sdto tbck tbckl tbckh tlrb tblr tlrs tbsd 160 65 65 30 30 35 35 ns ns ns ns ns ns ns master mode bick frequency bick duty bick ? ? to lrck bick ? ? to sdto fbck dbck tmblr tbsd ? 20 ? 20 64fs 50 20 35 hz % ns ns note 17. bick rising edge must not occur at the same time as lrck edge.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 10 - parameter symbol min typ max units control interface timing (3-wire serial mode): cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 17) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp - 4.7 4.0 4.7 4.0 4.7 0 0.25 - - 4.0 0 100 - - - - - - - 1.0 0.3 - 50 khz s s s s s s s s s s ns reset timing pdn pulse width (note 18) pdn ? ? to sdto valid (note 19) pwn ? ? to sdto valid (note 20) tpd tpdv tpdv 150 516 516 ns 1/fs 1/fs note 17. data must be held long enough to bridge the 300ns-transition time of scl. note 18. the AK5365 can be reset by bringing the pdn pin = ?l?. note 19. this cycle is the number of lrck rising edges from the pdn pin = ?h?. note 20. this cycle is the number of lrck rising edges from the pwn bit = ?1?. purchase of asahi kasei microsystems co., ltd i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system, provided the system conform to the i 2 c specifications defined by philips.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 11 - ? timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil clock timing lrck vih vil tblr bick vih vil tlrs sdto 50%dvdd tlrb tbsd audio interface timing (slave mode)
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 12 - lrck bick 50%dvdd sdto 50%dvdd tbsd tmblr dbck 50%dvdd audio interface timing (master mode) csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w write command input timing csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 write data input timing
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 13 - stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp i 2 c bus mode timing tpd pdn vil csn vih vil tpdv sdto 50%dvdd pdn vih vil tpdv sdto 50%dvdd power down & reset timing
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 14 - operation overview ? system clock mclk (256fs/384fs/512fs), bick (48fs ) and lrck (fs) clocks are required in slave mode. the lrck clock input must be synchronized with mclk, however the phase is not critical. mclk frequency is automatically detected in slave mode. table 1 shows the relationship of typical sampling frequency and the system clock frequency. mclk (256fs/384fs/512fs) is required in master mode. mclk frequency is selected by cks1-0 bits as shown in table 2. in master mode, after setting cks1-0 bits, there is a possibility the frequency and duty of lrck and bick outputs become an abnormal state. all external clocks (mclk, bick and lrck) must be present unless pdn pin = ?l? and pwn bit = ?1?. if these clocks are not provided, the AK5365 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the AK5365 in power-down mode (pdn pin = ?l? or pwn bit = ?0?). in master mode, the master clock (mclk) must be provided unless pdn pin = ?l?. mclk fs 256fs 384fs 512fs 32khz 8.192mhz 12.288mhz 16.384mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 48khz 12.288mhz 18.432mhz 24.576mhz 96khz 24.576mhz n/a n/a table 1. system clock example (slave mode) mclk cks1 cks0 32khz fs 48khz 48khz < fs 96khz 0 0 256fs 256fs default 0 1 512fs n/a 1 0 384fs n/a 11 n/a n/a table 2. master clock frequency select (master mode) ? audio interface format two kinds of data formats can be chosen with the dif bit (table 3) and the ctrl pin (table 4). the dif bit and ctrl pin are ored between pin and register. in both modes, the serial data is in msb first, 2?s compliment format. the sdto is clocked out on the falling edge of bick. the audio interface supports both master and slave modes. in master mode, bick and lrck are output with the bick frequency fixed to 64fs and the lrck frequency fixed to 1fs. mode dif bit sdto lrck bick figure 0 0 24bit, msb justified h/l 48fs figure 1 1 1 24bit, i 2 s compatible l/h 48fs figure 2 default table 3. audio interface format (ctrl pin = ?l?) mode ctrl pin sdto lrck bick figure 0 l 24bit, msb justified h/l 48fs figure 1 1 h 24bit, i 2 s compatible l/h 48fs figure 2 table 4. audio interface format (dif bit = ?0?)
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 15 - lrck bick(64fs) sdto(o) 0 23 22 1 2 4 0 20 21 24 31 0 12 23 22 0 1 0 23 22 20 21 31 23:msb, 0:lsb lch data rch data 24 321 22 23 23 1 2 3 4 figure 1. mode 0 timing lrck bick(64fs) sdto(o) 0 23 22 1 2 4 0 25 21 24 0 12 23 22 0 1 0 22 25 21 24 321 22 23 23 1 2 3 4 3 23:msb, 0:lsb lch data rch data figure 2. mode 1 timing ? master mode and slave mode the m/s pin selects either master or slave mode. m/s pin = ?h? selects master mode and ?l? selects slave mode. the AK5365 outputs bick and lrck in master mode. in slave mode, mclk, bick and lrck are input externally. bick, lrck slave mode bick = input lrck = input master mode bick = output lrck = output table 5. master mode/slave mode ? digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 1.0hz (@fs=48khz) and scales with sampling rate (fs).
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 16 - ? power-up/down the AK5365 is placed in the power-down mode by bringing pdn pin = ?l? and the digital filter is also reset at the same time. this reset should always be done after power-up. an analog initialization cycle starts after exiting the power-down mode. therefore, the output data sdto becomes available after 516 cycles of lrck. (1) power-up sequence 1 power supply (1) pdn pin adc internal state ipga sdto pdn inita normal 00h 00h 7fh 7fh ?0? fi output external clocks in slave mode the clocks can be stopped. mclk, lrck, bick external clocks in master mode the clocks can be stopped. mclk bick, lrck in master mode bick, lrck fixed to ?l? - inita : initializing period of adc analog section (516/fs). - fi : fade in. after exiting power down, ipga value fades in. - pdn : power down state. - the period of (1) should be min. 150ns in figure 3. figure 3. power-up sequence 1
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 17 - (2) power-up sequence 2 power supply (1) pdn pin adc internal state ipga sdto pdn inita normal 00h 00h 7fh 7fh ?0? fi output external clocks in slave mode mclk, lrck, bick external clocks in master mode mclk bick, lrck in master mode fixed to ?l? bick, lrck unsettling unsettling unsettling unsettling the clocks can be input. the clocks can be input. mclk mclk, bick, lrck - inita : initializing period of adc analog section (516/fs). - fi : fade in. after exiting power down, ipga value fades in. - pdn : power down state. - the period of (1) should be min. 150ns in figure 4. figure 4. power-up sequence 2
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 18 - ? input selector the AK5365 includes 5ch stereo input selectors (figure 5). the input selector is 5 to 1 selector. the input channel is set by the sel2-0 bits (table 6) and the sel2-0 pins (table 7). the sel2-0 pins should be fixed to ?lll? if the AK5365 is controlled by the sel 2-0 bits, because the setting of the sel2-0 pins are prior to the sel2-0 bits setting. sel2 bit sel1 bit sel0 bit input channel 0 0 0 lin1 / rin1 default 0 0 1 lin2 / rin2 0 1 0 lin3 / rin3 0 1 1 lin4 / rin4 1 0 0 lin5 / rin5 table 6. input selector (sel2-0 pin = ?lll?) sel2 pin sel1 pin sel0 pin input channel l l l lin1 / rin1 l l h lin2 / rin2 l h l lin3 / rin3 l h h lin4 / rin4 h l l lin5 / rin5 table 7. input selector (sel2-0 bit = ?000?) lin1 lin2 lin3 lin4 lin5 rin1 rin2 rin3 rin4 rin5 pre-amp pre-amp figure 5. input selector
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 19 - [input selector switching sequence] the input selector should be changed after soft mute to avoid the switching noise of the input selector (figure 6). 1. enable the soft mute before changing channel. 2. change channel. 3. disable the soft mute. smute attenuation channel datt level - (1) (2) lin1/rin1 lin2/rin2 (1) figure 6. input channel switching sequence example the period of (1) varies in the setting value of datt. it takes 1024/fs to mute when datt value is 0db. when changing channels, the input channel should be changed during (2). the period of (2) should be around 200ms because there is some dc difference between the channels. ? function of ctrl pin the ctrl pin sets the audio interface format and the type of serial control interface. when the ctrl pin is ?l?, the audio interface format is selected by the dif bit and the serial control interface is 3-wire control mode. when the ctrl pin is ?h?, the audio interface format is fixed to 24bit i 2 s compatible and the serial control interface is i 2 c-bus control mode. ctrl pin audio interface format serial control interface l note 3-wire control h 24bit, i 2 s compatible i 2 c-bus control table 8. ctrl pin function note: the audio interface format is ored between the ctrl pin and dif bit. when the ctrl pin is ?l?, the audio interface format can be selected between 24bit msb justified and 24bit i 2 s compatible by dif bit. when the ctrl pin is ?h?, the audio interface format is fixed to 24bit i 2 s compatible.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 20 - ? input attenuator the input atts are constructed by adding the input resistor (ri) for lin1-5/rin1-5 pins and the feedback resistor (rf) between lopin (ropin) pin and lout (rout) pin (figure 7). the input voltage range of the ipgal/ipgar pin is typically 0.2 x avdd (vrms). if the input voltage of the input selector exceeds 0.2 x avdd, the input voltage of the ipgal/ipgar pins must be attenuated to 0.2 x avdd by the input atts. table 9 shows the example of ri and rf. lin1 lin2 lin3 lin4 lin5 rin1 rin2 rin3 rin4 rin5 ipgal ropin rout ipgar lopin lout pre-amp pre-amp to ipga to ipga ri ri ri ri ri ri ri ri ri ri rf rf figure 7. input att ? example for input range input range ri [k ? ] rf [k ? ] att gain [db] ipgal/r pin 4vrms 47 12 ? 11.86 1.02vrms 2vrms 47 24 ? 5.84 1.02vrms 1vrms 47 47 0 1vrms table 9. input att example
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 21 - ? input volume the AK5365 includes two independent channel analog volumes (ipga) with 25 levels at 0.5db steps located in front of the adc. the digital volume controls (datt) have 128 levels (including mute) and is located after the adc. both the analog and digital volumes are controlled through the same register address. when the msb of the register is ?1?, the ipga changes and when the msb = ?0?, the datt changes. the ipga is a true analog volume control that improves the s/n ratio as seen in table 10. independent zero-crossing detection is used to ensure level changes only occur during zero-crossings. if there are no zero-crossings, the level will then change after a time-out period (table 11); the time-out period scales with fs. if a new value is written to the ipga register before the ipga changes at the zero crossing or time-out, the previous value becomes invalid. the timer (channel independent) for time-out is reset and the timer restarts for new ipga value. the datt is a pseudo-log volume that is linear-interpolated internally. when changing the level, the transition between att values has 8031 levels and is done by soft changes, eliminating any switching noise. input gain setting 0db +6db +12db fs=48khz, a-weight 103db 100db 96db table 10. pga+adc s/n ztm1 ztm0 zero crossing timeout period @fs=48khz 0 0 288/fs 6ms 0 1 1152/fs 24ms 1 0 2304/fs 48ms default 1 1 4608/fs 96ms table 11. zero crossing timeout period [writing operation at alc enable] writing to the area over 80h (table 17) of ipgl/r registers is ignored during alc operation. after alc is disabled, the ipga changes to the last written data by zero-crossing or time-out. in case of writing to the datt area under 7fh (table 17) of ipgl/r registers, the datt changes even if alc is enabled.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 22 - ? alc operation [1] alc limiter operation when the alc limiter is enabled, and either lch or rch exceed the alc limiter detection level (lmth bit), the ipga value is attenuated by the amount defined in the alc limiter att step (lmat bit) automatically. then the ipga value is changed commonly for l/r channels. when the zelmn bit = ?1?, the timeout period is set by the ltm1-0 bits. the operation for attenuation is done continuously until the input signal level becomes the alc limiter detection level (lmth bit) or less. if the alc bit does not change into ?0? or the alc pin does not change into ?l? after completing the attenuation, the attenuation operation repeats until the input signal level equals or exceeds the alc limiter detection level (lmth bit). when the zelmn bit = ?0?, the timeout period is set by the ztm1-0 bits. this enables the zero-crossing attenuation function so that the ipga value is attenuated at the zero-detect points of the waveform. when fr bit = ?1?, the alc operation corresponds to the impulse noise in additional to the normal alc operation. then if the impulse noise is supplied at zelmn bit = ?0?, the alc operation becomes the faster period than a set of ztm1-0 bits. in case of zelmn bit = ?1?, it becomes the same period as ltm1-0 bits. when fr bit = ?0?, the alc operation is the normal alc operation. [2] alc recovery operation the alc recovery refers to the amount of time that the AK5365 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. the alc recovery operation uses the wtm1-0 bits to define the wait period used after completing an alc limiter operation. if the input signal does not exceed the ?alc recovery waiting counter reset level?, the alc recovery operation starts. the ipga value increases automatically during this operation up to the reference level (ref7-0 bits). the alc recovery operation is done at a period set by the wtm1-0 bits. zero crossing is detected during wtm1-0, the alc recovery operation waits wtm1-0 period and the next recovery operation starts. during the alc recovery operation, when input signal level exceeds the alc limiter detection level (lmth bit), the alc recovery operation changes immediately into an alc limiter operation. in the case of ?(recovery waiting counter reset level) input signal < limiter detection level? during the alc recovery operation, the wait timer for the alc recovery operation is reset. therefore, in the case of ?(recovery waiting counter reset level) > input signal?, the wait timer for the alc recovery operation starts. when the impulse noise is input at fr bit = ?1?, the alc recovery operation becomes faster than a normal recovery operation. when the fr bit = ?0?, the alc recovery operation is done by normal period.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 23 - [3] alc level diagram (1) alc=off figure 8 and 9 show the level diagram example at alc=off. in figure 8, input att is ? 12db. input 4vrms 2vrms att ipga adc 0dbfs -12db -12db -12db 1vrms -12db +6db +12db figure 8. alc level diagram example (alc=off) in figure 9, input att is ? 6db. input 2vrms 1vrms att ipga adc 0dbfs -6db -6db -6db 0.5vrms -6db +6db +12db figure 9. alc level diagram example (alc=off)
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 24 - (2) alc=on figure 10 and 11 show the level diagram example at alc=on. in figure 10, input att is ? 12db and ref7-0 bits are ?8ch?. input 4vrms 2vrms att alc adc -12db -12db -12db 1vrms -12db 0.5vrms -0.5db -0.5dbfs -6dbfs -12dbfs 0dbfs +5.5db +6db 0.25vrms figure 10. alc level diagram example (alc=on) in figure 11, input att is ? 6db and ref7-0 bits are ?8ch?. input 2vrms 1vrms att alc adc -6db -6db 0.5vrms -6db 0.25vrms -6db -0.5db -0.5dbfs -6dbfs 0dbfs +5.5db +6db -12dbfs figure 11. alc level diagram example (alc=on)
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 25 - [4] example of alc operation the following registers should not be changed during the alc operation. ? ltm1-0, lmth, lmat, wtm1-0, ztm1-0, ratt, ref7-0, zelmn bits ? the ipga value of lch becomes the start value if the ipga value is different with lch and rch when the alc starts. ? writing to the area over 80h (table 17) of ipgl/r registers is ignored during alc operation. after alc is disabled, the ipga changes to the last written data by zero-crossing or time-out. in case of writing to the datt area under 7fh (table 17) of ipgl/r registers, the datt changes even if alc is enabled. manual mode finish alc mode and return to manual mode finish alc mode? yes no set (sel2-0 bits or sel2-0 pins) wr (ztm1-0, wtm1-0, ltm1-0) wr (lmat, ratt, lmth) wr (ref7-0) wr (ipga7-0) alc operation wr (alc = ?0?) wr (alc = ?1?) (1) (2) (1) (2) note : wr : write figure 12. registers set-up sequence at alc operation (1): enable soft mute (2): disable soft mute note : alc operation is enabled by the alc pin. note : all the bits about alc operation operate by the default value when an alc operation is started with the alc pin without setting up a bit about alc operation with the register. a bit about alc operation operate by the setting value when a bit about alc operation is set up with the register and an alc operation is started with the alc pin. note : after alc operation is disabled, the ipga changes to the last written data during or before alc operation.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 26 - [5] ipga value before and after alc operation [operation example 1] 1. set ipga = +12db at alc=off. datt portion is set to 0db internally. 2. alc=on after soft mute is enabled. 3. disable the soft mute. 4. during alc operation. the ipga changes from ? 9.5db to the value set by ref7-0 bits. 5. alc=off after soft mute is enabled. 6. disable the soft mute. the ipga return to +12db automatically. [operation example 2] 1. set ipga = +12db at alc=off. datt portion is set to 0db internally. 2. alc=on after soft mute is enabled. 3. disable the soft mute. 4. during alc operation. when the datt portion is set to ? 10db, the ipga changes from ? 19.5db to the value set by ref7-0 bits. 5. alc=off after soft mute is enabled. 6. disable the soft mute. the ipga setting is ? 10db. ? soft mute operation soft mute operation is performed in the digital domain of the adc output. soft mute can be controlled by smute bit or smute pin. the smute bit and smute pin are ored between pin and register. when smute bit goes ?1? or smute pin goes ?h?, the adc output data is attenuated by ? within 1024 lrck cycles. when the smute bit returned ?0? or smute pin goes ?l? the mute is cancelled and the output attenuation gradually changes to ipga value within 1024 lrck cycles. if the soft mute is cancelled before mute state after starting of the operation, the attenuation is discontinued and returned to ipga value. soft mute function and digital volume are common. smute attenuation datt level - gd gd (1) (2) (3) sdto figure 13. soft mute function (1) the output signal is attenuated by ? within 1024 lrck cycles (1024/fs). (2) digital output delay from the analog input is called the group delay (gd). (3) if the soft mute is cancelled before the mute, the attenuation is discontinued and returned to ipga value.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 27 - ? chip address in case of 3-wire control mode, the chip address is fixed to c1 bit = ?1? and c0 bit = ?0?. table 12 shows the relationship between chip address (c1-0 bits) and cad1 pin in i 2 c-bus control mode. cad1 pin c1 bit c0 bit l 0 fixed to ?1? h 1 fixed to ?1? table 12. chip address in i 2 c-bus control note : c1 bit should match with the input level of cad1 pin. ? serial control interface (1) 3-wire serial control mode (ctrl pin = ?l?) internal registers may be written by using the 3-wire p interface pins (csn, cclk and cdti). the data on this interface consists of a chip address (2bits, fixed to ?10?), read/write (1bit, fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. after a low-to-high transition of csn, data is latched for write operations. the clock speed of cclk is 5mhz (max). the value of internal registers is initialized at pdn pin = ?l?. csn cclk cdti 0 1 2 3 4 5 6 7 8 9 101112131415 c1 c0 r/w a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 c1 - c0 : chip address (c1="1", c0="0") r/w : read / write (fixed to "1" : write only) a4 - a0 : register address d7 - d0 : control data figure 14. serial control i/f timing
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 28 - (2) i 2 c-bus control mode (ctrl pin = ?h?) the AK5365 supports the standard-mode i 2 c-bus (max: 100khz). the AK5365 does not support a fast-mode i 2 c-bus system (max: 400khz). (2)-1. write operations figure 15 shows the data transfer sequence for the i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 21). after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit that is a data direction bit (r/w). t he most significant five bits of the slave address are fixed as ?00100?. the next one bit are cad1 (device address bits). this one bit identify the specific device on the bus. the hard-wired input pin (cad1 pin) set these device address bits (figure 16). if the slave address matches that of the AK5365, the AK5365 generates an acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse (figure 22). a r/w bit value of ?1? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the AK5365. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 17). the data after the second byte contains control data. the format is msb first, 8bits (figure 18). the AK5365 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 21). the AK5365 can perform more than one byte write operation per sequence. after receipt of the third byte the AK5365 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 07h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 23) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 15. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 cad1 1 r/w (cad1 should match with cad1 pin.) figure 16. the first byte 0 0 0 a4a3a2a1a0 figure 17. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 18. byte structure after the second byte
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 29 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the AK5365. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. after receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 07h prior to generating a stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the AK5365 supports two basic read operations: current address read and random address read. (2)-2-1. current address read the AK5365 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the AK5365 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but instead generates a stop condition, the AK5365 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 19. current address read (2)-2-2. random address read the random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit set to ?1?. the AK5365 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but instead generates a stop condition, the AK5365 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 20. random address read
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 30 - scl sda stop condition start condition s p figure 21. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 22. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 23. bit transfer on the i 2 c-bus
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 31 - ? control by pin and bit function pin bit alc alc enable pin (internal pull-down) ?l? : disable ?h? : enable alc enable bit ?0? : disable ?1? : enable input selector sel2-0 pin ?lll? : lin1/rin1 ?llh? : lin2/rin2 ?lhl? : lin3/rin3 ?lhh? : lin4/rin4 ?hll? : lin5/rin5 sel2-0 bit ?000? : lin1/rin1 ?001? : lin2/rin2 ?010? : lin3/rin3 ?011? : lin4/rin4 ?100? : lin5/rin5 soft mute smute pin (internal pull-down) ?l? : normal operation ?h? : soft muted smute bit ?0? : normal operation ?1? : soft muted audio interface format ctrl pin ?l? : 24bit msb justified ?h? : 24bit i 2 s compatible dif bit ?0? : 24bit msb justified ?1? : 24bit i 2 s compatible table 13. pin and bit control note : the sel2-0 pins should be fixed to ?lll? if the AK5365 is controlled by the sel2-0 bits, because the setting of the sel2-0 pins are prior to the sel2-0 bits setting. other functions are ored between pin and register. ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down & reset control 0 0 0 0 0 0 0 pwn 01h input selector control 0 0 0 0 0 sel2 sel1 sel0 02h clock & format control 0 0 0 0 dif cks1 cks0 smute 03h timer select 0 0 ltm1 ltm0 ztm1 ztm0 wtm1 wtm0 04h lch ipga control ipgl7 ipgl6 ipgl5 ipgl4 ipgl3 ipgl2 ipgl1 ipgl0 05h rch ipga control ipgr7 ipgr6 ipgr5 ipgr4 ipgr3 ipgr2 ipgr1 ipgr0 06h alc mode control 1 0 0 zelmn alc fr lmth ratt lmat 07h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 pdn pin = ?l? resets the registers to their default values. note: unused bits must contain a ?0? value. note: only write to address 00h to 07h.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 32 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down & reset control 0 0 00000pwn default 0 0 00000 1 pwn: power down control 0 : power down. all registers are not initialized. 1 : normal operation (default) ?0? powers down all sections and then both ipga and adc do not operate. the contents of all register are not initialized and enabled to write to the registers. when mclk and lrck are changed, it is not necessary to reset by the pdn pin or pwn bit because the AK5365 builds in reset-free circuit. however, it can be reduced the noise by reset. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h input selector control 0 0 0 0 0 sel2 sel1 sel0 default 0 0 00000 0 sel2-0: input selector (see table 6) initial values are ?000?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h clock & format control 0 0 0 0 dif cks1 cks0 smute default 0 0 00000 0 smute: soft mute control 0 : normal operation (default) 1 : sdto outputs soft-muted. cks1-0: master clock frequency select (see table 2) initial values are ?00?. dif: audio interface format (see table 3) initial values are ?0?. when ctrl pin is ?h?, audio interface format is fixed to i 2 s compatible.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 33 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h timer select 0 0 ltm1 ltm0 ztm1 ztm0 wtm1 wtm0 default 0 0 10101 1 wtm1-0: alc recovery waiting time (see table 14) a period of recovery operation when any limiter operation does not occur during the alc operation. wtm1 wtm0 alc recovery operation waiting period @fs=48khz 0 0 288/fs 6ms 0 1 1152/fs 24ms 1 0 2304/fs 48ms 1 1 4608/fs 96ms default table 14. alc recovery waiting time ztm1-0: zero crossing timeout (see table 15) when the ipga of each l/r channels perform zero crossing or timeout independently, the ipga value is changed by the p write operation, alc recovery operation or alc limiter operation (zelmn bit = ?0?). ztm1 ztm0 zero crossing timeout period @fs=48khz 0 0 288/fs 6ms 0 1 1152/fs 24ms 1 0 2304/fs 48ms default 1 1 4608/fs 96ms table 15. zero crossing timeout ltm1-0: alc limiter period (see table 16) when zelmn bit = ?1?, the ipga value is changed immediately. when the ipga value is changed continuously, the change is done by the period set by the ltm1-0 bits. ltm1 ltm0 alc limiter operation period @fs=48khz 0 0 3/fs 63 s 0 1 6/fs 125 s 1 0 12/fs 250 s default 1 1 24/fs 500 s table 16. alc limiter period
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 34 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h lch ipga control ipgl7 ipgl6 ipgl5 ipgl4 ipgl3 ipgl2 ipgl1 ipgl0 05h rch ipga control ipgr7 ipgr6 ipgr5 ipgr4 ipgr3 ipgr2 ipgr1 ipgr0 default 0 1 11111 1 ipgl/r7-0: input pga & digital volume control (see table 17) initial values are ?7fh?. digital att with 128 levels operates when writing data of less than 7fh. this att is a linear att with 8032 levels internally and these levels are assigned to pseudo-log data with 128 levels. the transition between att values has 8032 levels and is done by soft changes. for example, when att changes from 7fh to 7eh, the internal att value decreases from 8031 to 7775, one by one every fs cycle. it takes 8031 cycles (167ms@fs=48khz) from 7fh to 00h (mute). the ipgas are set to ?00h? when pdn pin goes ?l?. after returning to ?h?, the ipgas fade into the initial value, ?7fh? in 8031 cycles. the ipgas are set to ?00h? when pwn bit goes ?0?. after returning to ?1?, the ipgas fade into the current value. the adc output is ?0? during the first 516lrck cycles. writing to the area over 80h (table 17) of ipgl/r registers is ignored during alc operation. after alc is disabled, the ipga changes to the last written data by zero-crossing or time-out. in case of writing to the datt area under 7fh (table 17) of ipgl/r registers, the datt changes even if alc is enabled.
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 35 - data (hex) internal (datt) gain (db) step width (db) 98h - +12 - 97h - +11.5 0.5 96h - +11 0.5 : - : 0.5 82h - +1.0 0.5 81h - +0.5 0.5 80h - 0 - ipga analog volume with 0.5db step 7fh 8031 0 - 7eh 7775 ? 0.28 0.28 7dh 7519 ? 0.57 0.29 :: : : 70h 4191 ? 5.65 0.51 6fh 3999 ? 6.06 0.41 6eh 3871 ? 6.34 0.28 :: : : 60h 2079 ? 11.74 0.52 5fh 1983 ? 12.15 0.41 5eh 1919 ? 12.43 0.28 :: : : 50h 1023 ? 17.90 0.53 4fh 975 ? 18.32 0.42 4eh 943 ? 18.61 0.29 :: : : 40h 495 ? 24.20 0.54 3fh 471 ? 24.64 0.43 3eh 455 ? 24.94 0.30 :: : : 30h 231 ? 30.82 0.58 2fh 219 ? 31.29 0.46 2eh 211 ? 31.61 0.32 :: : : 20h 99 ? 38.18 0.67 1fh 93 ? 38.73 0.54 1eh 89 ? 39.11 0.38 :: : : 10h 33 ? 47.73 0.99 0fh 30 ? 48.55 0.83 0eh 28 ? 49.15 0.60 :: : : 05h 10 ? 58.10 1.58 04h 8 ? 60.03 1.94 03h 6 ? 62.53 2.50 02h 4 ? 66.05 3.52 01h 2 ? 72.07 6.02 00h 0 mute datt external 128 levels are converted to internal 8032 linear levels of datt. internal datt soft-changes between data. datt =2^m x (2 x l + 33) ? 33 m: msb 3-bits of data l: lsb 4-bits of data table 17. ipga code table
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 36 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h alc mode control 1 0 0 zelmn alc fr lmth ratt lmat default 0 0 1 0 1 0 0 0 lmat: alc limiter att step (see table 18) during the alc limiter operation, when either lch or rch exceeds the alc limiter detection level set by lmth bit, the number of steps attenuated from the current ipga value is set. for example, when the current ipga value is 94h and the lmat bit = ?1?, the ipga transition to 92h when the alc limiter operation starts, resulting in the input signal level being attenuated by 1db (=0.5db x 2). lmat att step 0 1 default 12 table 18. alc limiter att step ratt: alc recovery gain step (see table 19) during the alc recovery operation, the number of steps changed from the current ipga value is set. for example, when the current ipga value is 82h and ratt bit = ?1? is set, the ipga changes to 84h by the alc recovery operation and the output signal level is gained up by 1db (=0.5db x 2). when the ipga value exceeds the reference level (ref7-0 bits), the ipga value does not increase. ratt gain step 0 1 default 12 table 19. alc recovery gain step lmth: alc limiter detection level / recovery waiting counter reset level (see table 20) the alc limiter detection level and the alc recovery counter reset level may be offset by about 2db. lmth alc limiter detection level alc recovery waiting counter reset level 0 alc output ? 0.5dbfs ? 0.5dbfs > alc output ? 2.5dbfs default 1 alc output ? 2.0dbfs ? 2.0dbfs > alc output ? 4.0dbfs table 20. alc limiter detection level / recovery waiting counter reset level fr: alc fast recovery 0 : disable 1 : enable (default) when the impulse noise is input, the alc recovery operation becomes faster than a normal recovery operation. alc: alc enable flag 0 : alc disable (default) 1 : alc enable zelmn: zero crossing enable flag at alc limiter operation 0 : enable 1 : disable (default) when the zelmn bit = ?0?, the ipga of each l/r channel perform a zero crossing or timeout independently. the zero crossing timeout is the same as the alc recovery operation. when the zelmn bit = ?1?, the ipga value is changed immediately. the alc limiter period can be set up by a ztm 1-0 bits when zelmn bit = ?0?, it can be set up by a ltm1-0 bits when zelmn bit = ?1?
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 37 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 default 1 0 00100 1 ref7-0: reference value at alc recovery operation (see table 21) during the alc recovery operation, if the ipga value exceeds the setting reference value by gain operation, then the ipga does not become larger than the reference value. the ref7-0 bits should not be set up except for table 21. data (hex) gain (db) 98h +12.0 97h +11.5 96h +11.0 95h +10.5 :: 89h +4.5 default :: 81h +0.5 80h 0 table 21. reference value at alc recovery operation
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 38 - system design figure 24 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ? master mode, 3-wire control (ctrl pin = ?l?) lin5 1 2 3 4 5 6 7 8 9 10 11 test1 lin4 test2 lin3 test3 lin2 test4 lin1 lopin lout top view avdd rin5 44 43 42 test8 rin4 41 40 38 37 39 35 34 36 test7 rin3 test6 rin2 test5 rin1 m/s ctrl 47k 1 47k 1 47k 1 47k 1 47k 1 24k 4.7 47k 1 47k 1 47k 1 47k 1 47k 1 reset dsp and up 33 32 31 30 29 28 27 26 25 24 23 csn/cad1 cclk/scl cdti/sda sel2 sel1 sel0 smute alc pdn mclk lrck analog supply 4.75 ~ 5.25v ipgar 12 rout 13 ropin 14 15 16 avss 17 vcom 18 dvss 19 dvdd 20 21 sdto 22 bick 0.1 10 2.2 0.1 24k 4.7 10 0.1 digital supply 3.0 ~ 5.25v ipgal note: - avss and dvss of the AK5365 should be distributed separately from the ground of external digital devices (mpu, dsp etc.). - when lout/rout drives a capacitive load, resistors should be added in series between lout/rout and capacitive load. - all input pins except pull-down pin (alc, smute pins) should not be left floating. figure 24. typical connection diagram
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 39 - 1. grounding and power supply decoupling the AK5365 requires careful attention to power supply and grounding arrangements. avdd and dvdd are usually supplied from the analog supply in the system. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. avss and dvss of the AK5365 must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK5365 as possible, with the small value ceramic capacitor being the closest. 2. voltage reference inputs the differential voltage between avdd and avss sets the analog input range. vcom is a signal ground of this chip. an electrolytic capacitor 2.2f parallel with a 0.1f ceramic capacitor attached to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vref and vcom pins in order to avoid unwanted coupling into the AK5365. 3. analog inputs an analog input of AK5365 is single-ended input to pre-amp through the external resistor. for input signal range, adjust feedback resistor so that pre-amp output may become the input range (typ. 0.2 x avdd vrms) of ipga (ipgal, ipgar pin). between the pre-amp output (lout, rout pin) and the ipga input (ipgal, ipgar pin) is ac coupled with capacitor. when the impedance of ipgal/r pins is ?r? and the capacitor of between the pre-amp output and the ipga input is ?c?, the cut-off frequency is fc = 1/(2 rc). the adc output data format 2?s compliment. the internal hpf removes the dc offset. the AK5365 samples the analog inputs at 64fs. the digital filter rejects noise above the stop band except for multiples of 64fs. the AK5365 includes an anti-aliasing filter (rc filter) to attenuate a noise around 64fs. 4. attention to the pcb wiring lin1-5 and rin1-5 pins are the summing nodes of the pre-amp. attention should be given to avoid coupling with other signals on those nodes. this can be accomplished by making the wire length of the input resistors as short as possible. the same theory also applies to the lopin/ropin pins and feedback resistors; keep the wire length to a minimum. unused input pins among lin1-5 and rin1-5 pins should be left open. when external devices are connected to lout and rout pin, the input impedance of an external device which the lout and rout pins can drive is min 6.3k ? .
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 40 - package 44pin lqfp (unit: mm) 12.80 0.30 0.80 44 34 33 23 10.00 111 12 22 10.00 12.80 0.30 0.37 0.10 0.15 0.60 0.20 0 10 ~ 0.17 0.05 1.70max 0 ~ 0.2 ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [AK5365 ] ms0164-e-01 2002/08 - 41 - marking 1 akm AK5365vq xxxxxxx xxxxxxx : date code identifier (7 digits) important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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