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copyright ? cirrus logic, inc. 2006 (all rights reserved) http://www.cirrus.com august '06 ds717f1 108 db, 192 khz 4-in, 8-out codec features ? four 24-bit a/d, eight 24-bit d/a converters ? adc dynamic range ? 105 db differential ? 102 db single-ended ? dac dynamic range ? 108 db differential ? 105 db single-ended ? adc/dac thd+n ? -98 db differential ? -95 db single-ended ? compatible with industry-standard time division multiplexed (t dm) serial interface ? system sampling rates up to 192 khz ? programmable adc high-pa ss filter for dc offset calibration ? logarithmic digital volume control ? i2c ? & spi ? host control port ? supports logic levels between 5 v and 1.8 v ? popguard ? technology general description the CS42888 codec provides four multi-bit analog-to- digital and eight multi-bit digital-to-analog delta-sigma converters. the codec is capable of operation with ei- ther differential or single-e nded inputs and outputs, in a 64-pin lqfp package. four fully differential, or single-ended, inputs are avail- able on stereo adc1 and adc 2 . digital volume control is provided for each adc channel, with selectable over- flow detection. all eight dac channels provide digital volume control and can operate with differential or single-ended outputs. an auxiliary serial input is available for an additional two channels of pcm data. the CS42888 is available in a 64-pin lqfp package in commercial (-10 to +70) and automotive (-40 to +105) grades. the cdb42888 customer demonstra- tion board is also available for device evaluation and implementation suggestions. please refer to ?ordering information? on page 61 for complete ordering information. the CS42888 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as a/v receivers, dvd receivers, and automotive audio systems. control port & serial audio port supply = 1.8 v to 5 v mute control external mute control register configuration internal voltage reference reset pcm or tdm serial interface level translator serial audio input digital supply = 3.3 v to 5 v analog supply = 3.3 v to 5 v input master clock serial audio output multibit oversampling adc1 high pass filter differential or single- ended analog inputs 2 digital filters 2 multibit oversampling adc2 high pass filter 2 digital filters 2 auxilliary serial audio input differential or single-ended outputs interrupt adc overflow & clock error interrupt level translator i 2 c/spi software mode control data volume controls digital filters 8 multibit dac1-4 and analog filters 8 ? modulators CS42888
2 ds717f1 CS42888 table of contents 1. pin descriptions ........................................................................................................... ................... 6 1.1 digital i/o pin characteristics ........................................................................................... ................ 8 2. typical connection diagram ............................................................................................... .... 9 3. characteristics and specificat ions........... ................. ................ ................ ................ ......... 10 recommended operating conditions ................................................................................... 10 absolute maximum rating s ................ ................. ................ ................ ............. ............. ........... .10 analog input characteristics (commercial) .................................................................... 11 analog input characteristics (automotive) .. ................................................................... 12 adc digital filter characteristics ....................................................................................... 13 analog output characteristics (commercial) ................................................................ 14 analog output characteristics (automotive) ................................................................. 15 combined dac interpolation & on-chip analog filter response .............................. 17 switching specifications - adc/dac port ............................................................................ 18 switching characteristics - aux port ................................................................................. 20 switching specifications - control port - i2c mode ....................................................... 21 switching specifications - control port - spi format ................................................. 22 dc electrical characteristics .............................................................................................. 23 digital interface specifications & character istics ..................................................... 23 4. applications ................................................................................................................ .................... 24 4.1 overview .................................................................................................................. ....................... 24 4.2 analog inputs ............................................................................................................. ..................... 24 4.2.1 line-level inputs ....................................................................................................... ............ 24 4.2.2 high-pass filter and dc offset calibration ........................................................................... 25 4.3 analog outputs ............................................................................................................ ................... 25 4.3.1 initialization .......................................................................................................... .................. 25 4.3.2 output transient control ................................................................................................ ....... 27 4.3.3 popguard ................................................................................................................ ............... 27 4.3.3.1 power-up .............................................................................................................. ..... 27 4.3.3.2 power-down ............................................................................................................ .. 27 4.3.4 mute control ............................................................................................................ .............. 27 4.3.5 line-level outputs and filtering ........................................................................................ .... 28 4.3.6 digital volume control .................................................................................................. ......... 28 4.3.7 de-emphasis filter ...................................................................................................... .......... 28 4.4 system clocking ........................................................................................................... .................. 29 4.5 codec digital interface formats ........................................................................................... ........ 30 4.5.1 i2s ..................................................................................................................... ..................... 31 4.5.2 left-justified .......................................................................................................... ................ 31 4.5.3 right-justified ......................................................................................................... ............... 31 4.5.4 olm #1 .................................................................................................................. ................ 31 4.5.5 olm #2 .................................................................................................................. ................ 32 4.5.6 tdm ..................................................................................................................... .................. 32 4.5.7 i/o channel allocation .................................................................................................. ......... 33 4.6 aux port digital interface formats ........................................................................................ ......... 33 4.6.1 i2s ..................................................................................................................... ..................... 33 4.6.2 left-justified .......................................................................................................... ................ 33 4.7 control port descripti on and timing ....................................................................................... ........ 33 4.7.1 spi mode ................................................................................................................ ............... 34 4.7.2 i2c mode ................................................................................................................ ................ 34 4.8 interrupts ................................................................................................................ ......................... 36 4.9 recommended power-up sequen ce ............................................................................................. 36 4.10 reset and power-up ....................................................................................................... ............. 36 4.11 power supply, ground ing, and pcb layout ................................................................................. 3 6
ds717f1 3 CS42888 5. register quick reference .................................................................................................... ..... 38 6. register description ........................................................................................................ ........... 40 6.1 memory address poin ter (map) .............................................................................................. ....... 40 6.1.1 increment (incr) ........................................................................................................ .......... 40 6.1.2 memory address pointer (map[6:0]) ..................................................................................... 40 6.2 chip i.d. and revision regist er (address 01h) (read only) .......................................................... 40 6.2.1 chip i.d. (chip_id[3:0]) ................................................................................................ ........ 40 6.2.2 chip revision (rev_id[3:0]) ................. ............................................................................ .... 40 6.3 power control (address 02h) ...................... ......................................................................... .......... 41 6.3.1 power down adc pairs (pdn_adcx) ........... ...................................................................... 41 6.3.2 power down dac pairs (pdn_dacx) ........... ...................................................................... 41 6.3.3 power down (pdn) ........................................................................................................ ....... 41 6.4 functional mode (address 03h) ............................................................................................. ......... 42 6.4.1 dac functional mode (dac_fm[1:0]) .................................................................................. 42 6.4.2 adc functional mode (adc_fm[1:0]) .................................................................................. 42 6.4.3 mclk frequency (mfreq[2:0]) ........................................................................................... 42 6.5 interface formats (address 04 h) ........................................................................................... ......... 43 6.5.1 freeze controls (freeze) ................................................................................................ ... 43 6.5.2 auxiliary digital interface format (aux_dif) ........................................................................ 43 6.5.3 dac digital interface format (dac_dif[2:0]) ....................................................................... 43 6.5.4 adc digital interface format (adc_dif[2:0]) ....................................................................... 44 6.6 adc control & dac de-emphasis (address 05h) ......................................................................... 44 6.6.1 adc1-2 high-pass filter freeze (adc1-2_hpf freeze) ..... ............................................. 44 6.6.2 dac de-emphasis control (d ac_dem) ............................................................................... 45 6.6.3 adc1 single-ended mode (adc1 single) ......................................................................... 45 6.6.4 adc2 single-ended mode (adc2 single) ......................................................................... 45 6.7 transition control (address 06h) ................. ......................................................................... .......... 45 6.7.1 single volume control (dac_sngvol, ad c_sngvol) .................................................... 45 6.7.2 soft ramp and zero cross control (adc_s zc[1:0], dac_szc[1:0]) .................................. 46 6.7.3 auto-mute (amute) ....................................................................................................... ....... 46 6.7.4 mute adc serial port (mute adc_sp) ..... .......................................................................... 47 6.8 dac channel mute (address 07h) ............................................................................................ ..... 47 6.8.1 independent channel mute (aoutx_mute) ....................................................................... 47 6.9 aoutx volume control (addresse s 08h- 0fh) .......................................................................... 47 6.9.1 volume control (aoutx_vol [7:0]) ...................................................................................... 47 6.10 dac channel invert (address 10h) ......................................................................................... ..... 48 6.10.1 invert signal polarity (inv_aoutx) ....... ............................................................................. 4 8 6.11 ainx volume control (address 11h-14h) ..... ............................................................................... .48 6.11.1 ainx volume control (ainx_vol[7:0]) .............................................................................. 48 6.12 adc channel invert (address 17h) ......................................................................................... ..... 48 6.12.1 invert signal polarity (inv_ainx) ...................................................................................... .. 49 6.13 when enabled, these bits will inve rt the signal polarity of their respective channel s.status control (address 18h) ................................................................................................................. ...................... 49 6.13.1 interrupt pin control (int [1:0]) ....................................................................................... ..... 49 6.14 status (address 19h) (read only) ......................................................................................... ....... 49 6.14.1 dac clock error (dac_clk error) ........................................................................ 49 6.14.2 adc clock error (adc_clk error) ..... ................................................................... 50 6.14.3 adc overflow (adcx_ovfl) ....................... ...................................................................... 50 6.15 status mask (address 1ah) ................................................................................................ .......... 50 6.16 mutec pin control (address 1bh) .......................................................................................... .... 50 6.17 mutec polarity select (mcpolarity) ......... ............................................................................. 5 0 6.18 mute control active (mutec active) ....... ...................................................................... 50 7. external filters............................................................................................................ ................ 51 7.1 adc input filter .......................................................................................................... .................... 51
4 ds717f1 CS42888 7.1.1 passive input filter .................................................................................................... ............ 52 7.1.2 passive input filter w/attenuation ......... ............................................................................. ... 52 7.2 dac output filter ......................................................................................................... .................. 53 8. adc filter plots............................................................................................................ ................. 54 9. dac filter plots............................................................................................................ ................. 56 10. parameter definitions...................................................................................................... ......... 58 11. references................................................................................................................. .................... 59 12. package information........................................................................................................ ......... 60 12.1 thermal characteristics .................................................................................................. ........... 60 13. ordering information ....................................................................................................... ........ 61 14. revision history ........................................................................................................... ................ 61 list of figures figure 1.typical connection diagram ........................................................................................... .............. 9 figure 2.output test circuit for maximum load ................................................................................. ...... 16 figure 3.maximum loading ...................................................................................................... ................. 16 figure 4.serial audio interface slave mode timing ............................................................................. ..... 18 figure 5.tdm serial audio interface timing ...... .............................................................................. ......... 18 figure 6.serial audio interface master mode timing ............................................................................ .... 19 figure 7.serial audio interface slave mode timing ............................................................................. ..... 20 figure 8.control port timing - i2c format ..................................................................................... ............ 21 figure 9.control port timing - spi format ..................................................................................... ........... 22 figure 10.full-scale input ............................ ........................................................................ ..................... 25 figure 11.audio output initialization flow chart .............................................................................. ......... 26 figure 12.full-scale output ................................................................................................... ................... 28 figure 13.de-emphasis curve ................................................................................................... ............... 29 figure 14.i2s format .......................................................................................................... ....................... 31 figure 15.left-justified format ............................................................................................... .................. 31 figure 16.right-justified format .............................................................................................. ................. 31 figure 17.one-line mode #1 form at ............................................................................................. ........... 31 figure 18.one-line mode #2 form at ............................................................................................. ........... 32 figure 19.tdm format ................................. ......................................................................... .................... 32 figure 20.aux i2s format ............................ .......................................................................... ................... 33 figure 21.aux left-justified format ........................................................................................... .............. 33 figure 22.control port timing in spi mode ....... .............................................................................. ......... 34 figure 23.control port timing, i2c write ......... ............................................................................. ............. 35 figure 24.control port timing, i2c read ......... .............................................................................. ............ 35 figure 25.single-to-diffe rential active input filter .......................................................................... ........... 51 figure 26.single-en ded active input filter .................................................................................... ............ 51 figure 27.passive input filter ................................................................................................ ................... 52 figure 28.passive input filter w/attenuation .................................................................................. ........... 52 figure 29.active analog output filter ......................................................................................... .............. 53 figure 30.passive analog output filter ....... ................................................................................. ............ 53 figure 31.ssm stopband rejection .............................................................................................. ............ 54 figure 32.ssm transition band ................................................................................................. ............... 54 figure 33.ssm transition band (detail) ........................................................................................ ........... 54 figure 34.ssm passband ripple ................................................................................................. ............. 54 figure 35.dsm stopband rejection .............................................................................................. ............ 54 figure 36.dsm transition band ................................................................................................. ............... 54 figure 37.dsm transition band (detail) ......... ............................................................................... ........... 55 figure 38.dsm passband ripple ................................................................................................. ............. 55 figure 39.qsm stopband rejection .............................................................................................. ........... 55 figure 40.qsm transition band ................................................................................................. ............... 55
ds717f1 5 CS42888 figure 41.qsm transition band (d etail) ........................................................................................ ........... 55 figure 42.qsm passband ripple ................................................................................................. ............. 55 figure 43.ssm stopband rejection .............................................................................................. ............ 56 figure 44.ssm transition band ................................................................................................. ............... 56 figure 45.ssm transition band (detail) ........................................................................................ ............ 56 figure 46.ssm passband ripple ................................................................................................. ............. 56 figure 47.dsm stopband rejection .............................................................................................. ............ 56 figure 48.dsm transition band ................................................................................................. ............... 56 figure 49.dsm transition band (detail) ........................................................................................ ............ 57 figure 50.dsm passband ripple ................................................................................................. ............. 57 figure 51.qsm stopband rejection .............................................................................................. ........... 57 figure 52.qsm transition band ................................................................................................. ............... 57 figure 53.qsm transition band (d etail) ........................................................................................ ............ 57 figure 54.qsm passband ripple ................................................................................................. ............. 57 list of tables table 1. i/o power rails ...................................................................................................... ....................... 8 table 2. single-speed mode common frequencies ................................................................................ 2 9 table 3. double-speed mode common frequencies ............................................................................... 29 table 4. quad-speed mode common frequencies ................................................................................. 29 table 5. i2s, lj, rj clock ratios ............................................................................................. ................. 30 table 6. olm#1 clock ratios ................................................................................................... ................ 30 table 7. olm#2 clock ratios ................................................................................................... ................ 30 table 8. tdm clock ratios ..................................................................................................... .................. 30 table 9. serial audio interface channel allocations .... ....................................................................... ...... 33 table 10. mclk frequency settings for i2s, left and right justified interface fo rmats .......................... 42 table 12. dac digital interface formats ....................................................................................... ........... 43 table 11. mclk frequency settings for tdm & olm interface formats ................................................. 43 table 13. adc digital interface formats ....................................................................................... ........... 44 table 14. example aout volume settings ........... ............................................................................. ...... 47 table 15. example ain volume settings ............... .......................................................................... ......... 48
6 ds717f1 CS42888 1. pin descriptions pin name # pin description ad0/cs 1 address bit [0]/ chip select ( input ) - chip address bit in i2c mode. control signal used to select the chip in spi mode. ad1/cdin 2 address bit [1]/ spi data input ( input ) - chip address bit in i2c mode. input for spi data. rst 3 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. vlc 4 control port power ( input ) - determines the required signal level for the control port. see ?dig- ital i/o pin characteristics? on page 8 . adc_lrck 5 adc left/right clock ( input / output ) - determines which channel, left or right, is currently active on the adc serial audio data line. signals the start of a new tdm frame in the tdm digital interface format. vd 6, 24 digital power ( input ) - positive terminal of the power supply for the digital section. dgnd 7, 23 62 digital ground ( input ) - ground terminal of the power supply for the digital section. vls 8 serial port interface power ( input ) - determines the required signal level for the serial inter- faces. see ?digital i/o pin characteristics? on page 8 . adc_sclk 9 adc serial clock (input/output) - serial clock for the adc serial audio interface. input fre- quency must be 256xfs in the tdm digital interface format. mclk 10 master clock ( input ) - clock source for the delta-sigma modulators and digital filters. tsto 11 test out - this pin is an output used for test purpo ses only. this pin must be not be connected to any external trace or other connection. adc_sdout1 adc_sdout2 13 12 serial audio data output (output) - outputs for two?s complement serial audio data. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dac_sdin1 adc_sclk adc_lrck vlc scl/cclk ad1/cdin int vq filt+_adc vd vls mclk dac_sdin4 dac_sdin3 dac_sdin2 dgnd ain1- ain1+ mutec aout7+ aout7- aout6- aout6+ aout5+ aout5- 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 aout1- aout2- aout2+ aout1+ agnd va aout3- aout4- aout4+ aout3+ aout8- aout8+ tstn tstn filt+_dac rst tsto adc_sdout2 adc_sdout1 sda/cdout ad0/cs vd dgnd ain2- ain2+ tstn tstn dac_lrck dac_sclk aux_sclk aux_lrck aux_sdin dgnd ain4+ ain4- ain3+ ain3- va agnd 42888
ds717f1 7 CS42888 dac_sdin1 dac_sdin2 dac_sdin3 dac_sdin4 17 16 15 14 dac serial audio data input ( input ) - input for two?s complement serial audio data. dac_sclk 18 dac serial clock (input/output) - serial clock for the dac serial audio interface. input fre- quency must be 256xfs in the tdm digital interface format. dac_lrck 19 dac left/right clock ( input / output ) - determines which channel, left or right, is currently active on the dac serial audio data line. signals the start of a new tdm frame in the tdm digital interface format. aux_lrck 20 auxiliary left/right clock ( output ) - determines which channel, left or right, is currently active on the auxiliary serial audio data line. derived from the adc serial port and equals fs. aux_sclk 21 auxiliary serial clock (output) - serial clock for the auxi liary serial audio interface. aux_sdin 22 auxiliary serial input ( input ) - provides an additional serial input for two?s complement serial audio data. used only in the tdm digital interface format. aout1 +,- aout2 +,- aout3 +,- aout4 +,- aout5 +,- aout6 +,- aout7 +,- aout8 +,- 26, 25 27, 28 30, 29 31, 32 34, 33 36, 37 38, 39 40, 41 differential analog output ( output ) - the full-scale analog output level is specified in the ana- log characteristics table. each leg of the differential outputs may also be used single-ended. mutec 35 mute control ( output ) - used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. agnd 42, 56 analog ground ( input ) - ground reference for the analog section. vq 43 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage. va 44, 53 analog power ( input ) - positive power supply for the analog section. see ?digital i/o pin char- acteristics? on page 8 . ain1 +,- ain2 +,- ain3 +,- ain4 +,- 46, 45 48, 47 50, 49 52, 51 differential analog input ( input ) - signals are presented differentially or single-ended to the delta-sigma modulators. the full-scale input leve l is specified in the analog characteristics specification table. filt+_dac 54 positive voltage reference ( output ) - positive reference voltage for the internal sampling cir- cuits of the dac. filt+_adc 55 positive voltage reference ( output ) - positive reference voltage for the internal sampling cir- cuits of the adc. tstn 57, 58 59, 60 test in - this pin is an input used for test purposes only. it must be tied to ground for normal operation. int 61 interrupt ( output ) - signals either an adc overflow condition has occurred in one or more of the adc inputs, or a clocking error has occurred in the dac/adc as specified in the interrupt regis- ter. scl/cclk 63 serial control port clock ( input ) - serial clock for the control port interface. sda/cdout 64 serial control data i/o ( input/output ) - input/output for i2c data. output for spi data.
8 ds717f1 CS42888 1.1 digital i/o pin characteristics various pins on the CS42888 are powered from separate power supply rails. the logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings. power rail pin name i/o driver receiver vlc rst input - 1.8 v - 5.0 v, cmos scl/cclk input - 1.8 v - 5.0 v, cmos, with hysteresis sda/cdout input/ output 1.8 v - 5.0 v, cmos/open drain 1.8 v - 5.0 v, cmos, with hysteresis ad0/cs input - 1.8 v - 5.0 v, cmos ad1/cdin input - 1.8 v - 5.0 v, cmos int output 1.8 v - 5.0 v, cmos/open drain - vls mclk input - 1.8 v - 5.0 v, cmos adc_lrck input/ output 1.8 v - 5.0 v, cmos 1.8 v - 5.0 v, cmos adc_sclk input/ output 1.8 v - 5.0 v, cmos 1.8 v - 5.0 v, cmos adc_sdout1-2 input/ output 1.8 v - 5.0 v, cmos - dac_lrck input/ output 1.8 v - 5.0 v, cmos 1.8 v - 5.0 v, cmos dac_sclk input/ output 1.8 v - 5.0 v, cmos 1.8 v - 5.0 v, cmos dac_sdin1-4 input - 1.8 v - 5.0 v, cmos aux_lrck output 1.8 v - 5.0 v, cmos - aux_sclk output 1.8 v - 5.0 v, cmos - aux_sdin input - 1.8 v - 5.0 v, cmos va mutec output 3.3 v - 5.0 v, cmos - table 1. i/o power rails
ds717f1 9 CS42888 2. typical connection diagram 0.1 f 100 f 0.1 f + + vq filt+_dac 0.1 f 4.7 f va 0.01 f dgnd 0.1 f +1.8 v to +5 v digital audio processor micro- controller cs5341 a/d converter va vd agnd agnd connect dgnd and agnd near codec 0.01 f 0.1 f + 10 f 0.01 f +3.3 v to +5 v + 10 f 0.1 f 0.01 f +1.8 v to +5.0 v s/pdif cs8416 receiver rmck osc 2 k ? 2 k ? ** ** ** resistors are required for i 2 c control port operation 1. see the adc input filter section in the appendix. 2. see the dac output filter section in the appendix. optional connection +3.3 v to +5 v dgnd aout1+ aout1- aout2+ aout2- aout3+ aout3- aout4+ aout4- ain1+ ain1- analog input 1 input filter 1 analog input 2 input filter 1 analog input 3 input filter 1 analog input 4 input filter 1 ain2+ ain2- ain3+ ain3- ain4+ ain4- analog output filter 2 analog output filter 2 analog output filter 2 analog output filter 2 aout5+ aout5- aout6+ aout6- aout7+ aout7- aout8+ aout8- analog output filter 2 analog output filter 2 analog output filter 2 analog output filter 2 mutec mute drive (optional) dgnd 100 f + 0.1 f filt+_adc vd 0.1 f 0.01 f 39 38 41 35 45 48 52 51 47 43 54 4 1 2 64 63 3 61 14 15 16 17 19 18 12 13 5 9 10 20 22 8 44 742 56 21 23 62 55 49 50 46 40 37 36 33 34 33 34 29 30 28 27 25 26 53 24 6 scl/cclk sda/cdout ad1/cdin rst ad0/cs int vlc vls mclk aux_sdin dac_sdin1 adc_lrck adc_sclk aux_sclk aux_lrck adc_sdout2 dac_lrck dac_sclk adc_sdout1 dac_sdin2 dac_sdin3 dac_sdin4 figure 1. typical connection diagram
10 ds717f1 CS42888 3. characteristics a nd specifications recommended operating conditions (agnd=dgnd=0 v, all volta ges with respect to ground.) absolute maximum ratings (agnd = dgnd = 0 v; all voltag es with respect to ground.) warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. typical analog input/outp ut performance will slightly degrade at va = 3.3 v. 2. the adc_sdout may not meet timing requirements in tdm, double-speed mode. 3. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 4. the maximum over/under voltage is limited by the input current. parameters symbol min max units dc power supply analog (note 1) va 3.14 5.25 v digital vd 3.14 5.25 v serial audio interface (note 2) vls 1.71 5.25 v control port interface vlc 1.71 5.25 v ambient temperature commercial -cqz automotive -dqz t a -10 -40 +70 +105 c c parameters symbol min max units dc power supply analog digital serial port interface control port interface va vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 v v v v input current (note 3) i in -10ma analog input voltage (note 4) v in agnd-0.7 va+0.7 v digital input voltage s erial port interface (note 4) control port interface v ind-s v ind-c -0.3 -0.3 vls+ 0.4 vlc+ 0.4 v v ambient operating temperature (power applied) t a -50 +125 c storage temperature t stg -65 +150 c
ds717f1 11 CS42888 analog input characteristics (commercial) (test conditions (unless otherwise specified): t a = -10 to +70 c; vd = vls = vlc = 3.3 v5%, va = 5 v5%; full-scale input sine wa ve: 1 khz through the active input filter in figure 25 on page 51 and figure 26 on page 51 ; measurement bandwidth is 10 hz to 20 khz.) differential single-ended parameter min typ max min typ max unit fs=48 khz, 96 khz, 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 99 96 - 105 102 99 - - - 96 93 102 99 96 - - - db db db total harmonic distortion + noise -1 db (note 5) -20 db -60 db 40 khz bandwidth -1 db - - - - -98 -82 -42 -90 -92 - - - - - - - -95 -79 -39 -90 -89 - - - db db db db adc1-2 interchannel isolation - 90 - - 90 - db dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - 100 - - 100 - ppm/c analog input full-scale input voltage 1.06*va 1.12* va 1.18*va 0.53*va 0.56*va 0.59*va vpp differential input impedance (note 6) 18 - - - - - k ? single-ended input impedance (note 7) ---18--k ? common mode rejection ratio (cmrr) - 82 - - - - db
12 ds717f1 CS42888 analog input characteristics (automotive) (test conditions (unless otherwise specified): t a =-40 to +85 c; vd = vls = vlc = 3.3 v5%, va = 5 v5%; full-scale input sine wave: 1 khz through the active input filter in figure 25 on page 51 and figure 26 on page 51 ; measurement bandwidth is 10 hz to 20 khz.) notes: 5. referred to the typical full-scale voltage. 6. measured between ainx+ and ainx-. 7. measured between ainxx and agnd. differential single-ended parameter min typ max min typ max unit fs=48 khz, 96 khz, 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 97 94 - 105 102 99 - - - 94 91 - 102 99 96 - - - db db db total harmonic distortion + noise -1 db (note 5) -20 db -60 db 40 khz bandwidth -1 db - - - - -98 -82 -42 -87 -90 - - - - - - - -95 -79 -39 -87 -87 - - - db db db db adc1-2 interchannel isolation - 90 - - 90 - db dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - 100 - - 100 - ppm/c analog input full-scale input voltage 1.04*va 1.12*va 1.20*va 0.52*va 0.56*va 0.60*va vpp differential input impedance (note 6) 18 - - - - - k ? single-ended input impedance (note 7) ---18--k ? common mode rejection ratio (cmrr) - 82 - - - - db
ds717f1 13 CS42888 adc digital filter characteristics notes: 8. filter response is guaranteed by design. 9. response is clock-dependent and will scale with fs. note that the response plots ( figures 31 to 42 ) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. parameter (notes 8, 9) min typ max unit single-speed mode (note 9) passband (frequency response) to -0.1 db corner 0 - 0.4896 fs passband ripple - - 0.08 db stopband 0.5688 - - fs stopband attenuation 70 - - db total group delay - 12/fs - s double-speed mode (note 9) passband (frequency response) to -0.1 db corner 0 - 0.4896 fs passband ripple - - 0.16 db stopband 0.5604 - - fs stopband attenuation 69 - - db total group delay - 9/fs - s quad-speed mode (note 9) passband (frequency response) to -0.1 db corner 0 - 0.2604 fs passband ripple - - 0.16 db stopband 0.5000 - - fs stopband attenuation 60 - - db total group delay - 5/fs - s high-pass filter characteristics frequency response -3.0 db -0.13 db -1 20 - - hz hz phase deviation @ 20 hz - 10 - deg passband ripple - - 0 db filter settling time - 10 5 /fs 0 s
14 ds717f1 CS42888 analog output charact eristics (commercial) (test conditions (unless otherwise specified): t a =-10 to +70 c; vd = vls = vlc = 3.3 v5%, va = 5 v5%; full-scale 997 hz output sine wave (see note 11 ) into passive filter in figure 31 on page 54 and active filter in fig- ure 31 on page 54 ; measurement bandwidth is 10 hz to 20 khz.) parameter differential min typ max single-ended min typ max unit fs = 48 khz, 96 khz, 192 khz dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 102 99 - - 108 105 99 96 - - - - 99 96 - - 105 102 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -98 -85 -45 -93 -76 -36 -92 - - - - - - - - - - -95 -82 -42 -90 -73 -33 -89 - - - - - db db db db db db interchannel isolation (1 khz) - 100 - - 100 - db analog output full-scale output 1.235?va 1.300?va 1. 365?va 0.618?va 0.650?va 0.683?va vpp interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/c output impedance - 100 - - 100 - ? dc current draw from an aout pin (note 10) - - 10 - - 10 a ac-load resistance (r l ) (note 12) 3--3--k ? load capacitance (c l ) (note 12) - - 100 - - 100 pf
ds717f1 15 CS42888 analog output character istics (automotive) (test conditions (unless otherwise specified): t a = -40 to +85 c; vd = vls = vlc = 3.3 v5%, va = 5 v5%; full-scale 997 hz outp ut sine wave (see note 11 ) in figure 31 on page 54 and figure 31 on page 54 ; measure- ment bandwidth is 10 hz to 20 khz.) notes: 10. guaranteed by design. the dc current draw represen ts the allowed current draw from the aout pin due to typical leakage through the electrolytic dc-blocking capacitors. 11. one-half lsb of triangular pdf dither is added to data. 12. guaranteed by design. see figure 2 . r l and c l reflect the recommended minimum resistance and maximum capacitance required for the in ternal op-amp's stabilit y and signal integrity. in this circuit to- pology, c l will effectively move the domina nt pole of the two-pole amp in the output stage. increasing this value beyond the recommended 100 pf can cause the internal op-amp to become unstable. see ?external filters? on page 51 for a recommended output filter. parameter differential min typ max single-ended min typ max unit fs = 48 khz, 96 khz, 192 khz dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 100 97 - - 108 105 99 96 - - - - 97 94 - - 105 102 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -98 -85 -45 -93 -76 -36 -90 - - - - - - - - - - - -95 -82 -42 -90 -73 -33 -87 - - - - - db db db db db db interchannel isolation (1 khz) - 100 - - 100 - db analog output full-scale output 1.210?va 1.300?va 1.3 92?va 0.605?va 0.650?va 0.696?va vpp interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/c output impedance - 100 - - 100 - ? dc current draw from an aout pin (note 10) --10--10 a ac-load resistance (r l ) (note 12) 3--3--k ? load capacitance (c l ) (note 12) - - 100 - - 100 pf
16 ds717f1 CS42888 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k ? ) l 125 3 20 aoutxx 3.3 f analog output c l + r l dac1-4 agnd figure 2. output test circuit for ma ximum load figure 3. maximum loading
ds717f1 17 CS42888 combined dac interpol ation & on-chip anal og filter response notes: 13. response is clock-dependent and will scale with fs. note that the response plots ( figures 43 to 54 ) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 14. single- and double-speed mode measurement bandwidth is from stopband to 3 fs. quad-speed mode measurement bandwi dth is from stopband to 1.34 fs. 15. de-emphasis is only available in single-speed mode. parameter (notes 8, 13) min typ max unit single-speed mode passband (frequency response) to -0.05 db corner to -3 db corner 0 0 - - 0.4780 0.4996 fs fs frequency response 10 hz to 20 khz -0.2 - +0.08 db stopband 0.5465 - - fs stopband attenuation (note 14) 50 - - db group delay - 10/fs - s de-emphasis error (note 15) fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - +1.5/+0 +0.05/-0.25 -0.2/-0.4 db db db double-speed mode passband (frequency response) to -0.1 db corner to -3 db corner 0 0 - - 0.4650 0.4982 fs fs frequency response 10 hz to 20 khz -0.2 - +0.7 db stopband 0.5770 - - fs stopband attenuation (note 14) 55 - - db group delay - 5/fs - s quad-speed mode passband (frequency response) to -0.1 db corner to -3 db corner 0 0 - - 0.397 0.476 fs fs frequency response 10 hz to 20 khz -0.2 - +0.05 db stopband 0.7 - - fs stopband attenuation (note 14) 51 - - db group delay - 2.5/fs - s
18 ds717f1 CS42888 switching specificatio ns - adc/dac port (inputs: logic 0 = dgnd, logic 1 = vls, adc_sdout c load = 15 pf.) parameters (note 20) symbol min max units slave mode rst pin low pulse width (note 16) 1 -ms mclk frequency 0.512 50 mhz mclk duty cycle (note 17) 45 55 % input sample rate (lrck) single-speed mode double-speed mode (note 18) quad-speed mode (note 19) f s f s f s 4 50 100 50 100 200 khz khz khz lrck duty cycle 45 55 % sclk duty cycle 45 55 % sclk high time t sckh 8-ns sclk low time t sckl 8-ns lrck rising edge to sclk rising edge t fss t lcks 5-ns sclk rising edge to lrck falling edge t fsh 16 - ns sclk falling edge to adc_sdout output valid t dpd -35ns dac_sdin setup time before sclk rising edge t ds 3-ns dac_sdin hold time after sclk rising edge t dh 5-ns dac_sdin hold time after sclk rising edge t dh1 5-ns adc_sdout hold time after sclk rising edge t dh2 10 - ns adc_sdout valid before sclk rising edge t dval 15 - ns master mode output sample rate (l rck) all speed modes f s -mclk / 256khz lrck duty cycle 45 55 % sclk frequency - 64 x fs mhz sclk duty cycle 45 55 % lrck edge to sclk rising edge t lcks -5ns sclk falling edge to adc_sdout output valid t dpd -35ns dac_sdin setup time before sclk rising edge t ds 3-ns dac_sdin hold time after sclk rising edge t dh1 5-ns adc_sdoutx dac_sdinx t ds sclk lrck msb t dh t sckh t sckl t dpd msb t lcks msb-1 msb-1 adc_sdout1 dac_sdin1 t ds sclk (input) lrck (input) msb t dh1 t sckh t sckl t dval msb-1 msb msb-1 t fsh t fss t dh2 figure 4. serial audio interface slave mode ti ming figure 5. tdm serial audio interface timing
ds717f1 19 CS42888 notes: 16. after powering up the CS42888, rst should be held low after the power supplies and clocks are settled. 17. see table 10 on page 42 and table 11 on page 43 for suggested mclk frequencies. 18. when operating in tdm interface format, vls is limited to nominal 2.5 v to 5.0 v operation only. 19. adc - i2s, left-justified, right-justified interface formats only. dac - i2s, left-justified, right-justified and time division multiplexed interface formats only. 20. ?lrck? and ?sclk? shall refer to the adc and dac left/right clock and serial clock, respectively. adc_sdoutx dac_sdinx t ds sclk lrck msb t dh t dpd msb-1 msb msb-1 t lcks figure 6. serial audio interface master mode timing
20 ds717f1 CS42888 switching characte ristics - aux port (inputs: logic 0 = dgnd, logic 1 = vls.) parameters symbol min max units master mode output sample rate (aux _lrck) all speed modes f s - adc_lrck khz aux_sclk frequency - 64 adc_lrck khz aux_sclk duty cycle 45 55 % aux_lrck edge to sclk rising edge t lcks -5ns aux_sdin setup time before sclk rising edge t ds 3-ns aux_sdin hold time after sclk rising edge t dh 5-ns aux_sdin aux_sclk aux_lrck t sckh t sckl t lcks t ds msb t dh msb-1 figure 7. serial audio interface slave mode timing
ds717f1 21 CS42888 switching specifications - control port - i2c mode (vlc = 1.8 v - 5.0 v, vls = vd = 3.3 v, va = 5. 0 v; inputs: logic 0 = dgnd, logic 1 = vlc, sda c l =30pf) notes: 21. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. 22. guaranteed by design. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 21) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda (note 22) t rc -1s fall time scl and sda (note 22) t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t low t hdd t high t sud stop start sda scl t irs rst t hdst t rc t fc t sust t sus p start stop repeated t rd t fd t ack figure 8. control port timing - i2c format
22 ds717f1 CS42888 switching specificat ions - control po rt - spi format (vlc = 1.8 v - 5.0 v, vls = vd = 3.3 v, va = 5.0 v; inputs: logic 0 = dgnd, logic 1 = vlc, cdout c l =30pf) notes: 23. data must be held for sufficient time to bridge the transition time of cclk. 24. for f sck <1 mhz. parameter symbol min max units cclk clock frequency f sck 06.0mhz rst rising edge to cs falling t srs 20 - ns cs falling to cclk edge t css 20 - ns cs high time between transmissions t csh 1.0 - s cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 23) t dh 15 - ns cclk falling to cdout stable t pd -50ns rise time of cdout t r1 -25ns fall time of cdout t f1 -25ns rise time of cclk and cdin (note 24) t r2 - 100 ns fall time of cclk and cdin (note 24) t f2 - 100 ns cs cclk cdin cdout rst t srs t scl t sch t css t r2 t f2 t csh t dsu t dh msb msb t pd figure 9. control port timing - spi format
ds717f1 23 CS42888 dc electrical characteristics (agnd = 0 v; all voltages with respect to ground.) notes: 25. normal operation is defined as rst = hi with a 997 hz, 0 dbfs input to the dac and aux port, and a 1 khz, -1 db analog input to the adc port sampled at the highest f s for each speed mode. dac outputs are open, unless otherwise specified. 26. i dt measured with no external loading on pin 64 (sda). 27. valid with the recommended capa citor values on filt + and vq. increasing the capacitance will also increase the psrr. 28. power-down mode is defined as rst = lo with all clocks and data lines held static and no analog input. 29. guaranteed by design. the dc current draw represents the allowed current draw from the vq pin due to typical leakage through the electrolytic de-coupling capacitors. digital interface specific ations & characteristics notes: 30. see ?digital i/o pin characteristics? on page 8 for serial and control port power rails. parameters symbol min typ max units normal operation (note 25) power supply curr ent va = 5.0 v vls = vlc = vd = 3.3 v (note 26) i a i dt - - 80 60.6 - - ma ma power dissipation all supplies = 5 v - 600 850 mw power supply rejection ratio 1 khz (note 27) 60 hz psrr - - 60 40 - - db db power-down mode (note 28) power dissipation all supplies = va = 5 v - 1.25 - mw vq characteristics nominal voltage output impedance dc current source/sink (note 29) - - - 0.5?va 23 - - - 10 v k ? a filt+_adc nominal voltage filt+_dac nominal voltage - - va va - - v v parameters (note 30) symbol min typ max units high-level output voltage at i o =2 ma serial port control port mutec v oh vls-1.0 vlc-1.0 va-1.0 - - - - - - v v v low-level output voltage at i o =2 ma serial port control port mutec v ol - - - - - - 0.4 0.4 0.4 v v v high-level input voltage serial port control port v ih 0.7xvls 0.7xvlc - - - - v v low-level input voltage serial port control port v il - - - - 0.2xvls 0.2xvlc v v leakage current i in --10 a input capacitance (note 22) - - 10 pf mutec drive current - 3 - ma
24 ds717f1 CS42888 4. applications 4.1 overview the CS42888 is a highly integrated mixed signal 24-bi t audio codec comprised of 4 analog-to-digital con- verters (adc) implemented using multi-bit delta-sigma techniques and 8 digital-to-analog converters (dac) also implemented using multi-bit delta-sigma techniques. other functions integrated within the codec include indep endent digital volume controls for each dac, dig- ital de-emphasis filters for the dac, digital volume control with gain on each adc channel, adc high-pass filters, an on-chip voltage reference, and popguard te chnology that minimizes the effects of output tran- sients on power-up and power-down. all serial data is transmitted through two independent serial ports: the dac serial port and the adc serial port. each serial port can be configured independently to operate at different sample and clock rates, but both must run synchronous to each other. the serial audio interface ports allow up to 8 dac c hannels and 6 adc channels in a time-division multi- plexed (tdm) interface format. in the one-line mode (o lm) interface format, the CS42888 will allow up to 6 adc channels on one data line and up to 8 dac channels on 2 data lines. the CS42888 features an auxiliary port used to ac commodate an additional tw o channels of pcm data on the adc_sdout data line in the tdm digital interface format. see ?aux port digital interface formats? on page 33 for details. the CS42888 operates in one of three oversampling modes based on the input sample rate. when operat- ing the codec as a slave, mode selection is determ ined automatically based on the mclk frequency set- ting. when operating as a master, mode selection is determined by the adc and dac fm bits in register ?functional mode (address 03h)? on page 42 . single-speed mode (ssm) supports input sample rates up to 50 khz and uses a 128x oversampling ratio. doub le-speed mode (dsm) supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad-speed mode (qsm) supports input sample rates up to 200 khz and uses an oversampling ratio of 32x ( note: qsm for the adc is only supported in the i2s, left-justified, right-justified interface formats. qsm for the dac is supported in the i2s, left-justified, right-justified and time division multiplexed interface formats). all functions can be configured through software via a serial control port operable in spi mode or in i2c mode. figure 2 on page 16 shows the recommended connections for the CS42888. see ?register description? on page 40 for the default register settings and options. 4.2 analog inputs 4.2.1 line-level inputs ainx+ and ainx- are the line-level differential analog inputs internally biased to vq, approximately va/2. figure 10 on page 25 shows the full-scale analog input levels. the CS42888 also accommodates single- ended signals on all inputs, ain1-ain4. see ?adc input filter? on page 51 for the recommended input filters. for single-ended operation on adc1-adc2 (ain1 to ain4), the adcx_singl e bit in the register ?adc control & dac de-emphasis (address 05h)? on page 44 must be set appropriately (see figure 26 on page 51 for required external components). the gain/attenuation of the signal can be adj usted for each ainx independently through the ?ainx volume control (address 11h-14h)? on page 48 .
ds717f1 25 CS42888 the adc output data is in 2?s complement binary form at. for inputs above positive full scale or below neg- ative full scale, the adc will output 7fffffh or 800 000h, respectively, and ca use the adc overflow bit in the register ?status (address 19h) (read only)? on page 49 to be set to a ?1?. 4.2.2 high-pass filter and dc offset calibration the high-pass filter continuously su btracts a measure of the dc offset from the output of the decimation filter. if the high-pass filter is disabled during norm al operation, the current va lue of the dc offset for the corresponding channel is fr ozen and this dc offset will continue to be subtracted from the conversion re- sult. this feature makes it possible to pe rform a system dc offset calibration by: 1. running the CS42888 with the high-pass filter enabl ed until the filter settles. see the digital filter characteristics for fi lter settling time. disabling the high-pass filter and fr eezing the stored dc offset.the high-pass filter for adc1/adc2 can be enabled and disabled. the high-pass filters are controlled using the hpf_freeze bit in the register ?adc control & dac de-emphasis (address 05h)? on page 44 . 4.3 analog outputs 4.3.1 initialization the initialization and power-down sequence flow chart is shown in figure 11 on page 26 . the CS42888 enters a power-down state upon initial power-up. th e interpolation and decimation filters, delta-sigma modulators and control port registers are reset. the in ternal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and switched-capacitor low-pass filters are powered down. the device remains in the power-down state until the rst pin is brought high. the control port is acces- sible once rst is high, and the desired register settings can be loaded per the interface descriptions in the ?control port description and timing? on page 33 . once mclk is valid, vq will ramp up to va/2, and the internal voltage references, filt+_adc and filt+_dac, will begin powering up to normal opera tion. power is applied to the d/a converters and switched-capacitor filters, and t he analog outputs are clamped to the quiescent voltage, vq. once lrck is valid, mclk occurrences are counted over one lrck period to determine the mclk/lrck frequency ra- tio. after an approximate 2000 sample period delay, normal operation begins. full-scale differential input level = (ainx+) - (ainx-) = 5.6 v pp = 1.98 v rms ainx+ ainx- 3.9 v 2.5 v 1.1 v 5.0 v 3.9 v 2.5 v 1.1 v va figure 10. full-scale input
26 ds717f1 CS42888 software mode registers setup to desired settings. rst = low? no power 1. vq = ? 2. aout bias = ? 3. no audio signal generated. power-down (power applied) 1. vq = 0 v. 2. aout = vq. 3. no audio signal generated. 4. control port registers reset to default. control port active control port access detected? hardware mode not supported. codec will power up in an unknown state once all clocks and data are valid. it is recommended that the user setup up the codec via the control port before applying mclk. valid mclk applied? no pdn bit = '1'b? sub-clocks applied 1. lrck valid. 2. sclk valid. 3. audio samples processed. valid mclk/lrck ratio? no yes yes no yes no yes yes no normal operation 1. vq = va/2. 2. aout bias = vq. 3. audio signal generated per register settings. analog output freeze 1. vq = va/2. 2. aout bias = vq + last audio sample. 3. dac modulators stop operation. 4. audible pops. analog output mute 1. vq = va/2. 2. aout bias = vq. 3. dac outputs muted. 4. no audio signal generated. error: mclk/lrck ratio change error: mclk removed rst = low pdn bit set to '1'b power-up ramp 1. vq ramp up to va/2. 2. aout bias = vq. 400 ms delay power-down ramp 1. vq ramp down to 0 v. 2. aout bias = vq. 250 ms delay power-down mode 1. vq = 0 v. 2. aout bias = vq. 3. no audio signal generated. 4. control port registers retain settings. 2000 lrck delay popguard ? power-down transition 1. vq = 0 v. 2. aout bias = vq. 3. audible pops. no power transition 1. vq = 0 v. 2. aout bias = vq. 3. audible pops. error: power removed figure 11. audio output initialization flow chart
ds717f1 27 CS42888 4.3.2 output transient control the 42888 uses popguard technology to minimize the effects of output transients during power-up and power-down. this technique eliminates the audio tr ansients commonly produced by single-ended single- supply converters when it is im plemented with external dc-blocking c apacitors connected in series with the audio outputs. to make best use of this feature, it is necessary to understand its operation. see ?pop- guard? on page 27 for details. a mute control pin is also available for use with an optional mute circuit to mask output transients on the analog outputs. see ?mute control? on page 27 for details. when changing clock ratio or sample rate, it is recommended that zero data (or near zero data) be present on dac_sdinx for at least 10 lrck samples before the change is made. during the clocking change, the dac outputs will always be in a zero -data state. if no zero audio is pr esent at the time of switching, a slight click or pop may be heard as the dac out put automatically goes to its zero-data state. 4.3.3 popguard 4.3.3.1 power-up when the device is initially powered up, the audio ou tputs, aoutxx, are clamped to vq which is initially low. after the rst pin is brought high and mclk is applied, the outputs begin to ramp with vq towards the nominal quiescent voltage. this ramp takes ap proximately 400 ms to complete. the gradual voltage ramping allows time for the external dc-blocking capaci tors to charge to vq, effectively blocking the qui- escent dc voltage. once valid dac_lrck, dac_ sclk and dac_sdinx are applied, audio output be- gins approximately 2000 sample periods later. 4.3.3.2 power-down to prevent audio transients at power-down, the dc-blocking capacitors must fully discharge before turn- ing off the power. in order to do this, the pdn bit in register ?power control (address 02h)? on page 41 must be set to ?1? for a period of about 250 ms before removing power. during this time, voltage on vq and the audio outputs discharge gradu ally to agnd. if power is removed before this 250 ms time period has passed, a transient will occur when the va supply drops below that of vq. there is no minimum time for a power cycle. power may be re-applied at any time. 4.3.4 mute control the mute control pin, mutec, is ty pically connected to an external mute control circuit. the use of ex- ternal mute circuits is not mandatory, but may be desired for designs requiring the absolute minimum in extraneous clicks and pops. mutec is in high-impedance mode during power up or when the 42888 is in power-down mode by set- ting the pdn bit in the register ?power control (address 02h)? on page 41 to a ?1?. once out of power- down mode, the pin can be controlled by the user via the control port (see ?mutec pin control (address 1bh)? on page 50 ) or automatically asserted to the active state when zero data is present on all dac in- puts, when all dac outputs are muted, or when serial port clock errors occur. to prevent large transients on the output, it is recommended to mute the dac outputs before the mute control pin is asserted.
28 ds717f1 CS42888 4.3.5 line-level outputs and filtering the CS42888 contains on-chip buffer amplifiers capable of producing line-level differential as well as sin- gle-ended outputs on aout1-aout8. these amplifiers are biased to a quiescent dc level of approxi- mately vq. the delta-sigma conversion process produces high- frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. the remaining out-of-band noise can be attenuated using an off-chip low-pass filter. see ?dac output filter? on page 53 for recommended output filter. the ac tive filter configuration accounts for the normally differing ac loads on the aoutx+ and aoutx- differential output pins. also shown is a passive filter configuration which minimizes costs and the number of components. figure 12 shows the full-scale analog output levels. all out puts are internally biased to vq, approximately va/2. 4.3.6 digital volume control each dac?s output level is contro lled via the volume control registers operating over the range of 0 to -127.5 db attenuation with 0.5 db resolution. see ?aoutx volume control (addresses 08h- 0fh)? on page 47 . volume control changes are programmable to ramp in increments of 0.125 db at the rate con- trolled by the szc[1:0] bits in the digital volume cont rol register. see ?transition contro l (address 06h)? on page 45 . each output can be independently muted via mute control bits in the register ?dac channel mute (ad- dress 07h)? on page 47 . when enabled, each aoutx_mute bit attenuates the corresponding dac to its maximum value (-127.5 db). when the aoutx_mute bit is disabled, the corresponding dac returns to the attenuation level set in the volume control register. the attenuation is ramped up and down at the rate specified by the szc[1:0] bits. 4.3.7 de-emphasis filter the CS42888 includes on-chip digital de-emphasis optimi zed for a sample rate of 44.1 khz. the filter re- sponse is shown in figure 13 . the de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. aoutx+ aoutx- full-scale differential output level = (aoutx+) - (aoutx-) = 6.5 v pp = 2.3 v rms 4.125 v 2.5 v 0.875 v 5.0 v 4.125 v 2.5 v 0.875 v va figure 12. full-scale output
ds717f1 29 CS42888 de-emphasis is only available in single-speed mode. please see ?dac de-emphasis control (dac_dem)? on page 45 for de-emphasis control. 4.4 system clocking the codec (adc & dac) serial audio interface ports ope rate both as a slave or master. the serial ports accept externally generated clocks in slave mode and will generate synchronous cloc ks derived from an in- put master clock in master mode. in the tdm format the adc and dac serial ports will only operate as a slave. in olm #2 the serial ports will accept or output a 256fs sclk. see the registers ?dac functional mode (dac_fm[1:0])? on page 42 and ?adc functional mode (adc_fm[1:0])? on page 42 for setting up master/slave mode. the codec requires external generation of the master clock (mclk). the frequency of this clock must be an integer multiple of, and synchronous with, the system sample rate, fs. the required integer ratios, al ong with some common frequencies, are illu strated in tables tables 2 to 4 . the frequency range of mclk must be specified using the mfreq bits in register ?mclk frequency (mfreq[2:0])? on page 42 . sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 table 2. single-speed mode common frequencies sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22. 5792 33.8688 45.1584 96 12.2880 18.4320 24. 5760 36.8640 49.1520 table 3. double-speed mode common frequencies sample rate (khz) mclk (mhz) 64x 96x 128x 192x 256x 176.4 11.2896 16.9344 2 2.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 table 4. quad-speed mode common frequencies gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183khz 10.61khz figure 13. de-emphasis curve
30 ds717f1 CS42888 4.5 codec digital interface formats the adc and dac serial ports support the i2s, left -justified, right-justified, one-line mode (olm) and tdm digital interface formats with varying bit depths from 16 to 32 as shown in figures 15 - 19 . data is clocked out of the adc on the falling edge of sclk and clocked into the dac on the rising edge. the serial bit clock, dac_sclk and/or adc_sclk, must be synchronously derived from the master clock and be equal to 256x, 128x, 64x, 48x or 32x fs, depending on the interface format selected and desired speed mode. one-line mode #1 and one-line mode #2 will operate in master or slave mode. refer to table 5 for required clock ratios. the sclk to sample rate (lrck) ratios are shown in tables 5 through 8 . i2s, left-justified, right-justified ratio ssm dsm qsm mclk/lrck 256x, 384x, 512x, 768x, 1024x 128x, 192x, 256x, 384x, 512x 64x, 96x, 128x, 192x, 256x sclk/lrck (slave mode) 32x, 48x, 64x 32x, 48x, 64x 32x, 48x, 64x sclk/lrck (master mode) 64x 64x 64x table 5. i2s, lj, rj clock ratios olm #1 ssm dsm qsm mclk/lrck 256x, 384x, 512x, 768x, 1024x 256x, 384x, 512x n/a sclk/lrck (slave mode) 128x 128x n/a sclk/lrck (master mode) 128x 128x n/a table 6. olm#1 clock ratios olm #2 ssm dsm qsm mclk/lrck 256x, 384x, 512x, 768x, 1024x 256x, 384x, 512x n/a sclk/lrck (slave mode) 256x 256x n/a sclk/lrck (master mode) 256x 256x n/a table 7. olm#2 clock ratios tdm ssm dsm qsm (dac only) mclk/lrck 256x, 384x, 512x, 768x, 1024x 256x, 384x, 512x 256x sclk/lrck (slave mode) 256x 256x 256x sclk/lrck (master mode) n/a n/a n/a table 8. tdm clock ratios
ds717f1 31 CS42888 4.5.1 i2s 4.5.2 left-justified 4.5.3 right-justified 4.5.4 olm #1 olm #1 serial audio inte rface format operat es in single- or double-spee d mode only and will master or slave adc/dac_sclk at 128 fs. adc/dac_lrck adc/dac_sclk msb lsb msb lsb aout 1, 3, 5 or 7 left channel right channel adc_sdoutx dac_sdinx aout 2, 4, 6 or 8 msb ain 1 or 3 ain 2 or 4 figure 14. i2s format adc/dac_lrck adc/dac_sclk msb lsb msb lsb aout 1, 3, 5 or 7 left channel right channel adc_sdoutx dac_sdinx aout 2, 4, 6 or 8 msb ain 1 or 3 ain 2 or 4 figure 15. left-justified format adc/dac_lrck adc/dac_sclk msb lsb msb lsb aout 1, 3, 5 or 7 left channel right channel adc_sdoutx dac_sdinx aout 2, 4, 6 or 8 ain 1 or 3 ain 2 or 4 figure 16. righ t-justified format adc/dac_lrck adc/dac_sclk lsb msb 20 clks 64 clks 64 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb 20 clks 20 clks 20 clks 20 clks 20 clks left channel right channel 20 clks ain1 20 clks 20 clks 20 clks 20 clks 20 clks adc_sdout1 dac_sdin1 20 clks aout7 aout1 aout3 aout5 aout2 aout4 aout6 20 clks aout8 dac_sdin4 ain3 - ain2 ain4 - figure 17. one-line mode #1 format
32 ds717f1 CS42888 4.5.5 olm #2 olm #2 serial audio interface form at operates in single- or double- speed mode and will master or slave adc/dac_sclk at 256fs. 4.5.6 tdm tdm data is received most significant bit (msb) firs t, on the second rising edge of the dac_sclk occur- ring after a dac_lrck rising edge. all data is valid on the rising edge of dac_sclk. the ain1 msb is transmitted early, but is guaranteed valid for a specifie d time after sclk rises. all other bits are transmit- ted on the falling edge of adc_sclk. ea ch time slot is 32 bits wide, wi th the valid data sample left ?jus- tified within the time slot. valid data lengths are 16, 18, 20, or 24. adc/dac_sclk must operate at 256fs. adc/dac_lrck identifies the start of a new frame and is equal to the sample rate, fs. adc/dac_lrck is sampled as valid on the rising adc/dac_sclk ed ge preceding the most significant bit of the first data sample and must be hel d valid for at least 1 adc/dac_sclk period. note: the adc does not meet the timing requirements for proper operation in quad-speed mode. adc/dac_lrck adc/dac_sclk lsb msb 24 clks 128 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb 24 clks 24 clks 24 clks 24 clks 24 clks left channel right channel 24 clks ain1 24 clks 24 clks 24 clks 24 clks 24 clks adc_sdout1 dac_sdin1 24 clks aout7 aout1 aout3 aout5 aout2 aout4 aout6 24 clks aout8 dac_sdin4 ain3 - ain2 ain4 - 128 clks figure 18. one-line mode #2 format aout6 adc/dac_sclk lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb dac_sdin1 aout1 aout4 aout2 aout5 aout3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks aout8 lsb msb lsb msb aout7 32 clks 32 clks adc/dac_lrck 256 clks msb bit or word wide lsb - lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb adc_sdout1 ain1 ain4 ain2 - ain3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks aux2 lsb msb lsb msb aux1 32 clks 32 clks msb figure 19. tdm format
ds717f1 33 CS42888 4.5.7 i/o channel allocation 4.6 aux port digital interface formats these serial data lines are used when supporting the tdm mode of operation with an external adc or s/pdif receiver atta ched. the aux serial port operates only as a clock master. the aux_sclk will operate at 64xfs, where fs is equal to the adc sample rate (adc_lrck). if the aux_sdin signal is not being used, it should be tied to agnd via a pull-down resistor. the aux port will operate in either th e left-justified or i2s digital inte rface format with bit depths ranging from 16 to 24 bits. settings for the aux port are made through the register ?interface formats (address 04h)? on page 43 . 4.6.1 i2s 4.6.2 left-justified 4.7 control port description and timing the control port is used to access the registers a llowing the CS42888 to be configured for the desired op- erational modes and formats. the operation of the cont rol port may be complete ly asynchronous with re- spect to the audio sample rates. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port has two modes: spi and i2c, with the CS42888 acting as a slave device. spi mode is se- lected if there is a high-to-low transition on the ad0/cs pin, after the rst pin has been brought high. i2c mode is selected by connecting the ad0/cs pin through a resistor to vlc or dgnd, thereby permanently selecting the desired ad0 bit address state. digital input/output interface format analog output/input channel allocation from/to digital i/o dac_sdin1 i2s, lj, rj olm tdm aout 1,2 aout 1,2,3,4,5,6 aout 1,2,3,4,5,6,7,8 adc_sdout1 i2s, lj, rj olm tdm ain 1,2 ain 1,2,3,4 ain 1,2,3,4 (2 additional channels from aux_sdin) table 9. serial audio interface channel allocations aux_lrck aux_sclk msb lsb msb lsb aux1 left channel right channel aux_sdin aux2 msb figure 20. aux i2s format aux_lrck aux_sclk msb lsb msb lsb aux1 left channel right channel aux_sdin aux2 msb figure 21. aux left-justified format
34 ds717f1 CS42888 4.7.1 spi mode in spi mode, cs is the CS42888 chip-select signal, cclk is the control port bit clock (input into the CS42888 from the microcontroller), cdin is the inpu t data line from the microcontroller, cdout is the output data line to the microcontrolle r. data is clocked in on the risi ng edge of cclk and out on the falling edge. figure 22 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and mu st be 1001111. the eighth bit is a read/write indi- cator (r/w ), which should be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next eight bits are the data which will be placed into the register designated by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k ? resistor, if desired. there is a map auto-incremen t capability, enabled by the incr bit in the map register. if incr is a zero, the map will stay constant for successi ve read or writes. if incr is se t to a 1, the map will auto-increment after each byte is read or wr itten, allowing block reads or writes of successive registers. to read a register, the map has to be set to the co rrect address by executing a partial write cycle which finishes (cs high) immediately after the map byte. the map auto-increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). if the map auto-incr ement bit is set to 1, the data for successive registers will appear consecutively. 4.7.2 i2c mode in i2c mode, sda is a bidirectional da ta line. data is clocke d into and out of the pa rt by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two least-si gnificant bits of the chip address and should be connected through a resistor to vlc or dgnd as de sired. the state of the pins is sensed while the CS42888 is being reset. the signal timings for a read and write cycle are shown in figure 23 and figure 24 . a start condition is defined as a falling transition of sda while the clock is high. a stop condition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the CS42888 after a start condition consists of a 7-bit chip address field and a r/w bit (high for a read, low map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 1001111 1001111 map = memory address pointer, 8 bits, msb first high impedance figure 22. control port timing in spi mode
ds717f1 35 CS42888 for a write). the upper 5 bits of the 7-bit address fi eld are fixed at 10010. to communicate with a CS42888, the chip address field, which is the first byte sent to the CS42888, should match 10010 followed by the settings of the ad1 and ad0. the ei ghth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address poin ter (map) which selects the register to be read or written. if the op- eration is a read, the conten ts of the register pointe d to by the map will be outp ut. setting the auto-incre- ment bit in map allows successive re ads or writes of consecutive regist ers. each byte is separated by an acknowledge bit. the ack bit is output from the cs4288 8 after each input byte is read, and is input to the CS42888 from the microcontroller after each transmitted byte. since the read operation c annot set the map, an aborted write operation is used as a preamble. as shown in figure 24 , the write operation is aborted after the ackno wledge for the map byte by sending a stop con- dition. the following pseudocode illu strates an aborted wr ite operation followed by a read operation. send start condition. send 10010xx0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 10010xx1(chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto-increment bit in the map allows succes sive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 ad1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 23. control port timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 ad1 ad0 0 sda 1 0 0 1 0 ad1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 24. control port timing, i2c read
36 ds717f1 CS42888 4.8 interrupts the 42888 has a comp rehensive interrup t capability. the int output pin is intended to dr ive the interrupt input pin on the host microcontroller. the int pin may be configured as an active low or active high cmos driver or an open-drain driver. this last mode is us ed for active low, wired-or hook-ups, with multiple pe- ripherals connected to the microcontroller interrupt input pin. many conditions can cause an interrupt, as listed in the interrupt status register descriptions. see ?status (address 19h) (read only)? on page 49 . each source may be ma sked off through mask register bits. in ad- dition, each source may be set to ri sing edge, falling edge, or level sens itive. combined wi th the option of level sensitive or edge sensitive modes within the microcontroller, many different configurations are possi- ble, depending on the needs of the system designer. 4.9 recommended power-up sequence 1. hold rst low until the power supply and clocks are stable. in this state, the control port is reset to its default settings and vq will remain low. 2. bring rst high. the device will initially be in a low power state with vq low. all featur es will default as described in the ?register quick reference? on page 38 . 3. perform a write operation to the power control register ( ?power control (address 02h)? on page 41 ) to set bit 0 to a ?1?b. this will place the device in a power down state. 4. load the desired register settings wh ile keeping the pdn bit set to ?1?b. 5. mute all dacs. muting the dacs suppresses any nois e associated with the code c's first initialization after power is applied. 6. set the pdn bit in the power cont rol register to ?0?b. vq will ramp to approximately va/2 according to the popguard specification in section ?popguard? on page 27 . 7. following approximately 2000 lrck cycles, the devi ce is initialized and re ady for normal operation. 8. after the codec is initialized, wait ~90 lrck cycles (~1.9 ms @48 khz) and then unmute the dacs. 9. normal operation begins. 4.10 reset and power-up it is recommended that reset be activated if the anal og or digital supplies drop below the recommended op- erating condition to prevent power-glitch-related issues. the delta-sigma modulators settle in a matter of mi croseconds after the analog section is powered, either through the application of power or by setting the rst pin high. however, the voltage reference will take much longer to reach a final value due to the pres ence of external capacita nce on the adc/dac_filt+ pins. a time delay of approximately 400 ms is required after applying power to the device or after exiting a reset state. during this voltage re ference ramp delay, all serial port s and dac outputs will be automatically muted. 4.11 power supply, gr ounding, and pcb layout as with any high-resolution converter, the CS42888 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figure 2 shows the recommended power ar- rangements, with va connected to clean supplies. vd, which powers the digital circuitry, may be run from the system logic supply. alternatively, vd may be powered from the analog supply via a ferrite bead. in this case, no additional devices should be powered from vd. extensive use of power and ground planes, ground plane fill in un used areas and surf ace mount decoupling capacitors are recommended. decoupling capacitors shoul d be as near to the pins of the CS42888 as pos- sible. the low value ceramic capacitor should be the nearest to the pin and should be mounted on the same
ds717f1 37 CS42888 side of the board as the CS42888 to minimize inductance effects. all signals, especially clocks, should be kept away from the adc/dac_filt+, vq pins in orde r to avoid unwanted coupling into the modulators. the adc/dac_filt+ and vq decoupling capacitors, particular ly the 0.1 f, must be positioned to minimize the electrical path from adc/dac_filt+ and agnd. the cdb42448 evaluation board demonstrates the opti- mum layout and power supply arrangements. for optimal heat dissipation from the package, it is recommended that the area directly under the part be filled with copper and tied to the ground plan e. the use of vias co nnecting the topside ground to the back- side ground is also recommended.
38 ds717f1 CS42888 5. register qu ick reference note : the default value in all ?reserved? registers must be preserved. addr function 76543210 01h id chip_id3 chip_id2 chip_id1 chi p_id0 rev_id3 rev_id2 rev_id1 rev_id0 p40 default 0 0 0 0 0 0 0 1 02h power con- trol reserved pdn_adc2 pdn_adc1 pdn_da c4 pdn_dac3 pdn_dac2 pdn_dac1 pdn p41 default 0 0 0 0 0 0 0 0 03h functional mode dac_fm1 dac_fm0 adc_fm1 adc_fm0 mfreq2 mfreq1 mfreq0 reserved p42 default 1 1 1 1 0 0 0 0 04h interface formats freeze aux_dif dac_dif2 dac_dif1 dac_dif0 adc_dif2 adc_dif1 adc_dif0 p43 default 0 0 1 1 0 1 10 05h adc control (w/dac_dem) adc1-2_hpf freeze reserved dac_dem adc1 single adc2 single reserved reserved reserved p44 default 0 0 0 0 0 0 0 0 06h transition control dac_sng vol dac_szc1 dac_szc0 amute mute adc_sp adc_sng vol adc_szc1 adc_szc0 p45 default 0 0 0 1 0 0 0 0 07h channel mute aout8 mute aout7 mute aout6 mute aout5 mute aout4 mute aout3 mute aout2 mute aout1 mute p47 default 0 0 0 0 0 0 0 0 08h vol. control aout1 aout1 vol7 aout1 vol6 aout1 vol5 aout1 vol4 aout1 vol3 aout1 vol2 aout1 vol1 aout1 vol0 p47 default 0 0 0 0 0 0 0 0 09h vol. control aout2 aout2 vol7 aout2 vol6 aout2 vol5 aout2 vol4 aout2 vol3 aout2 vol2 aout2 vol1 aout2 vol0 p47 default 0 0 0 0 0 0 0 0 0ah vol. control aout3 aout3 vol7 aout3 vol6 aout3 vol5 aout3 vol4 aout3 vol3 aout3 vol2 aout3 vol1 aout3 vol0 p47 default 0 0 0 0 0 0 0 0 0bh vol. control aout4 aout4 vol7 aout4 vol6 aout4 vol5 aout4 vol4 aout4 vol3 aout4 vol2 aout4 vol1 aout4 vol0 p47 default 0 0 0 0 0 0 0 0 0ch vol. control aout5 aout5 vol7 aout5 vol6 aout5 vol5 aout5 vol4 aout5 vol3 aout5 vol2 aout5 vol1 aout5 vol0 p47 default 0 0 0 0 0 0 0 0 0dh vol. control aout6 aout6 vol7 aout6 vol6 aout6 vol5 aout6 vol4 aout6 vol3 aout6 vol2 aout6 vol1 aout6 vol0 p47 default 0 0 0 0 0 0 0 0 0eh vol. control aout7 aout7 vol7 aout7 vol6 aout7 vol5 aout7 vol4 aout7 vol3 aout7 vol2 aout7 vol1 aout7 vol0 p47 default 0 0 0 0 0 0 0 0 0fh vol. control aout8 aout8 vol7 aout8 vol6 aout8 vol5 aout8 vol4 aout8 vol3 aout8 vol2 aout8 vol1 aout8 vol0 p47 default 0 0 0 0 0 0 0 0 10h dac chan- nel invert inv_aout8 inv_aout7 inv_aout6 inv_aout5 inv_aout4 inv_aout3 inv_aout2 inv_aout1 p48 default 0 0 0 0 0 0 0 0
ds717f1 39 CS42888 11h vol. control ain1 ain1 vol7 ain1 vol6 ain1 vol5 ain1 vol4 ain1 vol3 ain1 vol2 ain1 vol1 ain1 vol0 p47 default 0 0 0 0 0 0 0 0 12h vol. control ain2 ain2 vol7 ain2 vol6 ain2 vol5 ain2 vol4 ain2 vol3 ain2 vol2 ain2 vol1 ain2 vol0 p48 default 0 0 0 0 0 0 0 0 13h vol. control ain3 ain3 vol7 ain3 vol6 ain3 vol5 ain3 vol4 ain3 vol3 ain3 vol2 ain3 vol1 ain3 vol0 p47 default 0 0 0 0 0 0 0 0 14h vol. control ain4 ain4 vol7 ain4 vol6 ain4 vol5 ain4 vol4 ain4 vol3 ain4 vol2 ain4 vol1 ain4 vol0 p48 default 0 0 0 0 0 0 0 0 15h reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 16h reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 17h adc chan- nel invert reserved reserved reserved rese rved inv_a4 inv_a3 inv_a2 inv_a1 p48 default 0 0 0 0 0 0 0 0 18h status con- trol reserved reserved reserved reserved int1 int0 reserved reserved p49 default 0 0 0 0 0 0 0 0 19h status reserved reserved reserved dac_clk error adc_clk error reserved adc2 ovfl adc1 ovfl p49 default 0 0 0 x x x x x 1ah status mask reserved reserved reserved dac_clk error_m adc_clk error_m reserved adc2 ovfl_m adc1 ovfl_m p50 default 0 0 0 0 0 0 0 0 addr function 76543210
40 ds717f1 CS42888 6. register description all registers are read/write except for the i.d. and revisi on register and interrupt status register which are read only. see the following bit-definition tables for bit assignme nt information. the default state of each bit after a power- up sequence or reset is listed in each bit description. 6.1 memory address pointer (map) not a register 6.1.1 increment (incr) default = 1 function: memory address pointer auto increment control 0 - map is not incremented automatically. 1 - internal map is automatically incremented after each read or write. 6.1.2 memory address pointer (map[6:0]) default = 0000001 function: memory address pointer (map) . sets the register address that will be read or written by the control port. 6.2 chip i.d. and revision re gister (address 01h) (read only) 6.2.1 chip i.d. (chip_id[3:0]) default = 0000 function: i.d. code for the CS42888. permanently set to 0000. 6.2.2 chip revision (rev_id[3:0]) default = 0001 function: CS42888 revision level. revision a is coded as 0001. 76543210 incr map6 map5 map4 map3 map2 map1 map0 76543210 chip_id3 chip_id2 chip_id1 chip_id0 rev_id3 rev_id2 rev_id1 rev_id0
ds717f1 41 CS42888 6.3 power control (address 02h) 6.3.1 power down ad c pairs (pdn_adcx) default = 0 0 - disable 1 - enable function: when enabled, the respective adc channel pair (a dc1 - ain1/ain2; and adc2 - ain3/ain4) will remain in a reset state. 6.3.2 power down da c pairs (pdn_dacx) default = 0 0 - disable 1 - enable function: when enabled, the respective dac channel pair (dac1 - aout1/aout2; da c2 - aout3/aout4; dac3 - aout5/aout6; and dac4 - aout7/aout8) will remain in a reset state. it is advised that any change of these bits be made while the dacs are muted or th e power down bit (pdn) is enabled to eliminate the possibility of audible artifacts. 6.3.3 power down (pdn) default = 0 0 - disable 1 - enable function: the entire device will enter a low-pow er state when this function is en abled. the contents of the control registers are retained in this mode. 76543210 reserved pdn_adc2 pdn_adc1 pdn_dac4 pdn_dac3 pdn_dac2 pdn_dac1 pdn
42 ds717f1 CS42888 6.4 functional mode (address 03h) 6.4.1 dac functional mode (dac_fm[1:0]) default = 11 master mode 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 200 khz sample rates) slave mode 11 - (auto-detect sample rates) function: selects the required range of sample rates for the dac serial port. 6.4.2 adc functional mode (adc_fm[1:0]) default = 11 master mode 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 200 khz sample rates) slave mode 11 - (auto-detect sample rates) function: selects the required range of sample rates for the adc serial port. 6.4.3 mclk frequency (mfreq[2:0]) default = 000 function: sets the appropriate frequency for the supplied mclk. for tdm and olm #2 operation, adc/dac_sclk must equal 256fs. for olm #1 operation, adc/dac_ sclk must equal 128fs. mclk can be equal to or greater than the higher frequency of adc_sclk or dac_sclk. 76543210 dac_fm1 dac_fm0 adc_fm1 adc_fm0 mfreq2 mfreq1 mfreq0 reserved ratio (xfs) mfreq2 mfreq1 mfreq0 description ssm dsm qsm 000 1.0290 mhz to 12.8000 mhz 256 128 64 001 1.5360 mhz to 19.2000 mhz 384 192 96 010 2.0480 mhz to 25.6000 mhz 512 256 128 011 3.0720 mhz to 38.4000 mhz 768 384 192 1xx 4.0960 mhz to 51.2000 mhz 1024 512 256 table 10. mclk frequency settings for i 2 s, left and right justified interface formats
ds717f1 43 CS42888 6.5 interface formats (address 04h) 6.5.1 freeze controls (freeze) default = 0 function: this function will freeze the previous settings of, and allow modification s to be made to the channel mutes, the dac and adc volume control/chan nel invert registers without the changes taking effect until the freeze is disabled. to have multiple changes in these control port registers take effect simultaneously, enable the freeze bit, make all register changes, then disable the freeze bit. 6.5.2 auxiliary digital interface format (aux_dif) default = 0 0 - left justified 1 - i2s function: this bit selects the digital interf ace format used for the aux serial port. the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 22 - 23 . 6.5.3 dac digital interfa ce format (dac_dif[2:0]) default = 110 function: these bits select the digital interface format used fo r the dac serial port. the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format; the options are detailed in the section ?codec digital interface formats? on page 30 . refer to table 9, ?serial audio interface channel allocations,? on page 33 . ratio (xfs) mfreq2 mfreq1 mfreq0 de scription ssm dsm qsm 000 1.0290 mhz to 12.8000 mhz 256 n/a n/a 001 1.5360 mhz to 19.2000 mhz 384 n/a n/a 010 2.0480 mhz to 25.6000 mhz 512 256 n/a 011 3.0720 mhz to 38.4000 mhz 768 384 n/a 1xx 4.0960 mhz to 51.2000 mhz 1024 512 256 table 11. mclk frequency settings for tdm & olm interface formats 76543210 freeze aux_dif dac_dif2 dac_dif1 dac_dif0 adc_dif2 adc_dif1 adc_dif0 dac_dif2 dac_dif1 dac_dif0 description format figure 00 0 left justified, up to 24-bit data 0 figure 15 00 1 i2s, up to 24-bit data 1 figure 14 01 0 right justified, 24-bit data 2 figure 16 table 12. dac digital interface formats
44 ds717f1 CS42888 6.5.4 adc digital interface format (adc_dif[2:0]) default = 110 function: these bits select the digital interface format used fo r the adc serial port. the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in the section ?codec digital interface formats? on page 30 . refer to table 9, ?serial audio interface channel allocations,? on page 33 . note: the adc does not meet quad-speed mode timing specifications in the tdm interface format. 6.6 adc control & dac de-e mphasis (address 05h) 6.6.1 adc1-2 high-pass filter freeze (adc1-2_hpf freeze) default = 0 function: when this bit is set, th e internal high-pass filter will be disabled for adc1 and adc2.the current dc offset value will be frozen and contin ue to be subtracted from the conversion result. see ?adc digital filter characteristics? on page 13 . 01 1 right justified, 16-bit data 3 figure 16 10 0 one-line #1, 20-bit 4 figure 17 10 1 one-line #2, 24-bit 5 figure 18 11 0 tdm mode, 24-bit (slave only) 6 figure 19 11 1 reserved -- adc_dif2 adc_dif1 adc_dif0 description format figure 000 left justified, up to 24-bit data 0 figure 15 001 i2s, up to 24-bit data 1 figure 14 010 right justified, 24-bit data 2 figure 16 011 right justified, 16-bit data 3 figure 16 100 one-line #1, 20-bit 4 figure 17 101 one-line #2, 24-bit 5 figure 18 110 tdm mode, 24-bit (slave only) 6 figure 19 111 reserved -- table 13. adc digital interface formats 76543210 adc1-2_hpf freeze reserved dac_dem adc1 single adc2 single reserved reserved reserved dac_dif2 dac_dif1 dac_dif0 description format figure table 12. dac digital interface formats
ds717f1 45 CS42888 6.6.2 dac de-emphasi s control (dac_dem) default = 0 0 - no de-emphasis 1 - de-emphasis enabled (auto-detect fs) function: enables the digital filter to maintain the standard 15 s/50 s digital de-emphasis f ilter response at the auto-detected sa mple rate of either 32, 44.1, or 48 khz. de-emphasis will not be enabled, regardless of this register setting, at any other sample rate. 6.6.3 adc1 single-ended mode (adc1 single) default = 0 0 - disabled; differential input to adc1 1 - enabled; single-ended input to adc1 function: when enabled, this bit allows the user to apply a si ngle-ended input to the positive terminal of adc1. a +6 db digital gain is automatically applied to the serial audio data of adc1. the negative leg must be driv- en to the common mode of the adc. see figure 26 on page 51 for a graphical description. 6.6.4 adc2 single-ended mode (adc2 single) default = 0 0 - disabled; differential input to adc2 1 - enabled; single-ended input to adc2 function: when enabled, this bit allows the user to apply a si ngle-ended input to the positive terminal of adc2. a +6 db digital gain is automatically applied to the serial audio data of adc2. the negative leg must be driv- en to the common mode of the adc. see figure 26 on page 51 for a graphical description. 6.7 transition control (address 06h) 6.7.1 single volume contro l (dac_sngvol, adc_sngvol) default = 0 function: the individual channel volume levels are independently controlled by their respec tive volume control reg- isters when this function is disabled. when enabled , the volume on all channels is determined by the aout1 and ain1 volume control register and the other volume control registers are ignored. 7654 3 210 dac_sngvol dac_szc1 dac_szc0 amute mute adc_sp adc_sngvol adc_szc1 adc_szc0
46 ds717f1 CS42888 6.7.2 soft ramp and zero cross control (adc_szc[1:0], dac_szc[1:0]) default = 00 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: immediate change when immediate change is selected, all volume-level changes will take effect immediately in one step. zero cross zero cross enable dictates that signal level changes , either by gain changes, attenuation changes or mut- ing, will occur on a signal zero crossi ng to minimize audible artifacts. the requested le vel change will oc- cur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing . the zero cross function is independently monitored and implemented for each channel. soft ramp soft ramp allows level changes, either by gain chang es, attenuation changes or muting, to be implement- ed by incrementally ramping, in 1/8 db steps, from the current level to th e new level at a rate of 1 db per 8 left/right clock periods. soft ramp on zero crossing soft ramp and zero cross enable dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur in 1/ 8 db steps and be implemented on a signal zero cro ssing. the 1/8 db level change will occu r after a timeout period be tween 512 and 1024 sa mple periods (10. 7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encoun ter a zero crossing. the zero cross function is inde- pendently monitored and implemented for each channel. 6.7.3 auto-mute (amute) default = 1 0 - disabled 1 - enabled function: the digital-to-analog conv erters of the CS42888 will mute the outp ut following the rece ption of 8192 con- secutive audio samples of static 0 or -1. a single sa mple of non-static data will release the mute. detection and muting is done indep endently for each channel. the quiescent voltage on the outp ut will be retained and the mutec pin will go active during the mute period . the muting function is affected, similar to vol- ume control changes, by the soft and zero cross bits (szc[1:0]).
ds717f1 47 CS42888 6.7.4 mute adc serial port (mute adc_sp) default = 0 0 - disabled 1 - enabled function: when enabled, the adc se rial port will be muted. 6.8 dac channel mute (address 07h) 6.8.1 independent channel mute (aoutx_mute) default = 0 0 - disabled 1 - enabled function: the respective digital-to-analog converter outputs of the CS42888 will mute when enabled. the quies- cent voltage on the outputs will be retained. the muting function is affected by the dac soft and zero cross bits (dac_szc[1:0]). when all channel s are muted, the mutec pin will become active. 6.9 aoutx volume control (a ddresses 08h- 0fh) 6.9.1 volume contro l (aoutx_vol[7:0]) default = 00h function: the aoutx volume control registers allow independent setting of the signal levels in 0.5 db increments from 0 db to -127.5 db. volume settings are decoded as shown in table 14 . the volume changes are implemented as dictated by the soft and zero cross bits (dac_szc[1:0]). all volume settings less than -127.5 db are equivalent to enabling the aoutx_mute bit for the given channel. 76543210 aout8_mute aout7_mute aout6_mute aout5_mute aout4_mute aout3_mute aout2_mute aout1_mute 76543210 aoutx_vol7 aoutx_vol6 aoutx_vol5 aoutx_vol4 aoutx_vol3 aoutx_vol2 aoutx_vol1 aoutx_vol0 binary code volume setting 00000000 0 db 00101000 -20 db 01010000 -40 db 01111000 -60 db 10110100 -90 db table 14. example aout volume settings
48 ds717f1 CS42888 6.10 dac channel invert (address 10h) 6.10.1 invert signal polarity (inv_aoutx) default = 0 0 - disabled 1 - enabled function: when enabled, these bits will invert the sign al polarity of their respective channels. 6.11 ainx volume control (address 11h-14h) 6.11.1 ainx volume c ontrol (ainx_ vol[7:0]) default = 00h function: the level of ain1 - ain6 can be adjusted in 0.5 db increments as dictated by the adc soft and zero cross bits (adc_szc[1:0]) from +24 to -64 db. levels are decoded in two?s complement, as shown in table 15 . 6.12 adc channel invert (address 17h) 76543210 inv_aout8 inv_aout7 inv_aout6 inv_aout5 inv_aout4 i nv_aout3 inv_aout2 inv_aout1 76543210 ainx_vol7 ainx_vol6 ainx_vol5 ainx_vol4 ainx_vol3 ainx_vol2 ainx_vol1 ainx_vol0 binary code volume setting 0111 1111 +24 db 0011 0000 +24 db 0000 0000 0 db 1111 1111 -0.5 db 1111 1110 -1 db 1000 0000 -64 db table 15. example ain volume settings 76543210 reserved reserved reserved reserved inv_ain4 inv_ain3 inv_ain2 inv_ain1
ds717f1 49 CS42888 6.12.1 invert signal polarity (inv_ainx) default = 0 0 - disabled 1 - enabled function: 6.13 when enabled, these bits will invert the sign al polarity of their respective channels. status control (address 18h) 6.13.1 interrupt pin control (int[1:0]) default = 00 00 - active high; high output indi cates interrupt condition has occurred 01 - active low, low output indicates an interrupt condition has occurred 10 - open drain, active low. requires an external pull-up resistor on the int pin. 11 - reserved function: determines how the interr upt pin (int) will indicate an interrupt condition. for dac and adc clock errors, the int pin is set to ?level active mode? and will become active during the clock error. for the adcx_ovfl error, the int pi n is set to level active mode and will become active during the overflow error. 6.14 status (address 19h) (read only) for all bits in this register, a ?1? means the associated error condition has occurred at least once since the register was last read. a?0? means the associated erro r condition has not occurred since the last reading of the register. reading the register resets all bits to 0. status bits that are masked off in the associated mask register will always be ?0? in this register. 6.14.1 dac clock e rror (dac_clk error) default = x function: indicates an invalid mclk to dac_lrck ratio. this status flag is set to ?level active mode? and becomes active during the error condition. see ?system clocking? on page 29 for valid clock ratios. 76543210 reserved reserved reserved reserved int1 int0 reserved reserved 765 4 3 2 1 0 reserved reserved reserved dac_clk error adc_clk error reserved adc2_ovfl adc1_ovfl
50 ds717f1 CS42888 6.14.2 adc clock erro r (adc_clk error) default = x function: indicates an invalid mclk to adc_lrck ratio. this status flag is set to ?level active mode? and becomes active during the error condition. see ?system clocking? on page 29 for valid clock ratios. 6.14.3 adc overflow (adcx_ovfl) default = x function: indicates that there is an over-range condition anyw here in the CS42888 adc signal path of each of the associated adc?s. these status flags become active on the arrival of the error condition. 6.15 status mask (address 1ah) default = 00000 function: the bits of this register serve as a mask for the error sources found in the register ?status (address 19h) (read only)? on page 49 . if a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the int pin and the status regi ster. if a mask bit is set to 0, the error is masked, meaning that its oc- currence will not affect the int pin or the status register. the bi t positions align with the corresponding bits in the status register. 6.16 mutec pin cont rol (address 1bh) 6.17 mutec polarity select (mcpolarity) default = 0 0 - active low 1 - active high function: determines the polarity of the mutec pin. 6.18 mute control ac tive (mutec active) default = 0 0 - mutec pin is not active. 1 - mutec pin is active. function: the mutec pin will go high or low (depending on the mu tec polarity select bit) when this bit is enabled. 765 4 32 1 0 reserved reserved reserved dac_clk error_m adc_clk error_m reserved adc2_ovfl_m adc1_ovfl_m 76543210 reserved reserved reserv ed reserved reserved rese rved mcpolarity mutec active
ds717f1 51 CS42888 7. external filters 7.1 adc input filter the analog modulator samples the i nput at 6.144 mhz (inter nal mclk=12.288 mhz). the digital filter will reject signals within the stopband of the filter. however, there is no rejection for input signals which are mul- tiples of the digital passband frequency (n 6.144 mhz), where n=0,1,2,... refer to figures 25 and 26 for a recommended analog input filter that will attenuate an y noise energy at 6.144 mhz , in addition to providing the optimum source impedance for the modulators. refer to figures 27 and 28 for low-cost, low-component- count passive input filters. the use of capacitors that have a large voltage coefficient (such as general-pur- pose ceramics) must be avoided since these can degrade signal linearity va + + - - 4.7 f 100 k ? 10 k ? 100 k ? 100 k ? 0.1 f 100 f 470 pf 470 pf c0g c0g 634 ? 634 ? 634 ? 91 ? 91 ? 2700 pf c0g 332 ? ainx+ ainx- adc1-2 figure 25. single-to-differential active input filter - + 470 pf c0g 634 ? 91 ? 2700 pf c0g 4.7 f 100 k ? 100 k ? 100 k ? va 4.7 f ain1+,2+,3+,4+ ain1-,2-,3-,4- adc1-2 figure 26. single-ended active input filter
52 ds717f1 CS42888 7.1.1 passive input filter the passive filter implementation shown in figure 27 will attenuate any noise e nergy at 6.144 mhz but will not provide optimum source im pedance for the adc m odulators. full analog performance will there- fore not be realized using a passive filter. figure 27 illustrates the unity gain, pa ssive input filter solution. in this topology the distortion performance is affect ed, but the dynamic range performance is not limited. 7.1.2 passive input fi lter w/attenuation some applications may require si gnal attenuation prior to the adc. the full-scale input voltage will scale with the analog power supply voltage. for va = 5.0 v , the full-scale input voltage is approximately 2.8 vpp, or 1 vrms (most consumer audio line-level outputs range from 1.5 to 2 vrms). figure 28 shows a passive input filter with 6 db of signal at tenuation. due to the relatively high input im- pedance on the analog inputs, the full distortion perf ormance cannot be realized. also, the resistor divider circuit will determine the input impedance into the input filt er. in the circuit shown in figure 28 , the input impedance is approximately 5 k ?. by doubling the resistor values, the input impedance will increase to 10 k ?. however, in this case the dist ortion performance will drop due to the increase in series resistance on the analog inputs. 2700 pf c0g 10 f 100 k ? 150 ? ain1+,2+,3+,4+ ain1-,2-,3-,4- adc1-2 4.7 f figure 27. passive input filter 2700 pf c0g 10 f 2.5 k ? ain1+,2+,3+,4+ ain1-,2-,3-,4- adc1-2 4.7 f 2.5 k ? figure 28. passive input filter w/attenuation
ds717f1 53 CS42888 7.2 dac output filter the CS42888 is a linear phase design and does not in clude phase or amplitude compensation for an exter- nal filter. therefore, the dac syste m phase and amplitude re sponse will be dependent on the external an- alog circuitry. shown below is th e recommended active and passive output filters. aoutx + aoutx - - + 390 pf c0g 562 ? 22 f 4.75 k ? 1800 pf c0g 887 ? 2.94 k ? 5.49 k ? 1.65 k ? 1.87 k ? 22 f 1200 pf c0g 5600 pf c0g 47.5 k ? dac1-4 figure 29. active analog output filter aoutx+ 3.3 f c 560 ? + 10 k ? r ext r ext + 560 c= 4 f s r ext 560 dac1-4 figure 30. passive analog output filter
54 ds717f1 CS42888 8. adc filter plots figure 31. ssm stopband rejection figure 32. ssm transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (normalized to fs) amplitude (db) figure 33. ssm transition band (detail) figure 34. ssm passband ripple -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db ) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 35. dsm stopband rejection f igure 36. dsm transition band
ds717f1 55 CS42888 ? -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (norm alized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (normalized to fs) amplitude (db ) figure 37. dsm transition band (detai l) figure 38. dsm passband ripple -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (norm alized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 frequency (norm alized to fs) amplitude (db) figure 39. qsm stopband rejection figure 40. qsm transition band -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28 frequency (norm alized to fs) amplitude (db) figure 41. qsm transition band (detail) figure 42. qsm passband ripple -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db)
56 ds717f1 CS42888 9. dac filter plots figure 43. ssm stopband rejection figure 44. ssm transition band 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -0.25 -0. 2 -0.15 -0. 1 -0.05 0 0.05 frequency (normalized to fs) amplitude db figure 45. ssm transition band (detail) figure 46. ssm passband ripple figure 47. dsm stopband rejection figure 48. dsm transition band
ds717f1 57 CS42888 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -0. 2 -0. 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 frequency (normalized to fs) amplitude db figure 49. dsm transition band (det ail) figure 50. dsm passband ripple 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) figure 51. qsm stopband rejection figure 52. qsm transition band 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) 0.4 0.45 0.5 0.55 0.6 0.65 0.7 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 amplitude (db) frequency(normalized to fs) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -1. 5 -1 -0. 5 0 frequency (normalized to fs) amplitude db figure 53. qsm transition band (detail) figure 54. qsm passband ripple
58 ds717f1 CS42888 10.parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specif ied band width made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measure- ment. this measurement te chnique has been accepted by the au dio engineering society, aes17-1991, and the electronic industries as sociation of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified band width (typically 10 hz to 20 khz), including di stortion components. expressed in decibels. measured at -1 and -20 dbfs as sug gested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right chann el pairs. measured for each channel at the convert- er's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channel pairs. units in decibels. gain error the deviation from the nominal full-scale ana log output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111... 111 to 000...000) from the ideal. units in mv.
ds717f1 59 CS42888 11.references 1. cirrus logic, an18: layout and design rules for data converters and other mixed signal devices , version 6.0, february 1998. 2. cirrus logic, techniques to measure and maximize the perf ormance of a 120 db, 96 khz a/d converter integrated circuit , by steven harris, steven green and ka leung . presented at the 103rd convention of the audio engineering society, september 1997. 3. cirrus logic, a stereo 16-bit delta-sigma a/ d converter for digital audio , by d.r. welland, b.p. del signo- re, e.j. swanson, t. tanaka, k. hamashita, s. hara, k. taka suka. paper presented at the 85th convention of the audio engineering society, november 1988. 4. cirrus logic, the effects of sampling clock jitter on nyquis t sampling analog-to-digital converters, and on oversampling delta sigma adc's , by steven harris. paper presented at the 87th convention of the au- dio engineering society, october 1989. 5. cirrus logic, an 18-bit dual-channel oversampling delta-sigm a a/d converter, with 19-bit mono applica- tion example , by clif sanchez. pape r presented at th e 87th convention of the audio engineering society, october 1989. 6. cirrus logic, how to achieve optimum performance fr om delta-sigma a/d and d/a converters , by steven harris. presented at the 93rd convention of the audio engineering society, october 1992. 7. cirrus logic, a fifth-order delta-sigma modulator with 110 db audio dynamic range , by i. fujimori, k. ha- mashita and e.j. swanson. paper pr esented at the 93rd conv ention of the audio engineering society, oc- tober 1992. 8. philips semiconductor, the i2c-bus specification: version 2.1 , january 2000. http://www.semicondu ctors.philips.com
60 ds717f1 CS42888 12.package information 12.1 thermal characteristics inches millimeters dim min nom max min nom max a --- 0.55 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.008 0.011 0.17 0.20 0.27 d 0.461 0.472 bsc 0.484 11.70 12.0 bsc 12.30 d1 0.390 0.393 bsc 0.398 9.90 10.0 bsc 10.10 e 0.461 0.472 bsc 0.484 11.70 12.0 bsc 12.30 e1 0.390 0.393 bsc 0.398 9.90 10.0 bsc 10.10 e* 0.016 0.020 bsc 0.024 0.40 0.50 bsc 0.60 l 0.018 0.024 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 parameter symbol min typ max units junction to ambient thermal impedance 2 layer board 4 layer board q ja ja - - 50 37 - - c/watt c/watt 64l lqfp package drawing e1 e d1 d 1 e l b a1 a
ds717f1 61 CS42888 13.ordering information 14.revision history product description package pb-free grade temp range container order # CS42888 4-in, 8-out codec for sur- round sound apps 64l-lqfp yes commercial -10 to +70 c rail CS42888-cqz tape & reel CS42888-cqzr automotive -40 to +105 c rail CS42888-dqz tape & reel CS42888-dqzr cdb42448 CS42888 evaluation board - - - - - cdb42448 revision changes pp1 initial release f1 updated temperature and vo ltage specifications in ?recommended operating conditions? on page 10 . added test conditions to the analog input and analog output characteristics tables. contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com. important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military a pplications, products s urgically implanted into the body, automotive sa fety or security de- vices, life support products or other cri tical applications. inclus ion of cirrus products in s uch applications is under- stood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs, and popguard are trademarks of cirrus logic, inc. all other brand and pro duct names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. spi is a registered trademark of motorola, inc.

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