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commercial temperature range march 1996 ?1996 integrated device technology, inc. dsc-2905/5 idt79r3041 ? integrated riscontroller ? for low-cost systems idt79r3041 IDT79RV3041 features: ? instruction set compatible with idt79r3000a and riscontroller family mips risc cpus ? high level of integration minimizes system cost risc cpu multiply/divide unit instruction cache data cache programmable bus interface programmable port width support ? on-chip instruction and data caches 2kb of instruction cache 512b of data cache ? flexible bus interface allows simple, low-cost designs superset pin-compatible with riscontroller adds programmable port width interface (8-, 16-, and 32-bit memory sub-regions) adds programmable bus interface timing support (extended address hold, bus turn around time, read/write masks) ? double-frequency clock input ? 16.67mhz, 20mhz, 25mhz and 33mhz operation ? 20mips at 25mhz ? low cost 84-pin plcc packaging ? on-chip 4-deep write buffer eliminates memory write stalls ? on-chip 4-word read buffer supports burst or simple block reads ? on-chip dma arbiter ? on-chip 24-bit timer ? boot from 8-bit, 16-bit, or 32-bit wide proms ? pin- and software-compatible family includes r3041, r3051, r3052 ? , and r3081 ? ? complete software support optimizing compilers real-time operating systems monitors/debuggers floating point emulation software page description languages figure 1. r3041 block diagram clock generator unit master pipeline control system control coprocessor integer cpu core exception/control registers bus interface registers general registers (32 x 32) alu shifter mult/div unit address adder pc control virtual address data cache 512b instruction cache 2kb physical address bus biu control dma arbiter 4-deep read buffer 4-deep write buffer clkin int(5:3) , sint(2:0) 32 32 sbrcond(3:2) data bus address/ data dma ctrl rd / wr ctrl sysclk portsize register counter registers tc r3051 superset bus interface unit data unpack unit data pack unit timing/ interface control 2905 drw 01 1 integrated device technology, inc. riscontroller, r3041, r3051, r3052, r3081, orion, idt/sim, and idt/kit are trademarks, and the idt logo is a registered trademark of integrated device technology, inc.
2 idt79r3041 integrated riscontroller for low cost systems commercial temperature range device instruction data floating bus name cache cache point options r3051 4kb 2kb software emulation muxed a/d r3052 8kb 2kb software emulation muxed a/d r3071 16kb 4kb on-chip hardware 1/2 frequency bus option r3081 or 8kb or 8kb r3041 2kb 512b software emulation 8-, 16-, and 32-bit port width support programmable timing support 2905 tbl 01 introduction the idt riscontroller family is a series of high-perfor- mance 32-bit microprocessors featuring a high-level of inte- gration, and targeted to high-performance but cost sensitive embedded processing applications. the riscontroller family is designed to bring the high-performance inherent in the mips risc architecture into low-cost, simplified, power sen- sitive applications. thus, functional units have been integrated onto the cpu core in order to reduce the total system cost, rather than to increase the inherent performance of the integer engine. nevertheless, the riscontroller family is able to offer 35mips of integer performance at 40mhz without requiring external sram or caches. further, the riscontroller family brings dramatic power reduction to these embedded applications, allowing the use of low-cost packaging. thus, the riscontroller family allows customer applications to bring maximum performance at minimum cost. the r3041 extends the range of price/performance achiev- table 1. pin-compatible riscontroller family figure 2. riscontroller family 5-stage pipeline cpu core the cpu core is a full 32-bit risc integer execution engine, capable of sustaining close to a single cycle execution rate. the cpu core contains a five stage pipeline, and 32 orthogonal 32-bit registers. the riscontroller family imple- ments the mips-i instruction set architecture (isa). in fact, the execution engine of the r3041 is the same as the execution engine of the r3000a. thus, the r3041 is binary compatible with those cpu engines, as well as compatible with other members of the riscontroller family. able with the riscontroller family, by dramatically lowering the cost of using the mips architecture. the r3041 is de- signed to achieve minimal system and components cost, yet maintain the high-performance inherent in the mips architec- ture. the r3041 also maintains pin and software compatibility with the riscontroller and r3081. the riscontroller family offers a variety of price/perfor- mance features in a pin-compatible, software compatible family. table 1 provides an overview of the current members of the riscontroller family. note that the r3051, r3052, and r3081 are also available in pin-compatible versions that include a full-function memory management unit, including 64-entry tlb. the r3051/2 and r3081 are described in separate manuals and data sheets. figure 1 shows a block level representation of the func- tional units within the r3041. the r3041 can be viewed as the embodiment of a discrete solution built around the r3000a. by integrating this functionality on a single chip, dramatic cost and power reductions are achieved. an overview of these blocks is presented here, followed with detailed information on each block. if current cpu cycle i#1 alu rd mem wb if i#2 alu rd mem wb if i#3 alu rd mem wb if i#4 alu rd mem wb if i#5 alu rd mem wb 2905 drw 02 the execution engine of the riscontroller family uses a five-stage pipeline to achieve close to single cycle execution. a new instruction can be started in every clock cycle; the execution engine actually processes five instructions concur- rently (in various pipeline stages). the five parts of the pipeline are the instruction fetch, read register, alu execution, memory, and write back stages. figure 2 shows the concurrency achieved by the riscontroller family pipeline.
3 idt79r3041 integrated riscontroller for low cost systems commercial temperature range system control co-processor the r3041 also integrates on-chip a system control co- processor, cp0. cp0 manages the exception handling capa- bility of the r3041, the virtual to physical address mapping of the r3041, and the programmable bus interface capabilities of the r3041. these topics are discussed in subsequent sections. the r3041 does not include the optional tlb found in other members of the riscontroller family, but instead performs the same virtual to physical address mapping of the base version of the riscontroller family. these devices still support distinct kernel and user mode operation, but do not require page management software or an on-chip tlb, leading to a simpler software model and a lower-cost processor. the memory mapping used by these devices is illustrated in figure 3. note that the reserved address spaces shown are for compatibility with future family members; in the current family members, references to these addresses are trans- lated in the same fashion as their respective segments, with no traps or exceptions taken. when using the base versions of the architecture, the system designer can implement a distinction between the user tasks and the kernel tasks, without having to execute page management software. this distinction can take the form of physical memory protection, accomplished by ad- dress decoding, or in other system specific forms. in systems which do not wish to implement memory protection, and wish to have the kernel and user tasks operate out of a single unified memory space, upper address lines can be ignored by the address decoder, and thus all references will be seen in the lower gigabyte of the physical address space. the r3041 adds additional resources into the on-chip cp0. these resources are detailed in the r3041 user's manual. they allow kernel software to directly control activity of the processor internal resources and bus interface, and include: ? cache configuration register: this register controls the data cache block size and miss refill algorithm. ? bus control register: this register controls the behavior of the various bus interface signals. ? count and compare registers: together, these two registers implement a programmable 24-bit timer, which can be used for dram refresh or as a general purpose timer. ? port size control register: this register allows the kernel to indicate the port width of reads and writes to various sub- regions of the physical address space. thus, the r3041 can interface directly with 8-, 16-, and 32-bit memory ports, including a mix of sizes, for both instruction and data references, without requiring additional external logic. figure 3. virtual to physical mapping of base architecture versions virtual physical 2905 drw 03 kernel cached (kseg2) kernel uncached (kseg1) kernel cached (kseg0) kernel/user cached (kuseg) kernel cached tasks 1023 mb kernel/user cached tasks 2047 mb inaccessible 512 mb kernel boot and i/o 512 mb 0xfff00000 0xc0000000 0xa0000000 0x00000000 0xffffffff 0x80000000 0x7fffffff 0x7ff00000 0x7fefffff 0x9fffffff 0xbfffffff 0xffefffff user reserved 1mb kernel reserved 1mb 0xfff00000 0xc0000000 0xbff00000 0x00000000 0xffffffff 0x40000000 0x3fffffff 0x20000000 0x1fffffff 0xbfefffff 0xbfffffff 0xffefffff kernel reserved 1mb user reserved 1mb
4 idt79r3041 integrated riscontroller for low cost systems commercial temperature range clock generation unit the r3041 is driven from a single 2x frequency input clock, capable of operating in a range of 40%-60% duty cycle. on- chip, the clock generator unit is responsible for managing the interaction of the cpu core, caches, and bus interface. the clock generator unit replaces the external delay line required in r3000a based applications. instruction cache the r3041 integrates 2kb of on-chip instruction cache, organized with a line size of 16 bytes (four 32-bit entries) a nd is direct mapped. this relatively large cache substantially contributes to the performance inherent in the r3041, and allows systems based on the r3041 to achieve high-perfor- mance even from low-cost memory systems. the cache is implemented as a direct mapped cache, and is capable of caching instructions from anywhere within the 4gb physical address space. the cache is implemented using physical addresses and physical tags (rather than virtual addresses or tags), and thus does not require flushing on context switch. data cache the r3041 incorporates an on-chip data cache of 512b, organized as a line size of 4 bytes (one word) and is direct mapped. this relatively large data cache contributes substan- tially to the performance inherent in the riscontroller family. as with the instruction cache, the data cache is implemented as a direct mapped physical address cache. the cache is capable of mapping any word within the 4gb physical address space. the data cache is implemented as a write through cache, to insure that main memory is always consistent with the internal cache. in order to minimize processor stalls due to data write operations, the bus interface unit incorporates a 4- deep write buffer which captures address and data at the processor execution rate, allowing it to be retired to main memory at a much slower rate without impacting system performance. bus interface unit the riscontroller family uses its large internal caches to provide the majority of the bandwidth requirements of the execution engine, and thus can utilize a simple bus interface connected to slow memory devices. the riscontroller family bus interface utilizes a 32-bit address and data bus multiplexed onto a single set of pins. the bus interface unit also provides an ale (address latch enable) output signal to de-multiplex the a/d bus, and simple handshake signals to process cpu read and write requests. in addition to the read and write interface, the r3041 incorpo- rates a dma arbiter, to allow an external master to control the external bus. the r3041 augments the basic riscontroller bus interface capability by adding the ability to directly interface with varying memory port widths, for instructions or data. for example, the r3041 can be used in a system with an 8-bit boot prom, 16- bit font/program cartridges, and 32-bit main memory, trans- parently to software, and without requiring external data packing, rotation, and unpacking. in addition, the r3041 incorporates the ability to change some of the interface timing of the bus. these features can be used to eliminate external data buffers and take advantage of lower speed and lower cost interface components. one of the bus interface options is the extended address hold mode which adds 1/2 clock of extra address hold time from ale falling. this allows easier interfacing to fpgas and asics. the r3041 incorporates a 4-deep write buffer to decouple the speed of the execution engine from the speed of the memory system. the write buffers capture and fifo proces- sor address and data information in store operations, and present it to the bus interface as write transactions at the rate the memory system can accommodate. during main memory writes, the r3041 can break a large datum (e.g. 32-bit word) into a series of smaller transactions (e.g. bytes), according to the width of the memory port being written. this operation is transparent to the software which initiated the store, insuring that the same software can run in true 32-bit memory systems. the riscontroller family read interface performs both single word reads and quad word reads. single word reads work with a simple handshake, and quad word reads can either utilize the simple handshake (in lower performance, simple systems) or utilize a tighter timing mode when the memory system can burst data at the processor clock rate. thus, the system designer can choose to use page or static column mode drams (and possibly use interleaving, if de- sired, in high-performance systems), or even to use simpler sram techniques to reduce complexity. in order to accommodate slower quad word reads, the riscontroller family incorporates a 4-deep read buffer fifo, so that the external interface can queue up data within the processor before releasing it to perform a burst fill of the internal caches. in addition, the r3041 can perform on-chip data packing when performing large datum reads (e.g., quad words) from narrower memory systems (e.g., 16-bits). once again, this operation is transparent to the actual software, simplifying migration of software to higher performance (true 32-bit) systems, and simplifying field upgrades to wider memory. since this capability works for either instruction or data reads, using 8-, 16-, or 32-bit boot proms is easily supported by the
5 idt79r3041 integrated riscontroller for low cost systems commercial temperature range r3041. system usage the idt riscontroller family is specifically designed to easily connect to low-cost memory systems. typical low-cost memory systems use inexpensive eproms, drams, and application specific peripherals. figure 4 shows some of the flexibility inherent in the r3041. in this example system, which is typical of a laser printer, a 32- bit prom interface is used due to the size of the pdl interpreter. an embedded system can optionally use an 8-bit figure 4. typical r3041-based application boot prom instead. a 16-bit font/program cartridge interface is provided for add-in cards. a 16-bit dram interface is used for a low-cost page frame buffer. in this system example, a field or manufacturing upgrade to a 32-bit page frame buffer is supported by the boot software and dram controller. embedded systems may optionally substitute srams for the drams. finally various 8/16/32-bit i/o ports such as rs-232/ 422, scsi, and lan as well as the laser printer engine interface are supported. such a system features a very low entry price, with a range of field upgrade options including the ability to upgrade to a more powerful member of the riscontroller family. clkin idt r3041 riscontroller address/ data control eprom and i/o controller dram controller 16-bit dram 16-bit add-on dram 32-bit eprom 16-bit font cartridge i/o r3051 local bus 2905 drw 04
6 idt79r3041 integrated riscontroller for low cost systems commercial temperature range development support the idt riscontroller family is supported by a rich set of development tools, ranging from system simulation tools through prom monitor and debug support, applications soft- ware and utility libraries, logic analysis tools, and sub-system modules. figure 5 is an overview of the system development process typically used when developing r3041 applications. the riscontroller family is supported in all phases of project development. these tools allow timely, parallel development of hardware and software for riscontroller family based applications, and include tools such as: ? optimizing compilers from mips technology, the acknowl- edged leader in optimizing compiler technology. ? cross development tools, available in a variety of develop- ment environments. ? the high-performance idt floating point emulation library software. ? the idt evaluation board, which includes ram, eprom, i/o, and the idt prom monitor. ? idt laser printer system boards, which directly drive a low- cost print engine, and runs adobe postscript ? page de- scription language ? adobe postscript page description language running on the idt riscontroller family. ? the idt/sim ? prom monitor, which implements a full prom monitor (diagnostics, remote debug support, peek/ figure 5. r3041 development environment cache3041 benchmarks evaluation board laser printer system dbg debugger pixie profiler mips compiler suite stand-alone libraries floating point library cross development tools adobe postscript pdl microsoft trueimage pdl peerlesspage bios idt/kit hardware models general cad tools risc sub-systems '341 evaluation board laser printer system logic analysis diagnostics idt/sim prom monitor remote debug real-time os software hardware system integration and verfification system development phase system architecture evaluation 2905 drw 05
7 idt79r3041 integrated riscontroller for low cost systems commercial temperature range poke, etc.). ? idt/kit ? (kernel integration toolkit), providing library sup- port and a frame work for the system run time environment. performance overview the riscontroller family achieves a very high-level of performance. this performance is based on: ? an efficient execution engine: the cpu performs alu operations and store operations in a single cycle, and has an effective load time of 1.3 cycles, and branch execution rate of 1.5 cycles (based on the ability of the compilers to avoid software interlocks). thus, the r3041 achieves 20 mips performance at 25mhz when operating out of cache. ? large on-chip caches: the riscontroller family contains caches which are substantially larger than those on the majority of embedded microprocessors. these large caches minimize the number of bus transactions required, and allow the riscontroller family to achieve actual sustained performance very close to its peak execution rate, even with low-cost memory systems. ? autonomous multiply and divide operations: the riscontroller family features an on-chip integer multiplier/ divide unit which is separate from the other alu. this allows the r3041 to perform multiply or divide operations in parallel with other integer operations, using a single multiply or divide instruction rather than using step operations. ? integrated write buffer: the r3041 features a four deep write buffer, which captures store target addresses and data at the processor execution rate and retires it to main memory at the slower main memory access rate. use of on- chip write buffers eliminates the need for the processor to stall when performing store operations. ? burst read support: the r3041 enables the system designer to utilize page mode, static column, or nibble mode rams when performing read operations to minimize the main memory read penalty and increase the effective cache hit rates. the performance differences among the various riscontroller family members depends on the application software and the design of the memory system. different family members feature different cache sizes, and the r3081 features a hardware floating point accelerator. since all these devices can be used in a pin and software compatible fashion, the system designer has maximum freedom in trading be- tween performance and cost. the memory simulation tools (e.g. cache3041) allows the system designers to analyze and understand the performance differences among these de- vices in their application. selectable features the riscontroller family uses two methods to allow the system designer to configure bus interface operation options. the first set of options are established via the reset configuration mode inputs, sampled during the device reset. after reset, the reset mode inputs become regular input or output signals. the second set of configuration options are contained in the system control co-processor registers. these co-pro- cessor registers configuration options are typically initialized with the boot prom and can also be changed dynamically by the kernel software. selectable features include: ? big endian vs. little endian operation : the part can be configured to operate with either byte ordering convention, and in fact may also be dynamically switched between the two conventions. this facilitates the porting of applications from other processor architectures, and also permits inter- communication between various types of processors and databases. ? data cache refill of one or four words : the memory system must be capable of performing 4 word transfers to satisfy instruction cache misses and 1 word transfers to satisfy uncached references. the data cache refill size option allows the system designers to choose between one and four word refill on data cache misses, depending on the performance each option brings to their application. ? bus turn around speed : the r3041 allows the kernel to increase the amount of time between bus transactions when changes in direction of the a/d bus occur (e.g., at the end of reads followed by writes). this allows transceivers and buffers to be eliminated from the system. ? extended address hold time : the r3041 allows the system designer to increase the amount of hold time avail- able for address latching, thus allowing slower speed (low cost) address latches, fpgas and asics to be used. ? programmable control signals : the r3041 allows the system designer to optimally configure various memory control signals to be active on reads only, writes only, or on both reads and writes. this allows the simplification of external logic, thus reducing system cost.
8 idt79r3041 integrated riscontroller for low cost systems commercial temperature range ? programmable memory port widths : the r3041 allows the kernel to partition the physical memory space into various sub-regions, and to individually indicate the port width of these sub-regions. thus, the bus interface unit can perform data packing and unpacking when communicating with narrow memory sub-regions. for example, these fea- tures, can be used to allow the r3041 to interface with narrow 8-bit boot proms, or to implement 16-bit only memory systems. thermal considerations the riscontroller family utilizes special packaging tech- niques to improve the thermal properties of high-speed pro- cessors. thus, all versions of the riscontroller family are packaged in cavity down packaging. the lowest cost members of the family use a standard cavity down, injection molded plcc package (the j pack- age). this package is used for all speeds of the r3041 family. higher speed and higher performance members of the riscontroller family utilize more advanced packaging tech- niques to dissipate power while remaining both low-cost and pin- and socket- compatible with the plcc package. thus, these members of the riscontroller family are available in the mquad package (the mj package), which is an all alumi- num package with the die attached to a normal copper lead- frame mounted to the aluminum casing. the mquad pack- age is pin and form compatible with the plcc package. thus, designers can choose to utilize this package without changing their pcb. the members of the riscontroller family are guaranteed in a case temperature range of 0 c to +85 c. the type of package, speed (power) of the device, and airflow conditions, affect the equivalent ambient conditions which meet this specification. the equivalent allowable ambient temperature, t a , can be calculated using the thermal resistance from case to ambient (? ca ) of the given package. the following equation relates ambient and case temperature: t a = t c - p * ? ca where p is the maximum power consumption at hot tempera- ture, calculated by using the maximum icc specification for the device. typical values for ? ca at various airflows are shown in table 2 for the plcc package. notes on system design the r3041 has been designed to simplify the task of high- speed system design. thus, set-up and hold-time require- ments have been kept to a minimum, allowing a wide variety of system interface strategies. to minimize these ac parameters, the r3041 employs feedback from its sysclk output to the internal bus interface unit. this allows the r3041 to reference input signals to the reference clock seen by the external system. the sysclk output is designed to provide relatively large ac drive to minimize skew due to slow rise or fall times. a typical part will have less than 2ns rise or fall (10% to 90% signal times) when driving the test load. therefore, the system designer should use care when designing for direct sysclk use. total loading (due to devices connected on the signal net and the routing of the net itself) should be minimized to ensure the sysclk output has a smooth and rapid transition. long rise and/or fall times may cause a degradation in the speed capability of an individual device. similarly, the r3041 employs feedback on its ale output to ensure adequate address hold time to ale. the system designer should be careful when designing the ale net to minimize total loading and to minimize skew between ale and the a/d bus, which will ensure adequate address access latch time. idt's field and factory applications groups can provide the system designer with assistance for these and other design issues. airflow (ft/min) ?ca 0 200 400 600 800 1000 "j" package 29 26 21 18 16 15 tqfp 55 40 35 33 31 30 2905 tbl 02 table 2. thermal resistance (? ca ) at various airflows
9 idt79r3041 integrated riscontroller for low cost systems commercial temperature range pin configurations idt r3041/rv3041 84-pin plcc/ top view (cavity down) v ss v cc a/d(14) a/d(13) a/d(12) a/d(11) a/d(10) a/d(9) v cc v ss a/d(8) a/d(7) a/d(6) a/d(5) a/d(4) a/d(3) v ss v cc a/d(2) a/d(1) a/d(0) burst/wrnear addr(3) addr(2) diag last ale rd wr dataen v cc v ss sysclk busgnt reset buserror ack rdcen busreq memstrobe v ss v cc clkin tristate be16(1) be16(0) addr(1) addr(0) int(5) v ss v cc int(4) int(3) sint(2) sint(1) sint(0) tc v ss v cc a/d(15) a/d(16) a/d(17) a/d(18) a/d(19) a/d(20) a/d(21) a/d(22) a/d(23) a/d(24) a/d(25) a/d(26) v cc v ss a/d(27) a/d(28) a/d(29) a/d(30) a/d(31) 184 12 75 33 54 sbrcond(3)/ iostrobe sbrcond(2)/ extdataen 13 14 2 3 4 5 6 7 8 9 10 11 83 82 81 80 79 78 77 76 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 v cc v ss v cc v ss 2905 drw 06
10 idt79r3041 integrated riscontroller for low cost systems commercial temperature range pin configurations 2905 drw 06 sbrcond(2)/ extdataen sbrcond(3)/ iostrobe 1 12 13 14 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 v ss v cc clkin tristate be16(1) be16(0) addr(1) addr(0) int(5) v ss v cc int(4) int(3) sint(2) sint(1) sint(0) tc v ss v cc v ss v cc a/d(14) a/d(13) a/d(12) a/d(11) a/d(10) a/d(9) v cc v ss a/d(8) a/d(7) a/d(6) a/d(5) a/d(4) a/d(3) v ss v cc a/d(2) a/d(1) a/d(0) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 54 52 53 55 56 57 58 59 60 51 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 nc nc nc nc nc nc nc nc a/d(15) a/d(16) a/d(17) a/d(18) a/d(19) a/d(20) a/d(21) a/d(22) a/d(23) a/d(24) a/d(25) a/d(26) a/d(27) a/d(28) a/d(29) a/d(30) a/d(31) v cc v ss v cc v ss nc nc nc nc burst/wrnear addr(3) addr(2) diag last ale rd wr dataen v cc v ss sysclk busgnt reset buserror ack rdcen busreq memstrobe v cc v ss nc nc nc nc idt r3041/rv3041 100-pin tqfp (cavity up) top view
11 idt79r3041 integrated riscontroller for low cost systems commercial temperature range pin description pin name i/o description a/d(31:0) i/o address/data: a 32-bit time multiplexed bus which indicates the desired address for a bus transaction in one phase, and which is used to transmit data between the cpu and external memory resources during the rest of the transfer. bus transactions on this bus are logically separated into two phases: during the first phase, information about the transfer is presented to the memory system to be captured using the ale output. this information consists of: address(31:4) : the high-order address for the transfer is presented on a/d(31:4). be(3:0): these strobes indicate which bytes of the 32-bit bus will be involved in the transfer, and are presented on a/d(3:0). be(3 ) indicates that a/d(31:24) will be used, and be(0) corresponds to a/d(7:0). these strobes are only valid for accesses to 32-bit wide memory ports. note that be(3:0) can be held in-active during reads by setting the appropriate bit of cp0; thus when latched, these signals can be directly used as write enable strobes. during the second phase, these signals are the data bus for the transaction. data(31:0): during write cycles, the bus contains the data to be stored and is driven from the internal write buffer. on read cycles, the bus receives the data from the external resource, in either a single data transaction or in a burst of four words, and places it into the on-chip read buffer. the byte lanes used during the transfer are a function of the datum size, the memory port width, and the system byte-ordering. addr(3:0) o low address (3:0) a 4-bit bus which indicates which word/halfword/byte is currently expected by the processor. for 32-bit port widths, only addr(3:2) is valid during the transfer; for 16-bit port widths, only addr(3:1) are valid; for 8-bit port widths, all of addr(3:0) are valid. these address lines always contain the address of the current datum to be transferred. in writes and single datum reads, the addresses initially output the specific target address, and will increment if the size of the datum is wider than the target memory port. for quad word reads, these outputs function as a counter starting at '0000', and incrementing according to the width of the memory port. i (1) during reset , the addr(3:0) pins act as reset configuration mode bit inputs for the bootprom16 , bootprom8 , reservedhigh, and extaddrhold options. the r3041 addr(1:0) output pins are designated as the unconnected rsvd(1:0) pins in the r3051 and r3081. diag o diagnostic pin. this output indicates whether the current bus read transaction is due to an on- chip cache miss and whether the read is an instruction or data. it is time multiplexed as described below: cached/ uncached : during the phase in which the a/d bus presents address information, this pin is an active high output which indicates whether or not the current read is a result of a cache miss. the value of this pin at this time other than in read cycles is undefined. i/ d: a high at this time indicates an instruction reference, and a low indicates a data reference. the value of this pin at this time other than in read cycles is undefined. the r3041 diag output pin is designated as the diag(1) output pin in the r3051 and r3081. ale o address latch enable: used to indicate that the a/d bus contains valid address information for the bus transaction. this signal is used by external logic to capture the address for the transfer, typically by using transparent latches. dataen o data enable: this signal indicates that the a/d bus is no longer being driven by the processor during read cycles, and thus the external memory system may enable the drivers of the memory system onto this bus without having a bus conflict occur. during write cycles, or when no bus trans- action is occurring, this signal is negated, thus disabling the external memory drivers. 2905 tbl 03 note: 1. reset configuration mode bit input when reset is asserted, normal signal function when reset is de-asserted.
12 idt79r3041 integrated riscontroller for low cost systems commercial temperature range pin description (continued): pin name i/o description burst/ o burst transfer/write near: on read transactions, the burst signal indicates that the current bus read wrnear is requesting a block of four contiguous words from memory. this signal is asserted only in read cycles due to cache misses; it is asserted for all i-cache miss read cycles, and for d-cache miss read cycles if the 4-word data block refill option is selected in the cp0 cache config register. on write transactions, the wrnear output tells the external memory system that the bus interface unit is performing back-to-back write transactions to an address within the same 256 byte page as the prior write transaction. this signal is useful in memory systems which employ page mode or static column drams, and allows nearby writes to be retired quickly. rd o read: an output which indicates that the current bus transaction is a read. wr o write: an output which indicates that the current bus transaction is a write. ack i acknowledge: an input which indicates to the device that the memory system has sufficiently processed the bus transaction. on write transactions, this signal indicates that the cpu may either progress to the next data item (for mini-burst writes of wide datums to narrow memories), or terminate the write cycle. on read transactions, this signal indicates that the memory system has sufficiently processed the read, and that the processor core may begin processing the data from this read transfer. rdcen i read buffer clock enable: an input which indicates to the device that the memory system has placed valid data on the a/d bus, and that the processor may move the data into the on-chip read buffer. sysclk o system reference clock: an output from the cpu which reflects the timing of the internal processor "system" clock. this clock is used to control state transitions in the read buffer, write buffer, memory controller, and bus interface unit. busreq i dma arbiter bus request: an input to the device which requests that the cpu tri-state its bus interface signals so that they may be driven by an external master. the negation of this input relinquishes mastership back to the cpu. busgnt o dma arbiter bus grant. an output from the cpu used to acknowledge that a busreq has been detected, and that the bus is relinquished to the external master. the r3041 adds an additional dma protocol, under the control of cp0. if the dma protocol is enabled, the r3041 can request that the external master relinquish bus mastership back to the processor by negating the busgnt output early, and waiting for the busreq input to be negated. sbrcond(3)/ i/o branch condition port/io strobe: the use of this signal depends on the setting of various bits of the iostrobe cp0 bus control register. if brcond mode is selected, this input is logically connected to cpcond(3), and can be used by the branch on co-processor condition instructions as an input port. the sbrcond(3) input has special internal logic to synchronize the input, and thus may be driven by asynchronous agents. if this pin is selected to function as iostrobe , it may be asserted as an output on reads, writes, or both, as programmed into cp0. this strobe asserts in the second clock cycle of a transfer, and thus can be used to strobe various control signals on the bus interface. sbrcond(2)/ i/o branch condition port/extended data enable: the use of this signal depends on the settings in the extdataen cp0 bus control register. if brcond mode is selected, this input is logically connected to cpcond(2), and can be used by the branch on co-processor condition instructions as an input port. the sbrcond(2) input has special internal logic to synchronize the input, and thus may be driven by asynchronous agents. if this pin is selected to function as extended data enable, it may be asserted as an output on reads, writes, or both, as programmed into cp0. this strobe can be used as an extended data enable strobe, in that it is held asserted for one-half clock cycle after the negation of rd or wr . this signal may typically be used as a write enable control line for transceivers, as a write line for i/o, or as an address mux select for drams. memstrobe o memory strobe: this active low output pulses low for each data read or written, as configured in the cp0 bus control register. thus, it can be used as a read strobe, write strobe, or both, for sram type memories or for i/o devices. the r3041 memstrobe output pin is designated as the brcond(0) input pin in the r3051 and r3081. 2905 tbl 04
13 idt79r3041 integrated riscontroller for low cost systems commercial temperature range pin name i/o description be16(1:0) o byte enable strobes for 16-bit memory port: these active low outputs are the byte lane strobes for accesses to 16-bit wide memory ports; they are not necessarily valid for 8- or 32-bit wide ports. if be16(1 ) is asserted, then the most significant byte (either d(31:24) or d(15:8), depending on system endianness) is going to be used in this transfer. if be16(0) is asserted, the least significant byte (d(23:16) or d(7:0)) will be used. be16(1:0) can be held inactive (masked) during read transfers, according to the programming of the cp0 bus control register. i (1) during reset , the be16(1:0) act as reset configuration mode bit inputs for two reservedhigh options. the be16(1:0) output pins are designated as the unconnected rsvd(3:2) pins in the r3051 and r3081. last o last datum in mini-burst: this active low output indicates that this is the last datum transfer in a given transaction. it is asserted after the next to last rdcen (reads) or ack (writes), and is negated when rd or wr is negated. the last output pin is designated in the r3051 and r3081 as the diag(0) output pin. tc o terminal count: this is an active low output from the processor which indicates that the on-chip timer has reached its terminal count. it will remain low for either 1.5 clock cycles, or until software resets the timer, depending on the mode selected in the cp0 bus control register. thus, the on-chip timer can function either as a free running timer for system functions such as dram refresh, or can operate as a software controlled time-slice timer, or real-time clock. the tc output pin is designated in the r3051 as the brcond(1) input pin, and in the r3081 as the run pin output. buserror i bus error: input to the bus interface unit to terminate a bus transaction due to an external bus error. this signal is only sampled during read and write operations. if the bus transaction is a read operation, then the cpu will take a bus error exception. int(5:3) i processor interrupt: during normal operation, these signals are logically the same as the int (5:0) sint(2:0) signals of the r3000a. during processor reset, these signals perform mode initialization of the cpu, but in a different (simpler) fashion than the interrupt signals on the original r3000a. i (1) during reset , int(3) and sint(0) act as reset configuration mode bit inputs for the addrdisplayandforcecachemiss and bigendian options. there are two types of interrupt inputs: the sint inputs are internally synchronized by the processor, and may be driven by an asynchronous external agent. the direct interrupt inputs are not internally synchronized, and thus must be externally synchronized to the cpu. the direct interrupt inputs have one cycle lower latency than the synchronized interrupts. clkin i master clock input: this is a double frequency input used to control the timing of the cpu. reset i master processor reset: this signal initializes the cpu. reset initialization mode selection is performed during the last cycle of reset . tristate i tri-state: this input to the r3041 requests that the r3041 tri-state all of its outputs. in addition to those outputs tri-stated during dma, tri-state will cause sysclk , tc , and busgnt to tri-state. this signal is intended for use during board testing and emulation during debug and board manufacture. the tristate input pin is designated as the unconnected rsvd(4)pin in the r3051 and r3081. vcc i power: these inputs must be supplied with the rated supply voltage (vcc). all vcc inputs must be connected to insure proper operation. vss i ground: these inputs must be connected to ground (gnd). all vss inputs must be connected to insure proper operation. pin description (continued): 2905 tbl 05 note: 1. reset configuration mode bit input when reset is asserted, normal signal function when reset is de-asserted.
14 idt79r3041 integrated riscontroller for low cost systems commercial temperature range advanced 16.67mhz 20mhz 25mhz 33mhz symbol parameter test conditions min. max. min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = C4ma 3.5 3.5 3.5 3.5 v v ol output low voltage v cc = min., i ol = 4ma 0.4 0.4 0.4 0.4 v v ih input high voltage (3) 2.0 2.0 2.0 2.0 v v il input low voltage (1) 0.8 0.8 0.8 0.8 v v ihs input high voltage (2,3) 3.0 3.0 3.0 3.0 v v ils input low voltage (1,2) 0.4 0.4 0.4 0.4 v c in input capacitance (4) 10 10 10 10 pf c out output capacitance (4) 10 10 10 10 pf i cc operating current v cc = 5v, t c = 25 c 225 250 300 370 ma i ih input high leakage v ih = vcc 100 100 100 100 m a i il input low leakage v il = gnd C100 C100 C100 C100 m a i oz output tri-state leakage v oh = 2.4v, v ol = 0.5v C100 100 C100 100 C100 100 C100 100 m a recommended operating temperature and supply voltage output loading for ac testing absolute maximum ratings (1, 3) r3041 symbol rating commercial unit v term terminal voltage with C0.5 to +7.0 v respect to gnd t c operating case temperature 0 to +85 c t bias temperature under bias C55 to +125 c t stg storage temperature C55 to +125 c v in input voltage C0.5 to +7.0 v notes: 2905 tbl 06 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v in minimum = C3.0v for pulse width less than 15ns. v in should not exceed v cc +0.5 volts. 3. not more than one output should be shorted at a time. duration of the short should not exceed 30 seconds. grade temperature gnd v cc commercial 0 c to +85 c 0v 5.0 5% (case) 2905 tbl 07 - + to device under test c ld -4ma +4ma v ref +1.5v 2905 drw 07 signal cld all signals 25 pf 2905 tbl 09 symbol parameter min. max. unit v ih input high voltage 3.0 v v il input low voltage 0 v v ihs input high voltage 3.5 v v ils input low voltage 0 v ac test conditions r3041 2905 tbl 08 dc electrical characteristics r3041 (t c = 0 c to +85 c, v cc = +5.0v 5%) notes: 2905 tbl 10 1. v il min. = C3.0v for pulse width less than 15ns. v il should not fall below C0.5 volts for larger periods. 2. v ihs and v ils apply to cikin and reset . 3. v ih should not be held above v cc + 0.5 volts. 4. guaranteed by design.
15 idt79r3041 integrated riscontroller for low cost systems commercial temperature range advanced ac electrical characteristics r3041 (1, 2, 3) (t c = 0 c to +85 c, v cc = +5.0v 5%) 2905 tbl 11 16.67mhz 20mhz 25mhz 33mhz symbol signals description min. max. min. max. min. max. min. max. unit t1 busreq , ack , buserror , rdcen set-up to sysclk rising 11 8 5.5 5.5 ns t1a a/d set-up to sysclk falling 12 9 7 7 ns t2 busreq , ack , buserror , rdcen hold from sysclk rising 4 3 2.5 2.5 ns t2a a/d hold from sysclk falling 2 2 1 1 ns t3 a/d, addr, diag, ale, wr tri-state from sysclk rising 13 10 10 10 ns burst / wrnear , rd , dataen (after driven condition) t4 a/d, addr, diag, ale, wr driven from sysclk falling 13 10 10 10 ns burst / wrnear , rd , dataen (after tri-state condition) t5 busgnt asserted from sysclk rising 10 8 7 7 ns t6 busgnt negated from sysclk falling 10 8 7 7 ns t7 wr , rd , burst / wrnear , tc valid from sysclk rising 8 6 5 5 ns t7a a/d valid from sysclk rising 12 9 8 8 ns t7b last valid from sysclk rising 12 9 8 8 ns t8 ale asserted from sysclk rising 5 4 4 4 ns t9 ale negated from sysclk falling 5 4 4 4 ns t10 a/d hold from ale negated 2 2 2 1.5 ns t11 dataen asserted from sysclk 19151515ns t12 dataen asserted from a/d tri-state (4) 0000ns t14 a/d driven from sysclk rising (4) 0000ns t15 wr , rd , dataen , burst / wrnear , negated from sysclk falling 9 7 6 6 ns last , tc t16 addr(3:0), be 16(1:0) valid from sysclk 11 8 77ns t17 diag valid from sysclk 15121111ns t18 a/d tri-state from sysclk 13101010ns t19 a/d sysclk to data out 16 13 12 12 ns t20 clkin pulse width high 12 10 8 6.5 ns t21 clkin pulse width low 12 10 8 6.5 ns t22 clkin clock period 30 250 25 250 20 250 15 250 ns t23 reset pulse width from vcc valid 200 200 200 200 m s t24 reset minimum pulse width 32 32 32 32 sys t25 reset set-up to sysclk falling 8 6 5 5 ns t26 int mode set-up to reset rising 8 6 5 5 ns t27 int mode hold from reset rising 2.5 2.5 2.5 2.5 ns t28 sint , sbrcond set-up to sysclk falling 8 6 5 5 ns t29 sint , sbrcond hold from sysclk falling 4 3 3 3 ns t30 int , brcond set-up to sysclk falling 8 6 5 5 ns t31 int , brcond hold from sysclk falling 4 3 3 3 ns tsys sysclk pulse width 2*t22 2*t22 2*t22 2*t22 2*t22 2*t22 2*t22 2*t22 ns t32 sysclk clock high time t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 ns t33 sysclk clock low time t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 ns
16 idt79r3041 integrated riscontroller for low cost systems commercial temperature range advanced ac electrical characteristics r3041 (cont.) 16.67mhz 20mhz 25mhz 33mhz symbol signals description min. max. min. max. min. max. min. max. unit t45 extdataen tri-state from sysclk rising 13 10 10 10 ns (after driven condition) t46 extdataen driven from sysclk falling 13 10 10 10 ns (after driven condition) t47 iostrobe valid from sysclk falling 10 8 7 7 ns t48 extdataen , dataen asserted from sysclk rising 15 12 9 9 ns t49 extdataen negated from sysclk rising 9 7 6 6 ns t50 memstrobe asserted from sysclk rising 19 15 15 15 ns t51 memstrobe negated from sysclk falling 19 15 15 15 ns t52 memstrobe asserted from addr(3:0) valid (4) 0000ns tderate all outputs timing deration for loading 0.5 0.5 0.5 0.5 ns/ over 25pf (4, 5) 25pf notes: 2905 tbl 12 1. all timings referenced to 1.5 volts, with a rise and fall time of less than 2.5ns. 2. all outputs tested with 25pf loading. 3. the ac values listed here reference timing diagrams contained in the r3041 hardware user's manual. 4. guaranteed by design. 5. this parameter is used to derate the ac timings according to the loading of the system. this parameter provides a deration for loads over the specified test condition; that is, the deration factor is applied for each 25pf over the specified test load condition. 6. timings t34 - t44 are reserved for other riscontroller family members. recommended operating temperature and supply voltage output loading for ac testing absolute maximum ratings (1, 3) rv3041 symbol rating commercial unit v term terminal voltage with C0.5 to +7.0 v respect to gnd t c operating case temperature 0 to +85 c t bias temperature under bias C55 to +125 c t stg storage temperature C55 to +125 c v in input voltage C0.5 to +7.0 v notes: 2905 tbl 06 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v in minimum = C3.0v for pulse width less than 15ns. v in should not exceed v cc +0.5 volts. 3. not more than one output should be shorted at a time. duration of the short should not exceed 30 seconds. grade temperature gnd v cc commercial 0 c to +85 c 0v 3.3 5% rv3041 (case) 2905 tbl 07 - + to device under test c ld -4ma +4ma v ref +1.5v 2905 drw 07 signal cld all signals 25 pf 2905 tbl 09 symbol parameter min. max. unit v ih input high voltage 3.0 v v il input low voltage 0 v v ihs input high voltage 3.0 v v ils input low voltage 0 v ac test conditions rv3041 2905 tbl 08
17 idt79r3041 integrated riscontroller for low cost systems commercial temperature range advanced advanced dc electrical characteristics rv3041 (t c = 0 c to +85 c, v cc = +3.3v 5%) 16.67mhz 20mhz 25mhz 33mhz symbol parameter test conditions min. max. min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = C4ma 2.4 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4ma 0.4 0.4 0.4 0.4 v v ih input high voltage (3) 2.0 2.0 2.0 2.0 v v il input low voltage (1) 0.8 0.8 0.8 0.8 v v ihs input high voltage (2,3) 2.5 2.5 2.5 2.5 v v ils input low voltage (1,2) 0.4 0.4 0.4 0.4 v c in input capacitance (4) 10 10 10 10 pf c out output capacitance (4) 10 10 10 10 pf i cc operating current v cc = 3.3v, t c = 25 c 130 150 180 225 ma i ih input high leakage v ih = vcc 100 100 100 100 ma i il input low leakage v il = gnd C100 C100 C100 C100 ma i oz output tri-state leakage v oh = 2.4v, v ol = 0.5v C100 100 C100 100 C100 100 C100 100 ma notes: 2905 tbl 10 1. v il min. = C3.0v for pulse width less than 15ns. v il should not fall below C0.5 volts for larger periods. 2. v ihs and v ils apply to cikin and reset . 3. v ih should not be held above v cc + 0.5 volts. 4. guaranteed by design. ac electrical characteristics rv3041 (1, 2, 3) (t c = 0 c to +85 c, v cc = +3.3v 5%) 16.67mhz 20mhz 25mhz 33mhz symbol signals description min. max. min. max. min. max. min. max. unit t1 busreq , ack , buserror , set-up to sysclk rising 11 8 5.5 5.5 ns rdcen t1a a/d set-up to sysclk falling 12 9 7 7 ns t2 busreq , ack , buserror , hold from sysclk rising 4 3 2.5 2.5 ns rdcen t2a a/d hold from sysclk falling 2 2 1 1 ns t3 a/d, addr, diag, ale, wr tri-state from sysclk rising 13 10 10 10 ns burst/wrnear , rd , dataen (after driven condition) t4 a/d, addr, diag, ale, wr driven from sysclk falling 13 10 10 10 ns burst/wrnear , rd , dataen (after tri-state condition) t5 busgnt asserted from sysclk rising 10 8 7 7 ns t6 busgnt negated from sysclk falling 10 8 7 7 ns t7 wr , rd , burst/wrnear , tc valid from sysclk rising 8 6 5 5 ns t7a a/d valid from sysclk rising 12 9 8 8 ns t7b last valid from sysclk rising 12 9 8 8 ns t8 ale asserted from sysclk rising 5 4 4 4 ns t9 ale negated from sysclk falling 5 4 4 4 ns t10 a/d hold from ale negated 2 2 2 1.5 ns t11 dataen asserted from sysclk 19 15 15 15 ns t12 dataen asserted from a/d tri-state (4) 0000ns t14 a/d driven from sysclk rising (4) 0000ns t15 wr , rd , dataen , negated from sysclk falling 9 7 6 6 ns burst/wrnear , last, tc t16 addr(3:0), be 16(1:0) valid from sysclk 11 87 7ns t17 diag valid from sysclk 15 12 11 11 ns 2905 tbl 11
18 idt79r3041 integrated riscontroller for low cost systems commercial temperature range advanced 16.67 mhz 20 mhz 25mhz 33mhz symbol signals description min. max. min. max. min. max. min. max. unit t18 a/d tri-state from sysclk 13 10 10 10 ns t19 a/d sysclk to data out 16 13 12 12 ns t20 clkin pulse width high 12 10 8 6.5 ns t21 clkin pulse width low 12 10 8 6.5 ns t22 clkin clock period 30 250 25 250 20 250 15 250 ns t23 reset pulse width from vcc valid 200 200 200 200 m s t24 reset minimum pulse width 32 32 32 32 sys t25 reset set-up to sysclk falling 8 6 5 5 ns t26 int mode set-up to reset rising 8 6 5 5 ns t27 int mode hold from reset rising 2.5 2.5 2.5 2.5 ns t28 sint , sbrcond set-up to sysclk falling 8 6 5 5 ns t29 sint , sbrcond hold from sysclk falling 4 3 3 3 ns t30 int , brcond set-up to sysclk falling 8 6 5 5 ns t31 int , brcond hold from sysclk falling 4 3 3 3 ns tsys sysclk pulse width 2*t22 2*t22 2*t22 2*t22 2*t22 2*t22 2*t22 2*t22 ns t32 sysclk clock high time t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 ns t33 sysclk clock low time t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 ns t45 extdataen tri-state from sysclk rising 13 10 10 10 ns (after driven condition) t46 extdataen driven from sysclk falling 13 10 10 10 ns (after driven condition) t47 iostrobe valid from sysclk falling 10 8 7 7 ns t48 extdataen , asserted from sysclk rising 15 12 9 9 ns t49 extdataen negated from sysclk rising 9 7 6 6 ns dataen t50 memstrobe asserted from sysclk rising 19 15 15 15 ns t51 memstrobe negated from sysclk falling 19 15 15 15 ns t52 memstrobe asserted from addr(3:0) valid (4) 0 000ns tderate all outputs timing deration for loading 0.5 0.5 0.5 0.5 ns/ over 25pf (4, 5) 25pf notes: 2905 tbl 12 1. all timings referenced to 1.5 volts, with a rise and fall time of less than 2.5ns. 2. all outputs tested with 25pf loading. 3. the ac values listed here reference timing diagrams contained in the r3041 hardware user's manual. 4. guaranteed by design. 5. this parameter is used to derate the ac timings according to the loading of the system. this parameter provides a deration for loads over the specified test condition; that is, the deration factor is applied for each 25pf over the specified test load condition. 6. timings t34 - t44 are reserved for other riscontroller family members. ac electrical characteristics rv3041 (cont.)
19 idt79r3041 integrated riscontroller for low cost systems commercial temperature range figure 11. mode selection and negation of reset sysclk reset t 25 t 26 mode vector inputs: sint(2:0), int(5:3) t 27 mode vector inputs: addr(3:0), be16(1:0) t 4 cpu drives external device drives signals 2905 drw 12 figure 10(b). warm reset sequence (internal pull-ups used) figure 10(a). warm reset sequence figure 9. power-on reset sequence figure 8. riscontroller family clocking clkin sysclk t 20 t 21 t 22 t 32 t sys t 33 2905 drw 08 v cc clkin reset t 23 2905 drw 09 clkin reset t 24 2905 drw 10 clkin reset t 23 2905 drw 11
20 idt79r3041 integrated riscontroller for low cost systems commercial temperature range figure 12(a). start of read timing with non-extended address hold option figure 12(b). start of read timing with extended address hold option addr be sysclk rd a/d(31:0) ale addr(3:2) dataen address memory turn bus sample data? cached? i/d t 7 t 14 t 18 t 10 t 8 t 9 t 12 t 17 t 17 t 11 diag t 16 t 7a 2905 drw 13 addr be sysclk rd a/d(31:0) ale addr(3:2) dataen address memory extend address sample data? cached? i/d t 7 t 14 t 18 t 8 t 9 t 12 t 17 t 17 diag t 16 t 7a 2905 drw 14 t 48
21 idt79r3041 integrated riscontroller for low cost systems commercial temperature range figure 12(d). start of write timing with extended address hold option addr be sysclk wr a/d(31:0) ale addr(3:2) address memory extended address end write? t 7 t 14 t 19 t 8 t 9 t 48 extdataen wrnear t 7 data out t 7a t 16 2905 drw 16 figure 12(c). start of write timing with non-extended address hold option addr be sysclk wr a/d(31:0) ale addr(3:2) address memory data phase end write? t 7 t 14 t 19 t 10 t 8 t 9 t 48 extdataen wrnear t 7 data out t 7a t 16 2905 drw 15
22 idt79r3041 integrated riscontroller for low cost systems commercial temperature range figure 13. single datum read phiclk sysclk rd a/d(31:0) ale addr(3:2) addr be dataen rdcen word address stall stall stall stall stall fixup ack burst diag start read extended address sample data end read run/ stall ack/ rdcen cached? i/d data input t 7 t 14 t 8 t 7 t 12 t 1 t 2 t 15 t 2a t 15 t 1a t 14 t 17 t 17 t 18 t 16 extdataen t 49 t 48 last t 15 memstrobe iostrobe t 47 t 50 t 17 t 16 t 18 t 12 t 15 t 51 ack/ rdcen ? ack/ rdcen ? t 9 t 7a 2905 drw 17 t 7b
23 idt79r3041 integrated riscontroller for low cost systems commercial temperature range phiclk sysclk rd a/d(31:0) ale addr(3:0) addr dataen rdcen 'nn00' stall stall stall ack last diag start read extended address sample data new transaction run/ stall ack/ rdcen cached? t 7 t 14 t 8 t 9 t 7b t 12 t 2 t 17 t 17 t 18 t 15 byte 0 t 2a t 1a t 14 t 15 byte 1 t 2a t 1a byte 2 t 2a t 1a byte 3 t 2a t 1a 'nn01' 'nn10' 'nn11' t 1 t 2 t 1 t 2 t 1 t 2 t 16 t 16 t 16 sample data sample data sample data rdcen rdcen rdcen i/d t 16 extdataen t 49 t 48 burst t 7 memstrobe iostrobe t 50 t 47 t 50 t 51 t 50 t 50 t 51 t 51 t 16 t 1 t 15 t 15 t 17 stall stall stall fixup t 18 t 12 t 15 t 51 t 7a 2905 drw 18 figure 14. mini-burst read of 32-bit datum from 8-bit wide memory port
24 idt79r3041 integrated riscontroller for low cost systems commercial temperature range phiclk sysclk rd a/d(31:0) ale addr(3:2) addr be dataen rdcen '00' stall stall stall refill/ fixup ack last diag start read extended address sample data new transaction run/ stall ack/ rdcen cached t 7 t 14 t 8 t 9 t 7b t 12 t 1 t 2 t 17 t 17 t 18 t 15 word 0 t 2a t 1a t 14 t 15 word 1 t 2a t 1a word 2 t 2a t 1a word 3 t 2a t 1a '01' '10' '11' t 1 t 2 t 1 t 2 t 1 t 2 refill/ stream/ fixup refill/ stream/ fixup refill/ stream/ fixup t 16 t 16 t 16 sample data sample data sample data rdcen rdcen rdcen i/d word 0 word 1 word 2 word 3 t 16 extdataen t 49 t 48 burst t 7 memstrobe iostrobe t 50 t 47 t 50 t 51 t 50 t 50 t 51 t 51 t 16 t 17 t 15 t 15 t 51 t 18 t 12 t 7a 2905 drw 19 figure 15. r3041 quad word read
25 idt79r3041 integrated riscontroller for low cost systems commercial temperature range figure 16(a). quad word read to 16-bit wide memory port phiclk sysclk rd a/d(31:0) ale addr(3:1) addr dataen rdcen '000' stall stall stall ack last diag start read extended address sample data run/ stall cached t 7 t 14 t 8 t 9 t 12 t 17 t 17 t 18 t 15 halfword 0 t 2a t 1a t 14 halfword 1 t 2a t 1a halfword 2 t 2a t 1a halfword 3 t 2a t 1a '001' '010' '011' t 1 t 2 t 1 t 2 t 1 t 2 t 16 t 16 t 16 sample data sample data sample data rdcen rdcen rdcen i/d t 16 extdataen t 48 burst t 7 memstrobe iostrobe t 50 t 47 t 51 t 50 t 51 t 51 t 16 '100' t 51 t 1 t 2 be16(1:0) '00' '00' '00' '00' t 16 t 16 t 16 t 16 '00' rdcen stall stall stall stall t 1 t 2 rdcen t 16 t 50 t 50 t 50 t 18 t 12 t 7a 2905 drw 20
26 idt79r3041 integrated riscontroller for low cost systems commercial temperature range figure 16(b). end of quad word read from 16-bit wide memory port phiclk sysclk rd a/d(31:0) ale addr(3:1) dataen rdcen '100' stall refill/ fixup ack last diag sample data new transaction ack/ rdcen t 1 t 2 t 15 halfword 4 t 2a t 1a t 14 t 15 halfword 5 t 2a t 1a halfword 6 t 2a t 1a halfword 7 t 2a t 1a '101' '110' '111' t 1 t 2 t 1 t 2 t 1 t 2 refill/ stream/ fixup refill/ stream/ fixup refill/ stream/ fixup t 16 t 16 t 16 sample data sample data sample data rdcen rdcen rdcen word 0 word 1 word 2 word 3 stall i/d t 16 extdataen t 49 burst t 7b memstrobe iostrobe t 17 t 50 t 51 t 50 t 51 t 50 t 51 be16(1:0) '00' '00' '00' '00' t 16 t 16 t 16 t 16 t 51 t 15 2905 drw 21
27 idt79r3041 integrated riscontroller for low cost systems commercial temperature range sysclk wr a/d(31:0) ale addr(3:2) addr be word address ack wrnear start write extended address data out/ ack? ack? negate write new transfer ack data output t 7a t 14 t 8 t 7 t 1 t 2 t 15 t 14 t 19 t 16 extdataen t 49 t 11 last t 15 memstrobe iostrobe t 47 t 50 t 16 t 15 t 51 t 7 2905 drw 22 t 7b figure 17. basic write to 32-bit memory port
28 idt79r3041 integrated riscontroller for low cost systems commercial temperature range sysclk wr a/d(31:0) ale addr(3:0) addr ack 'nnnn' last start write extended address new transaction ack t 7 t 14 t 8 t 9 t 1 t 2 t 19 t 15 t 14 'nnnn+1' t 1 t 16 ack t 16 extdataen t 49 t 48 wrnear t 7 memstrobe iostrobe t 50 t 47 t 51 t 50 t 2 t 7b t 16 'nnnn+2' t 16 t 50 t 1 t 2 ack t 51 byte n t 19 t 19 byte n+1 byte n+2 negate write t 15 t 51 t 15 t 52 t 52 t 7a 2905 drw 23 figure 18. tri-byte mini-burst write to 8-bit port
29 idt79r3041 integrated riscontroller for low cost systems commercial temperature range sysclk busreq busgnt a/d(31:0) addr(3:0) diag rd wr ale burst/ wrnear t 1 t 2 t 5 t 3 last, be16(1:0), memstrobe iostrobe t 45 extdataen tc 2905 drw 24 figure 19. request and relinquish of r3041 bus to external master
30 idt79r3041 integrated riscontroller for low cost systems commercial temperature range sysclk busreq busgnt a/d(31:0) addr(3:0) diag rd wr ale burst/ wrnear t 1 t 2 t 6 t 4 last, be16(1:0) memstrobe iostrobe tc extdataen t 46 2905 drw 25 figure 20. r3041 regaining bus mastership
31 idt79r3041 integrated riscontroller for low cost systems commercial temperature range figure 21. r3041 dma pulse protocol figure 22. synchronized interrupt input timing figure 24. synchronized branch condition input timing figure 23. direct interrupt input timing phi sysclk int(n) exception vector run cycle 2905 drw 28 t 30 t 31 phi sysclk sint(n) exception vector run cycle 2905 drw 27 t 29 t 28 sysclk cpu bus request busreq a/d(31:0) busgnt t 6 t 4 t 1 t 2 2905 drw 26 phi sysclk sbrcond(n) bczt/f instruction capture brcond 2905 drw 29 run cycle t 28 t 29
32 idt79r3041 integrated riscontroller for low cost systems commercial temperature range figure 25. tc tc tc tc tc output sysclk tc t 7 t 15 2905 drw 30 dwg # j84-1 # of leads 84 symbol min. max. a 165 .180 a1 .095 .115 b .026 .032 b1 .013 .021 c .020 .040 c1 .008 .012 d 1.185 1.195 d1 1.150 1.156 d2/e2 1.090 1.130 d3/e3 1.000 ref e 1.185 1.195 e1 1.150 1.156 e .050 bsc nd/ne 21 2905 tbl 13 2874 drw 02 d d1 pin 1 e1 e e 45 x .045 b c1 seating plane d2/e2 d3/e3 b1 c a a1 2905 drw 31 84 lead plcc (square) notes: 1. all dimensions are in inches, unless otherwise noted. 2. bscbasic lead spacing between centers. 3. d & e do not include mold flash or protutions. 4. formed leads shall be planar with respect to one another and within .004 at the seating plane. 5. nd & ne represent the number of leads in the d & e directions respec- tively. 6. d1 & e1 should be measured from the bottom of the package. 7. plcc is pin & form compatible with mquad; the mquad package is used in other riscontroller family members.
33 idt79r3041 integrated riscontroller for low cost systems commercial temperature range 100-pin tqfp 1 100 e1 e d1 d a1 a2 e draft angle = 12 a3 b 100-pin tqfp standoff 0.05 min max 0.102 lead coplanarity 6 4 0.30 rad typ. 0.20 rad typ. l a dwg # tqfp # of leads 100 symbol min. max. a 1.60 a1 0.5 0.15 a2 1.35 1.45 d 15.75 16.25 d1 13.95 14.05 e 15.75 16.25 e1 13.95 14.05 l 0.45 0.70 n 100 e 0.50bsc b 0.17 0.27 ccc 0.08 ddd 0.08 r 0.08 0.20 r1 0.08 q 0 7.0 q 1 11.0 13.0 q 2 11.0 13.0 c 0.09 0.16 2905 tbl 14
34 idt79r3041 integrated riscontroller for low cost systems commercial temperature range ordering information valid combinations idt 79r3041 - 16 tqfp, plcc package 79r3041 - 20 tqfp, plcc package 79r3041 - 25 tqfp, plcc package 79r3041 - 33 plcc package only 79rv3041 - 16 tqfp, plcc package 79rv3041 - 20 tqfp, plcc package 79rv3041 - 25 tqfp, plcc package 79rv3041 - 33 tqfp, plcc package idt xxxxx device type xx speed x package ? process/ temp. range blank 'j' 'pf' '16' '20' '25' '33' 79r3041 79rv3041 commercial temperature range 84-pin plcc 100-pin tqfp 16.67mhz 20.00mhz 25.00mhz 33.00mhz 5.0v integrated riscontroller for low-cost systems 3.3v integrated riscontroller for low-cost systems 2905 drw 32

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