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1 features ? independent multiple channels echo cancellation; from 32 channels of 64ms to 16 channels of 128ms with the ability to mix channels at 128ms or 64ms in any combination ? independent power down mode for each group of 2 channels for power management ? conforms to itu-t g.165 and g.168 recommendations ? field proven, high quality performance ? compatible to st-bus and gci interface at 2mb/s serial pcm ? pcm coding, m /a-law itu-t g.711 or sign magnitude ? per channel fax/modem g.164 2100hz or g.165 2100hz phase reversal tone disable ? per channel echo canceller parameters control ? transparent data transfer and mute ? non-linear processor with high quality subjective performance ? protection against narrow band signal divergence ? offset nulling of all pcm channels ? 10 mhz or 20 mhz master clock operation ? 3.3 volts operation with 5-volt tolerant inputs ? no external memory required ? non-multiplexed microprocessor interface ? ieee-1149.1 (jtag) test access port applications ? voice over ip network gateways ? voice over atm, frame relay ? t1/e1/j1 multichannel echo cancellation ? wireless base stations ? echo canceller pools ? dcme, satellite and multiplexer systems description the MT9300 voice echo canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to itu-t g.168 requirements. the MT9300 architecture contains 16 groups of two echo cancellers (eca and ecb) which can be con?gured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation. this provides 32 channels of 64 milliseconds to 16 channels of 128 milliseconds echo cancellation or any combination of the two con?gurations. the MT9300 supports itu-t g.165 and g.164 tone disable requirements. figure 1 - functional block diagram reset rout ic0 sout ds cs r/ w a10-a0 dta d7-d0 test port microprocessor interface timing unit echo canceller pool v ss v dd tdi tdo tck trst tms rin irq c4i f0i mclk ode sin serial to parallel parallel to serial pll fsel group 0 eca/ecb group 4 eca/ecb group 8 eca/ecb group 12 eca/ecb group 1 eca/ecb group 5 eca/ecb group 9 eca/ecb group 13 eca/ecb group 2 eca/ecb group 6 eca/ecb group 10 eca/ecb group 14 eca/ecb group 3 eca/ecb group 7 eca/ecb group 11 eca/ecb group 15 eca/ecb note: refer to figure 3 for echo canceller block diagram ordering information MT9300al 160-pin mqfp -40 c to +85 c ds5030 issue 2 may 1999 MT9300 multi-channel voice echo canceller advance information
MT9300 advance information 2 figure 2 - pin connections pin description pin # name description 1, 2, 17, 27, 37, 38, 48, 58, 76, 77, 81, 87, 98, 108, 118, 119, 138, 139, 148, 149 v ss ground. 8, 22, 32, 43, 53, 63, 79, 93, 103, 113, 124, 141, 142, 159 v dd positive power supply. nominally 3.3 volt. 57, 59, 114, 115, 116,117, 120, 121,122, 133, 134, 135, 144, 145, 157, ic0 internal connection. these pins must be connected to v ss for normal operation. 160 pin mqfp 79 85 87 89 71 73 75 77 93 67 91 69 65 83 81 95 111 117 119 121 103 105 107 109 125 99 123 101 97 115 113 127 49 47 45 43 41 57 59 55 53 51 39 37 35 61 63 33 17 11 9 725 23 21 19 3 29 52731 13 15 1 129 133 131 135 137 141 139 143 145 149 147 151 153 157 155 159 nc nc nc nc nc nc nc v dd nc nc nc ic0 v ss ic0 a10 a9 a8 v dd a7 a6 a5 a4 v ss a3 a2 a1 a0 v dd nc nc nc v dd nc v ss v ss nc nc nc nc nc nc nc nc v ss d7 d6 d5 d4 v dd d3 d2 d1 d0 v ss nc nc nc dt a r/ w cs ds irq v dd nc nc nc nc nc v ss v ss nc nc v ss v ss nc nc nc nc v dd nc nc nc ic0 ic0 ic0 nc nc v ss v ss mclk v dd v dd fsel ic0 ic0 pllvss pllvdd v ss v ss nc nc tms tdi tdo tck trst ic0 reset v dd nc ic0 ic0 nc v dd nc nc nc nc nc nc rin sin v ss rout sout ode nc v dd nc nc nc nc v ss nc nc nc nc v dd nc nc nc nc nc v ss nc nc nc nc nc v ss ic0 v ss v ss ic0 ic0 ic0 ic0 v dd c4i f0i
advance information MT9300 3 3 to 7, 14 to 16, 28 to 31, 33 to 36, 39 to 42, 60 to 62, 64 to 75, 78, 80, 82 to 86, 88 to 92, 94 to 97, 99 to102, 104, 123, 125 to 132, 136, 137, 150,151,160 nc no connection. these pins must be left open for normal operation. 9 irq interrupt request (open drain output) . this output goes low when an interrupt occurs in any channel. irq returns high when all the interrupts have been read from the interrupt fifo register. a pull-up resistor (1k typical) is required at this output. 10 ds data strobe (input) . this active low input works in conjunction with cs to enable the read and write operations. 11 cs chip select (input). this active low input is used by a microprocessor to activate the microprocessor port. 12 r/ w read/ write (input) . this input controls the direction of the data bus lines (d7-d0) during a microprocessor access. 13 dt a data transfer acknowledgment (open drain output) . this active low output indicates that a data bus transfer is completed. a pull-up resistor (1k typical) is required at this output. 18, 19, 20, 21, 23, 24, 25, 26 d0 - d3, d4 - d7 data bus d0 - d7 (bidirectional) . these pins form the 8-bit bidirectional data bus of the microprocessor port. 44, 45,46, 47,49, 50, 51,52,54, 55, 56 a0 - a10 address a0 to a10 (input) . these inputs provide the a10 - a0 address lines to the internal registers. 105 ode output drive enable (input). this input pin is logically andd with the ode bit-6 of the main control register. when both ode bit and ode input pin are high, the rout and sout st-bus outputs are enabled. when the ode bit is low or the ode input pin is low, the rout and sout st-bus outputs are high impedance. 106 sout send pcm signal output (output) . port 1 tdm data output streams. sout pin outputs serial tdm data streams at 2.048 mb/s with 32 channels per stream. 107 rout receive pcm signal output (output) . port 2 tdm data output streams. rout pin outputs serial tdm data streams at 2.048 mb/s with 32 channels per stream. 109 sin send pcm signal input (input). port 2 tdm data input streams. sin pin receives serial tdm data streams at 2.048 mb/s with 32 channels per stream. 110 rin receive pcm signal input (input). port 1 tdm data input streams. rin pin receives serial tdm data streams at 2.048 mb/s with 32 channels per stream. 111 f0i frame pulse (input). this input accepts and automatically identi?es frame synchronization signals formatted according to st-bus or gci interface speci?cations. 112 c4i serial clock (input). 4.096 mhz serial clock for shifting data in/out on the serial streams (rin, sin, rout, sout). pin description (continued) pin # name description
MT9300 advance information 4 140 mclk master clock (input). nominal 10mhz or 20mhz master clock input. may be connected to an asynchronous (relative to frame signal) clock source. 143 fsel frequency select (input). this input selects the master clock frequency operation. when fsel pin is low, nominal 19.2mhz master clock input must be applied. when fsel pin is high, nominal 9.6mhz master clock input must be applied. 146 pllv ss pll ground. must be connected to v ss 147 pllv dd pll power supply. must be connected to v dd 152 tms test mode select (3.3v input). jtag signal that controls the state transitions of the tap controller. this pin is pulled high by an internal pull-up when not driven. 153 tdi test serial data in (3.3v input). jtag serial test instructions and data are shifted in on this pin. this pin is pulled high by an internal pull-up when not driven. 154 tdo test serial data out (output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag scan is not enabled. 155 tck test clock (3.3v input). provides the clock to the jtag test logic. 156 trst test reset (3.3v input). asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin should be pulsed low on power-up or held low, to ensure that the MT9300 is in the normal functional mode. this pin is pulled by an internal pull-down when not driven. 158 reset device reset (schmitt trigger input). an active low resets the device and puts the MT9300 into a low-power stand-by mode. when the reset pin is returned to logic high and a clock is applied to the mclk pin, the device will automatically execute initialization routines, which preset all the control and status registers to their default power-up values. pin description (continued) pin # name description device overview the MT9300 architecture contains 32 echo cancellers divided into 16 groups. each group has two echo cancellers, echo canceller a and echo canceller b. each group can be con?gured in normal, extended delay or back-to-back con?gurations. in normal con?guration , a group of echo cancellers provides two channels of 64ms echo cancellation, which run independently on different channels. in extended delay con?guration, a group of echo cancellers achieves 128ms of echo cancellation by cascading the two echo cancellers (a & b). in back-to-back con?guration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel, providing full-duplex 64ms echo cancellation. each echo canceller contains the following main elements (see figure 3). ? adaptive filter for estimating the echo channel ? subtractor for cancelling the echo ? double-talk detector for disabling the ?lter adaptation during periods of double-talk ? non-linear processor for suppression of residual echo ? disable tone detectors for detecting valid disable tones at the input of receive and send paths ? narrow-band detector for preventing adaptive filter divergence caused by narrow-band signals ? offset null ?lters for removing the dc component in pcm channels ? 12db attenuator for signal attenuation ? parallel controller interface compatible with motorola microcontrollers ? pcm encoder/decoder compatible with m /a- law itu-t g.711 or sign-magnitude coding
advance information MT9300 5 figure 3 - echo canceller functional block diagram linear/ m /a-law + non-linear processor offset null m /a-law/ linear linear/ m /a-law microprocessor interface double-talk detector disable tone detector adaptive filter control narrow-band detector m /a-law/ linear offset null echo canceller (n), where 0 n 31 sout rin sin rout - programmable bypass disable tone detector (channel n) (channel n) (channel n) (channel n) st-bus st-bus port2 port1 12db attenuator muter mutes each echo canceller in the MT9300 has four functional states: mute , bypass , disable adaptation and enable adaptation . these are explained in the section entitled echo canceller functional states. adaptive filter for each group of echo cancellers, the adaptive filter is a 1024 tap fir adaptive ?lter which is divided into two sections. each section contains 512 taps providing 64ms of echo estimation. in normal con?guration , the ?rst section is dedicated to channel a and the second section to channel b. in extended delay con?guration , both sections are cascaded to provide 128ms of echo estimation in channel a. in back-to back con?guration , the ?rst section is used in the receive direction and the second section is used in the transmit direction for the same channel. double-talk detector double-talk is de?ned as those periods of time when signal energy is present in both directions simultaneously. when this happens, it is necessary to disable the ?lter adaptation to prevent divergence of the adaptive filter coef?cients. note that when double-talk is detected, the adaptation process is halted but the echo canceller continues to cancel echo using the previous converged echo pro?le. a double-talk condition exists whenever the relative signal levels of rin (lrin) and sin (lsin) meet the following condition: lsin > lrin + 20log 10 (dtdt) where dtdt is the double-talk detection threshold. lsin and lrin are signal levels expressed in dbm0. a different method is used when it is uncertain whether sin consists of a low level double-talk signal or an echo return. during these periods, the adaptation process is slowed down but it is not halted. the convergence speed is shown by the conv bit in the status register. in g.168 standard, the echo return loss is expected to be at least 6db. this implies that the double-talk detector threshold (dtdt) should be set to 0.5 (-6db). however, in order to get additional guardband, the dtdt is set internally to 0.5625 (-5db). in some applications the return loss can be higher or lower than 6db. the MT9300 allows the user to change the detection threshold to suit each applications need. this threshold can be set by writing the desired threshold value into the dtdt register. the dtdt register is 16 bits wide. the register value in hexadecimal can be calculated with the following equation: dtdt (hex) = hex(dtdt (dec) * 32768) where 0 < dtdt (dec) < 1 example: for dtdt = 0.5625 (-5db), the hexadecimal value becomes hex( 0.5625 * 32768 ) = 4800h
MT9300 advance information 6 non-linear processor (nlp) after echo cancellation, there is always a small amount of residual echo which may still be audible. the MT9300 uses an nlp to remove residual echo signals which have a level lower than the adaptive suppression threshold (tsup in g.168). this threshold depends upon the level of the rin (lrin) reference signal as well as the programmed value of the non-linear processor threshold register (nlpthr). tsup can be calculated by the following equation: tsup = lrin + 20log 10 (nlpthr) where nlpthr is the non-linear processor threshold register value and lrin is the relative power level expressed in dbm0. when the level of residual error signal falls below tsup, the nlp is activated further attenuating the residual signal to less than -65dbm0. to prevent a perceived decrease in background noise due to the activation of the nlp, a spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. this keeps the perceived noise level constant. consequently, the user does not hear the activation and de-activation of the nlp. the nlp processor can be disabled by setting the nlpdis bit to 1 in control register 2. the nlpthr register is 16 bits wide. the register value in hexadecimal can be calculated with the following equation: nlpthr (hex) = hex(nlpthr (dec) * 32768) where 0 < nlpthr (dec) < 1 the comfort noise injection can be disabled by setting the injdis bit to 1 in control register a1/ b1. it should be noted that the nlpthr is valid and the comfort noise injection is active only when the nlp is enabled. disable tone detector g.165 recommendation de?nes the disable tone as having the following characteristics: 2100 hz ( 21hz) sine wave, a power level between -6 to -31dbm0, and a phase reversal of 180 degrees ( 25 degrees) every 450ms ( 25ms). if the disable tone is present for a minimum of one second with at least one phase reversal, the tone detector will trigger. g.164 recommendation de?nes the disable tone as a 2100 hz ( 21hz) sine wave with a power level between 0 to -31dbm0. if the disable tone is present for a minimum of 400 milliseconds, with or without phase reversal, the tone detector will trigger. the MT9300 has two tone detectors per channels (for a total of 64) in order to monitor the occurrence of a valid disable tone on both rin and sin. upon detection of a disable tone, td bit of the status register will indicate logic high and an interrupt is generated (i.e. irq pin low). refer to figure 4 and to the interrupts section. figure 4 - disable tone detection once a tone detector has been triggered, there is no longer a need for a valid disable tone (g.164 or g.165) to maintain tone detector status (i.e. td bit high). the tone detector status will only release (i.e. td bit low) if the signals rin and sin fall below - 30dbm0, in the frequency range of 390hz to 700hz, and below -34dbm0, in the frequency range of 700hz to 3400hz, for at least 400ms. whenever a tone detector releases, an interrupt is generated (i.e. irq pin low). the selection between g.165 and g.164 tone disable is controlled by the phdis bit in control register 2 on a per channel basis. when the phdis bit is set to 1, g.164 tone disable requirements are selected. in response to a valid disable tone, the echo canceller must be switched from the enable adaptation state to the bypass state. this can be done in two ways, automatically or externally. in automatic mode, the tone detectors internally control the switching between enable adaptation and bypass states. the automatic mode can be activated by setting the autotd bit in control register 2 to high. in external mode, an external controller is needed to service the interrupts and poll the td bits td bit rin sin echo canceller a tone detector tone detector status reg eca td bit rin sin echo canceller b tone detector tone detector status reg ecb
advance information MT9300 7 in the status registers. following the detection of a disable tone (td bit high) on a given channel, the external controller must switch the echo canceller from enable adaptation to bypass state. narrow band signal detector (nbsd) single or dual frequency tones (i.e. dtmf tones) present in the receive input (rin) of the echo canceller for a prolonged period of time may cause the adaptive filter to diverge. the narrow band signal detector (nbsd) is designed to prevent this divergence by detecting single or dual tones of arbitrary frequency, phase, and amplitude. when narrow band signals are detected, the adaptation process is halted but the echo canceller continues to cancel echo. the nbsd can be disabled by setting the nbdis bit to 1 in control register 2. offset null filter adaptive ?lters in general do not operate properly when a dc offset is present at any inputs. to remove the dc component, the MT9300 incorporates offset null ?lters in both rin and sin inputs. the offset null ?lters can be disabled by setting the hpfdis bit to 1 in control register 2. device con?guration the MT9300 architecture contains 32 echo cancellers divided into 16 groups. each group has two echo cancellers which can be individually controlled (echo canceller a and b). they can be set in three distinct con?gurations: normal, back-to- back, and extended delay . see figure 5. nor mal con?gur ation in normal con?guration, the two echo cancellers (echo canceller a and b) are positioned in parallel, as shown in figure 5a, providing 64 milliseconds of echo cancellation in two channels simultaneously. bac k-to-bac k con?gur ation in back-to-back con?guration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel providing full-duplex 64ms echo cancellation. see figure 5c. this con?guration uses only one timeslot on port1 and port2 and the second timeslot normally associated with ecb contains unde?ned data. back-to-back con?guration allows a no-glue interface for applications where bidirectional echo cancellation is required. back-to-back con?guration is selected by writing 1 into the bbm bit of both control register a1 and control register b1 of a given group of echo cancellers. table 2 shows the 16 groups of 2 figure 5 - device con?guration rin rout sout sin echo path a optional -12db pad echo path b + - channel a channel a + - channel b channel b e.c.a e.c.b a) normal con?guration (64ms) adaptive filter (64ms) adaptive filter (64ms) optional -12db pad port1 port2 + - channel a channel a e.c.a sin sout rout rin b) extended delay con?guration (128ms) echo path a adaptive filter (128 ms) optional -12db pad port1 port2 + e.c.a sin sout rout rin c) back-to-back con?guration (64ms) - e.c.b + - echo echo path path adaptive filter (64ms) optional -12db pad adaptive filter (64ms) optional -12db pad port1 port2
MT9300 advance information 8 cancellers that can each be con?gured into back-to- back. examples of back-to-back con?guration include positioning one group of echo cancellers between a codec and a transmission device or between two codecs for echo control on analog trunks. extended dela y con?gur ation in this con?guration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds echo canceller. see figure 5b. this con?guration uses only one timeslot on port1 and port2 and the second timeslot normally associated with ecb contains unde?ned data. extended delay con?guration is selected by writing 1 into the extdl bit in echo canceller a, control register a1. for a given group, only echo canceller a, control register a1, has the extdl bit. control register b1, bit-0 must always be set to zero. table 2 shows the 16 groups of 2 cancellers that can each be con?gured into 64ms or 128ms echo tail capacity. echo canceller functional states each echo canceller has four functional states: mute, bypass, disable adaptation and enable adaptation . mute in normal and in extended delay con?gurations, writing a 1 into the muter bit replaces rin with quiet code which is applied to both the adaptive filter and rout. writing a 1 into the mutes bit replaces the sout pcm data with quiet code. in back-to-back con?gur ation, wr iting a 1 into the muter bit of echo canceller a, control register 2, causes quiet code to be transmitted on rout. writing a 1 into the mutes bit of echo canceller a, control register 2, causes quiet code to be transmitted on sout. in extended delay and in back -to -back con?gurations, muter and mutes bits of echo canceller b must always be 0. refer to figure 3 and to control register 2 for bit description. bypass the bypass state directly transfers pcm codes from rin to rout and from sin to sout. when bypass state is selected, the adaptive filter coef?cients are reset to zero. disab le adaptation when the disable adaptation state is selected, the adaptive filter coef?cients are frozen at their current value. in this state, the adaptation process is halted however the echo canceller continues to cancel echo. enab le adaptation in enable adaptation state, the adaptive filter coef?cients are continually updated. this allows the echo canceller to model the echo return path characteristics in order to cancel echo. this is the normal operating state. the echo canceller functions are selected in control register a1/b1 and control register 2 through four control bits: mutes, muter, bypass and adaptdis. refer to the registers description for details. MT9300 throughput delay the throughput delay of the MT9300 varies according to the device con?guration. for all device con?gurations, rin to rout has a delay of two frames and sin to sout has a delay of three frames. in bypass state, the rin to rout and sin to sout paths have a delay of two frames. serial pcm i/o channels there are two sets of tdm i/o streams, each with channels numbered from 0 to 31. one set of input streams is for receive (rin) channels, and the other set of input streams is for send (sin) channels. likewise, one set of output streams is for rout pcm channels, and the other set is for sout channels. see ?gure 6 for channel allocation. the arrangement and connection of pcm channels to each echo canceller is a 2 port i/o con?guration for each set of pcm send and receive channels, as illustrated in figure 3. linear 16 bits 2s complement sign/ magnitude m -law a-law ccitt (g.711) m -law a-law +zero (quiet code) 0000h 80h ffh d5h table 1 - quiet pcm code assignment
advance information MT9300 9 serial data interface timing the MT9300 provides st-bus and gci interface timing. the serial interface clock frequency, c4i, is 4.096 mhz. the input and output data rate of the st- bus and gci bus is 2.048 mb/s. the 8 khz input frame pulse can be in either st-bus or gci format. the MT9300 automatically detects the presence of an input frame pulse and identi?es it as either st-bus or gci. in st-bus format, every second falling edge of the c4i clock marks a bit boundary, and the data is clocked in on the rising edge of c4i, three quarters of the way into the bit cell (see figure 9). in gci format, every second falling edge of the c4i clock marks the bit boundary, and data is clocked in on the second falling edge of c4i, half the way into the bit cell (see figure 10). memory mapped control and status registers internal memory and registers are memory mapped into the address space of the host interface. the internal dual ported memory is mapped into segments on a per channel basis to monitor and control each individual echo canceller and associated pcm channels. for example, in normal con?guration , echo canceller #5 makes use of echo canceller b from group 2. it occupies the internal address space from 0a0h to 0bfh and interfaces to pcm channel #5 on all serial pcm i/o streams. figure 7 - memory mapping of per channel control and status registers as illustrated in figure 7, the per channel registers provide independent control and status bits for each echo canceller. figure 8 shows the memory map of the control/status register blocks for all echo cancellers. 00h control reg a1 01h decay step size reg 02h 03h base 04h 06h reserved flat delay reg control reg 2 status reg reserved 05h reserved 08h decay step number 07h reserved 0ah rin peak detect reg 0ch sin peak detect reg 0eh error peak detect reg 10h reserved 12h dtdt reg 14h reserved 16h nlpthr 18h step size, mu 1ah reserved 1ch reserved 1eh addr + echo canceller a 20h control reg b1 21h decay step size reg 22h 23h 24h 26h reserved flat delay reg control reg 2 status reg reserved 25h reserved 28h decay step number 27h reserved 2ah rin peak detect reg 2ch sin peak detect reg 2eh error peak detect reg 30h reserved 32h dtdt reg 34h reserved 36h nlpthr 38h step size, mu 3ah reserved 3ch reserved 3eh base addr + echo canceller b figure 6 - st-bus and gci interface channel assignment for 2mb/s data streams f0i rin/sin rout/sout channel 31 channel 0 125 m sec channel 1 channel 30 st-bus f0i gci interface note: refer to figures 9 and 10 for timing details
MT9300 advance information 10 when extended delay or back-to-back con?guration is selected, control register a1/b1 and control register 2 of the selected group of echo cancellers require special care. refer to the register description section. table 2 is a list of the channels used for the 16 groups of echo cancellers when they are con?gured as extended delay or back-to-back nor mal con?gur ation for a given group (group 0 to 15), 2 pcm i/o channels are used. for example, group 1 echo cancellers a and b, channels 2 and 3 are active. extended dela y con?gur ation for a given group (group 0 to 15), only one pcm i/o channel is active (echo canceller a) and the other channel carries dont care data. for example, group 2, echo canceller a (channel 4) will be active and echo canceller b (channel 5) will carry dont care data. bac k-to-bac k con?gur ation for a given group (group 0 to 15), only one pcm i/o channel is active (echo canceller a) and the other channel carries dont care data. for example, group 5, echo canceller a (channel 10) will be active and echo canceller b (channel 11) will carry dont care data. figure 8 - memory mapping power up sequence on power up, the reset pin must be held low for 100 m s. forcing the reset pin low will put the MT9300 in power down state. in this state, all internal clocks are halted, d<7:0>, sout, rout, dt a and irq pins are tristated. the 16 main control registers, the interrupt fifo register and the test register are reset to zero. when the reset pin returns to logic high and a valid mclk is applied, the user must wait 500 m s for pll to lock. c4i and f0i can be active during this period. once the pll has locked, the user must power up the 16 groups of echo cancellers individually, by writing a 1 into the pwup bit in each group of echo cancellers main control register. for each group of echo cancellers, when the pwup bit toggles from zero to one, echo cancellers a and b execute their initialization routine. the initialization routine sets their registers, base address+00 h to base address+3f h , to the default reset value and clears the adaptive filter coef?cients. two frames are necessary for the initialization routine to execute properly. once the initialization routine is executed, the user can set the per channel control registers, base address+00 h to base address+3f h , for the speci?c application. group channel group channel 0 0, 1 8 16, 17 1 2, 3 9 18, 19 2 4, 5 10 20, 21 3 6, 7 11 22, 23 4 8, 9 12 24, 25 5 10, 11 13 26, 27 6 12, 13 14 28, 29 7 14, 15 15 30, 31 table 2 - group and channel allocation 0000h --> channel 0, ec a ctrl/stat registers 001fh 0020h --> channel 1, ec b ctrl/stat registers 003fh 0040h --> channel 2, ec a ctrl/stat registers 005fh 0060h --> channel 3, ec b ctrl/stat registers 007fh 03c0h --> channel 30, ec a ctrl/stat registers 03dfh 03e0h --> channel 31, ec b ctrl/stat registers 03ffh 0400h --> 040fh main control registers <15:0> group 0 echo cancellers registers groups 2 --> 14 echo cancellers registers group 1 echo cancellers registers group 15 echo cancellers registers 0410h interrupt fifo register 0411h test register
advance information MT9300 11 power management each group of echo cancellers can be placed in power down mode by writing a 0 into the pwup bit in their respective main control register. when a given group is in power down mode, the corresponding pcm data are bypassed from rin to rout and from sin to sout with two frames delay. refer to the main control register section for description. the typical power consumption can be calculated with the following equation: p c = 60 * nb_of_groups + 40, in mw where 0 nb_of_groups 16 call initialization to ensure fast initial convergence on a new call, it is important to clear the adaptive ?lter. this is done by momentarily putting the echo canceller in bypass mode and then enabling adaptation. interrupts the MT9300 provides an interrupt pin ( irq) to indicate to the host processor when a g.164 or g.165 tone disable is detected and released. although the MT9300 may be con?gured to react automatically to tone disable status on any input pcm voice channels, the user may want for the external host processor to respond to tone disable information in an appropriate, application speci?c manner. each echo canceller will generate an interrupt when a tone disable occurs and will generate another interrupt when a tone disable releases. upon receiving an irq, the host cpu should read the interrupt fifo register. this register is a fifo memory containing the channel number of the echo canceller that has generated the interrupt. all pending interrupts from any of the echo cancellers and their associated input channel number are stored in this fifo memory. the irq always returns high after a read access to the interrupt fifo register. the irq pin will toggle low for each pending interrupt. after the host cpu has received the channel number of the interrupt source, the corresponding per channel status register can be read from internal memory to determine the cause of the interrupt (see figure 7 for address mapping of status register). the td bit indicates the presence of a tone disable. the mirq bit 5 in the main control register 0 masks interrupts from the MT9300. to provide more ?exibility, the mtdbi (bit-4) and mtdai (bit-3) bits in the main control register<15:0> allow tone disable to be masked or unmasked, from generating an interrupt on a per channel basis. refer to the registers description section. jtag support the MT9300 jtag interface conforms to the boundary-scan standard ieee1149.1. this standard speci?es a design-for-testability technique called boundary-scan test (bst). the operation of the boundary scan circuitry is controlled by an external test access port (tap) controller. jtag inputs are 3.3 volts compliant only. test access port (tap) the tap provides access to many test functions of the MT9300. it consists of three input pins and one output pin. the following pins are found on the tap. ? test clock input (tck) the tck provides the clock for the test logic. the tck does not interfere with any on-chip clock and thus remains independent. the tck permits shifting of test data into or out of the boundary-scan register cells concurrent with the operation of the device and without interfering with the on-chip logic. ? test mode select input (tms) the logic signals received at the tms input are interpreted by the tap controller to control the test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to v dd when it is not driven from an external source. ? test data input (tdi) serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the tms input. both registers are described in a subsequent section. the received input data is sampled at
MT9300 advance information 12 the rising edge of tck pulses. this pin is internally pulled to v dd when it is not driven from an external source. ? test data output (tdo) depending on the sequence previously applied to the tms input, the contents of either the instruction register or data register are serially shifted out towards the tdo. the data from the tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high impedance state. ? test reset ( trst) this pin is used to reset the jtag scan structure. this pin is internally pulled to v ss . instruction register in accordance with the ieee 1149.1 standard, the MT9300 uses public instructions. the jtag interface contains a 3-bit instruction register. instructions are serially loaded into the instruction register from the tdi when the tap controller is in its shifted-ir state. subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that will operate while the instruction is current, and to de?ne the serial test data register path, which is used to shift data between tdi and tdo during data register scanning. test data registers as speci?ed in ieee 1149.1, the MT9300 jtag interface contains three test data registers: ? boundary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the MT9300 core logic. ? bypass register the bypass register is a single stage shift register that provides a one-bit path from tdi tdo. ? device identi?cation register the device identi?cation register provides access to the following encoded information: device version number, part number and manufacturer's name.
advance information MT9300 13 registers description bit name description 7 reset when high, the power-up initialization is executed which presets all register bits including this bit and clears the adaptive filter coef?cients. 6 injdis when high, the noise injection process is disabled. when low noise injection is enabled. 5 bbm when high the back to back con?guration is enabled. when low the normal con?guration is enabled. note: do not enable extended-delay and bbm con?gurations at the same time. always set both bbm bits of the two echo cancellers (control register a1 and control register b1) of the same group to the same logic value to avoid con?ict. 4 pad when high, 12db of attenuation is inserted into the rin to rout path. when low the rin to rout path gain is 0db. 3 bypass when high, sin data is by-passed to sout and rin data is by-passed to rout. the adaptive filter coef?cients are set to zero and the ?lter adaptation is stopped. when low, output data on both sout and rout is a function of the echo canceller algorithm. 2 adpdis when high, echo canceller adaptation is disabled. the MT9300 cancels echo. when low, the echo canceller dynamically adapts to the echo path characteristics. 1 0 or 1 bits marked as 1 or 0 are reserved bits and should be written as indicated. 0 extdl or 0 when high, echo cancellers a and b of the same group are internally cascaded into one 128ms echo canceller. when low, echo cancellers a and b of the same group operate independently. note: do not enable both extended-delay and bbm con?gurations at the same time. control register b1 bit-0 is a reserved bit and should be written 0. echo canceller a, control register a1 read/write address: 00 h + base address 0 adpdis bypass pad bbm injdis reset 76543210 extdl echo canceller b, control register b1 read/write address: 20 h + base address 1 adpdis bypass pad bbm injdis reset 76543210 0 reset value: 00 h . reset value: 02 h .
MT9300 advance information 14 bit name description 7 tdis when high, tone detection is disabled. when low, tone detection is enabled. when both echo cancellers a and b tdis bits are high, tone disable processors are disabled entirely and are put into power down mode. 6 phdis when high, the tone detectors will trigger upon the presence of a 2100hz tone regardless of the presence/absence of periodic phase reversals. when low, the tone detectors will trigger only upon the presence of a 2100hz tone with periodic phase reversals. 5 nlpdis when high, the non-linear processor is disabled. when low, the non-linear processors function normally. useful for g.165 conformance testing. 4 autotd when high, the echo canceller puts itself in bypass mode when the tone detectors detect the presence of 2100hz tone. see phdis for quali?cation of 2100hz tones. when low, the echo canceller algorithm will remain operational regardless of the state of the 2100hz tone detectors. 3 nbdis when high, the narrow-band detector is disabled. when low, the narrow-band detector is enabled. 2 hpfdis when high, the offset nulling high pass ?lters are bypassed in the rin and sin paths. when low, the offset nulling ?lters are active and will remove dc offsets on pcm input signals. 1 mutes when high, data on sout is muted to quiet code. when low, sout carries active code. 0 muter when high, data on rout is muted to quiet code. when low, rout carries active code. echo canceller a, control register 2 echo canceller b, control register 2 muter mutes hpfdis nbdis autotd nlpdis phdis tdis 76543210 reset value: 00 h . read/write address: 01 h + base address read/write address: 21 h + base address
advance information MT9300 15 bit name description 7 res reserved bit. 6 td logic high indicates the presence of a 2100hz tone. 5 dtdet logic high indicates the presence of a double-talk condition. 4 res reserved bit. 3 res reserved bit. 2 res reserved bit. 1 tdg tone detection status bit gated with the autotd bit. logic high indicates that autotd has been enabled and the tone detector has detected the presence of a 2100hz tone. 0 nb logic high indicates the presence of a narrow-band signal on rin. echo canceller a, status register echo canceller b, status register nb tdg res res res dtdet td res 76543210 reset value: 00 h . read address: 02 h + base address read address: 22 h + base address
MT9300 advance information 16 fd 7 fd 6 fd 5 fd 4 fd 2 fd 1 fd 0 fd 3 power reset value 00h 76543210 echo canceller a, flat delay register (fd) read/write address: 04h + base address echo canceller b, flat delay register (fd) read/write address: 24h + base address power reset value 00h 76543210 ns 7 ns 6 ns 5 ns 4 ns 2 ns 1 ns 0 ns 3 echo canceller a, decay step number register (ns) read/write address: 07h + base address echo canceller b, decay step number register (ns) read/write address: 27h + base address power reset value 04h 76543210 0000 ssc 2 ssc 1 ssc 0 0 echo canceller a, decay step size control register (ssc) read/write address: 06h + base address echo canceller b, decay step size control register (ssc) read/write address: 26h + base address note: bits marked with 0 are reserved bits and should be written 0. amplitude of mu time flat delay (fd 7-0 ) step size (ss) 1.0 2 -16 fir filter length (512 or 1024 taps) number of steps (ns 7-0 ) the exponential decay registers (decay step number and decay step size) and flat delay register allow the lms adaptation step-size (mu) to be programmed over the length of the fir ?lter. a programmable mu pro?le allows the performance of the echo canceller to be optimized for speci?c applications. for example, if the characteristic of the echo response is known to have a ?at delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the mu pro?le can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the adaptive filter. note that in the following register descriptions, one tap is equivalent to 125 m s (64ms/512 taps). fd 7-0 flat delay : this register de?nes the ?at delay of the mu pro?le, (i.e., where the mu value is 2 -16 ). the delay is de?ned as fd 7-0 x 8 taps. for example; if fd 7-0 = 5, then mu=2 -16 for the ?rst 40 taps of the echo canceller fir ?lter. the valid range of fd 7-0 is: 0 fd 7-0 64 in normal mode and 0 fd 7-0 128 in extended-delay mode. the default value of fd 7- 0 is zero. ssc 2-0 decay step size control : this register controls the step size (ss) to be used during the exponential decay of mu. the decay rate is de?ned as a decrease of mu by a factor of 2 every ss taps of the fir ?lter, where ss = 4 x2 ssc 2-0 . for example; if ssc 2-0 = 4, then mu is reduced by a factor of 2 every 64 taps of the fir ?lter. the default value of ssc 2-0 is 04h. ns 7-0 decay step number : this register defines the number of steps to be used for the decay of mu where each step has a period of ss taps (see ssc 2-0 ). the start of the exponential decay is defined as: filter length (512 or 1024) - [decay step number (ns 7-0 ) x step size (ss)] where ss = 4 x2 ssc 2-0 . for example, if ns 7-0 =4 and ssc 2-0 =4, then the exponential decay start value is 512 - [ns 7-0 x ss] = 512 - [4 x (4x2 4 )] = 256 taps for a filter length of 512 taps.
advance information MT9300 17 power reset value n/a 76543210 rp 15 rp 14 rp 13 rp 12 rp 10 rp 9 rp 8 rp 11 echo canceller a, rin peak detect register 2 (rp) read address: 0dh + base address echo canceller b, rin peak detect register 2 (rp) read address: 2dh + base address power reset value n/a 76543210 rp 7 rp 6 rp 5 rp 4 rp 2 rp 1 rp 0 rp 3 echo canceller a, rin peak detect register 1 (rp) read address: 0ch + base address echo canceller b, rin peak detect register 1 (rp) read address: 2ch + base address these peak detector registers allow the user to monitor the receive in signal (rin) peak signal level. the information is in 16 -bit 2s complement linear coded format presented in two 8 bit registers for each echo canceller. the high byte is in register 2 and the low byte is in register 1. power reset value n/a 76543210 sp 15 sp 14 sp 13 sp 12 sp 10 sp 9 sp 8 sp 11 echo canceller a, sin peak detect register 2 (sp) read address: 0fh + base address echo canceller b, sin peak detect register 2 (sp) read address: 2fh + base address power reset value n/a 76543210 sp 7 sp 6 sp 5 sp 4 sp 2 sp 1 sp 0 sp 3 echo canceller a, sin peak detect register 1 (sp) read address: 0eh + base address echo canceller b, sin peak detect register 1 (sp) read address: 2eh + base address these peak detector registers allow the user to monitor the send in signal (sin) peak signal level. the information is in 16-bi t 2s complement linear coded format presented in two 8 bit registers for each echo canceller. the high byte is in register 2 and the low byte is in register 1. power reset value n/a 76543210 ep 15 ep 14 ep 13 ep 12 ep 10 ep 9 ep 8 ep 11 echo canceller a, error peak detect register 2 (ep) read address: 11h + base address echo canceller b, error peak detect register 2 (ep) read address: 31h + base address power reset value n/a 76543210 ep 7 ep 6 ep 5 ep 4 ep 2 ep 1 ep 0 ep 3 echo canceller a, error peak detect register 1 (ep) read address: 10h + base address echo canceller b, error peak detect register 1 (ep) read address: 30h + base address these peak detector registers allow the user to monitor the error signal peak level. the information is in 16-bit 2s complemen t linear coded format presented in two 8 bit registers for each echo canceller. the high byte is in register 2 and the low byte i s in register 1.
MT9300 advance information 18 power reset value 48h 7654 3 2 1 0 dtdt 15 dtdt 14 dtdt 13 dtdt 12 dtdt 10 dtdt 9 dtdt 8 dtdt 11 echo canceller a, double-talk detection threshold register 2 read/write address: 15h + base address echo canceller b, double-talk detection threshold register 2 read/write address: 35h + base address power reset value 00h 7 6543 2 1 0 dtdt 7 dtdt 6 dtdt 5 dtdt 4 dtdt 2 dtdt 1 dtdt 0 dtdt 3 echo canceller a, double-talk detection threshold register 1 read/write address: 14h + base address echo canceller b, double-talk detection threshold register 1 read/write address: 34h + base address this register allows the user to program the level of double-talk detection threshold (dtdt). the 16 bit 2s complement linear value defaults to 4800h= 0.5625 or -5db. the maximum value is 7fffh = 0.9999 or 0 db. the high byte is in register 2 and the low byte is in register 1. (dtdt) (dtdt) power reset value 0bh 76543210 nlp 15 nlp 14 nlp 13 nlp 12 nlp 10 nlp 9 nlp 8 nlp 11 echo canceller a, non-linear processor threshold register 2 read/write address: 19h + base address echo canceller b, non-linear processor threshold register 2 read/write address: 39h + base address power reset value 60h 76543210 nlp 7 nlp 6 nlp 5 nlp 4 nlp 2 nlp 1 nlp 0 nlp 3 echo canceller a, non-linear processor threshold register 1 read/write address: 18h + base address echo canceller b, non-linear processor threshold register 1 read/write address: 38h + base address this register allows the user to program the level of the non-linear processor threshold (nlpthr). the 16 bit 2s complement linear value defaults to 0b60h = 0.0889 or -21.0db. the maximum value is 7fffh = 0.9999 or 0 db. the high byte is in register 2 and the low byte is in register 1. (nlpthr) (nlpthr) power reset value 40h 76543210 mu 15 mu 14 mu 13 mu 12 mu 10 mu 9 mu 8 mu 11 echo canceller a, adaptation step size (mu) register 2 read/write address: 1bh + base address echo canceller b, adaptation step size (mu) register 2 read/write address: 3bh + base address power reset value 00h 76543210 mu 7 mu 6 mu 5 mu 4 mu 2 mu 1 mu 0 mu 3 echo canceller a, adaptation step size (mu) register 1 read/write address: 1ah + base address echo canceller b, adaptation step size (mu) register 1 read/write address: 3ah + base address this register allows the user to program the level of mu. mu is a 16 bit 2s complement value which defaults to 4000h = 1.0 the maximum value is 7fffh or 1.9999 decimal. the high byte is in register 2 and the low byte is in register 1. (mu) (mu)
advance information MT9300 19 bit name description 7 wr_all write all control bit: when high, group 0-15 echo cancellers registers are mapped into 0000h to 003f which is group 0 address mapping. useful to initialize the 16 groups of echo cancellers as per group 0. when low, address mapping is per figure 8. note: only the main control register 0 has the wr_all bit. 6 ode output data enable: this control bit is logically andd with the ode input pin. when both ode bit and ode input pin are high, the rout and sout outputs are enabled. when the ode bit is low or the ode input pin is low, the rout and sout outputs are high impedance . note: only the main control register 0 has the ode bit. 5 mirq mask interrupt: when high, all the interrupts from the tone detectors output are masked. the tone detectors operate as speci?ed in their echo canceller b, control register 2. when low, the tone detectors interrupts are active. note: only the main control register 0 has the mirq bit. 4 mtdbi mask tone detector b interrupt: when high, the tone detector interrupt output from echo canceller b is masked. the tone detector operates as speci?ed in echo canceller b, control register 2. when low, the tone detector b interrupt is active. 3 mtdai mask tone detector a interrupt: when high, the tone detector interrupt output from echo canceller a is masked. the tone detector operates as speci?ed in echo canceller a, control register 2. when low, the tone detector a interrupt is active. 2 format itu-t/sign mag: when high, both echo cancellers a and b for a given group, accept itu-t (g.711) pcm code. when low, both echo cancellers a and b for a given group, accept sign-magnitude pcm code . 1lawa/ m law: when high, both echo cancellers a and b for a given group, accept a-law companded pcm code. when low, both echo cancellers a and b for a given group, accept m -law companded pcm code. 0 pwup power-up: when high, both echo cancellers a and b and tone detectors for a given group, are active. when low, both echo cancellers a and b and tone detectors for a given group, are placed in power down mode. in this mode, the corresponding pcm data are bypassed from rin to rout and from sin to sout with two frames delay. when the pwup bit toggles from zero to one, the echo canceller a and b execute their initialization routine which presets their registers, base address+00h to base address+3fh, to default reset value and clears the adaptive filter coef?cients. two frames are necessary for the initialization routine to execute properly. once the initialization routine is executed, the user can set the per channel control registers for their speci?c application. main control register 0 (ec group 0) read/write address: 400 h pwup law format mtdai mtdbi mirq ode wr_all 76543210 reset value: 00 h .
MT9300 advance information 20 bit name description 7-5 unused unused bits. 4 mtdbi mask tone detector b interrupt: when high, the tone detector interrupt output from echo canceller b is masked. the tone detector operates as speci?ed in echo canceller b, control register 2. when low, the tone detector b interrupt is active. 3 mtdai mask tone detector a interrupt: when high, the tone detector interrupt output from echo canceller a is masked. the tone detector operates as speci?ed in echo canceller a, control register 2. when low, the tone detector a interrupt is active. 2 format itu-t/sign mag: when high, both echo cancellers a and b for a given group, select itu-t (g.711) pcm code. when low, both echo cancellers a and b for a given group, select sign-magnitude pcm code . 1lawa/ m law: when high, both echo cancellers a and b for a given group, select a-law companded pcm code. when low, both echo cancellers a and b for a given group, select m-law companded pcm code . 0 pwup power-up: when high, both echo cancellers a and b and tone detectors for a given group, are active. when low, both echo cancellers a and b and tone detectors for a given group, are placed in power down mode. in this mode, the corresponding pcm data are bypassed from rin to rout and from sin to sout with two frames delay. when the pwup bit toggles from zero to one, the echo cancellers a and b execute their initialization routine which presets their registers, base address+00h to base address+3fh, to default reset value and clears the adaptive filter coef?cients. two frames are necessary for the initialization routine to execute properly. once the initialization routine is executed, the user can set the per channel control registers for their speci?c application. pwup law format mtdai mtdbi unused unused unused 76543210 reset value: 00 h . main control register 1 (ec group 1) read/write address: 401 h main control register 2 (ec group 2) read/write address: 402 h main control register 3 (ec group 3) read/write address: 403 h main control register 4 (ec group 4) read/write address: 404 h main control register 5 (ec group 5) read/write address: 405 h main control register 6 (ec group 6) read/write address: 406 h main control register 7 (ec group 7) read/write address: 407 h main control register 8 (ec group 8) read/write address: 408 h main control register 9 (ec group 9) read/write address: 409 h main control register 10 (ec group 10) read/write address: 40a h main control register 11 (ec group 11) read/write address: 40b h main control register 12 (ec group 12) read/write address: 40c h main control register 13 (ec group 13) read/write address: 40d h main control register 14 (ec group 14) read/write address: 40e h main control register 15 (ec group 15) read/write address: 40f h
advance information MT9300 21 bit name description 7 irq logic high indicates an interrupt has occurred. irq bit is cleared after the interrupt fifo register is read. logic low indicates that no interrupt is pending and the fifo is empty. 6:5 0 unused bits. always zero 4:0 i<4:0> i<4:0> binary code indicates the channel number at which a tone detector state change has occurred. note: whenever a tone disable is detected or released, an interrupt is generated. bit name description 7:1 res reserved bits. must always be set to zero for normal operation. 0 tirq test irq: useful for the application engineer to verify the interrupt service routine. when high, any change to mtdbi and mtdai bits of the main control register will cause an interrupt and its corresponding channel number will be available from the interrupt fifo register. when low, normal operation is selected. interrupt fifo register i0 i1 i2 i3 i4 0 0 irq 76543210 reset value: 00 h . read address: 410 h (read only) test register tirq res res res res res res res 76543210 reset value: 00 h . read/write address: 411 h
MT9300 advance information 22 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. recommended operating conditions - voltages are with respect to ground (vss) unless otherwise stated. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing ? characteristics are over recommended operating conditions unless otherwise stated ? typical ?gures are at 25 c, v dd =3.3v and are for design aid only: not guaranteed and not subject to production testing. * note 1: maximum leakage on pins (output or i/o pins in high impedance state) is over an applied voltage ( v in ). absolute maximum ratings* parameter symbol min max units 1 supply voltage v dd -0.3 5.0 v 2 voltage on any 3.3v i/o pins (other than supply pins) v i3 v ss - 0.3 v dd +0.5 v 3 voltage on any 5v tolerant i/o pins (other than sup- ply pins) v i5 v ss - 0.3 5.5 v 4 continuous current at digital outputs i o 20 ma 5 package power dissipation p d 2.0 w 6 storage temperature t s -55 150 c characteristics sym min typ ? max units test conditions 1 operating temperature t op -40 +85 c 2 positive supply v dd 3.0 3.3 3.6 v 3 input high voltage on 3.3v tolerant v ih3 0.7v dd v dd v 4 input high voltage on 5v tolerant v ih5 0.7v dd 5.5 v 5 input low voltage v il 0.3v dd v dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 i n p u t s supply current i cc 250 m a reset = 0 i dd 308 375 ma all channels active 2 power consumption p c 1.0 1.35 w all channels active 3 input high voltage v ih 0.7v dd v 4 input low voltage v il 0.3v dd v 5 input leakage input leakage on pullup input leakage on pulldown i ih /i il i lu i ld -30 30 10 -55 65 m a m a m a v in =v ss to v dd or 5.5v v in =v ss v in =v dd see note 1 6 input pin capacitance c i 10 pf 7 o u t p u t s output high voltage v oh 0.8v dd vi oh = 12 ma 8 output low voltage v ol 0.4 v i ol = 12 ma 9 high impedance leakage i oz 10 m av in =v ss to 5.5v 10 output pin capacitance c o 10 pf
advance information MT9300 23 ? characteristics are over recommended operating conditions unless otherwise stated i ? characteristics are over recommended operating conditions unless otherwise stated ? typical ?gures are at 25 c, v dd =3.3v and for design aid only: not guaranteed and not subject to production testing ? characteristics are over recommended operating conditions unless otherwise stated ? typical ?gures are at 25 c, v dd =3.3v and for design aid only: not guaranteed and not subject to production testing * note1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . ac electrical characteristics ? - timing parameter measurement voltage levels - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym level units conditions 1 cmos threshold v tt 0.5v dd v 2 cmos rise/fall threshold voltage high v hm 0.7v dd v 3 cmos rise/fall threshold voltage low v lm 0.3v dd v ac electrical characteristics ? - frame pulse and c4i characteristic sym min typ ? max units notes 1 frame pulse width (st-bus, gci) t fpw 20 2* t cp -20 ns 2 frame pulse setup time before c4i falling (st-bus or gci) t fps 10 122 150 ns 3 frame pulse hold time from c4i falling (st-bus or gci) t fph 10 122 150 ns 4 c4i period t cp 190 244.1 300 ns 5 c4i pulse width high t ch 85 150 ns 6 c4i pulse width low t cl 85 150 ns 7 c4i rise/fall time t r , t f 10 ns ac electrical characteristics ? - serial streams for st-bus and gci backplanes characteristic sym min typ ? max units test conditions 1 rin/sin set-up time t sis 10 ns 2 rin/sin hold time t sih 10 ns 3 rout/sout delay - active to active t sod 60 ns c l =150pf 4 output data enable (ode) delay t ode 30 ns c l =150pf, r l =1k see note 1
MT9300 advance information 24 figure 9 - st-bus timing at 2.048 mb/s figure 10 - gci interface timing at 2.048 mb/s figure 11 - output driver enable (ode) v tt v tt f0i c4i t fpw rout/sout rin/sin t fph t sod t sih t ch t cl bit 0, channel 31 t fps t cp t sis v tt v tt bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 bit 0, channel 31 bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 v hm v lm t r t f v tt v tt f0i c4i t fpw sout/rout sin/rin t fph t sod t sih t ch t cl bit 7, channel 31) t fps t cp t sis v tt v tt bit 0, channel 0 bit 1, channel 0 bit 2, channel 0 bit 7, channel 31) bit 0, channel 0 bit 1, channel 0 bit 2, channel 0 t r t f v hm v lm v tt hiz hiz sout/rout ode t ode t ode valid data v tt
advance information MT9300 25 ? characteristics are over recommended operating conditions unless otherwise stated ? typical ?gures are at 25 c, v dd =3.3v and for design aid only: not guaranteed and not subject to production testing figure 12 - master clock ac electrical characteristics ? - master clock - voltages are with respect to ground (v ss ). unless otherwise stated. characteristic sym min typ ? max units notes 1 master clock frequency, - fsel = 0 - fsel = 1 f mcf0 f mcf1 19.0 9.5 20.0 10.0 21.0 10.5 mhz mhz 2 master clock low t mcl 20 ns 3 master clock high t mch 20 ns t mch t mcl v tt mclk
MT9300 advance information 26 ? characteristics are over recommended operating conditions unless otherwise stated ? typical ?gures are at 25 c, v dd =3.3v and for design aid only: not guaranteed and not subject to production testing * note 1:high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . figure 13 - motorola non-multiplexed bus timing ac electrical characteristics ? - motorola non-multiplexed bus mode characteristics sym min typ ? max units test conditions 1 cs setup from ds falling t css 0ns 2r/ w setup from ds falling t rws 0ns 3 address setup from ds falling t ads 0ns 4 cs hold after ds rising t csh 0ns 5r/ w hold after ds rising t rwh 0ns 6 address hold after ds rising t adh 0ns 7 data delay on read t ddr 79 ns c l =150pf, r l =1k 8 data hold on read t dhr 315nsc l =150pf, r l =1k see note 1 9 data setup on write t dsw 0ns 10 data hold on write t dhw 0ns 11 acknowledgment delay t akd 80 ns c l =150pf, r l =1k 12 acknowledgment hold time t akh 0 8 ns c l =150pf, r l =1k, see note 1 13 irq delay t ird 20 65 ns c l =150pf, r l =1k, see note 1 ds a0-a10 cs d0-d7 d0-d7 read write t css t csh t adh t dhr t rws r/ w t ads t rwh t dhw t akd t dsw t ddr t akh dta v tt v tt v tt v tt v tt v tt v tt valid address valid read data valid write data t ird irq v tt
package outlines metric quad flat pack - l suf?x note: governing controlling dimensions in parenthesis ( ) are in millimeters. dim 44-pin 64-pin 100-pin 128-pin min max min max min max min max a - 0.096 (2.45) - 0.134 (3.40) - 0.134 (3.40) - 0.154 (3.85) a1 0.01 (0.25) - 0.01 (0.25) - 0.01 (0.25) - 0.00 0.01 (0.25) a2 0.077 (1.95) 0.083 (2.10) 0.1 (2.55) 0.12 (3.05) 0.1 (2.55) 0.12 (3.05) 0.125 (3.17) 0.144 (3.60) b 0.01 (0.30) 0.018 (0.45) 0.013 (0.35) 0.02 (0.50) 0.009 (0.22) 0.015 (0.38) 0.019 (0.30) 0.018 (0.45) d 0.547 bsc (13.90 bsc) 0.941 bsc (23.90 bsc) 0.941 bsc (23.90 bsc) 1.23 bsc (31.2 bsc) d 1 0.394 bsc (10.00 bsc) 0.787 bsc (20.00 bsc) 0.787 bsc (20.00 bsc) 1.102 bsc (28.00 bsc) e 0.547 bsc (13.90 bsc) 0.705 bsc (17.90 bsc) 0.705 bsc (17.90 bsc) 1.23 bsc (31.2 bsc) e 1 0.394 bsc (10.00 bsc) 0.551 bsc (14.00 bsc) 0.551 bsc (14.00 bsc) 1.102 bsc (28.00 bsc) e 0.031 bsc (0.80 bsc) 0.039 bsc (1.0 bsc) 0.256 bsc (0.65 bsc) 0.031 bsc (0.80 bsc) l 0.029 (0.73) 0.04 (1.03) 0.029 (0.73) 0.04 (1.03) 0.029 (0.73) 0.04 (1.03) 0.029 (0.73) 0.04 (1.03) l1 0.077 ref (1.95 ref) 0.077 ref (1.95 ref) 0.077 ref (1.95 ref) 0.063 ref (1.60 ref) a 1 a index d 1 b e e 1 e pin 1 d a 2 notes: 1) not to scale 2) top dimensions in inches warning: this package diagram does not apply to the mt90810ak 100 pin package. please refer to the data sheet for exact dimensions. l l1 3) the governing controlling dimensions are in millimeters for design purposes ( )
package outlines note: governing controlling dimensions in parenthesis ( ) are in millimeters. dim 160-pin 208-pin 240-pin min max min max min max a - 0.154 (3.92) .161 (4.10) - 0.161 (4.10) a1 0.01 (0.25) 0.01 (0.25) 0.02 (0.50) 0.01 (0.25) 0.02 (0.50) a2 0.125 (3.17) 0.144 (3.67) .126 (3.20) .142 (3.60) 0.126 (3.2) 0.142 (3.60) b 0.009 (0.22) 0.015 (0.38) .007 (0.17) .011 (0.27) 0.007 (0.17) 0.010 (0.27) d 1.23 bsc (31.2 bsc) 1.204 (30.6) 1.360 bsc (34.6 bsc) d 1 1.102 bsc (28.00 bsc) 1.102 (28.00) 1.26 bsc (32.00 bsc) e 1.23 bsc (31.2 bsc) 1.204 bsc (30.6 bsc) 1.360 bsc (34.6 bsc) e 1 1.102 bsc (28.00 bsc) 1.102 bsc (28.00 bsc) 1.26 bsc (32.00 bsc) e 0.025 bsc (0.65 bsc) 0.020 bsc (0.50 bsc) 0.0197 bsc (0.50 bsc) l 0.029 (0.73) 0.04 (1.03) 0.018 (0.45) 0.029 (0.75) 0.018 (0.45) 0.029 (0.75) l1 0.063 ref (1.60 ref) 0.051 ref (1.30 ref) 0.051 ref (1.30 ref)
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.

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