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mixed-signal front end for broadband applications AD9878 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2005 analog devices, inc. all rights reserved. features low cost 3.3 v cmos mxfe? for broadband applications docsis, euro-docsis, dvb, davic compliant 232 mhz quadrature digital upconverter 12-bit direct if dac (txdac+?) up to 65 mhz carrier frequency dds programmable sampling clock rates analog tx output level adjust dual 12-bit, 29 msps direct if adcs with video clamp input 10-bit, 29 msps sampling adc 8-bit -? auxiliary dac direct interface to ad832x family of pga cable drivers applications cable set-top boxes cable and wireless modems functional block diagram 03277-001 ? i q 12 txid[5:0] - ? output ca port mclk oscin if10 input if12b input video in if12a input clamp level tx sdio if10[4:0] if12[11:0] flag[2:1] tx 16 dds sinc ?1 - ? 4 10 3 12 12 mux adc adc adc mux mux mux dac control registers pll figure 1. general description the AD9878 is a single-supply, cable modem/set-top box, mixed-signal front end. the device contains a transmit path interpolation filter, a complete quadrature digital upconverter, and a transmit dac. the receive path contains dual 12-bit adcs and a 10-bit adc. all internally required clocks and an output system clock are generated by the phase-locked loop (pll) from a single crystal oscillator or clock input. the transmit path interpolation filter provides an upsampling factor of 16 with an output signal bandwidth up to 4.35 mhz. carrier frequencies up to 65 mhz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (dds). the transmit dac resolution is 12 bits and can run at sampling rates as high as 232 msps. analog output scaling from 0 db to 7.5 db in 0.5 db steps is available to preserve snr when reduced output levels are required. the 12-bit adcs provide excellent undersampling performance, allowing this device to typicall y deliver better than 10 enobs with if inputs up to 70 mhz. the 12-bit if adcs can sample at rates up to 29 mhz, allowing them to process wideband signals. the AD9878 includes a programmable -? dac, which can be used to control an external component such as a variable gain amplifier (vga) or a voltage controlled tuner. the AD9878 also integrates a ca port that enables a host processor to interface with the ad832x family of programmable gain amplifier (pga) cable drivers or industry equivalent via the mxfe serial port (sport). the AD9878 is available in a 100-lead, lqfp package. the AD9878 is specified over the extended industrial (?40c to +85c) temperature range.
AD9878 rev. a | page 2 of 36 table of contents electrical characteristics ................................................................. 4 absolute maximum ratings............................................................ 7 explanation of test levels ........................................................... 7 thermal characteristics .............................................................. 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical performance characteristics ........................................... 10 terminology .................................................................................... 13 register bit definitions.................................................................. 14 register 0x00initialization .................................................... 15 register 0x01clock configuration....................................... 15 register 0x02power-down.................................................... 15 register 0x03flag control..................................................... 15 register 0x04-? control word........................................... 15 register 0x07video input configuration............................ 16 register 0x08adc clock configuration ............................ 16 register 0x0cdie revision.................................................... 16 register 0x0dtx frequency tuning words lsbs.............. 16 register 0x0edac gain control ......................................... 16 register 0x0ftx path configuration ................................... 16 registers 0x10 through 0x17burst parameter................... 17 serial interface for register control ............................................ 18 general operation of the serial interface ............................... 18 instruction byte .......................................................................... 18 serial interface port pin descriptions ..................................... 18 msb/lsb transfers..................................................................... 19 notes on serial port operation ................................................ 19 theory of operation ...................................................................... 20 transmit path.............................................................................. 21 data assembler........................................................................... 21 transmit timing......................................................................... 21 interpolation filter..................................................................... 21 half-band filters (hbfs) .......................................................... 21 cascade integrator comb (cic) filter.................................... 21 combined filter response........................................................ 21 digital upconverter ................................................................... 22 tx signal level considerations ................................................ 22 tx throughput and latency ..................................................... 23 dac.............................................................................................. 23 programming the ad8321/ad8323 or ad8322/ad8327/ad8238 cable-driver amplifiers............ 23 oscin clock multiplier ........................................................... 24 clock and oscillator circuitry ................................................. 24 programmable clock output refclk .................................. 24 power-up sequence ................................................................... 26 reset ............................................................................................. 26 transmit power-down .............................................................. 26 -? outputs ................................................................................ 27 receive path (rx) ....................................................................... 27 if10 and if12 adc operation ................................................ 27 adc voltage references ........................................................... 29 video input ................................................................................. 29 pcb design considerations.......................................................... 30 component placement .............................................................. 30 power planes and decoupling .................................................. 30 ground planes ............................................................................ 30 signal routing............................................................................. 30 outline dimensions ....................................................................... 36 ordering guide .......................................................................... 36
AD9878 rev. a | page 3 of 36 revision history 3/05rev. 0 to rev. a changed oscout to refclk.................................................. universal changes to electrical characteristics ........................................................4 changes to pin configuration and function descriptions....................8 changes to -? output signals (figure 32)............................................27 change to -? rc filter (figure 33) .......................................................27 changes to evaluation pcb schematic (figure 38 and figure 39)......31 updated outline dimensions...................................................................36 changes to ordering guide......................................................................36 5/03revision 0: initial version
AD9878 rev. a | page 4 of 36 electrical characteristics v as = 3.3 v 5%, v ds = 3.3 v 10%, f oscin = 27 mhz, f sysclk = 216 mhz, f mclk = 54 mhz (m = 8), adc clock derived from oscin, r set = 4.02 k?, maximum. fine gain, 75 ? dac load. table 1. parameter temp test level min typ max unit oscin and xtal characteristics frequency range full ii 3 29 mhz duty cycle 25c ii 35 50 65 % input impedance 25c iii 100||3 m?||pf mclk cycle-to-cycle jitter (f mclk derived from pll) 25c iii 6 ps rms tx dac characteristics maximum sample rate full ii 232 mhz resolution n/a n/a 12 bits full-scale output current full ii 4 10 20 ma gain error (using internal reference) 25c i ?2.0 ?1 +2.0 % fs offset error 25c i 1.0 % fs reference voltage (refio level) 25c i 1.18 1.23 1.28 v differential nonlinearity (dnl) 25c iii 2.5 lsb integral nonlinearity (inl) 25c iii 8 lsb output capacitance 25c iii 5 pf phase noise @ 1 khz offset, 42 mh z carrier 25c iii ?110 dbc/hz output voltage compliance range full ii ?0.5 +1.5 v wideband sfdr 5 mhz analog output, i out = 10 ma full ii 62.4 68 db 65 mhz analog output, i out = 10 ma full ii 50.3 53.5 db narrow-band sfdr (1 mhz window) 5 mhz analog output, i out = 10 ma full ii 71 74 db 65 mhz analog output, i out = 10 ma full ii 61 64 db tx modulator characteristics i/q offset full ii 50 55 db pass-band amplitude ripple (f < f iqclk /8) full ii 0.1 db pass-band amplitude ripple (f < f iqclk /4) full ii 0.5 db stop-band response (f > f iqclk 3/4) full ii ?63 db tx gain control gain step size 25c iii 0.5 db gain step error 25c iii <0.05 db settling time, 1% (full-scale step) 25c iii 1.8 s 10-bit adc characteristics resolution n/a n/a 10 bits maximum conversion rate full ii 29 mhz pipeline delay n/a n/a 4.5 adc cycles analog input input voltage range full ii 2 v ppd differential input impedance 25c iii 4||2 k?||pf full power bandwidth 25c iii 90 mhz dynamic performance (a in = ?0.5 dbfs, f = 5 mhz) signal-to-noise and distortion (sinad) full ii 57.6 59.7 db effective number of bits (enob) full ii 9.3 9.6 bits total harmonic distortion (thd) full ii ?71.1 ?63.6 db spurious-free dynamic range (sfdr) full ii 65.7 72.4 db reference voltage error, reft10 to refb10 (1.0 v) full i 4 100 mv
AD9878 rev. a | page 5 of 36 parameter temp test level min typ max unit dynamic performance (a in = ?0.5 dbfs, f = 50 mhz) signal-to-noise and distortion (sinad) full ii 54.8 57.8 db effective number of bits (enob) full ii 8.8 9.3 bits total harmonic distortion (thd) full ii ?63.3 ?56.9 db spurious-free dynamic range (sfdr) full ii 56.9 63.7 db 12-bit adc characteristics resolution n/a n/a 12 bits maximum conversion rate full ii 29 mhz pipeline delay n/a n/a 5.5 adc cycles analog input input voltage range full iii 2 v ppd differential input impedance 25c iii 4||2 k?||pf aperture delay 25c iii 2.0 ns aperture jitter 25c iii 1.2 ps rms full power bandwidth 25c iii 85 mhz input referred noise 25c iii 75 v reference voltage error, reft12 to refb12 (1 v) full i ?100 16 +100 mv dynamic performance (a in = ?0.5 dbfs, f = 5 mhz) adc sample clock = oscin signal-to-noise and distortion (sinad) full ii 61.0 67 db effective number of bits (enobs) full ii 9.8 10.8 bits signal-to-noise ratio (snr) full ii 64.2 66 db total harmonic distortion (thd) full ii ?72.7 ?61.7 db spurious-free dynamic range (sfdr) full ii 62.8 74.6 db adc sample clock = pll signal-to-noise and distortion (sinad) full ii 60.4 64.4 db effective number of bits (enob) full ii 9.74 10.4 bits signal-to-noise ratio (snr) full ii 62.4 65.1 db total harmonic distortion (thd) full ii ?72.7 ?61.8 db spurious-free dynamic range (sfdr) full ii 62.7 74.6 db dynamic performance (a in = ?0.5 dbfs, f = 50 mhz) adc sample clock = oscin signal-to-noise and distortion (sinad) full ii 61.0 65.2 db effective number of bits (enob) full ii 9.8 10.5 bits signal-to-noise ratio (snr) full ii 64.2 67.4 db total harmonic distortion (thd) full ii ?72.8 ?61.8 db spurious-free dynamic range (sfdr) full ii 62.8 74.6 db differential phase 25c iii <0.1 degrees differential gain 25c iii <1 lsb video adc performance (a in = ?0.5 dbfs, f = 5 mhz) adc sample clock = oscin signal-to-noise and distortion (sinad) full ii 46.7 53 db signal-to-noise ratio (snr) full ii 54.3 63.2 bits total harmonic distortion (thd) full ii ?50.2 ?45.9 db spurious-free dynamic range (sfdr) full ii 45.9 50 db channel-to-channel isolation tx dac-to-adc isolation (5 mhz analog output) isolation between tx and 10- bit adc 25c iii >60 db isolation between tx and 12- bit adcs 25c iii >80 db adc-to-adc isolation (a in = C0.5 dbfs, f = 5 mhz) isolation between if10 and if12a/b 25c iii >85 db isolation between if12a and if12b 25c iii >85 db
AD9878 rev. a | page 6 of 36 parameter temp test level min typ max unit timing characteristics (10 pf load) wake-up time n/a n/a 200 t mclk cycles minimum reset pulse width low, t rl n/a n/a 5 t mclk cycles digital output rise/fall time full ii 2.8 4 ns tx/rx interface mclk frequency, f mclk full ii 58 mhz txsync/txiq setup time, t su full ii 3 ns txsync/txiq hold time, t hu full ii 3 ns mclk rising edge to rxsync valid delay, t md full ii 0 1.0 ns refclk rising or falling edge to rxsync valid delay, t od full ii t oscin / 4 ? 2.0 t oscin / 4 + 3.0 ns refclk edge to mclk falling edge, t ee full ii ?1.0 +1.0 ns serial control bus maximum sclk frequency, f sclk full ii 15 mhz minimum clock pulse width high, t pwh full ii 30 ns minimum clock pulse width low, t pwl full ii 30 ns maximum clock rise/fall time full ii 1 s minimum data/chip-select setup time, t ds full ii 25 ns minimum data hold time, t dh full ii 0 ns maximum data valid time, t dv full ii 30 ns cmos logic inputs logic 1 voltage 25c ii v drvdd ? 0.7 v logic 0 voltage 25c ii 0.4 v logic 1 current 25c ii 12 a logic 0 current 25c ii 12 a input capacitance 25c iii 3 pf cmos logic outputs (1 ma load) logic 1 voltage 25c ii v drvdd ? 0.6 v logic 0 voltage 25c ii 0.4 v power supply supply current, i s (full operation) 25c ii 184 204 ma analog supply current, i as 25c iii 105 115 ma digital supply current, i ds 25c iii 79 89 ma supply current, i s standby (pwrdn pin active, i as + i ds ) 25c ii 124 137 ma full power-down (register 0x02 = 0xff) 25c ii 46 52 ma power-down tx path (register 0x02 = 0x60) 25c iii 124 ma power-down if12 rx path (register 0x02 = 0x1b) 25c iii 131 159 ma power supply rejection (differential signal) tx dac 25c iii <0.25 % fs 10-bit adc 25c iii <0.0001 % fs 12-bit adc 25c iii <0.0004 % fs
AD9878 rev. a | page 7 of 36 absolute maximum ratings table 2. parameter rating power supply (v avdd , v dvdd , v drvdd ) 3.9 v digital output current 5 ma digital inputs ?0.3 v to v drvdd + 0.3 v analog inputs ?0.3 v to v avdd + 0.3 v operating temperature ?40c to +85c maximum junction temperature 150c storage temperature ?65c to +150c lead temperature (soldering, 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explanation of test levels i. devices are 100% production tested at 25c and guaranteed by design and characterization testing for extended industrial operating temperature range (?40c to +85c). ii. parameter is guaranteed by design and/or characterization testing. iii. parameter is a typical value only. n/a. test level definition is not applicable. thermal characteristics thermal resistance of 100-lead lqfp: ja = 40.5c/w esd caution esd (electrostatic discharge) sensit ive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD9878 rev. a | page 8 of 36 pin configuration and fu nction descriptions 03277-002 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 avdd agnd video in agnd if12a+ if12a? agnd avdd reft12a refb12 a avdd agnd if12b+ if12b? agnd avdd reft12b refb12 b avdd agnd avdd10 agnd10 if10+ if10? agnd 76 reft10 75 refb10 74 agnd10 73 avdd10 72 drvdd 71 drgnd 70 refclk 69 sigdelt 68 flag1 67 flag2 66 ca_en 65 ca_data 64 ca_clk 63 dvddosc 62 oscin 61 xtal 60 dgndosc 59 agndpll 58 pllfilt 57 avddpll 56 dvddpll 55 dgndpll 54 avddtx 53 tx+ 52 tx? 51 txsync 26 (msb) txiq(5) 27 txiq(4) 28 txiq(3) 29 txiq(2) 30 txiq(1) 31 txiq(0) 32 dvdd 33 dgnd 34 dvdd 35 dgnd 36 profile 37 reset 38 dvdd 39 dgnd 40 sclk 41 cs 42 sdio 43 sdo 44 dgndtx 45 dvddtx 46 pwrdn 47 refio 48 fsadj 49 agndtx 50 drgnd 1 drvdd 2 (msb) if12(11) 3 if12(10) 4 if12(9) 5 if12(8) 6 if12(7) 7 if12(6) 8 if12(5) 9 if12(4) 10 if12(3) 11 if12(2) 12 if12(1) 13 if12(0) 14 (msb) if10(4) 15 if10(3) 16 if10(2) 17 if10(1) 18 if10(0) 19 rxsync 20 drgnd 21 drvdd 22 mclk 23 dvdd 24 dgnd 25 AD9878 top view (not to scale) figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic descriptions 1, 21, 70 drgnd pin driver digital ground 2, 22, 71 drvdd pin driver digital 3.3 v supply 3 (msb) if12(11) 12-bit adc digital ouput 4 to 14 if12[10:0] 12-bit adc digital ouput 15 (msb) if10(4) 10-bit adc digital ouput 16 to 19 if10[3:0] 10-bit adc digital ouput 20 rxsync sync output, 10-bit and 12-bit adcs 23 mclk master clock output 24, 33, 35, 39 dvdd digital 3.3 v supply 25, 34, 36, 40 dgnd digital ground 26 txsync sync input for transmit port 27 (msb) txiq(5) digital input for transmit port 28 to 32 txiq[4:0] digital input for transmit port 37 profile profile selection input 38 reset chip reset input 41 sclk sport clock 42 cs sport chip select 43 sdio sport data i/o
AD9878 rev. a | page 9 of 36 pin no. mnemonic descriptions 44 sdo sport data output 45 dgndtx tx path digital ground 46 dvddtx tx path digital 3.3 v supply 47 pwrdn power-down transmit path 48 refio txdac decoupling (to agnd) 49 fsadj dac output adjust (external resistor) 50 agndtx tx path analog ground 51, 52 tx?, tx+ tx path complementary outputs 53 avddtx tx path analog 3.3 v supply 54 dgndpll pll digital ground 55 dvddpll pll digital 3.3 v supply 56 avddpll pll analog 3.3 v supply 57 pllfilt pll loop filter connection 58 agndpll pll analog ground 59 dgndosc oscillator digital ground 60 xtal crystal oscillator inverted output 61 oscin oscillator clock input 62 dvddosc oscillator digital 3.3 v supply 63 ca_clk serial clock-to-cable driver 64 ca_data serial data-to-cable driver 65 ca_en serial enable-to-cable driver 66, 67 flag[2:1] programmable flag outputs 68 sigdelt -? dac output 69 refclk reference clock output 72, 80 avdd10 10-bit adc analog 3.3 v supply 73, 79 agnd10 10-bit adc analog ground 74 refb10 10-bit adc reference decoupling node 75 reft10 10-bit adc reference decoupling node 76, 81, 86, 89, 94, 97, 99 agnd 12-bit adc analog ground 77, 78 if10?, if10+ differential input to 10-bit adc 82, 85, 90, 93, 100 avdd 12-bit adc analog 3.3 v supply 83 refb12b adc12b reference decoupling node 84 reft12b adc12b reference decoupling node 87, 88 if12b?, if12b+ differential input to adc12b 91 refb12a adc12a reference decoupling node 92 reft12a adc12a reference decoupling node 95, 96 if12a?, if12a+ differential input to adc12a 98 video in video clamp input
AD9878 rev. a | page 10 of 36 typical performance characteristics frequency (mhz) magnitude (db) 024681012141618 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 20 03277-022 figure 3. dual-sideband spectral plot, f c = 5 mhz, f = 1 mhz, r set = 10 k? (i out = 4 ma), rbw = 1 khz frequency (mhz) magnitude (db) 024681012141618 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 20 03277-023 figure 4. dual-sideband spectral plot, f c = 5 mhz, f = 1 mhz, r set = 4 k? (i out = 10 ma), rbw = 1 khz frequency (mhz) magnitude (db) 55 57 59 61 63 65 67 69 70 73 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 75 03277-024 figure 5. dual-sideband spectral plot, f c = 65 mhz, f = 1 mhz, r set = 10 k? (i out = 4 ma), rbw = 1 khz frequency (mhz) magnitude (db) 55 57 59 61 63 65 67 69 71 73 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 75 03277-025 figure 6. dual-sideband spectral plot, f c = 65 mhz, f = 1 mhz, r set = 4 k? (i out = 10 ma), rbw = 1 khz frequency (mhz) magnitude (db) 0 20406080100 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 120 03277-026 figure 7. single sideband @ 65 mhz, f c = 66 mhz, f = 1 mhz, r set = 10 k? (i out = 4 ma), rbw = 2 khz frequency (mhz) magnitude (db) 0 20406080100 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 120 03277-027 figure 8. single sideband @ 65 mhz, f c = 66 mhz, f = 1 mhz, r set = 4 k? (i out = 10 ma), rbw = 2 khz
AD9878 rev. a | page 11 of 36 frequency (mhz) magnitude (db) 0 20406080100 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 120 03277-028 figure 9. single sideband @ 42 mhz, f c = 43 mhz, f = 1 mhz, r set = 10 k? (i out = 4 ma), rbw = 2 khz frequency (mhz) magnitude (db) 0 20406080100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 120 03277-029 figure 10. single sideband @ 42 mhz, f c = 43 mhz, f = 1 mhz, r set = 4 k? (i out = 10 ma), rbw = 2 khz frequency (mhz) magnitude (db) 0 20406080100 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 120 03277-030 figure 11. single sideband @ 5 mhz, f c = 6 mhz, f = 1 mhz, r set = 10 k? (i out = 4 ma), rbw = 2 khz frequency (mhz) magnitude (db) 0 20406080100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 120 03277-031 figure 12. single sideband @ 5 mhz, f c = 6 mhz, f = 1 mhz, r set = 4 k? (i out = 10 ma), rbw = 2 khz frequency (mhz) magnitude (db) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 2.5 03277-032 figure 13. single sideband @ 65 mhz, f c = 66 mhz, f = 1 mhz, r set = 10 k? (i out = 4 ma), rbw = 500 hz frequency (mhz) magnitude (db) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 2.5 03277-033 figure 14. single sideband @ 65 mhz, f c = 66 mhz, f = 1 mhz, r set = 4 k? (i out = 10 ma), rbw = 500 hz
AD9878 rev. a | page 12 of 36 frequency (mhz) magnitude (db) ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50 03277-034 figure 15. single sideband @ 65 mhz, f c = 66 mhz, f = 1 mhz, r set = 10 k? (i out = 4 ma), rbw = 50 hz magnitude (db) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequency (mhz) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 03277-035 figure 16. single sideband @ 65 mhz, f c = 66 mhz, f = 1 mhz, r set = 10 k? (i out = 4 ma), rbw = 10 hz magnitude (db) ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequency (mhz) 0 5 10 15 20 25 30 35 40 45 50 03277-036 figure 17. 16-qam @ 42 mhz spectral plot, rbw = 1 khz magnitude (db) ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequency (mhz) 0 5 10 15 20 25 30 35 40 45 50 03277-037 figure 18. 16-qam @ 5 mhz spectral plot, rbw = 1 khz
AD9878 rev. a | page 13 of 36 terminology differential nonlinearity error (dnl, no missing codes) an ideal converter exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. no missing codes indicates that all of the adc codes must be present over all operating ranges. integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. phase noise single-sideband, phase-noise power is specified relative to the carrier (dbc/hz) at a given frequency offset (1 khz) from the carrier. phase noise can be measured directly in single-tone transmit mode with a spectrum analyzer that supports noise marker measurements. it detects the relative power between the carrier and the offset (1 khz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10 log(rbw). it also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. spurious-free dynamic range (sfdr) the difference, in db, between the rms amplitude of the dac output signal (or adc input signal) and the peak spurious signal over the specified bandwidth (nyquist bandwidth, unless otherwise noted). pipeline delay (latency) the number of clock cycles between conversion initiation and the associated output data being made available. offset error the first code transition should occur at an analog value ? lsb above negative full scale. offset error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value ? lsb above negative full scale. the last transition should occur for an analog value 1? lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. aperture delay the aperture delay is a measure of the sample-and-hold amplifier (sha) performance that specifies the time delay between the rising edge of the sampling clock input and when the input signal is held for conversion. aperture jitter aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the adc. input referred noise the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsb, and converted to an equivalent voltage. this results in a noise figure that can be directly referred to the input of the mxfe. signal-to-noise and distortion (sinad) ratio sinad is the ratio of the rms value of the measured input signal to the rms sum of other spectral components below the nyquist frequency, including harmonics, but excluding dc. the value for sinad is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the number of bits. using the following formula, it is possible to get a measure of performance expressed as n, the effective number of bits: ( ) 02 . 6 db 76 . 1 ? = sinad n thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. it is expressed as a percentage, or in decibels. power supply rejection power supply rejection specifies the converters maximum full- scale change when the supplies are varied from nominal to minimum or maximum specified voltages. channel-to-channel isolation (crosstalk) in an ideal multichannel system, the signal in one channel does not influence the signal level of another channel. the channel- to-channel isolation specification is a measure of the change that occurs in a grounded channel as a full-scale signal is applied to another channel.
AD9878 rev. a | page 14 of 36 register bit definitions table 4. register map address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default (hex) type 0x00 sdio bidirectional lsb first reset oscin multiplier m[4:0] 0x08 read/write 0x01 pll lock detect mclk divider r[5:0] 0x00 read/write 0x02 power down pll power down dac tx power down digital tx power down adc12a power down adc12b power down adc10 power down reference adc12a power down reference adc12b 0x00 read/write 0x03 video input into adc12b flag 2 flag 1 flag 0 enable 0x00 read/write 0x04 msb/flag 0 -? output control word [7:0] 0x00 read/write 0x05 0x00 read/write 0x06 0x00 read only 0x07 video input enable clamp level for video input [6:0] 0x00 read/write 0x08 adc clocked directly from oscin rx port fast edge rate power down rxsync generator power down reference adc10 send adc12a data only send adc12b data only 0x80 read/write 0x09 0x00 read/write 0x0a 0x00 read/write 0x0b 0x00 read/write 0x0c version [3:0] 0x00 read/write 0x0d tx frequency tuning word profile 1 lsb [1:0] tx frequency tuning word profile 0 lsbs [1:0] 0x00 read/write 0x0e dac fine gain control [3:0] 0x00 read/write 0x0f tx path select profile 1 tx path ad8321/ad8323 gain control mode tx path bypass sinc C1 filter tx path spectral inversion tx path transmit single tone 0x00 read/write 0x10 tx path frequency tuning word profile 0 [9:2] 0x00 read/write 0x11 tx path frequency tuning word profile 0 [17:10] 0x00 read/write 0x12 tx path frequency tuning word profile 0 [25:18] 0x00 read/write 0x13 cable-driver amplifier, coarse gain control profile 0 [7:4] cable-driver amplifier, fine gain control profile 0 [3:0] 0x00 read/write 0x14 tx path frequency tuning word profile 1 [9:2] 0x00 read/write 0x15 tx path frequency tuning word profile 1 [17:10] 0x00 read/write 0x16 tx path frequency tuning word profile 1 [25:18] 0x00 read/write 0x17 cable-driver amplifier, coarse gain control profile 1 [7:4] cable-driver amplifier, fine gain control profile 1 [3:0] 0x00 read/write
AD9878 rev. a | page 15 of 36 register 0x00initialization bits 0 to 4: oscin multiplier this register field is used to program the on-chip clock multiplier that generates the chips high frequency system clock, f sysclk . for example, to multiply the external crystal clock f oscin by 16, program register 0x00, bits 4:0, to 0x10. the default clock multiplier value, m, is 0x08. valid entries range from 1 to 31. when m is set to 1, the pll is disabled and internal clocks are derived directly from oscin. the pll requires 200 mclk cycles to regain frequency lock after a change in m. after the recapture time of the pll, the frequency of f sysclk is stable. bit 5: reset writing 1 to this bit resets the registers to their default values and restarts the chip. the reset bit always reads back 0. the bits in register 0x00 are not affected by this software reset. however, a low level at the reset pin forces all registers, including all bits in register 0x00, to their default states. bit 6: lsb first active high indicates spi serial port access of instruction byte and data registers is lsb first. default low indicates msb-first format. bit 7: sdio bidirectional active high configures the serial port as a 3-signal port with the sdio pin used as a bidirectional input/output pin. default low indicates that the serial port uses four signals with sdio configured as an input and sdo configured as an output. register 0x01clock configuration bits [5:0]: mclk divider this register determines the output clock on the refclk pin. at default 0 (r = 0), refclk provides a buffered version of the oscin clock signal for other chips. the register can also be used to divide the chips master clock f mclk by r, where r is an integer between 2 and 63. the generated reference clock on refclk pin can be used for external frequency controlled devices. bit 7: pll lock detect when this bit is set low, the refclk pin functions in its default mode and provides an output clock with frequency f mckl /r, as described above. if this bit is set to 1, the refclk pin is configured to indicate whether the pll is locked to f oscin . in this mode, the refclk pin should be low-pass filtered with an rc filter of 1.0 k? and 0.1 f. a low output on refclk indicates that the pll has achieved lock with f oscin . register 0x02power-down unused sections of the chip can be powered down when the corresponding bits are set high. this register has a default value of 0x00, all sections active. bit 0: power down adc12b voltage reference active high powers down the voltage reference circuit for adc12b. bit 1: power down adc12a voltage reference active high powers down the voltage reference circuit for the adc12a. bit 2: power down adc10 active high powers down the 10-bit adc. bit 3: power down adc12b active high powers down the adc12b. bit 4: power down adc12a active high powers down the adc12a. bit 5: power down tx active high powers down the digital transmit section of the chip, similar to the function of the pwrdn pin. bit 6: power down dac tx active high powers down the dac. bit 7: power down pll active high powers down the oscin multiplier. register 0x03flag control bit 0: flag 0 enable when this bit is active high, the sigdelt pin maintains a fixed logic level determined directly by the msb of the -? control word of register 0x04. bit 1: flag 1 the logic level of this bit is applied at the flag1 pin. bit 4: flag 2 the logic level of this bit is applied at the flag2 pin. bit 5: video input into adc12b if the video input is enabled, setting this bit high sends the signal applied to the video in pin to the adc12b. otherwise, the signal applied to the video in pin is sent to the adc12a. register 0x04-? control word bits [7:0]: -? control word the -? control word is 8 bits wide and controls the duty cycle of the digital output on the sigdelt pin. changes to the -? control word take effect immediately for every register write. -? output control words have a default value of 0. the control words are in straight binary format, with 0x00 corresponding to the bottom of scale or 0% duty cycle, and 0xff corresponding to the top of scale or near 100% duty cycle. bit 7: flag 0 (-? control word msb) when the flag 0 enable bit (register 0x03, bit 0) is set, the logic level of this bit appears on the output of the sigdelt pin.
AD9878 rev. a | page 16 of 36 register 0x07video input configuration bits [6:0]: clamp level control value the 7-bit clamp-level control value is used to set an offset to the automatic clamp-level control loop. the actual adc output has a clamp-level offset equal to 16 times the clamp level control value. ( ) 16 - - x value control level clamp offset level clamp = the default value for the clamp-level control value is 0x20. this results in an adc output clamp-level offset of 512 lsbs. the valid programming range for the clamp-level control value is 0x16 to 0x127. bit 7: video input enable this bit enables the video input. in default with bit 7 = 0, both if12 adcs are connected to if inputs. if the video input is enabled by setting bit 7 = 1, the video input will be connected to the if12 adc selected by reg 0x03, bit 6. register 0x08adc clock configuration bit 0: send adc12b data only when this bit is set high, the device enters a nonmultiplexed mode, and only the data from the adc12b is sent to the if[11:0] digital output port. bit 1: send adc12a data only when this bit is set high, the device enters a nonmultiplexed mode, and only the data from the adc12a is sent to the if[11:0] digital output port. if both the send adc12b data only and send adc12a data only register bits are set high, the device sends both adc12a and adc12b data in the default multiplexed mode. bit 3: power down adc10 voltage reference active high powers down the voltage reference circuit for the adc10. bit 4: power down rxsync generator setting this bit to 1 powers down the 10-bit adcs sampling clock and makes the rxsync output pin stay low. it can be used for additional power saving on top of the power-down selections in register 0x02. bit 5: rx port fast edge rate setting this bit to 1 increases the output drive strength of all digital output pins, except mclk, refclk, sigdelt, and flag[2:1]. these pins always have high output drive capability. bit 7: adc clocked directly from oscin when set high, the adc sampling clock is derived directly from the input clock at oscin. in this mode, the clock supplied to the oscin pin should originate from an external crystal or low jitter crystal oscillator. when this bit is low, the adc sampling clock is derived from the internal pll and the frequency of the clock is equal to f oscin m/8. register 0x0cdie revision bits [3:0]: version the die version of the chip can be read from this register. register 0x0dtx frequency tuning words lsbs this register accommodates the 2 lsbs for each frequency tuning word (ftw). see the registers 0x10 through 0x17 burst parameter section. register 0x0edac gain control this register allows the user to program the dac gain if the tx gain control select bit 3 in register 0x0f is set to 0. table 5. dac gain control bits [3:0] dac gain (db) 0000 0.0 (default) 0001 0.5 0010 1.0 0011 1.5 1110 7.0 1111 7.5 register 0x0ftx pa th configuration bit 0: single tone tx mode active high configures the AD9878 for single-tone applications (e.g., fsk). the AD9878 supplies a single frequency output, as determined by the ftw selected by the active profile. in this mode, the txiq input data pins are ignored, but should be tied to a valid logic voltage level. default value is 0x00 (inactive). bit 1: spectral inversion tx when set to 1, inverted modulation is performed: ( ) ( ) [ ] . sin cos _ t q t i out modulator + = default is logic 0, noninverted modulation: () ( ) [ ] . sin cos _ t q t i out modulator ? = bit 2: bypass inv sinc tx filter active high configures the AD9878 to bypass the sin(x)/x com- pensation filter. default value is 0x00 (inverse sinc filter enabled). bit 3: ca interf ace mode select this bit changes the format of the AD9878 3-wire ca interface to a format in which the AD9878 digitally interfaces to external variable gain amplifiers. this is accomplished by changing the interpretation of the bits in register 0x13, register 0x17, register 0x1b, and register 0x1f. see the cable-driver gain control section for more detail.
AD9878 rev. a | page 17 of 36 setting this bit to 0 (default) configures the serial interface to be compatible with ad8321/ad8323/ad8328 variable cable gain amplifiers. setting this bit to 1 configures the serial interface to be compatible with ad8322/ad8327 variable cable gain amplifiers. bit 5: profile select the AD9878 quadrature digital upconverter can store two preconfigured modulation modes, called profiles. each profile defines a transmit ftw, cable-driver amplifier gain setting, and dac gain setting. the profile select bit or profile pin programs the current register profile to be used. if the profile pin is used to switch between profiles, the profile select bit should be set to 0 and tied low. registers 0x10 through 0x17 burst parameter tx frequency tuning words the ftw determines the dds-generated carrier frequency (f c ) and is formed via a concatenation of register addresses. the 26-bit ftw is spread over four register addresses. bit 25 is the msb, and bit 0 is the lsb. the carrier frequency equation is as follows: () 26 2 sysclk c f ftw f = where 2000 x 0 and , < = . changes to ftw bytes take effect immediately. cable-driver gain control the AD9878 has a 3-pin interface to the ad832x family of programmable gain cable-driver amplifiers. this allows direct control of the cable drivers gain through the AD9878. in its default mode, the complete 8-bit register value is transmitted over the 3-wire cable amplifier (ca) interface. if bit 3 of register 0x0f is set high, bits [7:4] of register 0x13 and register 0x17 determine the 8-bit word sent over the ca interface, according to the specifications in table 6. bits [3:0] of register 0x13 and register 0x17 determine the fine gain setting of the dac output, according to specifications in table 7. table 6. cable-driver gain control bits [7:4] ca interface transmit word 0000 0000 0000 (default) 0001 0000 0001 0010 0000 0010 0011 0000 0100 0100 0000 1000 0101 0001 0000 0110 0010 0000 0111 0100 0000 1000 1000 0000 table 7. dac output fine gain setting bits [3:0] dac fine gain (db) 0000 0.0 (default) 0001 0.5 0010 1.0 0011 1.5 1110 7.0 1111 7.5 new data is automatically sent over the 3-wire ca interface (and dac gain adjust) whenever the value of the active gain control register changes or a new profile is selected. the default value is 0x00 (lowest gain). the formula for the combined output-level calculation of AD9878 fine gain and ad8327 or ad8322 coarse gain is: () ( ) () 19 2 0 9878 8327 ? + + = () ( ) ( ) 14 2 0 9878 8322 ? + + = where: fine is the decimal value of bits [3:0]. coarse is the decimal value of bits [7:4]. v 9878(0) is the level at AD9878 output in dbmv for fine = 0. v 8327 is the level at output of ad8327 in dbmv. v 8322 is the level at output of ad8322 in dbmv.
AD9878 rev. a | page 18 of 36 serial interface for register control the AD9878 serial port is a flexible, synchronous, serial communications port that allows easy interface to many industry-standard microcontrollers and microprocessors. the interface allows read/write access to all registers that configure the AD9878. single or multiple byte transfers are supported. also, the interface can be programmed to read words either msb first or lsb first. the AD9878 serial interface port i/o can be configured to have one bidirectional i/o (sdio) pin, or two unidirectional i/o (sdio/sdo) pins. general operation of the serial interface there are two phases of a communication cycle with the AD9878. phase 1 is the instruction cycle, which is the writing of an in- struction byte into the AD9878, coincident with the first eight sclk rising edges. the instruction byte provides the AD9878 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the AD9878. the eight remaining sclk edges are for phase 2 of the commu- nication cycle. phase 2 is the actual data transfer between the AD9878 and the system controller. phase 2 of the communication cycle is a transfer of one to four data bytes, as determined by the instruction byte. normally, using one multibyte transfer is the preferred method. however, single-byte data transfers are useful to reduce cpu overhead when register access requires only one byte. registers change immediately upon writing to the last bit of each transfer byte. instruction byte the r/w bit of the instruction byte determines whether a read or a write data transfer occurs after the instruction byte write. logic high indicates a read operation; logic low indicates a write operation. the [n1:n0] bits determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in table 9. the timing diagrams are shown in figure 19 and figure 20. table 8. instruction byte information msb 17 16 15 14 13 12 11 lsb 10 r/w n1 n0 a4 a3 a2 a1 a0 table 9. bit decodes n1 n0 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes bits [a4:a0] determine which register is accessed during the data transfer portion of the communication cycle. for multi- byte transfers, this address is the starting byte address. the remaining register addresses are generated by the AD9878. 03277-005 sclk instruction bit 7 instruction bit 6 t sclk t dh t pwl t pwh t ds sdio cs t ds figure 19. timing diagram for register write 03277-006 sclk sdio sdo cs data bit n data bit n t dv figure 20. timing diagram for register read serial interface port pin descriptions sclkserial clock. the serial clock pin is used to synchronize data transfers from the AD9878 and to run the serial port state machine. the maximum sclk frequency is 15 mhz. input data to the AD9878 is sampled up on the rising edge of sclk. output data changes upon the falling edge of sclk. cs chip select. active low input starts and gates a commu- nication cycle. it allows multiple devices to share a common serial port bus. the sdo and sdio pins go into a high impedance state when cs is high. chip select should stay low during the entire communication cycle. sdioserial data i/o. data is always written into the AD9878 on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by bit 7 of register 0x00. the default is logic 0, which configures the sdio pin as unidirectional. sdoserial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the AD9878 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state.
AD9878 rev. a | page 19 of 36 msb/lsb transfers the AD9878 serial port can support either msb-first or lsb-first data formats. this functionality is controlled by the lsb-first bit in register 0x00. the AD9878 default serial port mode is msb-first (see figure 21), which is programmed by setting register 0x00 low. in msb-first mode, the instruction byte and data bytes must be written from the msb to the lsb. in msb-first mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle. when decrementing from 0x00, the address generator changes to 0x1f. when the lsb-first bit in register 0x00 is set active high, the AD9878 serial port is in lsb-first format (figure 22). in lsb- first mode, the instruction byte and data bytes must be written from the lsb to the msb. in lsb-first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle. when incrementing from 0x1f, the address generator changes to 0x00. cs r/w n1 n0 a4 a3 a2 a1 a0 d7 n d6 n d2 0 d1 0 d0 0 d7 n d6 n d2 0 d1 0 d0 0 sclk instruction cycle data transfer cycle sdio sdo 03277-003 figure 21. serial register interface timing, msb-first mode d0 0 d1 0 d2 0 d6 n d7 n sclk instruction cycle data transfer cycle sdio sdo cs a0 a1 a2 a3 a4 n0 n1 r/w d0 0 d1 0 d2 0 d6 n d7 n 03277-004 figure 22. serial register interface timing, lsb-first mode notes on serial port operation the AD9878 serial port configuration bits reside in bit 6 and bit 7 of register address 0x00. note that the configuration changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register might occur during a communication cycle. measures must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. the same considerations apply when setting the reset bit in register address 0x00. all other registers are set to their default values, but the software reset does not affect the bits in register address 0x00. it is recommended to use only single-byte transfers when changing serial port configurations or initiating a software reset. a write to bit 1, bit 2, and bit 3 of address 0x00 with the same logic levels as bit 7, bit 6, and bit 5 (bit pattern: xy1001yx binary) allows the user to reprogram a lost serial port config- uration and to reset the registers to their default values. a second write to address 0x00, with the reset bit low and the serial port configuration as specified above (xy), reprograms the oscin multiplier setting. a changed f sysclk frequency is stable after a maximum of 200 f mclk cycles (wake-up time).
AD9878 rev. a | page 20 of 36 theory of operation for a general understanding of the AD9878, refer to figure 23, a block diagram of the device architecture. the device consists of a transmit path, receive path, and auxiliary functions, such as a pll, a -? dac, a serial control port, and a cable amplifier interface. the transmit path contains an interpolation filter, a complete quadrature digital upconverter, an inverse sinc filter, and a 12-bit current output dac. the receive path contains a 10-bit adc and dual 12-bit adcs. all internally required clocks and an output system clock are generated by the pll from a single crystal or clock input. the 12-bit and 10-bit if adcs can convert direct if inputs of up to 70 mhz and run at sample rates of up to 29 msps. a video input with an adjustable signal clamping level, along with the 10-bit adc, allow the AD9878 to process an ntsc and a qam channel simultaneously. the programmable -? dac can be used to control external components, such as variable gain amplifiers (vgas) or voltage- controlled tuners. the ca port provides an interface to the ad832x family of programmable gain amplifier (pga) cable drivers, enabling host processor control via the mxfe serial port (sport). 03277-007 txiq[5:0] txsync mclk refclk ca port profile sdio if10[4:0] rxsync if12[11:0] fsadj xtal oscin - ? output flag[2:1] if10 input if12b input video in 6 3 12 12 12 AD9878 data assembler quadrature modulator fir lpf cic lpf cos sin dac gain control pll oscin m dds mux mux ca interface profile select serial interface 12 4 sinc ?1 mux dac if10 if12 adc adc 10 12 12 4 5 5 12 12 i q rx port tx output - ? input 4 4 4 8 flag0 sinc ?1 bypass ( f oscin ) ( f oscin ) ( f mclk ) mux 12 adc mux if12a input dac + ? clamp level - ? r 8 2 2 ( f iqclk ) ( f sysclk ) ( f oscin ) 4 4 figure 23. AD9878 block diagram
AD9878 rev. a | page 21 of 36 t su t hu mclk txsync txiq txi[11:6] txi[5:0] txq[11:6] txq[5:0] txi[11:6] txi[5:0] txq[11:6] txq[5:0] txi[11:6] txi[5:0] 03277-008 figure 24. tx timing diagram transmit path the transmit path contains an interpolation filter, a complete quadrature digital upconverter, an inverse sinc filter, and a 12-bit current output dac. the maximum output current of the dac is set by an external resistor. the tx output pga provides additional transmit signal level control. the transmit path interpolation filter provides an upsampling factor of 16 with an output signal bandwidth as high as 4.35 mhz for <1 db droop. carrier frequencies up to 65 mhz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (dds). the transmit dac resolution is 12 bits, and it can run at sampling rates of up to 232 msps. analog output scaling from 0 db to 7.5 db in 0.5 db steps is available to preserve snr when reduced output levels are required. data assembler the AD9878 data path operates on two 12-bit words, the i and q components, that form a complex symbol. the data assembler builds the 24-bit complex symbol from four consecutive 6-bit words read over the txiq [5:0] bus. these words are strobed into the data assembler synchronous to the master clock (mclk). a high level on txsync signals the start of a transmit symbol. the first two 6-bit words of the symbol form the i component; the second two 6-bit words form the q component. symbol components are assumed to be in twos complement format. the timing of the interface is fully described in the transmit timing section. the i/q sample rate f iqclk puts a bandwidth limit on the maximum transmit spectrum. this is the familiar nyquist limit (hereafter referred to as f nyq ) and is equal to half f iqclk . transmit timing the AD9878 has a master clock and expects 6-bit, multiplexed txiq data upon each rising edge (see figure 24). transmit symbols are framed with the txsync input. txsync high indicates the start of a transmit symbol. four consecutive 6-bit data packages form a symbol (i msb, i lsb, q msb, and q lsb). interpolation filter once through the data assembler, the iq data streams are fed through a 4 fir low-pass filter and a 4 cascaded integrator comb (cic) low-pass filter. the combination of these two filters results in the sample rate increasing by a factor of 16. in addition to the sample rate increase, the half-band filters provide the low-pass filtering characteristics necessary to suppress the spectral images between the original sampling frequency and the new (16 higher) sampling frequency. half-band filters (hbfs) hbf 1 and hbf 2 are both interpolating filters, each of which doubles the sampling rate. together, hbf 1 and hbf 2 have 26 taps and increase the sampling rate by a factor of 4 (4 f iqclk or 8 f nyq ). in relation to phase response, both hbfs are linear phase filters. as such, virtually no phase distortion is introduced within the pass band of the filters. this is an important feature, because phase dis- tortion is generally intolerable in a data transmission system. cascade integrator comb (cic) filter the cic filter is configured as a programmable interpolator and provides a sample rate increase by a factor of 4. the frequency response of the cic filter is given by: () () () () () 3 3 2 4 2 sin 4 sin 4 1 1 1 4 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? combined filter response the combined frequency response of the hbf and cic filters limits the input signal bandwidth that can be propagated through the AD9878.the usable bandwidth of the filter chain limits the maximum data rate that can be propagated through the AD9878. a look at the pass-band detail of the combined filter response (figure 25) indicates that to maintain an amplitude error of 1 db or less, signal bandwidth is restricted to about 60% or less of f nyq . max bw (1db droop) = 0.60 * f mclk /8 thus, in order to keep the bandwidth of the data in the flat portion of the filter pass band, the user must oversample the baseband data by at least a factor of two prior to presenting it to the AD9878. note that without oversampling, the nyquist bandwidth of the baseband data corresponds to f nyq . as such, the upper end of the data bandwidth suffers 6 db or more of attenuation due to the frequency response of the digital filters. furthermore, if the baseband data applied to the AD9878 has
AD9878 rev. a | page 22 of 36 been pulse shaped, there is an additional concern. typically, pulse shaping is applied to the baseband data via a filter with a raised cosine response. in such cases, an value is used to modify the bandwidth of the data, where the value of is such that . 1 0 < < a value of 0 causes the data bandwidth to correspond to the nyquist bandwidth. a value of 1 causes the data bandwidth to be extended to twice the nyquist bandwidth. thus, with 2 over- sampling of the baseband data and = 1, the nyquist bandwidth of the data corresponds with the i/q nyquist bandwidth. as stated earlier, this results in problems near the upper edge of the data bandwidth due to the frequency response of the filters. the maximum value of that can be implemented is 0.45, because the data bandwidth becomes ( ) nyq nyq f f 725 . 0 1 2 1 = + which puts the data bandwidth at the extreme edge of the flat portion of the filter response. if a particular application requires an value between 0.45 and 1, the user must oversample the baseband data by at least a factor of 4. over the frequency range of the data to be transmitted, the combined hbf 1, hbf 2, and cic filters introduce a worst-case droop of less than 0.2 db. frequency relative to i/q nyq bw magnitude (db) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 ?6 ?5 ?4 ?3 ?2 ?1 0 1 1.0 03277-009 figure 25. cascaded filter pass band digital upcoverter the digital quadrature modulator stage following the cic filters is used to frequency shift (upconvert) the baseband spectrum of the incoming data stream to the desired carrier frequency. the carrier frequency is controlled numerically by a direct digital synthesizer (dds). the dds uses the internal system clock (f sysclk ) to generate the desired carrier frequency with a high degree of precision. the carrier is applied to the i and q multipliers in a quadrature fashion (90 phase offset) and summed to yield a data stream that is the modulated carrier. the modulated carrier becomes the 12-bit sample sent to the dac. tx signal level considerations the quadrature modulator itself introduces a maximum gain of 3 db in signal level. to visualize this, assume that both the i and q data are fixed at the maximum possible digital value, x. then, the output of the modulator, z, is ( ) ( ) [ ] t x t x z ? = sin cos q xz x i 03277-010 figure 26. 16-quadrature modulation it can be shown that |z| assumes a maximum value of 2 2 2 x x x z = + = (a gain of +3 db). however, if the same number of bits represent |z| and x, an overflow occurs. to prevent this, an effective ?3 db attenuation is internally implemented on the i and q data path: x z = + = 2 1 2 1 the following example assumes a peak rms level of 10 db: lsbs 2000 db 2 . 0 lsbs 2047 = ? = value input component symbol maximum () rms lsbs 1265 db db 6 lsbs 2000 = ? = rms peak value rms input complex maximum the maximum complex input rms value calculation uses both i and q symbol components that add a factor of two (6 db) to the formula. table 10 shows typical i-q input test signals with amplitude levels related to 12-bit full scale (fs). table 10. i-q input test signals analog output digital input input level modulator output level single tone i = cos(f) fs ? 0.2 db fs ? 3.0 db (f c ? f) q = cos(f + 90) = ?sin(f) fs ? 0.2 db single tone i = cos(f) fs ? 0.2 db fs ? 3.0 db (f c + f) q = cos(f + 270) = +sin(f) fs ? 0.2 db dual tone i = cos(f) fs ? 0.2 dbfs fs ? 0.2 db fs (f c f) q = cos(f + 180) = ?cos(f) or q = +cos(f) fs ? 0.2 db
AD9878 rev. a | page 23 of 36 tx throughput and latency data inputs affect the output fairly quickly, but remain effective due to the AD9878 filter characteristics. data transmit latency through the AD9878 is easiest to describe in terms of f sysclk clock cycles (4 f mclk ). the numbers provided indicate the number of f sysclk cycles before the AD9878 output responds to a change in the input. latency of i/q data from the time it enters the data assembler (AD9878 input) to the time of dac output is 119 f sysclk clock cycles (29.75 f mclk cycles). dc values applied to the data assembler input take up to 176 f sysclk clock cycles (44 f mclk cycles) to propagate and settle at the dac output. frequency hopping is accomplished via changing the profile input pin. the time required to switch from one frequency to another is less than 232 f sysclk cycles (58.5 f mclk cycles). dac a 12-bit digital-to-analog converter (dac) is used to convert the digitally processed waveform into an analog signal. the worst- case spurious signals due to the dac are the harmonics of the fundamental signal and their al iases (see the analog devices dds tutorial at www.analog.com/dds ). the conversion process produces aliased components of the fundamental signal at ( ) . 3 , 2 , 1 = n f f n carrier sysclk these are typically filtered with an external rlc filter at the dac output. it is important for this analog filter to have a sufficiently flat gain and linear phase response across the bandwidth of interest to avoid modulation impairments. a relatively inexpensive seventh- order, elliptical, low-pass filter is sufficient to suppress the aliased components for hfc network applications. the AD9878 provides true and complement current outputs. the full-scale output current is set by the r set resistor at pin 49 and the dac gain register. assuming maximum dac gain, the value of r set for a full-scale i out is determined using the equation: out out dacrset set i i v r 4 . 39 32 = = for example, if a full-scale output current of 20 ma is desired, then r set = (39.4/0.02), or approximately 2 k?. the following equation calculates the full-scale output current, including the programmable dac gain control: () 20 5 . 0 5 . 7 10 4 . 39 gain n set out r i + ? = where n gain is the value of dac fine gain control [3:0]. the full-scale output current range of the AD9878 is 4 to 20 ma. full-scale output currents outside this range degrade sfdr performance. sfdr is also slightly affected by output matchingthat is, the two outputs should be terminated equally for best sfdr performance. the output load should be located as close as possible to the AD9878 package to minimize stray capacitance and inductance. the load can be a simple resistor to ground, an op amp current-to-voltage converter, or a transformer- coupled circuit. it is best not to directly drive a highly reactive load, such as an lc filter. driving an lc filter without a transformer requires that the filter be doubly terminated for best performancethat is, both the filter input and output should be resistively terminated with the appropriate values. the parallel combination of the two terminations determines the load that the AD9878 sees for signals within the filter pass band. for example, a 50 ? terminated input/output low-pass filter looks like a 25 ? load to the AD9878. the output compliance voltage of the AD9878 is ?0.5 v to +1.5 v. any signal developed at the dac output should not exceed 1.5 v; otherwise, signal distortion results. furthermore, the signal can extend below ground as much as 0.5 v without damage or signal distortion. the AD9878 true and complement outputs can be differentially combined for common-mode rejection using a broadband 1:1 transformer. using a grounded center tap results in signals at the AD9878 dac output pins that are symmetrical about ground. as previously mentioned, by differentially combining the two signals, the user can provide some degree of common-mode signal rejection. a differential combiner can consist of a transformer or an op amp. the object is to combine or amplify the difference between only two signals and to reject any commonusually undesirablecharacteristics, such as 60 hz hum or clock feedthrough, that is equally present on both signals. ad832x AD9878 variable gain cable driver amplifier 3 tx ca dac 75 ? low-pass filter ca_en ca_data ca_clk 03277-011 figure 27. cable amplifier connection connecting the AD9878 true and complement outputs to the differential inputs of the programmable gain cable drivers ad8321/ad8323 or ad8322/ad8327 (see figure 27) provides an optimized solution for the standard compliant cable modem upstream channel. the cable drivers gain can be programmed through a direct 3-wire interface using the AD9878 profile registers. programming the ad8321/ad8323 or ad8322/ad8327/ad8238 cable-driver amplifiers users can program the gain of the ad832x family of cable-driver amplifiers via the AD9878 cable amplifier control interface. two (one per profile) 8-bit registers within the AD9878 store the gain value to be written to the serial 3-wire port. typically, either the ad8321/ad8323 or ad8322/ad8327 variable gain cable amplifiers are connected to the chips 3-wire cable amplifier
AD9878 rev. a | page 24 of 36 interface. the tx gain control select bit in register 0x0f changes the interpretation of the bits in register 0x13, register 0x17, register 0x1b, and register 0x1f. see figure 28 and the cable-driver gain control section. ca_en ca_clk c a_dat a msb 8 t mclk 8 t mclk 8 t mclk 4 t mclk 4 t mclk lsb 03277-012 figure 28. cable amplifier interface timing data transfers to the programmable gain cable-driver amplifier are initiated by the following conditions: ? power-up and hardware reset: upon initial power-up and every hardware reset, the AD9878 clears the contents of the gain control registers to 0, which defines the lowest gain setting of the ad832x. thus, the AD9878 writes all 0s out of the 3-wire cable amplifier control interface. ? software reset: writing a 1 to bit 5 of address 0x00 initiates a software reset. upon a software reset, the AD9878 clears the contents of the gain control registers to 0 for the lowest gain and sets the profile select to 0. the AD9878 writes all 0s out of the 3-wire cable amplifier control interface if the gain is previously on a different setting (different from 0). ? change in profile selection: the AD9878 samples the profile input pin together with the two profile select bits and writes to the ad832x gain control registers when a change in profile and gain is determined. the data written to the cable-driver amplifier comes from the AD9878 gain control register associated with the current profile. ? write to the AD9878 cable-driver amplifier control registers: the AD9878 writes gain control data associated with the current profile to the ad832x when the selected AD9878 cable-driver amplifier gain setting is changed. once a new, stable gain value is detected (48 to 64 mclk cycles after initiation) a data write starts with ca_en going low. the AD9878 always finishes a write sequence to the cable- driver amplifier once it is started. the logic controlling data transfers to the cable-driver amplifier uses up to 200 mclk cycles and is designed to prevent erroneous write cycles from occurring. oscin clock multiplier the AD9878 can accept either an input clock into the oscin pin or a fundamental-mode crystal across the oscin and xtal pins as the devices main clock source. the internal pll then generates the f sysclk signal from which all other internal signals are derived. the dac uses f sysclk as its sampling clock. for dds applications, the carrier is typically limited to about 30% of f sysclk . for a 65 mhz carrier, the system clock required is above 216 mhz. the oscin multiplier function maintains clock integrity, as evidenced by the parts excellent phase noise characteristics and low clock-related spur in the output spectrum. external loop filter components, consisting of a series resistor (1.3 k?) and capacitor (0.01 f), provide the compensation zero for the oscin multiplier pll loop. the overall loop performance is optimized for these component values. clock and oscillator circuitry the AD9878s internal oscillator generates all sampling clocks from a simple, low cost, parallel resonance, fundamental fre- quency quartz crystal. figure 29 shows how the quartz crystal is connected between oscin (pin 61) and xtal (pin 60) with parallel resonant load capacitors, as specified by the crystal manufacturer. the internal oscillator circuitry can also be overdriven by a ttl-level clock applied to oscin with xtal left unconnected. m f f mclk oscin = an internal pll generates the dac sampling frequency, f sysclk , by multiplying the oscin frequency by m. the mclk signal (pin 23), f mclk , is derived by dividing f sysclk by 4. m f f oscin sysclk = 4 m f f oscin mclk = an external pll loop filter (pin 57), consisting of a series resistor and ceramic capacitor (figure 29: r1 = 1.3 k?, c12 = 0.01 f), is required for stability of the pll. also, a shield surrounding these components is recommended to minimize external noise coupling into the plls voltage-controlled oscillator input (guard trace connected to avddpll). figure 23 shows that adcs are either sampled directly by a low jitter clock at oscin or by a clock that is derived from the pll output. operating modes can be selected in register 0x08. sampling the adcs directly with the oscin clock requires that mclk is programmed to be twice the oscin frequency. programmable clock output refclk the AD9878 provides an auxiliary output clock on pin 69, refclk. the value of the mclk divider bit field, r, determines its output frequency, as shown in the following equations: 63 to 2 for , = = 0 for , = = in its default setting (0x00 in register 0x01), the refclk pin provides a buffered output of f oscin .
AD9878 rev. a | page 25 of 36 03277-013 c10 20pf c11 20pf c12 0.01 f guard trace r1 1.3k ? c13 0.1 f r set 4.02 ? c5 0.1 f c6 0.1 f c4 0.1 f cp2 10 f c2 0.1 f c3 0.1 f c1 0.1 f cp1 10 f c2 0.1 f c3 0.1 f c1 0.1 f cp1 10 f 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 avdd agnd video in agnd if12a+ if12a? agnd avdd reft12a refb12a avdd agnd if12b+ if12b? agnd avdd reft12b refb12b avdd agnd avdd10 agnd10 if10+ if10? agnd 76 reft10 75 refb10 74 agnd10 73 avdd10 72 drvdd 71 drgnd 70 refclk 69 sigdelt 68 flag1 67 flag2 66 ca_en 65 ca_data 64 ca_clk 63 dvddosc 62 oscin 61 xtal 60 dgndosc 59 agndpll 58 pllfilt 57 avddpll 56 dvddpll 55 dgndpll 54 avddtx 53 tx+ 52 tx? 51 txsync 26 (msb) txiq(5) 27 txiq(4) 28 txiq(3) 29 txiq(2) 30 txiq(1) 31 txiq(0) 32 dvdd 33 dgnd 34 dvdd 35 dgnd 36 profile 37 reset 38 dvdd 39 dgnd 40 sclk 41 cs 42 sdio 43 sdo 44 dgndtx 45 dvddtx 46 pwrdn 47 refio 48 fsadj 49 agndtx 50 drgnd 1 drvdd 2 (msb) if12(11) 3 if12(10) 4 if12(9) 5 if12(8) 6 if12(7) 7 if12(6) 8 if12(5) 9 if12(4) 10 if12(3) 11 if12(2) 12 if12(1) 13 if12(0) 14 (msb) if10(4) 15 if10(3) 16 if10(2) 17 if10(1) 18 if10(0) 19 rxsync 20 drgnd 21 drvdd 22 mclk 23 dvdd 24 dgnd 25 AD9878 top view (not to scale) figure 29. basic connection diagram
AD9878 rev. a | page 26 of 36 power-up sequence upon initial power-up, the reset pin should be held low until the power supply is stable (see figure 30). once reset is deasserted, the AD9878 can be programmed over the serial port. the on- chip pll requires a maximum of 1 ms after the rising edge of reset or a change of the multiplier factor (m) to completely settle. it is recommended that the pwrdn pin is held low during the reset and pll settling time. changes to adc clock select (register 0x08) or system clock divider n (register 0x01) should be programmed before the rising edge of pwrdn . once the pll is frequency locked and after the pwrdn pin is brought high, transmit data can be sent reliably. if the pwrdn pin cannot be held low throughout the reset and pll settling time period, the power-down digital tx bit, or the pwrdn pin, should be pulsed after the pll has settled. this ensures correct transmit filter initialization. 03277-014 v s 1ms min. 5mclk min. reset pwrdn figure 30. power-up sequence for tx data path reset to initiate a hardware reset, the reset pin should be held low for at least 100 ns. all internally generated clocks, except refclk, stop during reset. the rising edge of reset resets the pll clock multiplier and reinitializes the programmable registers to their default values. the same sequence as described in the power-up sequence section should be followed after a reset or change in m. a software reset (writing 1 into bit 5 of register 0x00) is func- tionally equivalent to a hardware reset, but does not force register 0x00 to its default value. transmit power-down a low level on the pwrdn pin stops all clocks linked to the digital transmit data path and resets the cic filter. deasserting pwrdn reactivates all clocks. the cic filter is held in a reset state for 80 mclk cycles after the rising edge of pwrdn to allow for flushing of the half-band filters with new input data. transmit data bursts should be padded with at least 20 symbols of null data directly before the pwrdn pin is deasserted. immediately after the pwrdn pin is deasserted, the transmit burst should start with a minimum of 20 null data symbols (see figure 31). this avoids unintended dac output samples caused by the transmit path latency and filter settling time. software power-down digital tx (bit 5 in register 0x02) is func- tionally equivalent to the hardware pwrdn pin and takes effect immediately after the last register bit is written over the serial port. pwrdn txiq txsync 20 null symbols data symbols 20 null symbols 00 0 0 00 00 5mclk min. 03277-015 figure 31. timing sequence to flush tx data path
AD9878 rev. a | page 27 of 36 -? outputs an on-chip -? output provides a digital logic bit stream with an average duty cycle that varies between 0% and (255/256)%, depending on the programmed code, as shown in figure 32. 00h 8 t mclk 01h 02h 80h ffh 256 8 t mclk 8 t mclk 256 8 t mclk 03277-016 figure 32. -? output signals this bit stream can be low-pass filtered to generate a programmable dc voltage of ( ) [ ] + ? = 256 - where: v 6 . 0 ? = v 4 . 0 = in cable set-top box applications, the output can be used to control external variable gain amplifiers or rf tuners. a single-pole, rc, low-pass filter provides sufficient filtering (see figure 33). in more demanding applications, where additional gain, level-shift, or drive capability is required, consider using a first- or second-order filter (see figure 34). AD9878 mclk dac 8 control word typical: r = 50k ? c = 0.01 f f ?3db = 1/(2 rc) = 318hz 8 - ? r dc (v l to v h ) c 03277-017 figure 33. -? rc filter 03277-018 AD9878 sigma-delta - ? r c v sd r v out r r1 v offset c op250 typical: r = 50k ? c = 0.01 f f ?3db = 1/(2 rc) = 318hz v out = (v sd + v offset ) (1 + r/r1)/2 figure 34. -? active filter with gain and offset receive path (rx) the AD9878 includes three high speed, high performance adcs. the 10-bit and dual 12-bit direct-if adcs deliver excellent under- sampling performance with input frequencies as high as 70 mhz. the sampling rate can be as high as 29 msps. the adc sampling frequency can be derived directly from the oscin signal, or from the on-chip oscin multiplier. for highest dynamic performance, choose an oscin frequency that can be directly used as the adc sampling clock. digital 12-bit adc outputs are multiplexed to one 12-bit bus, clocked by a frequency (f mclk ) four times the sampling rate. the if adcs use a multiplexer to a 12-bit interface with an output word rate of f mclk . if10 and if12 adc operation the if10 and if12 adcs have a common architecture and share several characteristics from an applications standpoint. most of the information in the following section is applicable to both if adcs; differences, where they exist, are highlighted. input signal range and digital output codes the if adcs have differential analog inputs labeled if+ and if?. the signal input, v ain , is the voltage difference between the two input pins, v ain = v if+ ? v if? . the full-scale input voltage range is determined by the internal reference voltages, reft and refb, which define the top and bottom of the scale. the peak input voltage to the adc is the difference between reft and refb, which is 1 v p-p. this results in an adc full-scale input voltage of 2 v ppd . the digital output codes are straight binary and are shown in table 11. table 11. digital output codes if12[11:0] input signal voltage 111111 v ain +1.0 v 111111 v ain = +1.0 v ? 1 lsb 111110 v ain = +1.0 v ? 2 lsb 100001 v ain = 0 v + 1 lsb 100000 v ain = 0.0 v 011111 v ain = 0 v ? 1 lsb 000001 v ain = ?1.0 v + 2 lsb 000000 v ain = ?1.0 v 000000 v ain < ?1.0 v
AD9878 rev. a | page 28 of 36 driving the input the if adcs have differential switched capacitor sample-and- hold amplifier (sha) inputs. the nominal differential input impedance is 4.0 k?||3 pf. this impedance can be used as the effective termination impedance when calculating filter transfer characteristics and voltage signal attenuation from nonzero source impedances. for best performance, additional requirements must be met by the signal source. the sha has input capacitors that must be recharged each time the input is sampled. this results in a dynamic input current at the device input, and demands that the source has low (<50 ?) output impedance at frequencies up to the adc sampling frequency. also, the source must have settling of better than 0.1% in less than half the adc clock period. another consideration for getting the best performance from the adc inputs is the dc biasing of the input signal. ideally, the signal should be biased to a dc level equal to the midpoint of the adc reference voltages, reft12 and refb12. nominally, this level is 1.2 v. when ac-coupled, the adc inputs self-bias to this voltage and require no additional input circuitry. figure 35 illustrates a recommended circuit that eases the burden on the signal source by isolating its output from the adc input. the 33 ? series termination resistors isolate the amplifier outputs from any capacitive load, which typically improves settling time. the series capacitors provide ac signal coupling, which ensures that the adc inputs operate at the optimal dc-bias voltage. the shunt capacitor sources the dynamic currents required to charge the sha input capacitors, removing this requirement from the adc buffer. the values of c c and c s should be calculated to determine the correct hpf and lpf corner frequencies. ain+ ain? 33 ? c c c s c c v s 33 ? 03277-019 figure 35. simple adc drive configuration receive timing the AD9878 sends multiplexed data to the if10 and if12 outputs upon every rising edge of mclk. rxsync frames the start of each if10 data symbol. the 10-bit and 12-bit adcs are read completely upon every second mclk cycle. rxsync is high for every second 10-bit adc data if the 10-bit adc is not in power-down mode. the rx timing diagram is shown in figure 36. t od t ee t md refclk mclk if10 data if10[9:5] if10[4:0] if10[9:5] if10[4:0] m/n = 2 if10[9:5] if10[4:0] if12a if12b if12b if12b if12a if12b rxsync if12 data rx port timing (default mode: muxed if12 adc data) m/n = 2 refclk if12a or if12b if12a or if12b if10[9:5] if10[4:0] if10[9:5] if10[4:0] if10[9:5] if10[4:0] if12a or if12b mclk if10 data rxsync if data t md t ee t od rx port timing (output data from only one if12 adc) 03277-020 figure 36. rx port timing
AD9878 rev. a | page 29 of 36 adc voltage references the AD9878 has three independent internal references for its 10-bit and 12-bit adcs. both 12-bit and 10-bit adcs are designed for 2 v p-p input voltages and have their own internal reference. figure 29 shows the proper connections of the reft and refb reference pins. external references might be necessary for systems that require high accuracy gain matching between adcs, or for improvements in temperature drift and noise characteristics. external references reft and refb must be centered at avdd/2, with offset voltages as specified by the following equations: v 5 . 0 2 : 12 , 10 + ? ? avdd reft v 5 . 0 2 : 12 , 10 ? ? ? avdd reft a differential level of 1 v between the reference pins results in a 2 v p-p adc input level ain. internal reference sources can be powered down when external references are used (address 0x02). video input for sampling video-type waveforms, such as ntsc and pal signals, the video input channel provides black-level clamping. figure 37 shows the circuit configuration for using the video channel input (pin 98). an external blocking capacitor is used with the on-chip video clamp circuit to level-shift the input signal to a desired reference point. the clamp circuit automatically senses the most negative portion of the input signal and adjusts the voltage across the input capacitor. this forces the black level of the input signal to be equal to the value programmed in the clamp level register (register address 0x07). by default, the video input is disabled and disconnected from both adcs. by setting register 0x07, bit 7 = 1, the video input is enabled and connected to the adc input as determined by the state of reg 0x03, bit 6 ( 0= adc12a connected, 1 = adc12b connected.) 2ma video input 0.1 f clamp level + fs/2 clamp level AD9878 offset buffer 12 + ? dac adc lpf clamp level 03277-021 figure 37. video clamp circuit input
AD9878 rev. a | page 30 of 36 pcb design considerations although the AD9878 is a mixed-signal device, the part should be treated as an analog component. the on-chip digital circuitry is designed to minimize the impact of digital switching noise on the operation of the analog circuits. following the recommendations in this section helps achieve the best performance from the mxfe. component placement the following guidelines for component placement are recommended to achieve optimal performance: ? manage the path of return currents to ensure that high frequency switching currents from the digital circuits do not flow into the ground plane under the mxfe or analog circuits. ? keep noisy digital signal paths and sensitive receive signal paths as short as possible. ? keep digital (noise-generating) and analog (noise-susceptible) circuits as far apart as possible. to best manage the return currents, pure digital circuits that generate high switching currents should be closest to the power supply entry. this keeps the highest frequency return current paths short and prevents them from traveling over the sensitive mxfe and analog portions of the ground plane. also, these circuits should be generously bypassed at each device to further reduce high frequency ground currents. the mxfe should be placed adjacent to the digital circuits, such that the ground return currents from the digital sections do not flow into the ground plane under the mxfe. the analog circuits should be placed furthest from the power supply. the AD9878 has several pins that are used to decouple sensitive internal nodes: refio, refb12a, reft12a, refb12b, reft12b, refb10, and reft10. the decoupling capacitors connected to these points should have low esr and esl, be placed as close as possible to the mxfe, and be connected directly to the analog ground plane. the resistor connected to the fsadj pin and the rc network connected to the pllfilt pin should also be placed close to the device and connected directly to the analog ground plane. power planes and decoupling the AD9878 evaluation board (figure 38 and figure 39) demonstrates a good power supply distribution and decoupling strategy. the board has four layers: two signal layers, one ground plane, and one power plane. the power plane is split into a 3-v dd section that is used for the 3 v digital logic circuits, a dvdd section that is used to supply the digital supply pins of the AD9878, an avdd section that is used to supply the analog supply pins of the AD9878, and a vanlg section that supplies the higher voltage analog components on the board. the 3-v dd section typically has the highest frequency currents on the power plane and should be kept the furthest from the mxfe and analog sections of the board. the dvdd portion of the plane carries the current used to power the digital portion of the mxfe to the device. this should be treated similarly to the 3-v dd power plane and be kept from going underneath the mxfe or analog components. the mxfe should largely sit above the avdd portion of the power plane. the avdd and dvdd power planes can be fed from the same low noise voltage source; however, they should be decoupled from each other to prevent the noise generated in the dvdd portion of the mxfe from corrupting the avdd supply. this can be done by using ferrite beads between the voltage source and dvdd, and between the source and avdd. both dvdd and avdd should have a low esr, bulk-decoupling capacitor on the mxfe side of the ferrite as well as low esr- and esl-decoupling capacitors on each supply pin (for example, the AD9878 requires 17 power supply decoupling capacitors). the decoupling capacitors should be placed as close as possible to the mxfe supply pins. an example of proper decoupling is shown in the AD9878 evaluation boards two-page schematic (figure 38 and figure 39). ground planes in general, if the component placing guidelines discussed earlier can be implemented, it is best to have at least one continuous ground plane for the entire board. all ground connections should be as short as possible. this results in the lowest impedance return paths and the quietest ground connections. if the components cannot be placed in a manner that keeps the high frequency ground currents from traversing under the mxfe and analog components, it might be necessary to put current-steering channels into the ground plane to route the high frequency currents around these sensitive areas. these current-steering channels should be used only when and where necessary. signal routing the digital rx and tx signal paths should be as short as possible. also, these traces should have a controlled impedance of about 50 ?. this prevents poor signal integrity and the high currents that can occur during undershoot or overshoot caused by ringing. if the signal traces cannot be kept shorter than about 1.5 inches, then series termination resistors (33 ? to 47 ?) should be placed close to all signal sources. it is a good idea to series terminate all clock signals at their source, regardless of trace length. the receive signals are the most sensitive signals on the evaluation board. careful routing of these signals is essential for good receive path performance. the if+/if? signals form a differential pair and should be routed together. by keeping the traces adjacent to each other, noise coupled onto the signals appears as common mode and is largely rejected by the mxfe receive input. keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the mxfe further reduces the possibility of noise corrupting these signals.
AD9878 rev. a | page 31 of 36 agnd1 agnd10 agnd10-a agnd2 agnd3 agnd4 agnd5 agnd6 agnd7 agndpll avdd1 avdd10 avdd10-a avdd2 avdd3 avdd4 avdd5 avddpll avddtx ca_clk ca_data dgndosc dgndpll drgnd drvdd dvddosc dvddpll flag1 flag2 if10b+ if10b? if12a+ if12a? if12b+ if12b? oscin pllfilt refb10 refclk refb12b refb12a reft12a reft12b reft10 sigdelt tx? tx+ video in ca_en xtal oscin xtal 76 73 79 81 86 89 94 97 99 58 82 72 80 85 90 93 100 56 53 63 64 59 54 70 71 62 55 67 66 78 77 96 95 88 87 61 57 74 91 83 69 75 92 84 68 52 51 98 60 65 dgnd1 dgnd2 dgnd3 dgnd4 dgndtx dvdd1 dvdd2 dvdd3 dvdd4 dvddtx fsadj if0 if1 if10 if2 if3 if4 if5 if6 if7 if8 if9 ifb0 ifb1 ifb2 ifb3 mclk profile refio rxsync sclk sdio sdo txiq0 txiq1 txiq2 txiq3 txiq5 txsync pwrdn reset drvdd1 if11 if0 if1 if10 if2 if3 if4 if5 if6 if7 if8 if9 if11 drgnd1 txiq4 ifb4 ifb0 ifb1 ifb2 ifb3 ifb4 agndtx drgnd2 drvdd2 50 25 34 36 40 45 1 21 2 22 24 33 35 39 46 49 14 13 4 3 12 11 10 9 8 7 6 5 19 18 17 16 15 23 37 48 20 41 43 44 32 31 30 29 28 27 26 42 47 38 cs sclk sdio sdo cs AD9878lqfp u2 txiq1 txiq2 txiq3 txiq5 txsync txiq0 profile1 txiq4 3 1 5 7 9 11 13 15 17 19 21 23 25 4 2 6 8 10 12 14 16 18 20 22 24 26 header ra ribbon digital transmit ribbon j2 r1 22 rp1 2 rcom 1 r2 3 r3 4 r4 5 r5 6 r6 7 r7 8 r8 9 r9 10 jp9 r29 10k ? drvdd pwrdn rc0805 drvdd rxsync avdd drvdd ca_clk avddtx dvddpll/ dvddosc ca_data ca_en flag2 flag1 sigdelt0 refclk mclk dvdd pwrdn dvddtx ifb[0:4] if[0:11] sdo, sdio, cs, sclk r10 10k ? rc0805 c21 0.1 f cc0603 c22 0.1 f cc0603 sw1 2 1 1 2 3 4 3 reset agnd; 5 reset reset adm1818-10art u1 vcc gnd c1 0.1 f cc0603 drvdd 5v ad8328 u4 ad8328 v cc gnd1 gnd2 v in + v in ? gnd3 dataen sdata clk gnd4 sleep nc byp v out ? v out + ramp txen v cc 1 gnd5 gnd 20 1 19 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 10 5v ad8328 ca_data ca_clk ca_sleep c117 0.1 f cc0603 c115 0.1 f cc0603 c72 0.1 f cc0603 c116 0.1 f cc0603 r28 1k ? rc0603 4 1 2 5 3 2 1 sp tokob5f tx_out j8 ad8328 agnd; 3, 4, 5 smaedge t6 r39 43.3 ? rc0605 r40 86.6 ? rc0605 ca_en l16 220 lc1210 l15 220 lc1210 l13 220 lc1210 l14 220 lc1210 c20 18pf cc0805 c57 33pf cc0805 c58 18pf cc0805 r38 75 ? rc0805 r36 75 ? rc0805 r37 59 ? rc0805 c114 0.01 f cc0603 c113 0.01 f cc0603 ab jp8 2 3 ab jp7 2 1 1 3 ad8328 ad8328 transf transf tx+ tx? 1 2 1 2 3 6 5 4 sp dip06rcup j4 tx_out agnd; 3, 4, 5 smaedge t1 r11 37.5 ? rc0605 r12 37.5 ? rc0605 c23 0.1 f cc0603 c24 0.1 f cc0603 c2 0.1 f cc0603 c3 0.1 f cc0603 c5 0.1 f cc0603 c4 10 f 10v + bcase c6 0.1 f cc0603 c7 0.1 f cc0603 c9 0.1 f cc0603 c8 10 f 10v + bcase c11 0.1 f cc0603 c13 0.1 f cc0603 c12 0.1 f cc0603 c14 10 f 16v + bcase tp2 wht tp4 wht tp1 wht tp5 wht tp6 wht tp15 wht tp3 wht c15 0.01 f cc0603 r3 100k ? rc0805 1 2 1 2 3 6 5 4 dip06rcup j13 if12b agnd; 3, 4, 5 smaedge t3 r27 49.9 ? rc0805 ab jp26 2 1 3 ad8138 8138? vcml r25 33 ? rc0805 c102 0.1 f cc0603 ba jp25 transf transf jp24 2 3 1 ad8138 8138+ r26 33 ? rc0805 c101 0.1 f cc0603 c98 20pf cc0805 if12b+ if12b? 1 2 1 2 3 6 5 4 dip06rcup j13 if10 agnd; 3, 4, 5 smaedge t5 r33 49.9 ? rc0805 ab jp32 2 1 3 ad8138 8138? vcml r32 33 ? rc0805 c112 0.1 f cc0603 ba jp31 transf transf jp30 2 3 1 ad8138 8138+ r31 33 ? rc0805 c111 0.1 f cc0603 c108 20pf cc0805 if10+ if10? r2 33 ? rc0805 c10 0.1 f cc0603 r1 75 ? rc07cup 1 video in agnd; 3, 4, 5 j1 smaedge 2 8 1 3 4 2 6 5 u9 ad8138 +in ?in vee vcc vo? voc vo+ j12 ad8138 agnd; 3, 4, 5 smaedge 1 2 r24 49.9 ? rc0805 r23 523 ? rc0805 r18 499 ? rc0805 r22 499 ? rc0805 r21 33 ? rc0805 r17 499 ? rc0805 r14 33 ? rc0805 a_buff+ 8138? a_buff? c96 10 f 16v + c97 0.1 f cc0805 bcase 1 2 1 2 3 6 5 4 dip06rcup j11 if12a agnd; 3, 4, 5 smaedge t2 r20 49.9 ? rc0805 ab jp23 2 1 3 ad8138 vcml r19 33 ? rc0805 c94 0.1 f cc0603 ba jp21 transf transf jp22 2 3 1 ad8138 r13 33 ? rc0805 c86 0.1 f cc0603 c92 20pf cc0805 if12a+ if12a? c95 47pf cc1206 c88 47pf cc1206 c87 0.1 f cc0805 r15 10k ? rc0805 r16 5.11k ? rc0805 jp4 vcml 8138+ c69 0.1 f c66 0.1 f cc0603 cc0603 c16 0.01 f cc0603 r4 1.3k ? rc0805 j3 oscin_clk agnd; 3, 4, 5 sma200up y1 val 1 2 3 c19 0.1 f cc0805 r9 49.9 ? rc0805 r7 500 ? rc0805 pot1 10k ? cw r6 500 ? rc0805 agnd; 3 v_clk; 5 u13 nc7sz04 24 r5 33 ? rc0805 v_clk c84 0.1 f cc0805 c110 0.1 f cc0805 bcase c83 10 f 16v + duty cycle oscin xtal ext_clk jp1 c18 18pf cc0805 c17 18pf cc0805 03277-038 + c90 0.1 f cc0805 bcase c91 10 f 16v figure 38. evaluation pcb schematic
AD9878 rev. a | page 32 of 36 + c60 10 f 16v bcase c63 0.1 f cc0805 val l8 3.3v_ana tp16 clr avddpll + c89 10 f 16v bcase c93 0.1 f cc0805 val l17 tp20 clr v_clk lc1210 + c59 10 f 16v bcase c62 0.1 f cc0805 c85 0.1 f cc0603 c76 0.1 f cc0603 c74 0.1 f cc0603 c71 0.1 f cc0603 c68 0.1 f cc0603 c65 0.1 f avdd cc0603 val l7 lc1210 tp18 clr lc1210 + c78 10 f 16v bcase c81 0.1 f cc0805 val l11 abuff? tp14 clr a_buff? lc1210 + c77 10 f 16v bcase c80 0.1 f cc0805 val l10 abuff+ tp12 clr a_buff+ lc1210 + c79 10 f 16v bcase c82 0.1 f cc0805 val l12 tp13 clr 5v_ad8328 lc1210 + c61 10 f 16v bcase c70 0.1 f cc0603 c73 0.1 f cc0603 c75 0.1 f cc0805 avddtx l9 c64 0.1 f cc0805 c67 0.1 f cc0603 val lc1210 tp17 clr + c25 10 f 16v bcase c28 0.1 f cc0805 c31 0.1 f cc0603 c34 0.1 f cc0603 c37 0.1 f cc0603 dvdd val l1 lc1210 tp19 clr + c26 10 f 16v bcase c29 0.1 f cc0805 c32 0.1 f cc0603 c35 0.1 f cc0603 c38 0.1 f cc0603 c39 0.1 f cc0603 drvdd val l2 lc1210 tp7 clr + c42 10 f 16v bcase c45 0.1 f cc0805 c56 0.1 f cc0603 c54 0.1 f cc0605 c51 0.1 f cc0805 c48 0.1 f cc0605 3.3v_buff val l6 lc1210 tp10 clr + c40 10 f 16v bcase c43 0.1 f cc0805 c52 0.1 f cc0603 c49 0.1 f cc0603 c46 0.1 f cc0605 dvddpll/ dvddosc val l4 lc1210 tp8 clr + c27 10 f 16v bcase c30 0.1 f cc0805 c33 0.1 f cc0603 c36 0.1 f cc0603 dvddtx val l3 lc1210 tp9 clr + c41 10 f 16v bcase c44 0.1 f cc0805 c47 0.1 f cc0603 c50 0.1 f cc0603 c55 0.1 f cc0603 c53 0.1 f cc0603 c100 0.1 f cc0603 5v_buff val l5 lc1210 tp11 clr tb1 3.3v_ana 1 tb1 gnd 2 tb1 ?5v_ana 3 tb1 gnd 4 tb1 +5v_ana 5 tb1 gnd 6 tb1 5v_dig 7 tb1 3.3v_dig 8 power 5v 3.3v_dig jp2 ad8328 jp5 invert clk a 13 2 b jp6 del_clk a 31 2 b a1 a2 a3 a4 a5 a6 a7 gnd1 gnd2 gnd3 b7 b6 b5 b4 b3 b2 b1 b0 nc vccb a0 vcca oe t/r a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 gnd1 gnd2 gnd3 nc t/r vcca vccb oe a1 a2 a3 a4 a5 a6 a7 gnd1 gnd2 gnd3 b7 b6 b5 b4 b3 b2 b1 b0 nc vccb a0 vcca oe t/r a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 gnd1 gnd2 gnd3 nc t/r vcca vccb oe mclk rxsync del_clk ifb[0:4] 3.3v_buff 5v_buff sdo 3 4 5 6 7 8 9 10 21 20 19 18 17 16 15 14 11 12 13 23 124 22 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 24 3 1 2 2 24 1 23 13 12 11 14 15 16 17 18 19 20 21 10 9 8 7 6 5 4 3 2 1 3 24 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 sdopc sdio cs sclk if2 if3 if1 if4 if5 if6 if7 if8 if9 if10 if11 if[0:11] 9 8 10 7 11 6 12 5 13 4 14 3 15 2 16 1 rp3 22 9 8 10 7 11 6 12 5 13 4 14 3 15 2 16 1 rp2 22 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 rp4 22 u6 74lvxc3245 tssop24 u5 74lvxc3245 tssop24 u7 74lvxc3245 tssop24 u8 74lvxc3245 tssop24 9 8 10 7 11 6 12 5 13 4 14 3 15 2 16 1 rp6 22 9 8 10 7 11 6 12 5 13 4 14 3 15 2 16 1 rp5 22 22 22 22 8 1 7 2 6 3 5 4 rp7 22 24 u3 nc7sz04 agnd; 3 5v_buff; 5 ab ifb4 if0 jp13 2 13 p1 rj45 1 2 3 4 5 6 7 8 9101112 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 pc parallel port j6 dcn2 5 rpt 12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 digital receive scs ssclk ssdio sdopc jp3 dvdd r34 1k ? rc0603 ca_sleep del_clk r8 100 ? rc0603 r35 33 ? j7 mclk agnd; 3, 4, 5 smaedge rc0603 1 2 j5 ribbon hdr040ra 03277-039 figure 39. evaluation pcb schematic (continued)
AD9878 rev. a | page 33 of 36 03277-040 figure 40. evaluation pcbtop assembly 03277-041 figure 41. evaluation pcbbottom assembly
AD9878 rev. a | page 34 of 36 03277-042 figure 42. evaluation pcb layouttop layer 03277-043 figure 43. evaluation pcb layoutbottom layer
AD9878 rev. a | page 35 of 36 03277-044 figure 44. evaluation pcbpower plane 03277-045 figure 45. evaluation pcbground plane
AD9878 rev. a | page 36 of 36 outline dimensions compliant to jedec standards ms-026bed top view (pins down) 1 25 26 51 50 75 76 100 14.00 bsc sq 0.50 bsc lead pitch 0.27 0.22 0.17 1.60 max 0.75 0.60 0.45 view a 16.00 bsc sq 12.00 ref pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 figure 46. 100-lead low profile quad flat package [lqfp] (st-100) dimensions shown in millimeters ordering guide model temperature range package description package option AD9878bst ?40c to +85c 100-lqfp st-100 AD9878bstz 1 ?40c to +85c 100-lqfp st-100 AD9878-eb evaluation board 1 z = pb-free part. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c03277C0C3/05(a)

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