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LTC2224 1 2224fa features descriptio u typical applicatio u sample rate: 135msps 67.3db snr up to 140mhz input 80db sfdr up to 150mhz input 775mhz full power bandwidth s/h single 3.3v supply low power dissipation: 630mw cmos outputs selectable input ranges: 0.5v or 1v no missing codes optional clock duty cycle stabilizer shutdown and nap modes data ready output clock pin compatible family 135msps: LTC2224 (12-bit), ltc2234 (10-bit) 105msps: ltc2222 (12-bit), ltc2232 (10-bit) 80msps: ltc2223 (12-bit), ltc2233 (10-bit) 48-pin 7mm 7mm qfn package wireless and wired broadband communication cable head-end systems power amplifier linearization communications test equipment 12-bit, 135msps adc the ltc 2224 is a 135msps, sampling 12-bit a/d con- verter designed for digitizing high frequency, wide dy- namic range signals. the LTC2224 is perfect for demand- ing communications applications with ac performance that includes 67.3db snr and 80db spurious free dy- namic range for signals up to 150mhz. ultralow jitter of 0.15ps rms allows undersampling of if frequencies with excellent noise performance. dc specs include 0.4lsb inl (typ), 0.3lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 0.5lsb rms . a separate output power supply allows the cmos output swing to range from 0.5v to 3.6v. the enc + and enc inputs may be driven differentially or single ended with a sine wave, pecl, lvds, ttl, or cmos inputs. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. 0.5v to 3.6v ov dd ognd + input s/h correction logic output drivers 12-bit pipelined adc core clock/duty cycle control flexible reference d11 d0 encode input refh refl analog input 2224 ta01 3.3v v dd applicatio s u sfdr vs input frequency sfdr (dbfs) input frequency (mhz) 0 600 500 400 2224 ta01b 100 200 300 95 90 85 80 75 70 65 60 55 50 4th or higher 2nd or 3rd , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
LTC2224 2 2224fa co verter characteristics u supply voltage (v dd ) ................................................. 4v digital output ground voltage (ognd) ....... 0.3v to 1v analog input voltage (note 3) ..... 0.3v to (v dd + 0.3v) digital input voltage .................... 0.3v to (v dd + 0.3v) digital output voltage ............... 0.3v to (ov dd + 0.3v) power dissipation ............................................ 1500mw operating temperature range LTC2224c ............................................... 0 c to 70 c LTC2224i .............................................40 c to 85 c storage temperature range ..................65 c to 125 c order part number uk part* marking t jmax = 125 c, ja = 29 c/w LTC2224uk LTC2224uk LTC2224cuk LTC2224iuk absolute axi u rati gs w ww u package/order i for atio uu w ov dd = v dd (notes 1, 2) the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) parameter conditions min typ max units resolution (no missing codes) 12 bits integral linearity error differential analog input (note 5) ? 0.4 1 lsb differential linearity error differential analog input ? 0.3 1 lsb integral linearity error single-ended analog input (note 5) 1lsb differential linearity error single-ended analog input 0.3 lsb offset error (note 6) ?5 335 mv gain error external reference ?.5 0.5 2.5 %fs offset drift 10 v/c full-scale drift internal reference 30 ppm/c external reference 15 ppm/c transition noise sense = 1v 0.5 lsb rms consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. top view uk package 48-lead (7mm 7mm) plastic qfn exposed pad is gnd (pin 49), must be soldered to pcb a in + 1 a in 2 refha 3 refha 4 reflb 5 reflb 6 refhb 7 refhb 8 refla 9 refla 10 v dd 11 v dd 12 36 d9 35 d8 34 d7 33 ov dd 32 ognd 31 d6 30 d5 29 d4 28 ov dd 27 ognd 26 d3 25 d2 49 48 gnd 47 v dd 46 v dd 45 gnd 44 v cm 43 sense 42 mode 41 of 40 d11 39 d10 38 ognd 37 ov dd gnd 13 v dd 14 gnd 15 enc + 16 enc 17 shdn 18 oe 19 clockout 20 do 21 ognd 22 ov dd 23 d1 24 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
LTC2224 3 2224fa symbol parameter conditions min typ max units v in analog input range (a in + ?a in ) 3.1v < v dd < 3.5v 0.5 to 1v v in, cm analog input common mode (a in + + a in )/2 differential input 1 1.6 1.9 v single ended input (note 7) 0.5 1.6 2.1 v i in analog input leakage current 0 < a in + , a in < v dd ? 1 a i sense sense input leakage 0v < sense < 1v ? 1 a i mode mode pin pull-down current to gnd 10 a t ap sample and hold acquisition delay time 0 ns t jitter sample and hold acquisition delay time jitter 0.15 ps rms cmrr analog input common mode rejection ratio 80 db full power bandwidth figure 8 test circuit 775 mhz symbol parameter conditions min typ max units snr signal-to-noise ratio 30mhz input (1v range) 62.8 db 30mhz input (2v range) 66.5 67.6 db 70mhz input (1v range) 62.8 db 70mhz input (2v range) 67.6 db 140mhz input (1v range) 62.5 db 140mhz input (2v range) 67.3 db 250mhz input (1v range) 61.8 db 250mhz input (2v range) 65.9 db sfdr spurious free dynamic range 30mhz input (1v range) 84 db 30mhz input (2v range) 72 84 db 70mhz input (1v range) 84 db 70mhz input (2v range) 84 db 140mhz input (1v range) 84 db 140mhz input (2v range) 84 db 250mhz input (1v range) 77 db 250mhz input (2v range) 77 db sfdr spurious free dynamic range 30mhz input (1v range) 90 db 4th harmonic or higher 30mhz input (2v range) 90 db 70mhz input (1v range) 90 db 70mhz input (2v range) 90 db 140mhz input (1v range) 90 db 140mhz input (2v range) 90 db 250mhz input (1v range) 90 db 250mhz input (2v range) 90 db s/(n+d) signal-to-noise plus 30mhz input (1v range) 62.8 db distortion ratio 30mhz input (2v range) 66 67.4 db 70mhz input (1v range) 62.8 db 70mhz input (2v range) 67.2 db imd intermodulation distortion f in1 = 138mhz, f in2 = 140mhz 81 dbc a alog i put u u dy a ic accuracy u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. a in = ?dbfs. (note 4)
LTC2224 4 2224fa digital i puts a d digital outputs u u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) i ter al refere ce characteristics uu u (note 4) parameter conditions min typ max units v cm output voltage i out = 0 1.575 1.600 1.625 v v cm output tempco 25 ppm/ c v cm line regulation 3.1v < v dd < 3.5v 3 mv/v v cm output resistance ?ma < i out < 1ma 4 ? symbol parameter conditions min typ max units encode inputs (enc + , enc ) v id differential input voltage 0.2 v v icm common mode input voltage internally set 1.6 v externally set (note 7) 1.1 1.6 2.5 v r in input resistance 6k ? c in input capacitance (note 7) 3 pf logic inputs (oe, shdn) v ih high level input voltage v dd = 3.3v 2v v il low level input voltage v dd = 3.3v 0.8 v i in input current v in = 0v to v dd ?0 10 a c in input capacitance (note 7) 3 pf logic outputs ov dd = 3.3v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3.3v 50 ma v oh high level output voltage i o = ?0 a 3.295 v i o = ?00 a 3.1 3.29 v v ol low level output voltage i o = 10 a 0.005 v i o = 1.6ma 0.09 0.4 v ov dd = 2.5v v oh high level output voltage i o = ?00 a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = ?00 a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v
LTC2224 5 2224fa symbol parameter conditions min typ max units v dd analog supply voltage 3.1 3.3 3.5 v ov dd output supply voltage 0.5 3.3 3.6 v i vdd analog supply current 191 206 ma p diss power dissipation 630 680 mw p shdn shutdown power shdn = high, oe = high, no clk 2 mw p nap nap mode power shdn = high, oe = low, no clk 35 mw symbol parameter conditions min typ max units f s sampling frequency 1 135 mhz t l enc low time duty cycle stabilizer off 3.5 3.7 500 ns duty cycle stabilizer on 2 3.7 500 ns t h enc high time duty cycle stabilizer off 3.5 3.7 500 ns duty cycle stabilizer on 2 3.7 500 ns t ap sample-and-hold aperture delay 0 ns t oe output enable delay (note 7) 510 ns t d enc to data delay (note 7) 1.3 2.1 3.5 ns t c enc to clockout delay (note 7) 1.3 2.1 3.5 ns data to clockout skew (t c - t d ) (note 7) ?.6 0 0.6 ns pipeline latency 5 cycles ti i g characteristics u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) power require e ts w u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 8) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3.3v, ov dd = 1.8v, f sample = 135mhz, differential enc + /enc = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is defined as the deviation of a code from a ?est straight line?fit to the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from 0.5 lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2? complement output mode. note 7: guaranteed by design, not subject to test. note 8: v dd = 3.3v, ov dd = 1.8v, f sample = 135mhz, differential enc + /enc = 2v p-p sine wave, input range = 1v p-p with differential drive, output c load = 5pf.
LTC2224 6 2224fa typical perfor a ce characteristics uw 79331 21767 123 322 29529 100000 80000 60000 40000 20000 0 2058 2059 2060 2061 2057 input frequency (mhz) 0 snr (dbfs) 69 67 65 63 61 59 57 55 600 500 400 2224 g04 100 200 300 input frequency (mhz) 0 snr (dbfs) sfdr (dbfs) 69 67 65 63 61 59 57 55 600 500 400 2224 g05 100 200 300 input frequency (mhz) 0 600 500 400 2224 g06 100 200 300 95 90 85 80 75 70 65 60 55 50 sfdr (dbfs) input frequency (mhz) 0 600 500 400 2224 g07 100 200 300 95 90 85 80 75 70 65 60 55 50 sfdr (dbfs) input frequency (mhz) 0 600 500 400 2224 g09 100 200 300 95 90 85 80 75 70 65 60 55 50 sfdr (dbfs) input frequency (mhz) 0 600 500 400 2224 g08 100 200 300 95 90 85 80 75 70 65 60 55 50 2224 g02 2224 g03 count output code 0 4096 2224 g01 1024 2048 3072 output code code 0 4096 1024 2048 3072 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 error (lsb) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 error (lsb) LTC2224: inl, 2v range LTC2224: dnl, 2v range LTC2224: shorted input noise histogram LTC2224: snr vs input frequency, ?db, 2v range LTC2224: sfdr (hd2 and hd3) vs input frequency, ?db, 2v range LTC2224: snr vs input frequency, ?db, 1v range LTC2224: sfdr (hd2 and hd3) vs input frequency, ?db, 1v range LTC2224: sfdr (hd4+) vs input frequency, ?db, 2v range LTC2224: sfdr (hd4+) vs input frequency, ?db, 1v range
LTC2224 7 2224fa typical perfor a ce characteristics uw sample rate (msps) 0 sfdr and snr (dbfs) 160 2224 g10 40 80 120 140 20 60 100 100 95 90 85 80 75 70 65 60 sfdr snr sample rate (msps) 0 sfdr and snr (dbfs) 160 2224 g11 40 80 120 140 20 60 100 100 95 90 85 80 75 70 65 60 sfdr snr sample rate (msps) 0 i vdd (ma) 80 220 210 200 190 180 170 160 150 2224 g12 40 160 120 20 100 60 180 140 2v range 1v range sample rate (msps) 0 i ovdd (ma) 40 80 100 180 2224 g13 20 60 120 140 160 20 10 0 input levels (dbfs) ?0 sfdr (dbc and dbfs) ?0 ?0 ?0 ?0 2224 g14 ?0 100 90 80 70 60 50 40 30 20 10 0 0 dbfs dbc LTC2224: sfdr and snr vs sample rate, 2v range, f in = 30mhz, ?db LTC2224: sfdr and snr vs sample rate, 1v range, f in = 30mhz, ?db LTC2224: i vdd vs sample rate, 5mhz sine wave input, ?db LTC2224: i ovdd vs sample rate, 5mhz sine wave input, ?db, ov dd = 1.8v LTC2224: sfdr vs input level, f in = 70mhz, 2v range
LTC2224 8 2224fa typical perfor a ce characteristics uw 2224 g18 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2224 g19 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2224 g20 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2224 g23 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2224 g22 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2224 g21 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2224 g15 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2224 g16 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2224 g17 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) LTC2224: 8192 point fft, f in = 30mhz, ?db, 2v range LTC2224: 8192 point fft, f in = 30mhz, ?db, 1v range LTC2224: 8192 point fft, f in = 70mhz, ?db, 2v range LTC2224: 8192 point fft, f in = 70mhz, ?db, 1v range LTC2224: 8192 point fft, f in = 140mhz, ?db, 2v range LTC2224: 8192 point fft, f in = 140mhz, ?db, 1v range LTC2224: 8192 point fft, f in = 250mhz, ?db, 2v range LTC2224: 8192 point fft, f in = 250mhz, ?db, 1v range LTC2224: 8192 point fft, f in = 500mhz, ?db, 1v range
LTC2224 9 2224fa a in + (pin 1): positive differential analog input. a in ?(pin 2): negative differential analog input. refha (pins 3, 4): adc high reference. bypass to pins 5, 6 with 0.1 f ceramic chip capacitor, to pins 9, 10 with a 2.2 f ceramic capacitor and to ground with a 1 f ceramic capacitor. reflb (pins 5, 6): adc low reference. bypass to pins 3, 4 with 0.1 f ceramic chip capacitor. do not connect to pins 9, 10. refhb (pins 7, 8): adc high reference. bypass to pins 9, 10 with 0.1 f ceramic chip capacitor. do not connect to pins 3, 4. refla (pins 9, 10): adc low reference. bypass to pins 7, 8 with 0.1 f ceramic chip capacitor, to pins 3, 4 with a 2.2 f ceramic capacitor and to ground with a 1 f ceramic capacitor. v dd (pins 11, 12, 14, 46, 47): 3.3v supply. bypass to gnd with 0.1 f ceramic chip capacitors. adjacent pins can share a bypass capacitor. gnd (pins 13, 15, 45, 48): adc power ground. enc + (pin 16): encode input. the input is sampled on the positive edge. enc (pin 17): encode complement input. the input is sampled on the negative edge. bypass to ground with 0.1 f ceramic for single-ended encode signal. shdn (pin 18): shutdown mode selection pin. connect- ing shdn to gnd and oe to gnd results in normal operation with the outputs enabled. connecting shdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting shdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting shdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance. uu u pi fu ctio s oe (pin 19): output enable pin. refer to shdn pin function. clockout (pin 20): data valid output. latch data on the falling edge of clockout. d0 ?d11 (pins 21, 24, 25, 26, 29, 30, 31, 34, 35, 36, 39, 40): digital outputs. d11 is the msb. ognd (pins 22, 27, 32, 38): output driver ground. ov dd (pins 23, 28, 33, 37): positive supply for the output drivers. bypass to ground with 0.1 f ceramic chip capacitors. of (pin 41): over/under flow output. high when an over or under flow has occurred. mode (pin 42): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and turns the clock duty cycle stabilizer off. connecting mode to 1/3 v dd selects offset binary output format and turns the clock duty cycle stabi- lizer on. connecting mode to 2/3 v dd selects 2? comple- ment output format and turns the clock duty cycle stabi- lizer on. connecting mode to v dd selects 2? complement output format and turns the clock duty cycle stabilizer off. sense (pin 43): reference programming pin. connecting sense to v cm selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sense selects an input range of v sense . 1v is the largest valid input range. v cm (pin 44): 1.6v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. exposed pad (pin 49): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground.
LTC2224 10 2224fa fu n ctio n al block diagra uu w figure 1. functional block diagram diff ref amp ref buf 2.2 f 1 f 0.1 f 0.1 f 1 f internal clock signals refh refl differential input low jitter clock driver range select 1.6v reference enc + refha reflb refla refhb enc shift register and correction oe m0de ognd ov dd 2224 f01 input s/h sense v cm a in a in + 2.2 f first pipelined adc stage fifth pipelined adc stage fourth pipelined adc stage second pipelined adc stage third pipelined adc stage output drivers control logic shdn of d11 d0 clockout
LTC2224 11 2224fa timing diagram ti i g diagra s w u w t ap n + 1 n + 2 n + 4 n + 3 n analog input t h t oe t oe t d t c t l n ?5 n ?4 n ?3 n ?2 n ?1 enc enc + clockout d0-d11, of 2224 td01 oe data of, d0-d11, clockout
LTC2224 12 2224fa applicatio s i for atio wu u u dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log ( (v2 2 + v3 2 + v4 2 + . . . vn 2 )/v1) where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the fifth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa ?fb and 2fb ?fa. the intermodulation distortion is defined as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. full power bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full scale input signal. aperture delay time the time from when a rising enc + equals the enc voltage to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = ?0log (2 ?f in ?t jitter )
LTC2224 13 2224fa converter operation as shown in figure 1, the LTC2224 is a cmos pipelined multistep converter. the converter has five pipelined adc stages; a sampled analog input will result in a digitized value five cycles later (see the timing diagram section). for optimal ac performance the analog inputs should be driven differentially. for cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. the encode input is differen- tial for improved common mode noise immunity. the LTC2224 has two phases of operation, determined by the state of the differential enc + /enc input pins. for brevity, the text will refer to enc + greater than enc as enc high and enc + less than enc as enc low. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when enc is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the ?nput s/h?shown in the block diagram. at the instant that enc transitions from low to high, the sampled input is held. while enc is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of enc. when enc goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is re- peated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the LTC2224 cmos differential sample-and-hold. the analog inputs are connected to the sampling capacitors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capaci- tance associated with each input. c sample 1.6pf v dd v dd LTC2224 a in + 2224 f02 c sample 1.6pf v dd a in enc enc + 1.6v 6k 1.6v 6k c parasitic 1pf c parasitic 1pf 15 ? 15 ? figure 2. equivalent input circuit applicatio s i for atio wu uu
LTC2224 14 2224fa during the sample phase when enc is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. when enc transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when enc is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. single-ended input for cost sensitive applications, the analog inputs can be driven single-ended. with a single-ended input the har- monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in should be connected to 1.6v or v cm . common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.6v. the v cm output pin (pin 44) may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2 f or greater capacitor. input drive impedance as with all high performance, high speed adcs, the dynamic performance of the LTC2224 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reactance can influence sfdr. at the falling edge of enc, the sample- and-hold circuit will connect the 1.6pf sampling capacitor to the input pin and start the sampling period. the sam- pling period ends when enc rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 ? or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the LTC2224 being driven by an rf transformer with a center tapped secondary. the second- ary center tap is dc biased with v cm , setting the adc input 25 ? 25 ? 25 ? 25 ? 0.1 f a in + a in 12pf 2.2 f v cm LTC2224 analog input 0.1 ft1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size 2224 f03 figure 3. single-ended to differential conversion using a transformer applicatio s i for atio wu uu
LTC2224 15 2224fa signal at its optimum dc level. terminating on the trans- former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 ? for each adc input. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain band- width of most op amps will limit the sfdr at high input frequencies. figure 5 shows a single-ended input circuit. the imped- ance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. the 25 ? resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. for input frequen- cies higher than 100mhz, the capacitor may need to be decreased to prevent excessive signal loss. for input frequencies above 100mhz the input circuits of figure 6, 7 and 8 are recommended. the balun trans- former gives better high frequency response than a flux coupled center tapped transformer. the coupling capaci- tors allow the analog inputs to be dc biased at 1.6v. in figure 8 the series inductors are impedance matching elements that maximize the adc bandwidth. reference operation figure 9 shows the LTC2224 reference circuitry consisting of a 1.6v bandgap reference, a difference amplifier and switching and control circuit. the internal voltage refer- ence can be configured for two pin selectable input ranges of 2v ( 1v differential) or 1v ( 0.5v differential). tying the sense pin to v dd selects the 2v range; typing the sense pin to v cm selects the 1v range. the 1.6v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.6v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. applicatio s i for atio wu uu 25 ? 25 ? a in + a in 12pf 2.2 f 3pf 3pf v cm LTC2224 2224 f04 + + cm analog input high speed differential amplifier ltc6600-20 or lt1993 figure 4. differential drive with an amplifier figure 5. single-ended drive 25 ? 0.1 f analog input v cm a in + a in 1k 12pf 2224 f05 2.2 f 1k 25 ? 0.1 f LTC2224
LTC2224 16 2224fa and reflb for the low reference. the multiple output pins are needed to reduce package inductance. bypass capaci- tors must be connected as shown in figure 9. other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in figure 10. an external reference can be used by applying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1 f ceramic capacitor. applicatio s i for atio wu uu figure 7. recommended front end circuit for input frequencies between 250mhz and 500mhz 25 ? 25 ? 0.1 f a in + a in 2pf 2.2 f v cm LTC2224 analog input 0.1 f 0.1 f t1 t1 = ma/com etc1-1-13 resistors, capacitors, inductors are 0402 package size 2224 f08 4.7nh 4.7nh figure 6. recommended front end circuit for input frequencies between 100mhz and 250mhz 25 ? 25 ? 12 ? 12 ? 0.1 f a in + a in 8pf 2.2 f v cm LTC2224 analog input 0.1 f 0.1 f t1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size 2224 f06 figure 8. recommended front end circuit for input frequencies above 500mhz 25 ? 25 ? 0.1 f a in + a in 2.2 f v cm LTC2224 analog input 0.1 f 0.1 f t1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size 2224 f07 v cm refha reflb sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ?v sense for 0.5v < v sense < 1v 1.6v refla refhb 2.2 f 2.2 f internal adc high reference buffer 0.1 f 2224 f09 LTC2224 4 ? diff amp 1 f 1 f 0.1 f internal adc low reference 1.6v bandgap reference 1v 0.5v range detect and control figure 9. equivalent reference circuit v cm sense 1.6v 0.8v 2.2 f 12k 1 f 12k 2224 f10 LTC2224 figure 10. 1.6v range adc the difference amplifier generates the high and low refer- ence for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has four pins: two each of refha and refhb for the high reference and two each of refla
LTC2224 17 2224fa input range the input range can be set based on the application. the 2v input range will provide the best signal-to-noise perfor- mance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 5db. see the typical performance character- istics section. driving the encode inputs the noise performance of the LTC2224 can depend on the encode signal quality as much as on the analog input. the enc + /enc inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 1.6v bias. the bias resistors set the dc operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. any noise present on the encode signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen- cies) take the following into consideration: applicatio s i for atio wu uu 1. differential drive should be used. 2. use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. if the adc is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.1v to 2.5v. each input may be driven from ground to v dd for single-ended drive. maximum and minimum encode rates the maximum encode rate for the LTC2224 is 135msps. for the adc to operate properly, the encode signal should have a 50% ( 5%) duty cycle. each half cycle must have at least 3.5ns for the adc internal circuitry to have enough settling time for proper operation. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the enc + pin to sample the analog input. the falling edge of enc + is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. the lower limit of the LTC2224 sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the specified minimum operating fre- quency for the LTC2224 is 1msps. v dd v dd LTC2224 2224 f11 v dd enc enc + 1.6v bias 1.6v bias 1:4 0.1 f clock input 50 ? 6k 6k to internal adc circuits figure 11. transformer driven enc + /enc
LTC2224 18 2224fa applicatio s i for atio wu uu digital outputs table 1 shows the relationship between the analog input voltage, the digital data bits and the overflow bit. digital output buffers figure 13 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, which are isolated from the adc power and ground. the addi- tional n-channel transistor in the output driver allows operation down to voltages as low as 0.5v. the internal resistor in series with the output makes the output appear as 50 ? to external circuitry and may eliminate the need for external damping resistors. 2224 f12a enc 1.6v v threshold = 1.6v enc + 0.1 f LTC2224 2224 f12b enc enc + 130 ? 3.3v 3.3v 130 ? d0 q0 q0 mc100lvelt22 LTC2224 83 ? 83 ? figure 12a. single-ended enc drive, not recommended for low jitter figure 12b. enc drive using a cmos to pecl translator as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the LTC2224 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. for full speed operation the capacitive load should be kept under 5pf. lower ov dd voltages will also help reduce interference from the digital outputs and improve the snr. data format the LTC2224 parallel digital output can be selected for offset binary or 2? complement format. the format is selected with the mode pin. connecting mode to gnd or 1/3v dd selects offset binary output format. connecting mode to 2/3v dd or v dd selects 2? complement output format. an external resistor divider can be used to set the 1/3v dd or 2/3v dd logic values. table 2 shows the logic states for the mode pin. LTC2224 2224 f13 ov dd v dd v dd 0.1 f 43 ? typical data output ognd ov dd 0.5v to 3.6v predriver logic data from latch oe figure 13. digital output buffer table 1. output codes vs input voltage a in + ?a in d11 ?d0 d11 ?d0 (2v range) of (offset binary) (2? complement) >+1.000000v 1 1111 1111 1111 0111 1111 1111 +0.999512v 0 1111 1111 1111 0111 1111 1111 +0.999024v 0 1111 1111 1110 0111 1111 1110 +0.000488v 0 1000 0000 0001 0000 0000 0001 0.000000v 0 1000 0000 0000 0000 0000 0000 ?.000488v 0 0111 1111 1111 1111 1111 1111 ?.000976v 0 0111 1111 1110 1111 1111 1110 ?.999512v 0 0000 0000 0001 1000 0000 0001 ?.000000v 0 0000 0000 0000 1000 0000 0000 LTC2224 19 2224fa applicatio s i for atio wu uu overflow bit the converter is either overranged or underranged when of outputs a logic high. output clock the adc has a delayed version of the enc + input available as a digital output, clockout. the clockout pin can be used to synchronize the converter data to the digital sys- tem. this is necessary when using a sinusoidal encode. data will be updated just after clockout rises and can be latched on the falling edge of clockout. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example if the converter is driving a dsp powered by a 1.8v supply then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage up to 3.6v. ognd can be powered with any voltage from gnd up to 1v and must be less than ov dd . the logic outputs will swing be- tween ognd and ov dd . output enable the outputs may be disabled with the output enable pin, oe. oe high disables all data outputs including of and clockout. the data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. the output hi-z state is intended for use during long periods of inactivity. sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mw. when exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode, which typically dissipates 35mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap mode all digital outputs are disabled and enter the hi-z state. grounding and bypassing the LTC2224 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an inter- nal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital signal alongside an analog signal or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , refha, refhb, refla and reflb pins as shown in the block diagram on the front page of this data sheet. bypass capacitors must be located as close to the pins as possible. of particular importance are the capaci- tors between refha and reflb and between refhb and refla. these capacitors should be as close to the device as possible (1.5mm or less). size 0402 ceramic capacitors are recommended. the 2.2 f capacitor between refha and refla can be somewhat further away. the traces connect- ing the pins and bypass capacitors must be kept short and should be made as wide as possible. the LTC2224 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the LTC2224 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the pc board. it is critical that all ground pins are connected to a ground plane of sufficient area.
LTC2224 20 2224fa applicatio s i for atio wu uu clock sources for undersampling undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. a clock source that degrades snr of a full-scale signal by 1db at 70mhz will degrade snr by 3db at 140mhz, and 4.5db at 190mhz. in cases where absolute clock frequency accuracy is relatively unimportant and only a single adc is required, a 3v canned oscillator from vendors such as saronix or vectron can be placed close to the adc and simply connected directly to the adc. if there is any distance to the adc, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. you must not allow the clock to overshoot the supplies or performance will suffer. do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. the lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the adc may be beneficial. this filter should be close to the adc to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the adc. if you are sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. if your clock is also used to drive digital devices such as an fpga, you should locate the oscillator, and any clock fan-out devices close to the adc, and give the routing to the adc precedence. the clock signals to the fpga should have series termination at the source to prevent high frequency noise from the fpga disturbing the substrate of the clock fan-out device. if you use an fpga as a programmable divider, you must re-time the signal using the original oscillator, and the re- timing flip-flop as well as the oscillator should be close to the adc, and powered with a very quiet supply. for cases where there are multiple adcs, or where the clock source originates some distance away, differential clock distribution is advisable. this is advisable both from the perspective of emi, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multi- layer pcbs. the differential pairs must be close together, and distanced from other signals. the differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.
LTC2224 21 2224fa applicatio s i for atio wu uu evaluation circuit schematic of the LTC2224 gnd gnd gnd v cc 2le 1le 2oe 1oe 1d1 1d2 1d3 1d4 1d5 1d6 1d7 1d8 2d1 2d2 2d3 2d4 2d5 2d6 2d7 2d8 gnd v cc gnd gnd v cc gnd gnd v cc 1q1 1q2 1q3 1q4 1q5 1q6 1q7 1q8 2q1 2q2 2q3 2q4 2q5 2q6 2q7 2q8 a in + a in refha refha gnd gnd reflb reflb refhb refhb refla refla v dd v dd v dd v dd v dd enc + enc shdn oe v cm sense mode clockout d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 of ov dd ov dd ov dd ov dd ognd ognd ognd ognd gnd gnd u1 LTC2224* 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 34 45 39 42 25 48 24 1 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 28 31 21 15 18 10 4 7 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 rn1d 33 ? rn1c 33 ? rn1b 33 ? rn1a 33 ? rn2d 33 ? rn2c 33 ? rn2b 33 ? rn2a 33 ? rn3d 33 ? rn3c 33 ? rn3b 33 ? rn3a 33 ? a0 a1 a2 a3 v cc wp scl sda 1 2 3 4 8 7 6 5 r10 10k r9 10k r8 10k c17 0.1 f c16 0.1 f c33 0.1 f v cc v cc nc7sv86p5x 4 4 5 1 2 1 2 3 5 3 v cc clockout clockout jp1 u3 u2 r3 33 ? d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 1 2 3 4 13 15 5 6 7 8 9 10 46 47 11 12 14 16 17 18 19 44 43 42 20 21 24 25 26 29 30 31 34 35 36 39 40 41 37 33 28 23 38 32 27 22 48 45 c13 0.1 f c12 0.1 f c10 0.1 f c11 33pf c15 2.2 f c7 2.2 f c6 0.1 f c9 0.1 f c5 1 f c8 1 f v cc c21 0.1 f c20 0.1 f c19 0.1 f c18 0.1 f c24 0.1 f c22 0.1 f v dd v dd v dd v cm ext ref v dd v cm ext ref r12 1k r13 1k r14 1k 2/3v dd 1/3v dd gnd jp4 mode jp3 sense clk clk v dd v dd shdn v dd gnd jp2 v cc c4 0.1 f c1 0.1 f c3 0.1 f r5 50 ? r2 24.9 ? r4 24.9 ? r6* r1* c2* v cm analog input t1* j1 r19 opt r17 105k c32 0.1 f c25 4.7 f c31 0.1 f c30 0.1 f c29 0.1 f v cc out adj gnd byp in gnd gnd shdn r18 100k 1 2 3 4 8 7 6 5 c26 0.1 f c23 0.1 f r15 100 ? r16 100 ? encode input clk clk t2 etc1-1t j3 v dd v dd 3.3v pwr gnd gnd c27 10 f 6.3v c28 0.01 f u6 lt1763 v cc v dd gnd 49 pi74vcx16373a 24lc025 3201s-40g1 nc7sv86p5x c34 1 f 2224 ai01 u4 u5 assembly type u1 r1, r6 c2 t1 dc751a-i LTC2224cuk 24.9 ? 12pf etc1-1t dc751a-j ltc2234cuk 24.9 ? 12pf etc1-1t dc751a-k LTC2224cuk 12.4 ? 8.2pf etc1-1-13 dc751a-l ltc2234cuk 12.4 ? 8.2pf etc1-1-13 *version type
LTC2224 22 2224fa applicatio s i for atio wu uu silkscreen top layer 1 component side layer 2 gnd plane layer 3 power plane layer 4 bottom side
LTC2224 23 2224fa package descriptio u 7.00 0.10 (4 sides) pin 1 top mark (see note 6) pin 1 chamfer 0.40 0.10 48 47 1 2 bottom view?xposed pad 5.15 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (uk48) qfn 1103 recommended solder pad pitch and dimensions 0.70 0.05 5.15 0.05 (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline note: 1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2224 24 2224fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 0106 rev a ? printed in usa related parts part number description comments ltc1748 14-bit, 80msps, 5v adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1750 14-bit, 80msps, 5v wideband adc up to 500mhz if undersampling, 90db sfdr lt1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain lt1994 low noise, low distortion fully differential low distortion: ?4dbc at 1mhz input/output amplifier/driver ltc2202 16-bit, 10msps, 3.3v adc, lowest noise 150mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 78db snr, 100db sfdr, 64-pin qfn ltc2220-1 12-bit, 185msps, 3.3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64-pin qfn ltc2222 12-bit, 105msps, 3.3v adc, high if sampling 475mw, 68.4db snr, 84db sfdr, 48-pin qfn ltc2222-11 11-bit, 105msps, 3.3v adc, high if sampling 475mw, 65.7db snr, 84db sfdr, 48-pin qfn ltc2223 12-bit, 80msps, 3.3v adc, high if sampling 366mw, 68.5db snr, 84db sfdr, 48-pin qfn LTC2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2232 10-bit, 105msps, 3.3v adc, high if sampling 475mw, 61.3db snr, 78db sfdr, 48-pin qfn ltc2233 10-bit, 80msps, 3.3v adc, high if sampling 366mw, 61.3db snr, 78db sfdr, 48-pin qfn ltc2234 10-bit, 135msps, 3.3v adc, high if sampling 630mw, 61.2db snr, 78db sfdr, 48-pin qfn ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if amplifier/adc driver with 450mhz 1db bw, 47db oip3, digital gain control digitally controlled gain 10.5db to 33db in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion high iip3: 20dbm at 1.9ghz, integrated lo quadrature generator quadrature demodulator lt5516 800mhz to 1.5ghz direct conversion high iip3: 21.5dbm at 900mhz, integrated lo quadrature generator quadrature demodulator lt5517 40mhz to 900mhz direct conversion high iip3: 21dbm at 800mhz, integrated lo quadrature generator quadrature demodulator lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 500 ? single-ended rf and lo ports

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