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| www..com PCI 9054 Data Book www..com www..com PCI 9054 Data Book Version 2.1 January 2000 Website: http://www.plxtech.com Email: apps@plxtech.com Phone: 408 774-9060 800 759-3735 FAX: 408 774-2169 www..com 2000 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products. PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. Other brands and names are the property of their respective owners. Order Number: 9054-SIL-DB-P1-2.1 Printed in the USA, January 2000 www..com Contents Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxviii 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2. Company and Product Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1. PCI 9054 I/O Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2. Data Pipe Architecture Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2.1. Dual DMA Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2.2. PCI Initiator (Direct Master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2.3. PCI Target (Direct Slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2.4. PCI Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3. PCI 9054 PCI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3.1. High Performance Motorola MPC850 or MPC860 PowerQUICC Designs . . . . . . . . . . . . . . . . . . . . 1.2.3.2. High Performance CompactPCI Adapter Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3.2.1. Hot Swap Capable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3.2.2. Hot Swap Friendly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3.3. PCI Bus Embedded Host Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4. PCI 9054 Major Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5. PCI 9054 Data Assignment Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5.1. PCI 9050/9080 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5.2. Pin Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5.3. Register Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6. PCI 9054, PCI 9080, and PCI 9050 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.7. PCI 9054 Signal Listing (M, C, or J Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-3 1-3 1-3 1-3 1-3 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-5 1-5 1-7 1-7 1-7 1-7 1-8 1-9 2. M Mode Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1. PCI Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1. PCI Target Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2. PCI Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2.1. DMA Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2.2. Direct Local-to-PCI Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3. PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2. Local Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1. Local Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2. PCI Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3. PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-1 2-1 2-1 2-1 2-2 2-2 2-2 2-2 2-2 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. v www..com Contents 2.2.4. Wait State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.4.1. Wait States--Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.4.2. Wait States--PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.5. Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode) . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.5.1. Burst and Bterm Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.5.2. Burst-4 Lword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.5.2.1. Continuous Burst Mode (Bterm "Burst Terminate" Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.5.3. Partial Lword Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.6. Local Bus Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.7. Local Bus Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.8. PCI Target Accesses to 8- or 16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.9. Local Bus Data Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.3. Big Endian/Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3.1. PCI Bus Little Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3.2. Local Bus Big/Little Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3.2.1. 32-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3.2.2. 16-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3.2.3. 8-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3.2.4. Local Bus Big/Little Endian Mode Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4. Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4.1. Vendor and Device ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4.1.1. Serial EEPROM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4.1.2. Local Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4.2. Serial EEPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4.2.1. Long Serial EEPROM Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.4.2.2. Extra Long Serial EEPROM Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.4.2.3. New Capabilities Function Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.4.2.4. Recommended Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.4.2.5. Serial EEPROM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.4.3. Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.4.3.1. PCI Bus Access to Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.4.3.2. Local Bus Access to Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.4.4. Serial EEPROM Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 3. M Mode Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1. Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1. PCI Bus Input RST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2. Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2. PCI 9054 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3. Response to FIFO Full or Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4. Direct Data Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1. PCI Initiator Operation (Local Master-to-PCI Target) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.1. PCI Initiator Memory and I/O Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.2. PCI Initiator FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.3. PCI Initiator Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.4. PCI Initiator I/O Configuration Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.5. PCI Initiator I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.6. RETRY# Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.6.1. PCI Initiator Write FIFO Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.6.2. PCI Initiator Delayed Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.7. PCI Initiator Configuration (PCI Configuration Type 0 or Type 1 Cycles) . . . . . . . . . . . . . . . . . . . . 3.4.1.7.1. PCI Initiator Configuration Cycle Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.8. PCI Initiator PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.9. PCI Initiator/Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.10. PCI Initiator Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-3 3-3 3-4 3-5 3-5 3-5 3-5 3-5 3-5 3-6 3-6 3-7 3-7 PCI 9054 Data Book v2.1 vi (c) PLX Technology, Inc. All rights reserved. www..com Contents 3.4.2. IDMA/SDMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.2.1. IDMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.2.2. SDMA Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.3. PCI Target Operation (PCI Master-to-Local Bus Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.3.1. PCI Target Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.3.2. PCI Target PCI v2.1 Delayed Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.3.3. PCI Target PCI Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.3.4. PCI Target Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.4.3.5. PCI Target PCI-to-Local Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.4.3.5.1. PCI Target Local Bus Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.4.3.5.2. PCI Target PCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.4.3.5.3. PCI Target Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.4.3.5.3.1. PCI Target Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.4.3.6. PCI Target Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.4.4. Deadlock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.4.4.1. Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.4.4.1.1. Software/Hardware Solution for Systems without Backoff Capability . . . . . . . . . . . . . . . . . . . 3-16 3.4.4.1.2. Preempt Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.4.4.2. Software Solutions to Deadlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.5. DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.5.1. DMA PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.5.2. Block DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.5.2.1. Block DMA PCI Dual Address Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.5.3. Scatter/Gather DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.5.3.1. Scatter/Gather DMA PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.5.3.2. DMA Clear Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.5.4. DMA Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.5.4.1. DMA Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.5.5. DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.5.6. DMA Channel 0/1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.5.7. DMA Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.5.7.1. Local-to-PCI Bus DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.5.7.2. PCI-to-Local Bus DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.5.7.3. DMA Local Bus Error Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.5.7.4. DMA Unaligned Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.5.8. Demand Mode DMA, Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.5.9. End of Transfer (EOT#) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.5.10. DMA Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.5.11. Local Bus Latency and Pause Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.6. M Mode Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.6.1. M Mode PCI Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.6.2. M Mode PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 3.6.3. M Mode DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 4. C and J Modes Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1. PCI Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1. PCI Target Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2. PCI Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2.1. DMA Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2.2. Direct Local-to-PCI Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3. PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2. Local Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1. Local Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2. PCI Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3. PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-1 4-1 4-1 4-1 4-2 4-2 4-2 4-2 4-2 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. vii www..com Contents 4.2.4. Wait State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.4.1. Wait States--Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.4.2. Wait States--PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.5. Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode) . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.5.1. Burst and Bterm Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.5.2. Burst-4 Lword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.5.2.1. Continuous Burst Mode (Bterm "Burst Terminate" Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.5.3. Partial Lword Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.6. Recovery States (J Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.7. Local Bus Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.8. Local Bus Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.9. PCI Target Accesses to 8- or 16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.10. Local Bus Data Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3. Big Endian/Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.1. PCI Bus Little Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.2. Local Bus Big/Little Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.2.1. 32-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.2.2. 16-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.2.3. 8-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.2.4. Local Bus Big/Little Endian Mode Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4. Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.1. Vendor and Device ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.1.1. Serial EEPROM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.1.2. Local Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.2. Serial EEPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.2.1. Long Serial EEPROM Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.4.2.2. Extra Long Serial EEPROM Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.4.2.3. New Capabilities Function Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.4.2.4. Recommended Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.4.2.5. Serial EEPROM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.4.3. Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.4.3.1. PCI Bus Access to Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4.3.2. Local Bus Access to Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4.4. Serial EEPROM Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 5. C and J Modes Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1. Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1. PCI Bus Input RST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2. Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2. PCI 9054 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3. Response to FIFO Full or Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4. Direct Data Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1. PCI Initiator Operation (Local Master-to-PCI Target) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1.1. PCI Initiator Memory and I/O Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1.2. PCI Initiator FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1.3. PCI Initiator Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1.4. PCI Initiator I/O Configuration Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1.5. PCI Initiator I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1.6. PCI Initiator Configuration (PCI Configuration Type 0 or Type 1 Cycles) . . . . . . . . . . . . . . . . . . . . 5.4.1.6.1. PCI Initiator Configuration Cycle Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1.7. PCI Initiator PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1.8. PCI Initiator/Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1.9. PCI Initiator Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2. PCI Target Operation (PCI Master-to-Local Bus Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2.1. PCI Target Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2.2. PCI Target PCI v2.1 Delayed Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2.3. PCI Target PCI Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-1 5-1 5-1 5-1 5-1 5-1 5-4 5-4 5-4 5-5 5-5 5-5 5-6 5-6 5-6 5-8 5-8 5-9 5-9 5-9 PCI 9054 Data Book v2.1 viii (c) PLX Technology, Inc. All rights reserved. www..com Contents 5.4.2.4. PCI Target Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.4.2.5. PCI Target PCI-to-Local Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4.2.5.1. PCI Target Local Bus Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4.2.5.2. PCI Target PCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4.2.5.3. PCI Target Byte Enables (C Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.4.2.5.4. PCI Target Byte Enables (J Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.4.2.5.4.1. PCI Target Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.4.2.6. PCI Target Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.3. Deadlock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.3.1. Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.3.1.1. Software/Hardware Solution for Systems without Backoff Capability . . . . . . . . . . . . . . . . . . . 5-14 5.4.3.1.2. Preempt Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.4.3.2. Software Solutions to Deadlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.5. DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.5.1. DMA PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.5.2. Block DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.5.2.1. Block DMA PCI Dual Address Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.5.3. Scatter/Gather DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.5.3.1. Scatter/Gather DMA PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.5.3.2. DMA Clear Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.5.4. DMA Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.5.4.1. DMA Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.5.5. DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.5.6. DMA Channel 0/1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.5.7. DMA Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.5.7.1. Local-to-PCI Bus DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.5.7.2. PCI-to-Local Bus DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.5.7.3. DMA Unaligned Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.5.8. Demand Mode DMA, Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.5.9. End of Transfer (EOT#) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.5.10. DMA Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.5.11. Local Bus Latency and Pause Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.6. C Mode Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.6.1. C Mode PCI Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.6.2. C Mode PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 5.6.3. C Mode DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63 5.7. J Mode Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73 5.7.1. J Mode PCI Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73 5.7.2. J Mode PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77 5.7.3. J Mode DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81 6. PCI Local Interrupts and User I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1. Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1. PCI Interrupts (INTA#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2. Local Interrupt Input (LINT#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3. Local Interrupt Output (LINT#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.4. Master/Target Abort Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.5. Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6. Doorbell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6.1. Local-to-PCI Doorbell Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6.1.1. M Mode Local-to-PCI Doorbell Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6.1.2. C and J Modes Local-to-PCI Doorbell Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6.2. PCI-to-Local Doorbell Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.7. Built-In Self Test Interrupt (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.8. DMA Channel 0/1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.9. All Modes PCI SERR# (PCI NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.10. M Mode PCI SERR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6-1 6-1 6-2 6-2 6-2 6-2 6-3 6-3 6-3 6-3 6-3 6-3 6-4 6-4 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. ix www..com Contents 6.1.11. Local NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.12. M Mode Local TEA# (Local NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.13. C and J Modes Local LSERR# (Local NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2. User Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6-4 6-4 6-5 7. Intelligent I/O (I2O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1. I2O-Compatible Message Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1. Inbound Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2. Outbound Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3. I2O Pointer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.4. Inbound Free List FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.5. Inbound Post Queue FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.6. Outbound Post Queue FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.7. Outbound Post Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.8. Inbound Free Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.9. Outbound Free List FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.10. I2O Enable Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-1 7-1 7-2 7-2 7-3 7-3 7-5 7-5 7-5 7-5 8. PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1. PCI Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2. System Changes Power Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3. Wake-Up Request Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-1 8-2 8-2 9. CompactPCI Hot Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1. Hot Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2. Controlling Connection Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2.1. Hardware Connection Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2.1.1. Board Slot Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2.1.2. Board Healthy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2.1.3. Platform Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2.2. Software Connection Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2.2.1. Ejector Switch and Blue LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2.2.2. ENUM# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2.2.3. Hot Swap Control/Status Register (HS_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2.2.4. Hot Swap Capabilities Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9-1 9-1 9-1 9-2 9-2 9-2 9-3 9-3 9-3 9-3 9-4 10. PCI Vital Product Data (VPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1. VPD Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2. VPD Serial EEPROM Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3. Sequential Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.4. Random Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10-1 10-1 10-1 10-2 PCI 9054 Data Book v2.1 x (c) PLX Technology, Inc. All rights reserved. www..com Contents 11. Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1. New Register Definitions Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2. Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.1. PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.2. Local Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.3. Runtime Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.4. DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.5. Messaging Queue Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3. PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.4. Local Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11.5. Runtime Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11.6. DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34 11.7. Messaging Queue Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40 12. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2. Pinout Common to All Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.3. M Bus Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.4. C Bus Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12.5. J Bus Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12.6. NANDTREE Test Access Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 13. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1. General Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2. Local Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3. Local Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 14. Package, Signal, and Pinout Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1. 176-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2. 225-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 A. General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1. Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.2. United States and International Representatives, and Distributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.3. Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index-1 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. xi www..com PCI 9054 Data Book v2.1 xii (c) PLX Technology, Inc. All rights reserved. www..com Figures 1-1. Typical Adapter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2. PCI 9054 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-3. High-Performance MPC850 or MPC860 PowerQUICC Adapter Design . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1-4. High-Performance CompactPCI Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1-5. High-Performance Embedded Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 2-1. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-2. Big/Little Endian--32-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-3. Big/Little Endian--16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-4. Big/Little Endian--8-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-5. Serial EEPROM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-6. PCI 9054 Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-7. Address Decode Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 3-1. PCI Initiator Access of the PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-2. PCI Initiator Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-3. PCI Initiator Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-4. Block DMA Mode Initialization (Single Address or Dual Address PCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-5. Dual Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3-6. PCI Target PCI v2.1 Delayed Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-7. PCI Target PCI 9054 Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-8. PCI Target Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3-9. PCI Target Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3-10. Local Bus PCI Target Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3-11. DMA, PCI-to-Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3-12. DMA, Local-to-PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3-13. Dual Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3-14. Scatter/Gather DMA Mode from PCI-to-Local Bus (Control Access from the Local Bus) . . . . . . . . . 3-19 3-15. Scatter/Gather DMA Mode from Local-to-PCI Bus (Control Access from the PCI Bus) . . . . . . . . . . . 3-19 3-16. Scatter/Gather DMA Mode Descriptor Initialization [PCI SAC/DAC PCI Address (DMADAC0, DMADAC1) Register Dependent] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3-17. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address (DMAMODE0[18], DMAMODE1[18]) Descriptor Dependent (PCI Address High Added) . . . . . . . . 3-21 3-18. Local-to-PCI Bus DMA Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3-19. PCI-to-Local Bus DMA Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 4-1. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4-2. Big/Little Endian--32-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-3. Big/Little Endian--16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-4. Big/Little Endian--8-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-5. Serial EEPROM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4-6. PCI 9054 Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4-7. Address Decode Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 5-1. PCI Initiator Access of the PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5-2. PCI Initiator Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-3. PCI Initiator Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-4. Block DMA Mode Initialization (Single Address or Dual Address PCI) . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5-5. Dual Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. xiii www..com Figures 5-6. PCI Target PCI v2.1 Delayed Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5-7. PCI Target PCI 9054 Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5-8. PCI Target Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5-9. PCI Target Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5-10. Local Bus PCI Target Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5-11. DMA, PCI-to-Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5-12. DMA, Local-to-PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5-13. Dual Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5-14. Scatter/Gather DMA Mode from PCI-to-Local Bus (Control Access from the Local Bus) . . . . . . . . . 5-17 5-15. Scatter/Gather DMA Mode from Local-to-PCI Bus (Control Access from the PCI Bus) . . . . . . . . . . . 5-17 5-16. Scatter/Gather DMA Mode Descriptor Initialization [PCI SAC/DAC PCI Address (DMADAC0, DMADAC1) Register Dependent] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5-17. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address (DMAMODE0[18], DMAMODE1[18]) Descriptor Dependent] (PCI Address High Added) . . . . . . . 5-19 5-18. Local-to-PCI Bus DMA Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5-19. PCI-to-Local Bus DMA Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 6-1. Interrupt and Error Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6-2. Mailbox and Doorbell Message Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 7-1. Typical I2O Server/Adapter Card Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-2. Driver Architecture Compared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-3. Circular FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 9-1. Redirection of BD_SEL# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9-2. Board Healthy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9-3. PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9-4. Hot Swap Capabilities Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 10-1. VPD Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 13-1. PCI 9054 Local Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13-2. PCI 9054 Local Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13-3. PCI 9054 ALE Output Delay to the Local Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 14-1. 176-Pin PQFP Package Mechanical Dimensions--Topside and Cross-Section Views . . . . . . . . . . . 14-1 14-2. 176-Pin PQFP PCB Layout Suggested Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14-3. 176-Pin PQFP PCI 9054 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14-4. 225-Pin PBGA Package Mechanical Dimensions--Topside, Underside, and Cross-Section Views . 14-4 14-5. 225-Pin PBGA PCB Layout Suggested Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14-6. 225-Pin PBGA Package Layout (Underside View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 PCI 9054 Data Book v2.1 xiv (c) PLX Technology, Inc. All rights reserved. www..com Tables 1-1. FIFO Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1-2. Programmable Local Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1-3. PCI 9054 Data Assignment Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1-4. Comparison of PCI 9054, PCI 9080, and PCI 9050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1-5. PCI 9054 PCI Signal Listing (M, C, or J Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1-6. PCI 9054 Local Signal Listing (M, C, or J Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 2-1. PCI Target Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2. DMA Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-3. Local-to-PCI Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-4. Local-to-PCI I/O Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-5. Local-to-PCI Configuration Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-6. Local Bus Types (176-Pin PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-7. Local Bus Types (225-Pin PBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-8. Burst and Bterm on the Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-9. Burst-4 Lword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-10. PCI Bus Little Endian Byte Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-11. Byte Number and Lane Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-12. Big/Little Endian Program Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-13. Cycles Reference Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-14. Upper Lword Lane Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-15. Upper Word Lane Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-16. Lower Word Lane Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-17. Upper Byte Lane Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-18. Lower Byte Lane Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-19. Serial EEPROM Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2-20. Long Serial EEPROM Load Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2-21. Extra Long Serial EEPROM Load Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2-22. New Capabilities Function Support Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 3-1. Response to FIFO Full or Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2. PCI Target Burst Mode Cycle Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3-3. Data Bus TSIZ[0:1] Contents for Single Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-4. Data Bus TSIZ[0:1] Requirements for Single Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-5. DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3-6. Normal DMA with EOT Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3-7. Demand Mode DMA, Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3-8. Any DMA Transfer Channel 0/1 with EOT Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 4-1. PCI Target Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-2. DMA Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-3. Local-to-PCI Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-4. Local-to-PCI I/O Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-5. Local-to-PCI Configuration Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-6. Local Bus Types (176-Pin PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-7. Local Bus Types (225-Pin PBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-8. Burst and Bterm on the Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. xv www..com Tables 4-9. Burst-4 Lword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-10. PCI Bus Little Endian Byte Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-11. Byte Number and Lane Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-12. Big/Little Endian Program Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-13. Cycles Reference Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-14. Upper Lword Lane Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-15. Upper Word Lane Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-16. Lower Word Lane Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-17. Upper Byte Lane Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-18. Lower Byte Lane Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-19. Serial EEPROM Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4-20. Long Serial EEPROM Load Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4-21. Extra Long Serial EEPROM Load Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4-22. New Capabilities Function Support Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 5-1. Response to FIFO Full or Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5-2. DMA Local Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 7-1. Queue Starting Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7-2. Circular FIFO Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 9-1. Hot Swap Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 11-1. New Registers Definitions Summary (As Compared to the PCI 9080) . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11-2. PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11-3. Local Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11-4. Runtime Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11-5. DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11-6. Messaging Queue Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 12-1. Pin Type Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-2. Power and Ground Pins (176-Pin PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12-3. Power and Ground Pins (225-Pin PBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12-4. Serial EEPROM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12-5. PCI System Bus Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12-6. Local Bus Mode and Processor Independent Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12-7. M Bus Mode Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12-8. C Bus Mode Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12-9. J Bus Mode Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 . . . . . . . . . . . . . . . . . . 12-16 12-10. Sequential Interconnection of the PCI 9054 NANDTREE (Pin Definition) 13-1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-2. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-3. Capacitance (Sample Tested Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-4. Thermal Resistance of Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-5. Electrical Characteristics over Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13-6. AC Electrical Characteristics (Local Inputs) over Operating Range (M Mode) . . . . . . . . . . . . . . . . . . 13-3 13-7. AC Electrical Characteristics (Local Inputs) over Operating Range (C and J Modes) . . . . . . . . . . . . 13-4 13-8. AC Electrical Characteristics (Local Outputs) over Operating Range (M Mode) . . . . . . . . . . . . . . . . 13-5 13-9. AC Electrical Characteristics (Local Outputs) over Operating Range (C and J Modes) . . . . . . . . . . . 13-6 PCI 9054 Data Book v2.1 xvi (c) PLX Technology, Inc. All rights reserved. www..com Tables 14-1. 176-Pin PQFP Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14-2. 225-Pin PBGA Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14-3. 225-Pin PBGA PCI 9054 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 A-1. Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. xvii www..com PCI 9054 Data Book v2.1 xviii (c) PLX Technology, Inc. All rights reserved. www..com Registers 11-1. (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11-2. (PCICR; PCI:04h, LOC:04h) PCI Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11-3. (PCISR; PCI:06h, LOC:06h) PCI Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11-4. (PCIREV; PCI:08h, LOC:08h) PCI Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11-5. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11-6. (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11-7. (PCILTR; PCI:0Dh, LOC:0Dh) PCI Bus Latency Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11-8. (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11-9. (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11-10. (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to Local, Runtime, and DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11-11. (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local, Runtime, and DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11-12. (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to Local Address Space 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11-13. (PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses to Local Address Space 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11-14. (PCIBAR4; PCI:20h, LOC:20h) PCI Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11-15. (PCIBAR5; PCI:24h, LOC:24h) PCI Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11-16. (PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11-17. (PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11-18. (PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11-19. (PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11-20. (CAP_PTR; PCI:34h, LOC:34h) New Capability Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-21. (PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-22. (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-23. (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-24. (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-25. (PMCAPID; PCI:40h, LOC:180h) Power Management Capability ID . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-26. (PMNEXT; PCI:41h, LOC:181h) Power Management Next Capability Pointer . . . . . . . . . . . . . . . 11-15 11-27. (PMC; PCI:42h, LOC:182h) Power Management Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11-28. (PMCSR; PCI:44h, LOC:184h) Power Management Control/Status . . . . . . . . . . . . . . . . . . . . . . . 11-16 11-29. (PMCSR_BSE; PCI:46h, LOC:186h) PMCSR Bridge Support Extensions . . . . . . . . . . . . . . . . . . 11-16 11-30. (PMDATA; PCI:47h, LOC:187h) Power Management Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11-31. (HS_CNTL; PCI:48h, LOC:188h) Hot Swap Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11-32. (HS_NEXT; PCI:49h, LOC:189h) Hot Swap Next Capability Pointer . . . . . . . . . . . . . . . . . . . . . . . 11-17 11-33. (HS_CSR; PCI:4Ah, LOC:18Ah) Hot Swap Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11-34. (PVPDCNTL; PCI:4Ch, LOC:18Ch) PCI Vital Product Data Control . . . . . . . . . . . . . . . . . . . . . . . 11-18 11-35. (PVPD_NEXT; PCI:4Dh, LOC:18Dh) PCI Vital Product Data Next Capability Pointer. . . . . . . . . . 11-18 11-36. (PVPDAD; PCI:4Eh, LOC:18Eh) PCI Vital Product Data Address . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11-37. (PVPDATA; PCI:50h, LOC:190h) PCI VPD Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11-38. (LAS0RR; PCI:00h, LOC:80h) Local Address Space 0 Range Register for PCI-to-Local Bus . . . 11-19 11-39. (LAS0BA; PCI:04h, LOC:84h) Local Address Space 0 Local Base Address (Remap) . . . . . . . . . 11-19 11-40. (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/DMA Arbitration. . . . . . . . . . . . . . . . . . . . . . 11-20 11-41. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11-42. (LMISC; PCI:0Dh, LOC:8Dh) Local Miscellaneous Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. xix www..com Registers 11-43. (PROT_AREA; PCI:0Eh, LOC:8Eh) Serial EEPROM Write-Protected Address Boundary . . . . . . 11-22 11-44. (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11-45. (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) and BREQo Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11-46. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor . . 11-24 11-47. (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for PCI Initiator-to-PCI . . . . . . . . . . . . . . . . . 11-25 11-48. (DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for PCI Initiator-to-PCI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11-49. (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for PCI Initiator-to-PCI I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11-50. (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for PCI Initiator-to-PCI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11-51. (DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11-52. (LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI-to-Local Bus . . 11-27 11-53. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap) . . . . . . . . 11-28 11-54. (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor . . . . . . . . . . . . . . . 11-28 11-55. (DMDAC; PCI:FCh, LOC:17Ch) PCI Initiator PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . 11-28 11-56. (MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11-57. (MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11-58. (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11-59. (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11-60. (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11-61. (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11-62. (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11-63. (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 11-64. (P2LDBELL; PCI:60h, LOC:E0h) PCI-to-Local Doorbell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 11-65. (L2PDBELL; PCI:64h, LOC:E4h) Local-to-PCI Doorbell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 11-66. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11-67. (CNTRL; PCI:6Ch, LOC:ECh) Serial EEPROM Control, PCI Command Codes, User I/O Control, and Init Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11-68. (PCIHIDR; PCI:70h, LOC:F0h) PCI Hardcoded Configuration ID . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11-69. (PCIHREV; PCI:74h, LOC:F4h) PCI Hardcoded Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11-70. (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34 11-71. (DMAPADR0; PCI:84h, LOC:104h) DMA Channel 0 PCI Address . . . . . . . . . . . . . . . . . . . . . . . . 11-35 11-72. (DMALADR0; PCI:88h, LOC:108h) DMA Channel 0 Local Address . . . . . . . . . . . . . . . . . . . . . . . 11-35 11-73. (DMASIZ0; PCI:8Ch, LOC:10Ch) DMA Channel 0 Transfer Size (Bytes) . . . . . . . . . . . . . . . . . . . 11-35 11-74. (DMADPR0; PCI:90h, LOC:110h) DMA Channel 0 Descriptor Pointer . . . . . . . . . . . . . . . . . . . . . 11-35 11-75. (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 11-76. (DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address . . . . . . . . . . . . . . . . . . . . . . . . 11-37 11-77. (DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address . . . . . . . . . . . . . . . . . . . . . . . 11-37 11-78. (DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes). . . . . . . . . . . . . . . . . . . . 11-37 11-79. (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer . . . . . . . . . . . . . . . . . . . . . 11-37 11-80. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status. . . . . . . . . . . . . . . . . . . . . . 11-38 11-81. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status. . . . . . . . . . . . . . . . . . . . . . 11-38 11-82. (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 11-83. (DMATHR; PCI:B0h, LOC:130h) DMA Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 11-84. (DMADAC0; PCI:B4h, LOC:134h) DMA Channel 0 PCI Dual Address Cycle Address Register . . 11-39 PCI 9054 Data Book v2.1 xx (c) PLX Technology, Inc. All rights reserved. www..com Registers 11-85. (DMADAC1; PCI:B8h, LOC:138h) DMA Channel 1 PCI Dual Address Cycle Address . . . . . . . . . 11-39 11-86. (OPQIS; PCI:30h, LOC:B0h) Outbound Post Queue Interrupt Status . . . . . . . . . . . . . . . . . . . . . . 11-40 11-87. (OPQIM; PCI:34h, LOC:B4h) Outbound Post Queue Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . 11-40 11-88. (IQP; PCI:40h) Inbound Queue Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40 11-89. (OQP; PCI:44h) Outbound Queue Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40 11-90. (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 11-91. (QBAR; PCI:C4h, LOC:144h) Queue Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 11-92. (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 11-93. (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 11-94. (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11-95. (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11-96. (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11-97. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11-98. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11-99. (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 11-100. (QSR; PCI:E8h, LOC:168h) Queue Status/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. xxi www..com PCI 9054 Data Book v2.1 xxii (c) PLX Technology, Inc. All rights reserved. www..com Timing Diagrams 2-1. Initialization from Serial EEPROM (2K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2-2. Initialization from Serial EEPROM (4K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2-3. PCI Configuration Write to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2-4. PCI Configuration Read to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2-5. PCI Memory Write to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2-6. PCI Memory Read to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2-7. Local Interrupt Asserting PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 3-1. Local Bus Arbitration (BR#, BG#, BB#, and so forth) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3-2. PCI Initiator Single Write Cycle, Zero Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3-3. PCI Initiator Single Read Cycle, One Wait State (WAIT# Asserted for One Clock) . . . . . . . . . . . . . . 3-28 3-4. PCI Initiator Burst Write Cycle of Four Lwords, Zero Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3-5. PCI Initiator Burst Read Cycle of Four Lwords, Zero Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 3-6. PCI Initiator Deferred Read Mode (RETRY#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3-7. PCI Initiator Burst Read with Read Ahead Mode (Prefetch Counter Set to Eight Lwords) . . . . . . . . . 3-32 3-8. Local Configuration Write to Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3-9. Local Configuration Read from Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3-10. PCI Initiator Burst Write of Six Lwords beyond MPC860 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3-11. PCI Initiator Burst Read of Six Lwords beyond MPC860 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 3-12. PCI Target Single Write Cycle, Zero Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 3-13. PCI Target Single Write Cycle, One Wait State by Delaying TA# . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 3-14. Local Bus Single Write Cycle, Zero Wait States, Burst Enabled, 16-Bit Local Bus . . . . . . . . . . . . . . 3-38 3-15. Local Bus Single Write Cycle, One Wait State, Burst Disabled, 8-Bit Local Bus . . . . . . . . . . . . . . . . 3-39 3-16. PCI Target Single Read Cycle, Zero Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 3-17. PCI Target Single Read Cycle, One Wait State Using TA# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 3-18. PCI Target Single Read Cycle, Zero Wait States, 16-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 3-19. PCI Target Single Read Cycle, One Wait State, Burst Disabled, 8-Bit Local Bus . . . . . . . . . . . . . . . 3-43 3-20. PCI Target Burst Write Cycle of Four Lwords, Bterm Disabled, Burst Enabled . . . . . . . . . . . . . . . . . 3-43 3-21. PCI Target Burst Read Cycle of Four Lwords, Bterm Disabled, Burst Enabled . . . . . . . . . . . . . . . . . 3-44 3-22. PCI Target Burst Write Cycle of Eight Lwords, Bterm Disabled, Burst Enabled . . . . . . . . . . . . . . . . . 3-44 3-23. PCI Target Burst Read Cycle of Eight Lwords, Bterm Disabled, Burst Enabled . . . . . . . . . . . . . . . . 3-45 3-24. PCI Target Burst Write Cycle of 10 Lwords, Zero Wait States beyond MPC860 Protocol, Bterm Enabled, Burst Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 3-25. PCI Target Burst Read Cycle of 10 Lwords, Zero Wait States beyond MPC860 Protocol, Bterm Enabled, Burst Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3-26. Initialization from Serial EEPROM (2K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3-27. Initialization from Serial EEPROM (4K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 3-28. PCI Configuration Write to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 3-29. PCI Configuration Read to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 3-30. PCI Memory Write to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 3-31. PCI Memory Read to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 3-32. Local Interrupt Asserting PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 3-33. Master Abort Condition During PCI Initiator Read Cycle Causes TEA# . . . . . . . . . . . . . . . . . . . . . . . 3-51 3-34. DMA PCI-to-Local, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords . . . . . . . . . . . . . . 3-52 3-35. DMA Local-to-PCI, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords . . . . . . . . . . . . . . 3-53 3-36. DMA Local-to-PCI, Address Unaligned, Bterm Disabled, Burst Enabled, PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. xxiii www..com Timing Diagrams Transfer Size = Six Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54 3-37. DMA PCI-to-Local, Address Unaligned, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 3-38. DMA Local-to-PCI, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts in the Middle of the Quad-Lword of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56 3-39. DMA Local-to-PCI, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at the Last Data of the First Quad-Lword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 3-40. DMA PCI-to-Local, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts in the Middle of the First Quad-Lword of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58 3-41. DMA PCI-to-Local, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at the Last Data of the First Quad-Lword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59 3-42. DMA Local-to-PCI, Bterm Enabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at End of Third Local Data beyond MPC860 Protocol . . . . . . . . . . . . . . . . . . . . . . . 3-60 3-43. DMA PCI-to-Local, Bterm Enabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at End of Third Local Data beyond MPC860 Protocol . . . . . . . . . . . . . . . . . . . . . . . 3-61 3-44. Local Bus Latency Timer (Eight Clocks) and Pause Timer (Four Clocks) in DMA Operation . . . . . . 3-62 3-45. Local Bus Latency Timer (Eight Clocks) and Pause Timer (Four Clocks) in DMA Operation beyond MPC860 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62 3-46. DMA PCI-to-Local, Bterm Enabled, Burst Enabled, Transfer Size = 10 Lwords, beyond MPC860 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63 3-47. DMA Local-to-PCI, Bterm Enabled, Burst Enabled, Transfer Size = 10 Lwords, beyond MPC860 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64 3-48. IDMA Single Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 4-1. Initialization from Serial EEPROM (2K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4-2. Initialization from Serial EEPROM (4K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4-3. PCI Configuration Write to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4-4. PCI Configuration Read to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4-5. PCI Memory Write to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4-6. PCI Memory Read to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4-7. Local Interrupt Asserting PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 5-1. Local Bus Arbitration (LHOLD and LHOLDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5-2. PCI Initiator Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5-3. PCI Initiator Single Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5-4. PCI Initiator Memory Write of 12 Lwords with WAIT# Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5-5. PCI Initiator Burst Read of Seven Lwords with WAIT# Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5-6. PCI Initiator Memory Read of 12 Lwords with Prefetch Counter Set to 16 . . . . . . . . . . . . . . . . . . . . . . 5-29 5-7. Memory Write and Invalidate with Cache Line Size of Eight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5-8. PCI Initiator Memory Read with Keep Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5-9. PCI Initiator Memory Read with Drop Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5-10. PCI Bus Request (REQ#) Delay During Direct Master Write (Eight-PCI Clock Delay) . . . . . . . . . . . 5-33 5-11. PCI Initiator Locked Read Followed by Write and Release (LLOCK# and LOCK#) . . . . . . . . . . . . . . 5-34 5-12. BREQo and Deadlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 5-13. Local Bus Write to Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5-14. Local Bus Read to Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5-15. PCI Initiator Configuration Read--Type 1 or Type 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5-16. PCI Initiator Configuration Write--Type 1 or Type 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 5-17. Initialization from Serial EEPROM (2K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 5-18. Initialization from Serial EEPROM (4K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 5-19. PCI Configuration Write to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 PCI 9054 Data Book v2.1 xxiv (c) PLX Technology, Inc. All rights reserved. www..com Timing Diagrams 5-20. PCI Configuration Read to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 5-21. PCI Memory Write to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 5-22. PCI Memory Read to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 5-23. Local Interrupt Asserting PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 5-24. PCI Target Single Write (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 5-25. PCI Target Burst Cycle Write (16-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 5-26. PCI Target Burst Cycle Write (8-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 5-27. PCI Target Single-Cycle Read (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 5-28. PCI Target Single Read with One Wait State Using READY# Input (32-Bit Local Bus) . . . . . . . . . . . 5-47 5-29. PCI Target Single Read with One Wait State Using Internal Wait State (32-Bit Local Bus) . . . . . . . . 5-48 5-30. PCI Target Non-Burst Write (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 5-31. PCI Target Non-Burst Write (8-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 5-32. PCI Target Non-Burst Local Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 5-33. PCI Target Burst Write with Bterm Enabled (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 5-34. PCI Target Burst Write with Bterm Disabled (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 5-35. PCI Target Burst Read with Prefetch Counter Set to 8 (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . 5-54 5-36. PCI Target Burst Read with Prefetch Counter Set to 5 (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . 5-55 5-37. PCI Target Burst Write (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56 5-38. PCI Target Burst Write (16-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 5-39. PCI Target Burst Write with External Wait States (8-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 5-40. Delayed Read Transaction PCI Specification v2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-58 5-41. PCI Target Read No Flush Mode (Read Ahead Mode), Prefetch Enabled, Prefetch Count Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59 5-42. PCI Target Burst Write Suspended by BREQi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60 5-43. Locked PCI Target Read Followed by Write and Release (LLOCKo#) . . . . . . . . . . . . . . . . . . . . . . . 5-61 5-44. PCI Target in BIGEND Local Bus with BIGEND# Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 5-45. DMA Aligned PCI Address to Aligned Local Address, Bterm Enabled, Burst Enabled . . . . . . . . . . . 5-63 5-46. DMA Aligned PCI Address to Aligned Local Address, Bterm Disabled, Burst Enabled . . . . . . . . . . . 5-64 5-47. Scatter/Gather DMA with Descriptor on Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 5-48. Scatter/Gather DMA from Local-to-PCI with Descriptor on PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . 5-66 5-49. Demand DMA, Terminate with BLAST# (Local-to-PCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 5-50. DMA Local-to-PCI, Terminate with EOT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 5-51. DMA PCI-to-Local, Terminate with EOT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 5-52. DMA PCI-to-Local with Local Bus Pause and Latency Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70 5-53. Single-Cycle Demand DMA Mode (PCI-to-Local) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71 5-54. Multiple-Cycle Demand DMA Mode (PCI-to-Local) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72 5-55. PCI Initiator Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73 5-56. PCI Initiator Single Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74 5-57. PCI Initiator Burst Write of 10 Lwords, Zero Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75 5-58. PCI Initiator Burst Read of 10 Lwords, Zero Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-76 5-59. PCI Target Single Write (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77 5-60. PCI Target Single Read (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78 5-61. PCI Target Burst Write with Bterm Enabled (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79 5-62. PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus), Prefetech Counter Set to 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80 5-63. DMA Aligned PCI Address to Aligned Local Address, Bterm Enabled, Burst Enabled . . . . . . . . . . . 5-81 5-64. DMA Aligned Local Address to Aligned PCI Address, Bterm Enabled, Burst Enabled . . . . . . . . . . . 5-82 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. xxv www..com PCI 9054 Data Book v2.1 xxvi (c) PLX Technology, Inc. All rights reserved. www..com PREFACE The information contained in this document is subject to change without notice. Although an effort has been made to keep the information accurate, there may be misleading or even incorrect statements made herein. The following is a list of additional documentation to provide the reader with more information about the PCI 9054 and related subjects: * PCI Local Bus Specification, Revision 2.1 PCI Special Interest Group 2575 NE Kathryn #17, Hillsboro, OR, 97124, USA Tel: 800 433-5177 (domestic only) or 503 693-6232, Fax: 503 693-8344, http://www.pcisig.com * PCI Hot-Plug Specification, Revision 1.0 PCI Special Interest Group 2575 NE Kathryn #17, Hillsboro, OR, 97124, USA Tel: 800 433-5177 (domestic only) or 503 693-6232, Fax: 503 693-8344, http://www.pcisig.com * PCI Power Management Interface Specification, Revision 1.0, June 30, 1997 PCI Special Interest Group 2575 NE Kathryn #17, Hillsboro, OR, 97124, USA Tel: 800 433-5177 (domestic only) or 503 693-6232, Fax: 503 693-8344, http://www.pcisig.com * PICMG 2.1 R1.0 CompactPCI(R) Hot Swap Specification PCI Industrial Computer Manufacturers Group (PICMG) c/o Rogers Communications, 401 Edgewater Place, Suite 500, Wakefield, MA 01880, USA Tel: 781 246-9318, Fax: 781 224-1239, http://www.picmg.org * Intelligent I/O (I2O) Architecture Specification Revision 1.5 I2O Special Interest Group 404 Balboa Street, San Francisco, CA, 94118, USA Tel: 415 750-8352, Fax: 415 751-4829, http://www.i2osig.org PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. xxvii www..com Revision History REVISION HISTORY Date 09/16/1997 01/21/1998 Revision 0.30 0.90 Comments Revised version 0.2 Red Book to include PCI 9054 special functions. Added special functions: Power Management, Vital Product Data (VPD), and CompactPCI Hot Swap functionality; PCI Hot Plug; MPC850 or MPC860 Operation mode; 176-pin PQFP and 225-pin PBGA pinouts. Portions of the CompactPCI Specification used for the CompactPCI Hot Swap section. Incorporated changes from January and February review meetings. Incorporated engineering feedback and PCI 9054 flier text. Updated Local timing specifications. Changed title to "data book" and removed references to inches in Tables 14-1 and 14-2. Added serial EEPROM information to Table 1-4. Added information to BB# description in Tables 1-5 and 12-7. Changed TA# information for PCI Target and DMA modes in Section 2.2.4.1. Added cross-references to other sections for Bust Forever mode in Tables 2-8 and 2-9. Added burst information to Section 2.2.5.1. Added VPD information relating to long serial EEPROM loads to Section 2.4.2.1. Added "Register Bits Affected" information to Tables 2-20 and 2-21. Added port size information to Table 3-3. Changed DMA PCI DAC information in Section 3-5.1. Added Section 5.5.2.1, "Block DMA PCI Dual Address Cycle." Added Section 5.5.3.1, "Scatter/Gather DMA PCI Dual Address Cycle." Changed captions for Figures 1-3, 5/16, and 5-17. Added recommendation to not assert EOT# during a descriptor load on the Local Bus to Sections 3.5.9 and 5.5.9. Clarified INTCSR[11]=0 information in Section 6.1.3. Added further VPD information to Section 10 (specifically 10.1 and 10.14). Changed PCIBAR register information and corrected the serial EEPROM information for 3Ch in Table 11-2. Changed the PCI:0Ch and LOC:8Ch information in Table 11-3. Changed the Read information from "Yes" to "PCI" in Tables 11-40 through 11-43 (PVPDCNTL, PVPD_NEXT, PVPDAD, and PVPDATA). Changed CNTRL[27] description to "Reserved" in Table 11-73. Swapped pinouts for TSIZ[0:1] and LBE[3:2]#: M Mode-- TSIZ0 is now pin 92 (PQFP) and pin N14 (PBGA). TSIZ1 is now pin 91 (PQFP) and pin P15 (PBGA). C and J Modes--LBE3# is now pin 92 (PQFP) and pin N14 (PBGA). LBE2# is now pin 91 (PQFP) and pin P15 (PBGA). Corrected minor typographical errors. 02/13/1998 06/26/1998 09/02/1998 0.90 0.91 0.92 PCI 9054 Data Book v2.1 xxviii (c) PLX Technology, Inc. All rights reserved. www..com Revision History Date 11/12/1998 Revision 1.0 Comments Separated entire book by placing M mode and C and J modes into their own sections. Globally changed "negate" to "de-assert." Changed "Half Word" to "Word" and "Word" to "Lword" in M mode sections. Globally changed "driven" to "asserted" in multiple tables. Globally added a slash to "PCI Initiator/Target Abort." Added "PCI" to "Dual Address Cycle" text references. Changed "PCI command 7h" to "PCI command code = 7h." Updated timing diagrams for all modes. Changed "Arbitration" to "Control Access" in Scatter/Gather DMA Mode from Local-to-PCI Bus figure captions. Corrected inputs and outputs for DMA 0/1 Local and PCI FIFOs in the PCI 9054 Internal Block Diagram. Changed "Local Initialization" and "Serial EEPROM" section descriptions. Added new Section 1.5, "PCI 9054 Data Assignment Convention." Split signal listings into PCI and Local in Tables 1-5 and 1-6. Added exception for MWI mode to Sections 2.1.2 and 4.1.2. Changed assertion and bus ownership information in Sections 2.2.1 and 4.2.1. Local Bus cycle description changed in Sections 2.2.2 and 4.2.2. Further changes to Section 4.2.2 added regarding use of BLAST#. Added New Capabilities function support information, Sections 2.4.2.3 and 4.4.2.3. Added Hot Swap Next Capability Pointer information to Tables 2-21 and 4-21. Changed Serial EEPROM Memory map information in Figures 2-5 and 4-5. Updated Response to FIFO Full or Empty information in Tables 3-1 and 5-1. Corrected references to Local Configuration and PCI Configuration DMA registers in Sections 3.1.1 and 5.1.2. Added Master Enable (PCICR) and PCI Command Code (CNTRL) to bullet list in Sections 3.4.1 and 5.4.1. Added Continuous Burst information to Section 3.4.1.3 (M mode only). Added Lword information to FIFO description in Sections 3.4.3 and 5.4.2. Miscellaneous changes made to DMA Operation information in Sections 3.5, 3.5.2 and 5.5, 5.5.2. Changed DMA descriptor "Note" text in Sections 3.5.3 and 5.5.3. Added new Sections 3.5.3.2 and 5.5.3.2, "DMA Clear Count Mode." Changed current descriptor and Channel Done bit text in Sections 3.5.6, 5.5.6, and 6.1.8. Descriptor Pointer and Memory Descriptor Block(s) text changes applied to Figures 3-16, 3-17, 5-16, and 5-17. Changed sections describing "End of Transfer (EOT#) Input" and "Local Bus Latency and Pause Timers" to third-level headings. Moved "DMA Arbitration" section to appear after "End of Transfer (EOT#) Input." Added "PCI Initiator" to "Read Ahead mode" text and changed "Multiple-Cycle reads" to "Burst-Cycle reads" and "are set" to "are asserted" to the "Read" portion of Sections 3.4.1.3 and 5.4.1.3. Added DMA Local Bus Timer information to Sections 3.5.11 and 5.5.11. Removed text describing generation of a new ADS# from Section 4.2.5.1. Changed "End of Chain bits are programmed" to "End of Chain bits are detected" in Sections 3.5.3 and 5.5.3. Changed Doorbell register information in Figure 6-1. Swapped sequence of Sections 6.1 and 6.2. Applied significant revisions to Section 8, including System Changes Power Mode and Wake-Up Request examples. Combined "Hot Swap Switch" and "Status LED" sections into new Section 9.1.2.2.1, "Ejector Switch and Blue LED." Added new content to section. Corrected register "Value after Reset" values in Section 11. Revised timing information in Tables 13-6 through 13-9, AC Electrical Characteristics for Local inputs and outputs. Corrected information for B9, C6, D10, and P6 in PBGA Pinout in Table 14-3. Added new Section 15, "Ordering Instructions." PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. xxix www..com Revision History Date 04/1999 Revision 1.1 Comments Restyled headers and footers. Minor typographical changes. Signal angle corrections to various timing diagrams. All references to CS# changed to CCS#. Changed "Direct Slave" to "PCI Target" and "Direct Master" to "PCI Initiator." Dates changed to reflect new revision. First para in preface changed to reflect that the document is subject to change without notice. Changed the following timing diagrams: "Initialization from Serial EEPROM (2K)" and "Initialization from Serial EEPROM (4K)" (all occurrences). Also changed Timing Diagrams 5-13, 5-14, and 5-32. C and J mode graphics, changed "LD" references to "LA/LAD." Section 2.2.5.1, changed two Lwords to four Lwords in the case of 16- and 8-bit Local Bus bursts. Section 2.2.8, changed C and J mode signal name to M mode equivalent (regarding Transfer Size bits, TSIZ[0:1]). Section 4.2.1, added LHOLDA asserted. Sections 4.4.3.2 and 5.4.3.1, changed M mode signal names to their C and J mode equivalents. Figure 5-12, added BLAST#. Section 5.5.9, changed second para DMAMODE0[14]=1 and DMAMODE1[14]=1 to [15]=1. Third para changed DMAMODE0[14]=0 and DMAMODE1[14]=0 to [15]=0 and added "depending on the Local Bus width." Timing Diagram 5-32 title changed to read "PCI Target Non-Burst Local Bus Read." Section 6, entirely restructured. Table 11-47, changed bit 4 description to reference C and J Modes and M Mode byte lane descriptions separately. Table 11-86, changed Channel 1 to Channel 0 in Bit 2 description. Section 12 Pin summary note regarding pull-up and pull-down resistors, corrected M, C, and J mode pin references. Table 12-7, changed BB# pin type from "TP" to "OC." Note to Table 13-5, changed I2O to "I2O simultaneously switching outputs." Tables 13-6 and 13-7, changed Worst Case values from "2" to "1" for all signals listed. Section 14, added "PQFP" and "PBGA" suggested land patterns for PCB layout. Section 16, created new section, listing US and international representatives and distributors. PCI 9054_AB revision information added. Merged Features and Company and Product Background sections into one to streamline and be consistent. Minor typographical changes. Table 1-6, Local Signal LIsting (M, C, or J Modes) TA# input and output reversed. Following text moved from Section 2.2.4.1 to Section 4.2.4.1 and TA# changed to READY#. "In PCI Target and DMA modes, the TA# signal has no effect until the wait state counter--(LBRD0[21:18, 5:2]), (LBRD1[5:2]), (DMAMODE0[5:2]), and/or (DMAMODE1[5:2])--reaches zero. TA# then controls the number of wait states by being de-asserted in the middle of the data transaction." Section 2.2.5.1, "BDIP# output is not supported in this case" changed to BDIP# output is supported in burst forever..." Section 2.2.5.2.1, added "...PCI 9054_AB supports the BDIP# signal for continuous bursts greater than four Lwords, which differs from MPC850/860 protocol..." Section 2.2.9, added statement regarding parity being checked for Direct Slave reads, Direct Master write and DMA Local Bus reads. Section 2.4.2 and 4.4.2, added information on the PCI 9054_AB revision offering the ability to manually access the EEPROM. Section 2.4.2.1 and Section 4.4.2.1, added bit to read back the serial EEPROM value. Tables 3-3 and 3-4, added bit range to TSIZ heading. Table 3-5, revised table to reflect correct information. Section 6.1.12, added statement regarding the PCI 9054 tolerating TEA# input assertion only during PCI Target or DMA transactions. Section 9.1.2.2.3, added statement regarding the PCI 9054 Hot Swap register (HS_CSR) being accessible for writes from the Local Bus. Register 11-33, revised write status in bits 1, 6, and 7. Register 11-67, revised bit 27 to a read bit, not reserved. Table 13-5, revised ICC Max range to 200. Table 14-2, revised 225-Pin PBGA Package Mechanical Dimensions. 06/1999 2.0 PCI 9054 Data Book v2.1 xxx (c) PLX Technology, Inc. All rights reserved. www..com Revision History Date 08/1999 Revision 2.0 Comments Global, changed "kilobit" to "KB." Minor text changes, additions and deletions throughout book. Section 2.2.5.3 Lword in some instances changed to quad-word. Section 2.2.9 "Direct Slave" changed to "PCI Target," and "Direct Master" changed to "PCI Initiator." Section 2.4.2 "32 bits" changed to "33 bits." In fifth para, output changed to high. Swapped Sections 3.4.1.8 and 3.5.1. Figure 3-10, added Space 1, now reads "Space 0/1" Tables 3-3 and 3-4, added "Single" in title to read "Single Write Cycles" and "Single Read Cycles." Figure 3-17, added "(PCI Address High Added)." Section 3.5.4.1, deleted first two methods. Section 3.5.9, supplemented with BTERM# disable and enable statements. TDs 3-2 through 3-7, revised GNT# signal. TD 3-10, revised GNT#, and TD 3-11, revised GNT# and BDIP# signals. TDs 3-14, 3-15, 3-18, and 3-19, supplemented LA[0:31] signal. TDs 3-24 and 3-25, revised BDIP# signal. TD 3-33, revised TEA# signal. TDs 3-46 and 3-47, revised BDIP# signal. TD 3-48, revised MDREQ# signal. Section 4.2.2, supplemented text in last para. Section 4.4.2 "32 bits" changed to "33 bits." In fifth para, output changed to high. Swapped Sections 5.4.1.7 and 5.5.1. Figure 5-10, added Space 1, now reads "Space 0/1" Figure 5-17, added "(PCI Address High Added)." Section 5.5.4.1, deleted first two methods. TD 5-4, revised LD[31:0] and WAIT# (input) signals. Figure 6-2, changed LINTo# to LINT#. Section 9.1.2.2.2, third para revised. 9.1.2.2.3.1, value of "0x00" changed to "0x06." Register 11-20, bits 7:0, write changed from "No" to "Local." Sections 15 and 16 changed to Appendix A and Appendix B. Published Addendum for page 12-1 replacement, to include missing information previously included in the v1.0 release. Section 1.2.4, Keep Bus Mode paras, changed "Initiator" to "Target." Table 1-4, deleted "Tolerant" and "Signaling." Table 2-14, changed byte numbers high to low. Section 2.4.2, para 4, last sentence, changed "EEDO" to "EEDI" and "EEDI" to "EEDO." Table 2-21, added "/Status" to Serial EEPROM Offset 54h. Section 3.4.1.9, removed "and BI#" from first sentence of third para. Figure 5-12, reversed last arrow on left side "AD (addr & data)." Section 5.5.7.3, removed last line of third para, "All reads are Lwords." TD 5-25 and 5-26, Changed "Single-Cycle" to "Burst Cycle." 6.1.5., added sentence about clearing mailbox registry. Table 11-2, replaced missing Local Access column. Register 11-40, Bit 29, deleted two "ands." Register 11-45, Bit 4, changed to all modes, added "/RETRY#." Register 11-67, Bit 17, changed "Writing" to "Reading." Section 12.1, Notes, changed. Sections 13.2 and 13.3, deleted note. Consolidated Appendices A and B into one appendix. 10/1999 01/2000 2.0 2.1 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. xxxi www..com www..com PCI 9054 PCI I/O Accelerator January 2000 Version 2.1 I2O Compatible, CompactPCI Hot Swap Friendly PCI Bus Master Interface Chip for Adapters and Embedded Systems 1 1.1 INTRODUCTION FEATURES * 3.3V, 5V tolerant PCI and Local signaling supports Universal PCI Adapter designs, 3.3V core, lowpower CMOS in 176-pin PQFP and 225-pin PBGA * Supports Local Bus Direct-Connect to the Motorola MPC850 or MPC860 PowerQUICCTM, Intel i960 family and IBM PPC401 CPUs and similar bus protocol devices * Programmable Local Bus runs up to 50 MHz and supports non-multiplexed 32-bit address/data, multiplexed 32-bit, and slave accesses of 8-, 16-, or 32-bit Local Bus devices * Serial EEPROM interface * Three PCI-to-Local Address spaces * Programmable Local Bus wait states * Programmable prefetch counter * Local Bus runs asynchronously to the PCI Bus * Eight 32-bit Mailbox and two 32-bit Doorbell registers * Performs Big Endian Little Endian conversion * PCI-to-Local Delayed Read mode * Local-to-PCI Deferred Read mode (M mode only) * Flexible 3.3V, 5V Tolerant Local Bus operation up to 50 MHz * Industrial Temp Range operation * PCI Specification version 2.2 (v2.2) compliant 32-bit, 33-MHz Bus Master Interface Controller with PCI Power Management features for adapters and embedded systems * General Purpose Bus Master Interface featuring advanced Data Pipe ArchitectureTM technology, which includes two DMA engines, programmable Target and Initiator Data Transfer modes and PCI messaging functions * PCI v2.2 Vital Product Data (VPD) configuration support * PCI Dual Address Cycle (DAC) support * PCI Hot Plug and CompactPCI Hot Swap compliant * I2OTM v1.5-Ready Messaging Unit * Two independent DMA channels for Local Bus memory to and from PCI Host Bus Data transfers * Supports Type 0 and Type 1 Configuration cycles * Programmable Burst Management * Programmable Interrupt Generator * Six programmable FIFOs for zero wait state burst operation * PCI Local Data transfers up to 132 MB/s Boot ROM CPU Local Memory I/O Device (LAN, Disk, Comm, etc.) Local Bus PCI 9054 Registers Local Bus Interface FIFOs Serial EEPROM PCI Local Runtime DMA I2O Control: - DMA - I2O - Unaligned Transfer Address Translation: - Address Space PCI Interface PCI Bus Figure 1-1. Typical Adapter Block Diagram PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 1-1 Section 1--Introduction www..com Section 1 Introduction Features Internal Registers PCI Config. Local Config. Runtime DMA I2O Messaging Serial EEPROM Initialization PCI Bus State Machines PCI Master (for PCI Initiator Xfers) FIFOs PCI Initiator Write PCI Initiator Read DMA0/1 PCI/Loc DMA0/1 Loc/PCI PCI Target Write PCI Target Read Local Bus State Machines Local Slave (for PCI Initiator Xfers) Local Master (for Ch 0/1 DMA Xfers) Local Master (for PCI Target Xfers) Local Bus Interface: - Dynamic Bus Width of 8,16, or 32 bits - Endian Conversion - Muxed or non-Muxed Addr/Data PCI Bus Interface PCI Master (for Ch 0/1 DMA Xfers) PCI Slave (for PCI Target Xfers) Control Logic I2O Messaging DMA DMA Scatter/Gather Unaligned Xfer Figure 1-2. PCI 9054 Internal Block Diagram PCI 9054 Data Book v2.1 1-2 (c) PLX Technology, Inc. All rights reserved. www..com 1.2 COMPANY AND PRODUCT BACKGROUND 1.2.2 1.2.2.1 Data Pipe Architecture Technology Dual DMA Channels PLX Technology, Inc., the world leader in PCI-to-Local Bus I/O Accelerator chips, supports OEM customers in a wide variety of PCI applications. Customer applications include PC workstations and servers, PCI add-in boards, embedded PCI communication systems (such as routers and switches), and industrial PCI implementations (such as CompactPCI, PMC, and Passive Backplane PCI). PLX Technology, Inc., is an active participant in industry standard committees, including the PCI SIG, I2O SIG, and PICMG, and maintains active developer technology and cross-marketing partnerships with industry leaders, such as Intel, IBM, Hewlett-Packard, Motorola, Integrated Systems, WindRiver, and others. Focused on providing complete solutions for PCI implementations, PLX provides design assistance to customers in the form of Reference Design Kits (RDK) and Software Development Kits (SDK). Depending upon the application, these kits may include reference boards, API libraries, software debug tools, and sample device drivers with source, enabling customers to quickly bring new designs to production. New tools, application notes, FAQs, and information updates are constantly added to our website (www.plxtech.com) for the convenience of PLX customers. Our expertise and total solutions for the PCI interface allow customers to focus on adding value in their designs without worrying about the complexities of implementing PCI, I2O, and CompactPCI. * Dual independent channels provide flexible prioritization scheme * Programmable Burst length, including unlimited burst * Direct hardware control of DMA * * * Demand mode DMA operation Block mode or Scatter/Gather operation End of Transfer (EOT) signal * Shuttle mode DMA channel support provides automatic invalidation of used DMA descriptors * Unaligned transfer support * Supports PCI Bus Mastering from the Local Slave-only devices * Scatter/Gather list management * * Descriptors can be found in PCI Bus or Local Bus memory Allows independent Scatter/Gather ring management 1 IDMA PowerQUICC MPC850 or MPC860 Memory 2 Local Bus DMA 0 DMA 1 PCI 9054 I/O Accelerator ROM 1.2.1 PCI 9054 I/O Accelerator PCI Bus The PCI 9054, a 32-bit 33-MHz PCI Bus Master I/O Accelerator, is the most advanced general-purpose bus Master device available. It offers a robust PCI Specification v2.2 implementation enabling Burst transfers up to 132 MB/second. The PCI 9054 incorporates the industry leading PLX Data Pipe ArchitectureTM technology, including DMA engines, programmable PCI Initiator and Target Data-Transfer modes, and PCI messaging functions. Figure 1-3. High-Performance MPC850 or MPC860 PowerQUICC Adapter Design 1.2.2.2 * * * * PCI Initiator (Direct Master) Type 0 and Type 1 Configuration cycles Supports all PCI Memory and I/O cycles Initiator Read prefetching Burst length control-programmable threshold pointer * Unaligned transfer control * Big/Little Endian conversion PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 1-3 Section 1--Introduction Company and Product Background Section 1 Introduction www..com Section 1 Introduction Company and Product Background 1.2.2.3 PCI Target (Direct Slave) * Multiple independent address spaces * Dynamic Local Bus width control * Target Read prefetching * Big/Little Endian conversion * Local Bus priority control * PCI Latency Timer the Local Bus. This is a prime example of how the PCI 9054 provides superior general purpose Bus Master performance and provides designers using the PowerQUICC processor with greater flexibility in implementing multiple simultaneous I/O transfers. The PCI 9054 has unlimited bursting capability, which enhances any MPC850 or MPC860 PowerQUICC design. 1.2.3.2 1.2.2.4 PCI Messaging High Performance CompactPCI Adapter Designs * Complete Messaging Unit with mailbox and doorbell registers * Queue management pointers that can be used for message passing under the I2O protocol or a custom protocol 1.2.3 1.2.3.1 PCI 9054 PCI Applications High Performance Motorola MPC850 or MPC860 PowerQUICC Designs Another key application for the PCI 9054 is CompactPCI adapters for telecom and networking applications. These applications include high performance communications such as WAN/LAN controller cards, high-speed modem cards, Frame Relay cards, and telephony cards for telecom switches and remote-access systems. The PCI 9054 has integrated key features to enable live-insertion of Hot Swap CompactPCI adapters. The PCI 9054 PICMG v2.1-compatible Hot Swap Friendly PCI interface includes both Hot Swap Capable and Hot Swap Friendly features. A key application for the PCI 9054 is Motorola MPC850- or MPC860-based adapters for telecom and networking applications. These applications include high performance communications such as WAN/LAN controller cards, high-speed modem cards, Frame Relay cards, and routers and switches. The PCI 9054 simplifies designs by providing an industry-leading enhanced direct-connect interface to the MPC850 or MPC860 processor. The flexible PCI 9054 3.3V, 5V tolerant I/O buffers, combined with a Local Bus operation up to 50 MHz, is ideally suited for current and future PowerQUICC processors. The PCI 9054 also provides support for the MPC850 or MPC860 IDMA channel for movement of data between the internal MPC850 or MPC860 I/O and the PCI Bus. In addition, the PCI 9054 also makes use of the advanced Data Pipe Architecture technology, allowing unlimited Burst capability, as shown in Figure 1-3. 1. For PowerQUICC IDMA operation, the PCI 9054 transfers data to the PCI Bus under the control of the IDMA handshake protocol. At the same time, the PCI 9054 Data Pipe Architecture technology DMA can be operated bidirectionally, with the PCI 9054 as the Master for both buses, to manage transfers of data from the Local Bus to the PCI Bus or from the PCI Bus to 1.2.3.2.1 Hot Swap Capable * PCI Specification v2.1 or better * Vcc tolerant from early power * Tolerant of asynchronous reset * Tolerant of precharge voltage * Limited I/O pin leakage at precharge voltage 1.2.3.2.2 Hot Swap Friendly * Incorporates the Hot Swap Control/Status register (HS_CSR) * Incorporates an Extended Capability Pointer (ECP) mechanism * Incorporates added resources for software control of ENUM#, the ejector switch, and the status LED, which indicates insertion and removal to the user 2. PCI 9054 Data Book v2.1 1-4 (c) PLX Technology, Inc. All rights reserved. www..com I/O Chips (Datacom, Telecom, Storage, etc.) I/O CPU VPD Support. Fully supports the Vital Product Data (VPD) PCI extension, which provides an alternate access method other than Expansion ROM for VPD. PCI Dual-Address Cycle (DAC) Support (64-bit Address Space). Supports PCI Dual Address Cycle beyond the low 4-GB Address space. PCI DAC can be used during PCI 9054 PCI Bus Master operation (DMA, PCI Initiator). PCI Hot Plug and CompactPCI Hot Swap Compliant. Compliant with PCI Hot Plug and CompactPCI Hot Swap adapter specifications. I2O Ready Messaging Unit. Incorporates the I2O Ready Messaging Unit, which enables the adapter or embedded system to communicate with other I2O-supported devices. The I2O Messaging Unit is fully compatible with the PCI extension of I2O Specification v1.5. Dual Independently Programmable DMA Controllers with Programmable FIFOs. Provides two independently programmable DMA controllers with shared programmable FIFOs. Each channel supports Block and Scatter/Gather DMA modes, as well as End of Transfer (EOT) mode. The PCI 9054 supports Demand Mode DMA for DMA Channel 0. PCI Host Capability. In PCI Initiator mode, the PCI 9054 can assert Type 1 and Type 0 PCI Configuration cycles. Six Programmable FIFOs for Zero Wait State Burst Operation. The following table enumerates the FIFO depth. Table 1-1. FIFO Depth Local Bus PCI 9054 I/O Accelerator ROM RAM Figure 1-4. High-Performance CompactPCI Adapter 1.2.3.3 PCI Bus Embedded Host Design Another application for the PCI 9054 is PCI Hostembedded system designs, such as network switches and routers, printer engines, set-top boxes, and industrial equipment. In this configuration, the PCI 9054 Data Pipe Architecture technology allows high-performance transfer modes. In addition, the PCI 9054 supports both Type 0 and Type 1 PCI Configuration cycles that allow the PCI 9054 to configure other PCI devices or cards in the system. I/O Chips (Datacom, Telecom, Storage, etc.) CPU I/O I/O Local Bus PCI 9054 I/O Accelerator Memory I/O PCI Bus PCI I/O PCI Bus FIFO PCI Initiator Read PCI Initiator Write Length 16 Lwords 32 Lwords 16 Lwords 32 Lwords 32 Lwords 32 Lwords PCI Slots PCI Target Read PCI Target Write Figure 1-5. High-Performance Embedded Adapter DMA Read DMA Write 1.2.4 PCI 9054 Major Features PCI Local Data Transfers up to 132 MB/sec. 5 Volt Tolerant Operation. The PCI 9054 requires 3.3V Vcc. It provides 3.3V signaling with 5V I/O tolerance on both the PCI and Local Buses. PCI v2.1 and v2.2 Compliant. Compliant with all aspects of PCI Specification v2.1 and v2.2, including PCI Power Management features. Supports four power states for PCI Power Management functionsD0, D1, D2, and D3hotand the Power Management Event interrupt (PME#). PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 1-5 Section 1--Introduction Company and Product Background Section 1 Introduction www..com Section 1 Introduction Company and Product Background Local Bus Direct Interface. Supports Local Bus direct interface to the Motorola MPC850 or MPC860 family, the Intel i960 family, the IBM PPC401 family, and other similar bus-protocol devices. Programmable Local Bus. Runs up to 50 MHz and supports non-multiplexed 32-bit address/data, multiplexed 32-bit, and Slave accesses of 8-, 16-, or 32-bit Local Bus devices. Serial EEPROM Interface. Contains an optional serial EEPROM interface (optional only if a Local processor is being used) that can be used to load configuration information. This is useful for loading information that is unique to a particular adapter (such as the Network ID or the Vendor ID). Three PCI-to-Local Address Spaces. The PCI 9054 supports three PCI-to-Local Address spaces when the PCI 9054 is in PCI Target or PCI Slave mode. These spaces (Space 0, Space 1, and Expansion ROM spaces) allow any PCI Bus Master to access the Local Memory spaces with programmable wait states, bus width, burst capabilities, and so forth. Programmable Prefetch Counter. The PCI 9054 can be programmed to prefetch data during PCI Target and PCI Initiator prefetches (known or unknown size). To perform burst reads, prefetching must be enabled. The prefetch size can be programmed to match the Master burst length, or can be used as Read Ahead mode data. The PCI 9054 reads single data (8, 16, or 32 bit) if the Master initiates a single cycle; otherwise, the PCI 9054 prefetches the programmed size. Mailbox Registers. Contains eight 32-bit Mailbox registers that may be accessed from the PCI or Local Bus. Doorbell Registers. Includes two 32-bit doorbell registers. One asserts interrupts from the PCI Bus to the Local Bus. The other asserts interrupts from the Local Bus to the PCI Bus. Big/Little Endian Conversion. Supports dynamic switching between Big Endian (Address Invariance) and Little Endian (Data Invariance) operations for PCI Target, PCI Initiator, DMA, and internal register accesses on the Local Bus. The PCI 9054 supports on-the-fly Endian conversion for Space 0, Space 1, and Expansion ROM space. The Local Bus can be Big/Little Endian by using the BIGEND# input pin or programmable internal register configuration. When BIGEND# is asserted, it overrides the internal register configuration during PCI Initiator and internal register accesses on the Local Bus. Note: The PCI Bus is always Little Endian. Programmable Local Bus Modes. The PCI 9054 is a PCI Bus Master interface chip that connects a PCI Bus to one of three Local Bus types (M, C, or J mode), selected through mode pins. The PCI 9054 may be connected to any Local Bus with a similar design with little or no glue logic. Table 1-2 lists the three modes. Table 1-2. Programmable Local Bus Modes Mode M C J Description 32-bit address/32-bit data, non-multiplexed direct connect interface to MPC850 or MPC860 32-bit address/32-bit data, non-multiplexed 32-bit address/32-bit data, multiplexed Clock. The Local Bus interface runs from a Local clock to provide the necessary internal clocks. This clock runs asynchronously to the PCI clock. Read Ahead Mode. Supports Read Ahead mode, where prefetched data can be read from the PCI 9054 internal PCI Target Read FIFO instead of from the Local Bus. The address must be subsequent to the previous address and 32-bit aligned (next address = current address + 4). This feature allows for increased bandwidth and reduced data latency. M Mode of Operation. The PCI 9054 is designed with a seamless interface to the Motorola MPC850 or MPC860 RISC processors. The PCI 9054 communicates with the MPC850 or MPC860 using five possible Data-Transfer modes: * * * * * Configuration Register Access PCI Initiator Operation PCI Target Operation DMA Operation IDMA/SDMA Operation PCI 9054 Data Book v2.1 1-6 (c) PLX Technology, Inc. All rights reserved. www..com C and J Modes of Operation. The PCI 9054 is designed with a seamless interface to the Intel i960 and the IBM PPC401 family RISC processors. The PCI 9054 communicates with these processors using four possible Data-Transfer modes: * * * * Configuration Register Access PCI Initiator Operation PCI Target Operation DMA Operation Subsystem ID and Subsystem Vendor ID. Contains Subsystem ID and Subsystem Vendor ID in the PCI Configuration Register Space in addition to System and Vendor IDs. The PCI 9054 also contains a permanent Vendor ID (10B5h) and Device ID (9054h). Direct Bus Master. Supports PCI accesses from a Local Bus Master. Burst transfers are supported for memorymapped devices and single-transfers are supported for memory-mapped and I/O devices. The PCI 9054 also supports PCI Bus interlock (LOCK#) cycles. PCI Target. Supports Burst Memory-Mapped and Single I/O-Mapped accesses to the Local Bus. The Read and Write FIFOs enable high-performance bursting. Interrupt Generator. Can assert PCI and Local interrupts from external and internal sources. Unaligned DMA Transfer Support. Can transfer data on any byte-boundary combination of the PCI and Local Address spaces. Keep Bus Mode (M Mode). The PCI 9054 can be programmed to keep the PCI Bus by generating wait state(s) if the PCI Target Write FIFO becomes full. The PCI 9054 can also be programmed to keep the Local Bus (BB# asserted) if the PCI Target Write FIFO becomes empty or the PCI Target Read FIFO becomes full. The Local Bus is dropped in either case when the Local Bus Latency Timer is enabled and expires. Keep Bus Mode (C and J Modes). The PCI 9054 can be programmed to keep the PCI Bus by generating wait state(s) if the PCI Target Write FIFO becomes full. The PCI 9054 can also be programmed to keep the Local Bus (LHOLD asserted) if the PCI Target Write FIFO becomes empty or the PCI Target Read FIFO becomes full. The Local Bus is dropped in either case when the Local Bus Latency Timer is enabled and expires. New Capabilities Structure. Supports New Capabilities registers to define additional capabilities of the PCI functions. Posted Memory Writes. Supports the Posted Memory Writes (PMW) for maximum performance and to avoid potential deadlock situations. RST# Timing. Supports response to first configuration accesses after de-assertion of RST# under 225 clocks. 1.2.5 PCI 9054 Data Assignment Convention Table 1-3 describes the PCI 9054 data assignment convention. Table 1-3. PCI 9054 Data Assignment Convention Data Width 1 byte (8 bits) 2 bytes (16 bits) 4 bytes (32 bits) PCI 9054 Convention Byte Word Lword 1.2.5.1 1.2.5.2 PCI 9050/9080 Compatibility Pin Compatibility The PCI 9054 is not pin compatible with the PCI 9080 nor with the PCI 9050. 1.2.5.3 Register Compatibility All registers implemented in the PCI 9080 are implemented in the PCI 9054. The PCI 9054 includes many new bit definitions and several new registers. (Refer to Section 11.1 for details.) The PCI 9054 is not register-compatible with the PCI 9050. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 1-7 Section 1--Introduction Company and Product Background Section 1 Introduction www..com Section 1 Introduction Company and Product Background 1.2.6 PCI 9054, PCI 9080, and PCI 9050 Comparison Feature PCI 9054 176 PQFP, 225 PBGA 2 3 Yes Eight 32-bit Two 32-bit 6 32 Lwords (128 bytes) 16 Lwords (64 bytes) 32 Lwords (128 bytes) Single bidirectional Read/Write FIFO 16 Lwords (64 bytes) Single bidirectional Read/Write FIFO Yes Yes No Yes (One channel only) Identical to the PCI 9080 except the PCI 9054 contains additional registers related to added functionality Yes Yes Yes Yes Yes Yes Yes Yes 3.3V 3.3V Yes Yes 2K bit, 4K bit devices Reads allowed via Vital Product Data Function (refer to Section 10) Table 1-4. Comparison of PCI 9054, PCI 9080, and PCI 9050 PCI 9080 208 PQFP 2 3 Yes Eight 32-bit Two 32-bit 8 32 Lwords (128 bytes) 16 Lwords (64 bytes) 32 Lwords (128 bytes) Read and Write FIFOs 16 Lwords (64 bytes) Read and Write FIFOs Yes Yes Yes Yes PCI 9050 160 PQFP 0 5 No Eight 32 bit Two 32 bit -- -- 2 N/A Package Size/Type Number of DMA Channels Local Address Spaces PCI Initiator Mode Mailbox Registers Doorbell Registers Number of FIFOs FIFO Depth--PCI Target Write and PCI Initiator Write FIFO Depth--PCI Target Read and PCI Initiator Read FIFO Depth--DMA Channel 0 FIFO Depth--DMA Channel 1 N/A LLOCKo# Pin for Lock Cycles WAIT# Pin for Wait State Generation BPCLKo Pin; Buffered PCI Clock DREQ0# and DACK0# Pins for Demand Mode DMA Support Yes No Yes No Register Addresses -- -- Big Endian Little Endian Conversion PCI Specification v2.1 Deferred Reads PCI Specification v2.2 PCI Power Management, PCI Hot Plug Compliant, CompactPCI Hot Swap Compliant PCI v2.2 VPD Support Programmable Prefetch Counter Memory Write and Invalidate Cycle Additional Device and Vendor ID Registers I2O Messaging Unit Core and Local Bus Vcc PCI Bus Vcc 3.3V PCI Bus and Local Bus Signaling 5V Tolerant PCI Bus and Local Bus Serial EEPROM Support Serial EEPROM Read Control Yes Yes No No Yes Yes Yes Yes 5V 3.3/5V Yes (if PCI Vcc is 3.3V) Yes (if PCI Vcc is 5V) 1K bit, 2K bit devices Reads allowed via Serial EEPROM Control Register (CNTRL) Yes Yes No No Yes No No No 5V 5V No Yes -- 1K bit device PCI 9054 Data Book v2.1 1-8 (c) PLX Technology, Inc. All rights reserved. www..com 1.2.7 PCI 9054 Signal Listing (M, C, or J Modes) Bus Mode All Table 1-5. PCI 9054 PCI Signal Listing (M, C, or J Modes) Symbol AD[31:0] Signal Name Address and Data Total Pins 32 Function All multiplexed on the same PCI pins. The Bus transaction consists of an Address phase, followed by one or more Data phases. The PCI 9054 supports both Read and Write bursts. All multiplexed on the same PCI pins. During the Address phase of a transaction, defines the bus command. During the Data phase, used as byte enables. Refer to the PCI spec for further detail if needed. When actively driven, indicates the driving device has decoded its address as the Target of the current access. As an input, indicates whether any device on the bus is selected. Driven by the current Master to indicate beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, Data transfers continue. When FRAME# is de-asserted, the transaction is in the final Data phase. Indicates to the agent that access to the bus is granted. Every Master has its own REQ# and GNT#. Used as a chip select during Configuration Read and Write transactions. PCI Interrupt request. Indicates ability of the initiating agent (Bus Master) to complete the current Data phase of the transaction. Indicates an atomic operation that may require multiple transactions to complete. Even parity across AD[31:0] and C/BE[3:0]#. All PCI agents require parity generation. PAR is stable and valid one clock after the Address phase. For Data phases, PAR is stable and valid one clock after either IRDY# is asserted on a Write transaction or TRDY# is asserted on a Read transaction. Once PAR is valid, it remains valid until one clock after current Data phase completes. Provides timing for all transactions on PCI and is an input to every PCI device. The PCI 9054 operates up to 33 MHz. Reports data parity errors during all PCI transactions, except during a special cycle. Wake-up event interrupt. Indicates to arbiter that this agent must use the bus. Every Master has its own GNT# and REQ#. Used to bring PCI-specific registers, sequencers, and signals to a consistent state. Reports address parity errors, data parity errors on the Special Cycle command, or any other system error where the result is catastrophic. Indicates the current Target is requesting that the Master stop the current transaction. Indicates ability of the Target agent (selected device) to complete the current Data phase of the transaction. C/BE[3:0]# All Bus Command and Byte Enables 4 DEVSEL# All Device Select 1 FRAME# All Cycle Frame 1 GNT# IDSEL INTA# IRDY# LOCK# PAR All All All All All All Grant Initialization Device Select Interrupt A Initiator Ready Lock Parity 1 1 1 1 1 1 PCLK PERR# PME# REQ# RST# SERR# All All All All All All Clock Parity Error Power Management Event Request Reset Systems Error 1 1 1 1 1 1 STOP# TRDY# All All Stop Target Ready 1 1 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 1-9 Section 1--Introduction Company and Product Background Section 1 Introduction www..com Section 1 Introduction Company and Product Background Table 1-6. PCI 9054 Local Signal Listing (M, C, or J Modes) Symbol ADS# ALE BB# Bus Mode C, J J M Signal Name Address Strobe Address Latch Enable Bus Busy Total Pins 1 1 1 Function Indicates valid address and start of new Bus access. Asserted for first clock of Bus access. Asserted during Address phase and de-asserted before Data phase and before next LCLK rising edge. As an input, the PCI 9054 monitors this signal to determine whether an external Master has ended a Bus cycle. As an output, the PCI 9054 asserts this signal after an external arbiter has granted ownership of the Local Bus and BB# is inactive from another Master. Signal requires an external pull-up resistor value of 510W be applied to guarantee a fast transition to the inactive state when the PCI 9054 relinquishes ownership of the Local Bus. As an input, driven by the Bus Master during a Burst transaction. The Master de-asserts before the last Data phase on the bus. As an output, driven by the PCI 9054 during the Data phase of a Burst transaction. The PCI 9054 de-asserts before the last Burst Data phase on the bus. Asserted by the Local Bus arbiter in response to BR#. Indicates the requesting Master is next. Whenever BR# is asserted, indicates that the Target device does not support Burst transactions. Multiplexed input/output pin. Can be asserted during the Local Bus Address phase of a PCI Initiator transfer or Configuration register access to specify use of Big Endian Byte ordering. Big Endian Byte order for PCI Initiator transfers or Configuration register accesses is also programmable through the Configuration registers. If wait is selected, then PCI 9054 issues WAIT# when it is a Master on the Local Bus and has internal wait states setup. As a Slave, the PCI 9054 accepts WAIT# as an input from the Bus Master. Signal driven by the current Local Bus Master to indicate the last transfer in a Bus access. Asserted by the Master to request use of the Local Bus. The Local Bus arbiter asserts BG# when the Master is next in line for bus ownership. Asserted to indicate a Local Bus Master requires the bus. If enabled through the PCI 9054 Configuration registers, the PCI 9054 releases the bus during a DMA transfer if this signal is asserted. Asserted to indicate the PCI 9054 requires the bus to perform a PCI Target PCI-to-Local Bus access while a PCI Initiator access is pending on the Local Bus. Can be used with external logic to assert backoff to a Local Bus Master. Operational parameters are set up through the PCI 9054 Configuration registers. As input to the PCI 9054: For processors that burst up to four Lwords. If the Bterm Mode bit is disabled through the PCI 9054 Configuration registers, the PCI 9054 also bursts up to four Lwords. If enabled, the PCI 9054 continues to burst until a BTERM# input is asserted. BTERM# is a Ready input that breaks up a Burst cycle and causes another Address cycle to occur. Used in conjunction with the PCI 9054 programmable wait state generator. As output from the PCI 9054: Asserted, along with READY#, to request break up of a burst and start of a new Address cycle (PCI Aborts only). BDIP# M Burst Data in Progress 1 BG# BI# M M Bus Grant Burst Inhibit 1 1 1 BIGEND#/ WAIT# All M Big Endian Select WAIT Input/Output Select (WAIT# is available at this location only in M mode) BLAST# BR# C, J M Burst Last Bus Request 1 1 BREQi C, J Bus Request 1 BREQo C, J Bus Request Out 1 BTERM# C, J Burst Terminate 1 PCI 9054 Data Book v2.1 1-10 (c) PLX Technology, Inc. All rights reserved. www..com Table 1-6. PCI 9054 Local Signal Listing (M, C, or J Modes) (Continued) Symbol BURST# Bus Mode M Burst Signal Name Total Pins 1 Function As an input, driven by the Master along with address and data indicating a Burst transfer is in progress. As an output, driven by the PCI 9054 along with address and data indicating a Burst transfer is in progress. Internal PCI 9054 registers are selected when CCS# is asserted low. See USERi/DACK0#/LLOCKi#. CCS# DACK0# DEN# DMPAF DP[0:3] DP[3:0] DREQ0# DT/R# All All J All M C, J All J Configuration Register Select 1 Data Enable 1 Used in conjunction with DT/R# to provide control for data transceivers attached to the Local Bus. See MDREQ#/DMPAF/EOT#. Data Parity 4 Parity is even for each of up to four byte lanes on the Local Bus. Parity is checked for writes or reads to the PCI 9054. Parity is asserted for reads from or writes by the PCI 9054. See USERo/DREQ0#/LLOCKo#. Data Transmit/Receive 1 Used in conjunction with DEN# to provide control for data transceivers attached to the Local Bus. When asserted, indicates the PCI 9054 receives data. Serial EEPROM Chip Select. Multiplexed Write/Read data to a serial EEPROM pin. Serial EEPROM clock pin. Interrupt output asserted when an adapter using PCI 9054 has been freshly inserted or is ready to be removed from a PCI slot. See MDREQ#/DMPAF/EOT#. EECS EEDI/ EEDO EESK ENUM# EOT# LA[28:2] All All All All All J Serial EEPROM Chip Select Serial EEPROM Data IN/ Serial EEPROM Data OUT Serial Data Clock Enumeration 1 1 1 1 Local Address Bus 27 Carries the middle 27 bits of the physical address bus. During bursts, it is incremented to indicate successive Data cycles. The lowest two bits, LA[3:2], carry the Word address of the 32-bit Memory address. All bits are incremented during a Burst access. Carries the 32 bits of the physical Address Bus. Carries the upper 30 bits of physical Address Bus. During bursts, LA[31:2] increment to indicate successive Data cycles. During an Address phase, the bus carries the upper 30 bits of the physical Address Bus. During a Data phase, the bus carries 32 bits of data. LA[0:31] LA[31:2] LAD[31:0] M C J Address Bus 32 30 Address/Data Bus 32 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 1-11 Section 1--Introduction Company and Product Background Section 1 Introduction www..com Section 1 Introduction Company and Product Background Table 1-6. PCI 9054 Local Signal Listing (M, C, or J Modes) (Continued) Symbol LBE[3:0]# Bus Mode C Signal Name Byte Enables Total Pins 4 Function Encoded, based on the bus-width configuration, as follows: 32-Bit Bus The four byte enables indicate which of the four bytes are active during a Data cycle: BE3# Byte Enable 3--LD[31:24] BE2# Byte Enable 2--LD[23:16] BE1# Byte Enable 1--LD[15:8] BE0# Byte Enable 0--LD[7:0] 16-Bit Bus BE3#, BE1# and BE0# are encoded to provide BHE#, LA1, and BLE#, respectively: BE3# Byte High Enable (BHE#)--LD[15:8] BE2# not used BE1# Address bit 1 (LA1) BE0# Byte Low Enable (BLE#)--LD[7:0] 8-Bit Bus BE1# and BE0# are encoded to provide LA1 and LA0, respectively: BE3# not used BE2# not used BE1# Address bit 1 (LA1) BE0# Address bit 0 (LA0) Encoded, based on the bus-width configuration, as follows: 32-Bit Bus The four byte enables indicate which of the four bytes are active during a Data cycle: BE3# Byte Enable 3--LAD[31:24] BE2# Byte Enable 2--LAD[23:16] BE1# Byte Enable 1--LAD[15:8] BE0# Byte Enable 0--LAD[7:0] 16-Bit Bus BE3#, BE1# and BE0# are encoded to provide BHE#, LAD1, and BLE#, respectively: BE3# Byte High Enable (BHE#)--LAD[15:8] BE2# not used BE1# Address bit 1 (LAD1) BE0# Byte Low Enable (BLE#)--LAD[7:0] 8-Bit Bus BE1# and BE0# are encoded to provide LAD1 and LAD0, respectively: BE3# not used BE2# not used BE1# Address bit 1 (LAD1) BE0# Address bit 0 (LAD0) J LCLK LD[0:31] LD[31:0] LEDon/ LEDin LFRAME# LHOLD All M C All All C, J Local processor Clock Data Bus 1 32 Local clock input. Carries 8-, 16-, or 32-bit data quantities, depending upon bus-width configuration. All Master accesses to the PCI 9054 are 32 bits only. As an output, acts as the Hot Swap board indicator LED. As an input, monitors the CompactPCI board latch status. Could be used to monitor PCI Bus activity. Available only on the PBGA package. Asserted to request use of the Local Bus. The Local Bus arbiter asserts LHOLDA when control is granted. LEDon/LEDin PCI Buffered FRAME# Signal Hold Request 1 1 1 PCI 9054 Data Book v2.1 1-12 (c) PLX Technology, Inc. All rights reserved. www..com Table 1-6. PCI 9054 Local Signal Listing (M, C, or J Modes) (Continued) Symbol LHOLDA Bus Mode C, J Signal Name Hold Acknowledge Total Pins 1 Function Asserted by the Local Bus arbiter when control is granted in response to LHOLD. Bus should not be granted to the PCI 9054 unless requested by LHOLD. As an input to the PCI 9054, when asserted low, causes a PCI interrupt. As an output, a synchronous level output that remains asserted as long as an interrupt condition exists. If edge level interrupt is required, disabling and then enabling Local interrupts through INTCSR creates an edge if an interrupt condition still exists or a new interrupt condition occurs. See USERi/DACK0#/LLOCKi#. See USERo/DREQ0#/LLOCKo#. LINT# All Local Interrupt 1 LLOCKi# LLOCKo# LRESETo# LSERR# All All All C, J Local Bus Reset Out System Error Interrupt Output 1 1 Asserted when the PCI 9054 chip is reset. Can be used to drive RESET# input of a Local processor. Synchronous level output asserted when the PCI Bus Target Abort bit is set (PCISR[11]=1) or Received Master Abort bit is set (PCISR[13]=1). If edge level interrupt is required, disabling and then enabling LSERR# interrupts through the interrupt/control status creates an edge if an interrupt condition still exists or a new interrupt condition occurs. Asserted low for reads and high for writes. Multiplexed input or output pin. MDREQ#: IDMA M mode Data transfer request start. Always asserted, indicating Data transfer should start. De-asserted only when the PCI Initiator FIFO becomes full. Programmable through a Configuration register. DMPAF: PCI Initiator Write FIFO Almost Full status output. Programmable through a Configuration register. EOT#: Terminates the current DMA transfer. Note: EOT# serves as a general purpose EOT. Before asserting EOT#, user should be aware of DMA channel activity. LW/R# C, J Write/Read 1 1 MDREQ#/ M IDMA Data Transfer Request (MDREQ# is available at this location in M mode only) PCI Initiator Programmable Almost Full End of Transfer for Current DMA Channel Bus Mode 2 DMPAF/ EOT# All All MODE[1:0] All Selects the PCI 9054 bus operation mode: Mode 0 Mode 1 Bus Mode 1 1 M 1 0 J 0 1 Reserved 0 0 C Asserted high for reads and low for writes. When the PCI 9054 is a Bus Master, indicates that Read data on the bus is valid or that a Write Data transfer is complete. Used in conjunction with the PCI 9054 programmable wait state generator. When a Local Bus access is made to the PCI 9054, indicates that Read data on the bus is valid or that a Write Data transfer is complete. Driven by the PCI 9054 when it is a Slave to indicate a Local Master must back off and restart the cycle. In Deferred Read mode, indicates the Master should return for requested data. As an output, when a Local Bus access is made to the PCI 9054, indicates a Write Data transfer can complete or that Read data on the bus is valid. As an input, when the PCI 9054 is a Bus Master, indicates a Write Data transfer is complete or that Read data on the bus is valid. RD/WR# READY# M C, J Read/Write Ready Input/Output 1 1 RETRY# M Retry 1 TA# M Transfer Acknowledge 1 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 1-13 Section 1--Introduction Company and Product Background Section 1 Introduction www..com Section 1 Introduction Company and Product Background Table 1-6. PCI 9054 Local Signal Listing (M, C, or J Modes) (Continued) Symbol TEA# TEST Bus Mode M All Signal Name Transfer Error Acknowledge Test Pin Total Pins 1 1 Function Driven by the Target device, indicating an error condition has occurred during a Bus cycle. Pulled high for test and low for normal operation. When pulled high: All outputs except USERo/DREQ0#/LLOCKo# and LEDon/LEDin are placed in tri-state. USERo/DREQ0#/LLOCKo# provides NANDTREE output. Indicates the valid address and start of new Bus access. Asserted for the first clock of a Bus access. Driven by current Master along with the address, indicating the data-transfer size. Refer to Section 3.4.3.5.3 for more information. Multiplexed input/output pin. USERi: General-purpose input that can be read by way of the PCI 9054 Configuration registers. DACK0#: When a channel is programmed through the Configuration registers to operate in Demand mode, this output indicates a DMA transfer is being executed. DACK0# corresponds to PCI 9054 DMA Ch 0. LLOCKi#: Indicates an atomic operation that may require multiple transactions to complete. Used by the PCI 9054 for direct Local access to the PCI Bus. TS# TSIZ[0:1] M M Address Strobe Transfer Size 1 2 All USERi/ User Input 1 DACK0#/ Demand Mode DMA Acknowledge LLOCKi# Local Lock Input All USERo/ User Output 1 Multiplexed input/output pin. USERo: General-purpose output controlled from the PCI 9054 Configuration registers. DREQ0#: When a channel is programmed through the Configuration registers to operate in Demand mode, this input serves as a DMA request. DREQ0# corresponds to PCI 9054 DMA Ch 0. LLOCKo#: Indicates an atomic operation for a PCI Target PCI-to-Local Bus access may require multiple transactions to complete. DREQ0#/ Demand DMA Request LLOCKo# Local Lock Output VDD All Power (+3.3V) 15 Three-volt power supply pins for core and I/O buffers. Liberal .01 to .1 F decoupling capacitors should be placed near the PCI 9054. Ground pins. As an input, can be asserted to cause the PCI 9054 to insert wait states for Local PCI Initiator accesses to the PCI Bus. Can be thought of as a Ready input from an external Master for PCI Initiator accesses. As an output, asserted by the PCI 9054 when internal wait state generator causes wait states. Can be thought of as an output providing PCI 9054 Ready status. See BIGEND#/WAIT#. VSS WAIT# All C, J Ground Wait Input/Output 12 1 WAIT# M Wait Input/Output 1 PCI 9054 Data Book v2.1 1-14 (c) PLX Technology, Inc. All rights reserved. www..com 2 2.1 M MODE BUS OPERATION PCI BUS CYCLES 2.1.2.1 DMA Master Command Codes DMA controllers of the PCI 9054 can assert the Memory cycles listed in Table 2-2. Table 2-2. DMA Master Command Codes Section 2--M Bus Op 2-1 Command Type Memory Read Memory Write Memory Read Multiple PCI Dual Address Cycle The PCI 9054 is compliant with PCI Specification v2.2. Refer to PCI Specification v2.2 for specific PCI Bus functions. 2.1.1 PCI Target Command Codes Code (C/BE[3:0]#) 0110 (6h) 0111 (7h) 1100 (Ch) 1101 (Dh) 1110 (Eh) 1111 (Fh) As a Target, the PCI 9054 allows access to the PCI 9054 internal registers and the Local Bus, using the commands listed in Table 2-1. All Read or Write accesses to the PCI 9054 can be Byte, Word, or Lword (longword) accesses, defined as 32 bit. All memory commands are aliased to basic memory commands. All I/O accesses to the PCI 9054 are decoded to an Lword boundary. Byte enables are used to determine which bytes are read or written. An I/O access with illegal byte enable combinations is terminated with a Target Abort. Table 2-1. PCI Target Command Codes Command Type I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple PCI Dual Address Cycle Memory Read Line Memory Write and Invalidate Memory Read Line Memory Write and Invalidate 2.1.2.2 Direct Local-to-PCI Command Codes For direct Local-to-PCI Bus accesses, the PCI 9054 asserts the cycles listed in Table 2-3 through Table 2-5. Table 2-3. Local-to-PCI Memory Access Command Type Memory Read Memory Write Memory Read Multiple PCI Dual Address Cycle Memory Read Line Memory Write and Invalidate Code (C/BE[3:0]#) 0010 (2h) 0011 (3h) 0110 (6h) 0111 (7h) 1010 (Ah) 1011 (Bh) 1100 (Ch) 1101 (Dh) 1110 (Eh) 1111 (Fh) Code (C/BE[3:0]#) 0110 (6h) 0111 (7h) 1100 (Ch) 1101 (Dh) 1110 (Eh) 1111 (Fh) Table 2-4. Local-to-PCI I/O Access Command Type Code (C/BE[3:0]#) 0010 (2h) 0011 (3h) 2.1.2 PCI Master Command Codes I/O Read I/O Write The PCI 9054 can access the PCI Bus to perform DMA or PCI Initiator Local-to-PCI Bus transfers. During a PCI Initiator or DMA transfer, the command code assigned to the PCI 9054 internal register location (CNTRL[15:0]) is used as the PCI command code (except for Memory Write and Invalidate mode for DMA cycles where (DMPBAM[9]=1). Table 2-2 through Table 2-5 list various PCI Master Command codes. Notes: Programmable internal registers determine PCI command codes when the PCI 9054 is the Master. DMA cannot perform I/O or configuration accesses. Table 2-5. Local-to-PCI Configuration Access Command Type Configuration Memory Read Configuration Memory Write Code (C/BE[3:0]#) 1010 (Ah) 1011 (Bh) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. www..com Section 2 M Mode Bus Operation Local Bus Cycles 2.1.3 PCI Arbitration 2.2.1 Local Bus Arbitration The PCI 9054 asserts REQ# to request the PCI Bus. The PCI 9054 can be programmed using the PCI Request Mode bit (MARBR[23]) to de-assert REQ# when it asserts FRAME# during a Bus Master cycle, or to keep REQ# asserted for the entire Bus Master cycle. The PCI 9054 always de-asserts REQ# for a minimum of two PCI clocks between Bus Master ownership that includes a Target disconnect. The PCI Initiator Write Delay bits (DMPBAM[15:14]) can be programmed to delay the PCI 9054 from asserting PCI REQ# during a PCI Initiator Write cycle. DMPBAM can be programmed to wait 0, 4, 8, or 16 PCI Bus clocks after the PCI 9054 has received its first Write data from the Local Bus Master and is ready to begin the PCI Write transaction. This function is useful in applications where a Local Master is bursting and a Local Bus clock is slower than the PCI Bus clock. This allows Write data to accumulate in the PCI 9054 PCI Initiator Write FIFO, which provides for better use of the PCI Bus. The PCI 9054 asserts BR# to request the Local Bus. It owns the Local Bus when BG# is asserted. Upon receiving BG#, the PCI 9054 waits for BB# to de-assert. The PCI 9054 then asserts BB# at the next rising edge of the Local clock after acknowledging BB# is de-asserted (no other device is acting as the Local Bus Master). The PCI 9054 continues to assert BB# while acting as the Local Bus Master (that is, it holds the bus until instructed to release BB#) when the Local Bus Latency Timer is enabled and expires (MARBR[7:0]) or the transaction is complete. Note: The Local Bus Pause Timer applies only to DMA operation. It does not apply to PCI Target operation. 2.2.2 PCI Initiator Local Bus cycles can be Single or Burst cycles. As a Local Bus Target, the PCI 9054 allows access to the PCI 9054 internal registers and the PCI Bus. Local Bus PCI Initiator accesses to the PCI 9054 must be for a 32-bit non-pipelined bus. Non-32-bit PCI Initiator accesses to the PCI 9054 require simple external logic (latch array to combine date into a 32-bit bus). 2.2 LOCAL BUS CYCLES The PCI 9054 interfaces a PCI Host bus to several Local Bus types, as listed in Table 2-6 and Table 2-7. It operates in one of three modes, selected through MODE[1:0] (PQFP--Pins 157 and 156; PBGA--Pins B7 and E8), corresponding to M, J, and C bus types. Table 2-6. Local Bus Types (176-Pin PQFP) Pin 157 1 1 0 0 2.2.3 PCI Target The PCI Bus Master reads from and writes to the Local Bus (the PCI 9054 is a PCI Bus Target and a Local Bus Master). Pin 156 1 0 1 0 Mode M Reserved J C -- Bus Type 32-bit non-multiplexed 2.2.4 Wait State Control PCI Bus Local Bus Accessing PCI 9054 from Local Bus 32-bit multiplexed 32-bit non-multiplexed Accessing PCI 9054 from PCI Bus Table 2-7. Local Bus Types (225-Pin PBGA) Pin B7 1 1 0 0 PCI 9054 de-asserts TRDY# when waiting on the Local Bus PCI Bus de-asserts IRDY# or simply ends the cycle when it's not ready PCI 9054 accessing PCI Bus PCI 9054 can be programmed to de-assert IRDY# when its PCI Initiator Read FIFO is full PCI Bus de-asserts TRDY# when it's not ready PCI 9054 generates READY# when data is valid on the following clock edge Local Processor generates wait states with WAIT# Pin E8 1 0 1 0 Mode M Reserved J C -- Bus Type 32-bit non-multiplexed 32-bit multiplexed 32-bit non-multiplexed PCI 9054 PCI 9054 accessing Local Bus PCI 9054 generates wait states with WAIT# (programmable) Local Bus can respond to PCI 9054 requests with READY# In M mode, the PCI 9054 provides a direct connection to the MPC850 or MPC860 address and data lines, regardless of the PCI 9054 Little Endian or Big Endian modes. Figure 2-1. Wait States Note: The figure represents a sequence of Bus cycles. PCI 9054 Data Book v2.1 2-2 (c) PLX Technology, Inc. All rights reserved. www..com Local Bus Cycles Section 2 M Mode Bus Operation The TA# signal overwrites the programmable wait state counter, and could be used to introduce additional wait states. On the Local Bus, BTERM# is not supported, but the Bterm bit can be used to gain maximum performance and data throughput. * If the Burst Mode bit is enabled, but the Bterm Mode bit is disabled, then the PCI 9054 bursts four Lwords. BDIP# is de-asserted at the last Lword transfer before its completion (LA[3:2]=11) and a new TS# is asserted at the first Lword (LA[3:2]=00) of the next burst. * If the Burst Mode and Bterm Mode bits are both enabled, then the PCI 9054 bursts until the transfer counter counts to "0", the Local Latency Timer is enabled and expires, the EOT function is introduced, or DREQ0# is de-asserted during DMA transactions. For PCI Target transactions, the PCI 9054 bursts until BI# is asserted, implying a new TS# is required, or the Local Latency Timer is enabled and expires. The PCI 9054 does not release bus ownership during BI# assertion. BDIP# output is supported in Burst Forever mode with a different behavior then MPC860 protocol. Refer to Section 2.2.5.2. Notes: If Address Increment is disabled, the DMA transaction bursts beyond four Lwords. If the Bterm Mode bit is disabled, the PCI 9054 performs the following: * * * 32-bit Local Bus--Bursts up to four Lwords 16-bit Local Bus--Bursts up to four Lwords 8-bit Local Bus--Bursts up to four Lwords 2.2.4.1 Wait States--Local Bus In PCI Initiator mode, when accessing the PCI 9054 registers, the PCI 9054 acts as a Local Bus Slave. The PCI 9054 asserts external wait states with the TA# signal. In PCI Target and DMA modes, the PCI 9054 acts as a Local Bus Master. The Internal Wait States bit(s) (LBRD0[21:18, 5:2], (LBRD1[5:2]), DMAMODE0[5:2], and/or DMAMODE1[5:2]) can be used to program the number of internal wait states between the first addressto-data (and subsequent data-to-data in Burst mode). In PCI Target and DMA modes, if TA# is enabled and active, it continues the Data transfer, regardless of the wait state counter. 2.2.4.2 Wait States--PCI Bus To insert PCI Bus wait state(s), the PCI Bus Master throttles IRDY# and the PCI Bus Slave throttles TRDY#. 2.2.5 Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode) Note: In the following sections, Bterm refers to the PCI 9054 internal register bit, and BTERM# refers to the PCI 9054 external signal. In every case, it transfers 16 bytes of data. 2.2.5.2 2.2.5.1 Burst and Bterm Modes Table 2-8. Burst and Bterm on the Local Bus Mode Single Cycle Single Cycle Burst-4 Burst-4 Lword Mode Burst 0 0 1 Bterm 0 1 0 Result One TS# per data (default). One TS# per data. One TS# per four data (recommended for MPC850 or MPC860). PCI Target or DMA--One TS# per Burst data or until BI# is asserted (refer to Section 2.2.5.2.1). If the Burst Mode bit is enabled and the Bterm Mode bit is disabled, bursting can start only on a 16-byte boundary and continue up to the next 16-byte address boundary. After data before the boundary is transferred, the PCI 9054 asserts a new Address cycle (TS#). Table 2-9. Burst-4 Lword Mode Bus Width 32 bit 16 bit 8 bit Burst Four Lwords or up to a quad Lword boundary (LA3, LA2 = 11) Eight words or up to a quad Lword boundary (LA2, LA1 = 11) Sixteen bytes or up to a quad Lword boundary (LA1, LA0 = 11) Burst Forever 1 1 Note: BI# is supported in Burst-4 mode. Refer to the MPC850 or MPC860 data manual. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 2-3 Section 2--M Bus Op www..com Section 2 M Mode Bus Operation Local Bus Cycles 2.2.5.2.1 Continuous Burst Mode (Bterm "Burst Terminate" Mode) If both the Burst and Bterm Mode bits are enabled, the PCI 9054 can operate beyond the Burst-4 Lword mode. Bterm mode enables the PCI 9054 to perform long bursts to special external M-mode interface devices that can accept bursts of longer than four Lwords. The PCI 9054 asserts one Address cycle and continues to burst data. The external address is incremented during bursts. If a device requires a new Address cycle, it can assert BI# input anywhere after the first Data phase to cause the PCI 9054 to assert a new Address cycle (TS#). The BI# input acknowledges the current Data transfer and requests that a new Address cycle be asserted (TS#), for the next Data transfer. If the Bterm Mode bit is enabled, the PCI 9054 de-asserts BURST# only if its Read FIFO is full, its Write FIFO is empty, or if a transfer is complete. If the transfer starts on a non quad-word aligned address, the PCI 9054 single cycles the data until the next quad-word aligned address and bursts forever the remainder of the data. The PCI 9054_AB supports the BDIP# signal for continuous bursts greater than four Lwords, which differs from MPC850/860 protocol. When Bterm and Burst functions are enabled for PCI Target and/or DMA transactions, and Slow Terminate mode is enabled for DMA, the PCI 9054 drives the BDIP# signal high until one data before the last burst transfer data. On the last data transfer, the PCI 9054 asserts BDIP# low, indicating the last transfer of the burst transaction. BDIP# is driven low for as long as data is valid on the bus and is de-asserted on the following clock, along with the BURST# signal. During Burst Forever Write transactions in M mode, the PCI 9054 passes all bytes from the PCI Bus to the Local Bus, if C/BE# begins to toggle on the nonquadaligned address by keeping TSIZ[0:1] at a constant value of 0 and issues TS# for the toggled address. However, if C/BE# toggles on the quad-word-aligned address, the PCI 9054 begins the Local Bus Burst and toggles TSIZ[0:1], along with TS#, for all data that follows when a burst resumes. It is recommended to keep all bytes enabled during a PCI Write Burst transaction. 2.2.5.3 Partial Lword Accesses Lword accesses, in which not all byte enables are asserted, are broken into Single-Cycle accesses. Burst start addresses can be any quad-word boundary. The PCI 9054 first performs a Single cycle, if the Burst Start Address in a PCI Target or DMA transfer is not aligned to a quad-word or Lword boundary. It then starts to burst on the quad-word boundary if there is remaining data that is not a whole Lword during DMA (for example, it results in a Single cycle at the end). 2.2.6 Local Bus Read Accesses For all Single-Cycle Local Bus Read accesses, the PCI 9054 reads only bytes corresponding to byte enables requested by the PCI Initiator. For all Burst Read cycles, the PCI 9054 passes all the bytes and can be programmed to: * Prefetch * Perform Read Ahead mode * Generate internal wait states * Enable external wait control (TA# input) * Enable type of Burst mode to perform 2.2.7 Local Bus Write Accesses For Local Bus writes, only bytes specified by a PCI Bus Master or the PCI 9054 DMA controller are written. 2.2.8 PCI Target Accesses to 8- or 16-Bit Local Bus Direct PCI access to an 8- or 16-bit Local Bus results in the PCI Bus Lword being broken into multiple Local Bus transfers. For each transfer, byte enables are encoded to provide Transfer Size bits (TSIZ[0:1]). 2.2.9 Local Bus Data Parity Generation or use of Local Bus data parity is optional. Signals on the data parity pins do not affect operation of the PCI 9054. The PCI Bus parity checking and generation is independent of the Local Bus parity checking and generation. PCI Bus parity checking may result in assertion of PERR#, a PCI Bus system PCI 9054 Data Book v2.1 2-4 (c) PLX Technology, Inc. All rights reserved. www..com Big Endian/Little Endian Section 2 M Mode Bus Operation error (SERR#), or other means of PCI Bus transfer termination as a result of the parity error on the PCI data address, command code, and byte enables. The Local Bus Parity Check is passive and only provides parity information to the Local processor during PCI Initiator, PCI Target, and DMA transfers. There is one data parity pin for each byte lane of the PCI 9054 data bus (DP[0:3]). "Even data parity" is asserted for each lane during Local Bus reads from the PCI 9054 and during PCI 9054 Master writes to the Local Bus. Even data parity is checked during Local Bus writes to the PCI 9054 and during PCI 9054 reads from the Local Bus. Parity is checked for each byte lane with an asserted byte enable. If a parity error is detected, TEA# is asserted in the Clock cycle following the data being checked. Parity is checked for PCI Target reads, PCI Initiator writes, and DMA Local Bus reads. The PCI 9054 sets a status bit and asserts an interrupt (TEA#) in the clock cycle following data being checked if a parity error is detected. However, the Data Parity Error Status bit and interrupt are never set or asserted unless the TA# signal is active and asserted low. This applies only when the TA# signal is disabled in the PCI 9054 register. A workaround for this is to disable the TA# Enable bit and externally pull TA# low. 2.3.2 Local Bus Big/Little Endian Mode The PCI 9054 Local Bus can be programmed to operate in Big or Little Endian mode. Table 2-11. Byte Number and Lane Cross-Reference Byte Number Big Endian 3 2 1 0 Little Endian 0 1 2 3 Byte Lane LD[31:24] LD[23:16] LD[15:8] LD[7:0] Table 2-12. Big/Little Endian Program Mode BIGEND# Pin 0 0 1 1 BIGEND Register (1=Big, 0=Little) 0 1 0 1 Endian Mode Big Big Little Big Table 2-13 lists registers which contain information about the following cycles. Table 2-13. Cycles Reference Tables Cycles Local access to the Configuration registers PCI Initiator, Memory, and I/O PCI Target Register Bits BIGEND[0] BIGEND[1] BIGEND[2], Space 0, and BIGEND[3], Expansion ROM 2.3 2.3.1 BIG ENDIAN/LITTLE ENDIAN PCI Bus Little Endian Mode PCI Bus is a Little Endian bus (that is, the address is invariant and data is Lword-aligned to the lowermost byte lane). Table 2-10. PCI Bus Little Endian Byte Lanes Byte Number 0 1 2 3 In Big Endian mode, the PCI 9054 transposes data byte lanes. Data is transferred as listed in Table 2-14 through Table 2-18. 2.3.2.1 Byte Lane AD[7:0] AD[15:8] AD[23:16] AD[31:24] 32-Bit Local Bus--Big Endian Mode Data is Lword aligned to uppermost byte lane (Data Invariance). Table 2-14. Upper Lword Lane Transfer Burst Order First transfer Byte Lane Byte 3 appears on Local Data [31:24] Byte 2 appears on Local Data [23:16] Byte 1 appears on Local Data [15:8] Byte 0 appears on Local Data [7:0] PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 2-5 Section 2--M Bus Op www..com Section 2 M Mode Bus Operation Big Endian/Little Endian Little Endian 31 BYTE 3 BYTE 2 BYTE 1 BYTE 0 0 2.3.2.3 8-Bit Local Bus--Big Endian Mode For an 8-bit Local Bus, the PCI 9054 can be programmed to use upper or lower byte lanes. Table 2-17. Upper Byte Lane Transfer Burst Order Byte Lane Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [31:24] Byte 2 appears on Local Data [31:24] Byte 3 appears on Local Data [31:24] 31 BYTE 0 BYTE 1 BYTE 2 BYTE 3 0 First transfer Second transfer Third transfer Fourth transfer Big Endian Figure 2-2. Big/Little Endian--32-Bit Local Bus Table 2-18. Lower Byte Lane Transfer Burst Order Byte Lane Byte 0 appears on Local Data [7:0] Byte 1 appears on Local Data [7:0] Byte 2 appears on Local Data [7:0] Byte 3 appears on Local Data [7:0] 2.3.2.2 16-Bit Local Bus--Big Endian Mode First transfer Second transfer Third transfer For a 16-bit Local Bus, the PCI 9054 can be programmed to use upper or lower word lanes. Table 2-15. Upper Word Lane Transfer Burst Order First transfer Fourth transfer 31 BYTE 3 Little Endian BYTE 2 BYTE 1 Second Cycle 0 BYTE 0 First Cycle Byte Lane Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [23:16] Second transfer Byte 2 appears on Local Data [31:24] Byte 3 appears on Local Data [23:16] Fourth Cycle Third Cycle 7 BYTE 0 0 0 15 23 Table 2-16. Lower Word Lane Transfer Burst Order First transfer Byte Lane Byte 0 appears on Local Data [15:8] Byte 1 appears on Local Data [7:0] Second transfer Byte 2 appears on Local Data [15:8] Byte 3 appears on Local Data [7:0] 16 7 0 BYTE 0 31 24 7 0 BYTE 0 Big Endian 7 0 Figure 2-4. Big/Little Endian--8-Bit Local Bus 8 7 BYTE 0 31 BYTE 3 Little Endian BYTE 2 BYTE 1 First Cycle 0 BYTE 0 15 Second Cycle 0 BYTE 0 BYTE 1 0 Big Endian 31 BYTE 0 15 Big Endian BYTE 1 15 16 0 Figure 2-3. Big/Little Endian--16-Bit Local Bus PCI 9054 Data Book v2.1 2-6 (c) PLX Technology, Inc. All rights reserved. www..com Serial EEPROM Section 2 M Mode Bus Operation 2.3.2.4 Local Bus Big/Little Endian Mode Accesses 2.4.1.2 Local Initialization For each of the following transfer types, the PCI 9054 Local Bus can be independently programmed to operate in Little Endian or Big Endian mode: * Local Bus accesses to the PCI 9054 Configuration registers * PCI Target PCI accesses to Local Address Space 0 * PCI Target PCI accesses to Local Address Space 1 * PCI Target PCI accesses to the Expansion ROM * DMA Channel 0 accesses to the Local Bus * DMA Channel 1 accesses to the Local Bus * PCI Initiator accesses to the PCI Bus For Local Bus accesses to the Internal Configuration registers and PCI Initiator accesses, use BIGEND# to dynamically change the Endian mode. Notes: The PCI Bus is always Little Endian. Only byte lanes are swapped, not individual bits. The PCI 9054 issues a Retry to all PCI accesses until the Local Init Status bit (LMISC[2]) is set. This bit can be programmed three different ways: 1. 2. By the Local processor, through the Local Configuration register. By the serial EEPROM, during a serial EEPROM load, if the Local processor does not set this bit or if this bit is missing. If the Local processor and/or the serial EEPROM are missing, the serial EEPROM remains blank and the PCI 9054 reverts to the default values and sets this bit (refer to Table 2-19). 3. 2.4.2 Serial EEPROM Operation 2.4 SERIAL EEPROM Functional operation described can be modified through the PCI 9054 programmable internal registers. 2.4.1 Vendor and Device ID Registers Three Vendor and Device ID registers are supported: * PCIIDR--Contains normal Device and Vendor IDs. Can be loaded from the serial EEPROM or Local processor(s). * PCISVID--Contains Subsystem and Subvendor IDs. Can be loaded from the serial EEPROM or Local processor(s). * PCIHIDR--Contains hardcoded PLX Vendor and Device IDs. After reset, the PCI 9054 attempts to read the serial EEPROM to determine its presence. An active Start bit set to 0 indicates a serial EEPROM is present. The PCI 9054 supports 93CS56L (2K bit) or 93CS66L (4K bit). (Refer to manufacturer's data sheet for the particular serial EEPROM being used.) The first Lword is then checked to verify that the serial EEPROM is programmed. If the first Lword (33 bits) is all ones, a blank serial EEPROM is present. If the first Lword (33 bits) is all zeros, no serial EEPROM is present. For both conditions, the PCI 9054 reverts to the default values. (Refer to Table 2-19.) CNTRL[28] is set to 1 if programmed (real or random data if a serial EEPROM is detected). The 3.3V serial EEPROM clock (EESK) is derived from the PCI clock. The PCI 9054 generates the serial EEPROM clock by internally dividing the PCI clock by 132. The serial EEPROM can be read or written from the PCI or Local Buses. The Serial EEPROM Control Register bits (CNTRL[28:24]) control the PCI 9054 pins that enable reading or writing of serial EEPROM data bits. (Refer to manufacturer's data sheet for the particular serial EEPROM being used.) The PCI 9054_AB revision provides the ability to manually access the serial EEPROM. This may be accomplished by using bits 24 through 27 of the CNTRL register (EESK, EECS, and EEDI/EEDO, controlled by software). Bit 24 is used to generate EESK (clock), bit 25 controls the chip select, and bit 26 sets/clears EEDI. Bit 27, when read, returns the value of EEDO. 2.4.1.1 Serial EEPROM Initialization During serial EEPROM initialization, the PCI 9054 responds to PCI Target accesses with a Retry. During serial EEPROM initialization, the PCI 9054 responds to a Local processor access by delaying acknowledgement of the cycle (TA#). PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 2-7 Section 2--M Bus Op www..com Section 2 M Mode Bus Operation Serial EEPROM Setting bits 24, 25, and 26 to 1, causes the output to go high. A pull-up resistor is required on EEDO to go high when bit 26 is set. When reading the serial EEPROM, bit 26 must be set to 1. To perform the read, the basic approach is to set the EECS and EEDO bits (bits 25 and 26) to the desired level and then toggle EESK high and low until done. For example, reading the serial EEPROM at location 0 involves the following steps: Table 2-19. Serial EEPROM Guidelines Local Processor None Serial EEPROM None System Boot Condition The PCI 9054 uses default values. The EEDI/EEDO pin must be pulled low--a 1 K-ohm resistor is required (rather than pulled high, which is typically done for this pin). If the PCI 9054 detects all zeros, it reverts to default values. None 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Clear EESK, EEDO and EECS bits. Toggle EESK high, then low. Set EECS high. Toggle EESK high, then low. Set EEDO bit high (start bit). Toggle EESK high, then low. Repeat step 6. Clear EEDO. Toggle EESK bit high, then low eight times (clock in Local Address 0). Set EEDO to float the EEDO pin for reading. Toggle EESK high, then low 16 times (clock in one word from serial EEPROM). After each clock pulse, read bit 27 and save. Clear EECS bit. Toggle EESK high, then low. Read is now complete. Present Present None Present Programmed Boot with serial EEPROM values. The Local Init Status bit (LMISC[2]) must be set by the serial EEPROM. Blank None The PCI 9054 detects a blank device and reverts to default values. The Local processor programs the PCI 9054 registers, then sets the Local Init Status bit (LMISC[2]=done). Note: Some systems may hang if PCI Target reads and writes take too long (during initialization, the PCI Host also performs PCI Target accesses). The value of the PCI Target Retry Delay Clocks (LBRD0[31:28]) may resolve this. Programmed Load serial EEPROM, but the Local processor can reprogram the PCI 9054. Either the Local processor or the serial EEPROM must set the Local Init Status bit (LMISC[2]=done). Blank The PCI 9054 detects a blank serial EEPROM and reverts to default values. Notes:In some systems, the Local processor may be too late to reconfigure the PCI 9054 registers before the BIOS configures them. The serial EEPROM can be programmed through the PCI 9054 after the system boots in this condition. The serial EEPROM can also be read or written, using the VPD function (refer to Section 10). The PCI 9054 has two serial EEPROM load options: * Long Load Mode--Default. The PCI 9054 loads 17 Lwords from the Serial EEPROM and the Extra Long Load bit (LBRD0[25]) * Extra Long Load Mode--The PCI 9054 loads 22 Lwords if the Serial EEPROM and the Extra Long Load bit (LBRD0[25]) is set to 1 during a Long Load 2.4.2.1 Long Serial EEPROM Load The registers listed in Table 2-20 are loaded from the serial EEPROM after a reset is de-asserted if the Serial EEPROM Extra Long Load bit is not set (LBRD0[25]=0). The serial EEPROM is organized in words (16 bit). The PCI 9054 first loads the Most Significant Word bits (MSW[31:16]), starting from the most significant bit ([31]). The PCI 9054 then loads the Least Significant Word bits (LSW[15:0]), starting again from the most significant bit ([15]). Therefore, the PCI 9054 loads the Device ID, Vendor ID, class code, and so forth. PCI 9054 Data Book v2.1 2-8 (c) PLX Technology, Inc. All rights reserved. www..com Serial EEPROM Section 2 M Mode Bus Operation The serial EEPROM values can be programmed using a Data I/O programmer. The values can also be programmed using the PCI 9054 VPD function (refer to Section 10) or through the Serial EEPROM Control register (CNTRL). The CNTRL register allows programming of the serial EEPROM, one bit at a time. To read back the value Table 2-20. Long Serial EEPROM Load Registers Serial EEPROM Offset 0h 2h 4h 6h 8h Ah Ch Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h Device ID Vendor ID Class Code Class Code / Revision Maximum Latency / Minimum Grant Interrupt Pin / Interrupt Line Routing MSW of Mailbox 0 (User Defined) LSW of Mailbox 0 (User Defined) MSW of Mailbox 1 (User Defined) LSW of Mailbox 1 (User Defined) MSW of Range for PCI-to-Local Address Space 0 LSW of Range for PCI-to-Local Address Space 0 from the serial EEPROM, the CNTRL[27] bit (refer to Section 2.4.2) or the VPD function should be utilized. With full utilization of VPD, the designer can perform reads and writes from/to the serial EEPROM, 32 bits at a time. Values should be programmed in the order listed in Table 2-20. The 34, 16-bit words listed in the table are stored sequentially in the serial EEPROM. Description Register Bits Affected PCIIDR[31:16] PCIIDR[15:0] PCICCR[23:8] PCICCR[7:0] / PCIREV[7:0] PCIMLR[7:0] / PCIMGR[7:0] PCIIPR[7:0] / PCIILR[7:0] MBOX0[31:16] MBOX0[15:0] MBOX1[31:16] MBOX1[15:0] LAS0RR[31:16] LAS0RR[15:0] LAS0BA[31:16] LAS0BA[15:0] MARBR[31:16] MARBR[15:0] PROT_AREA[15:0] LMISC[7:0] / BIGEND[7:0] EROMRR[31:16] EROMRR[15:0] EROMBA[31:16] EROMBA[15:0] LBRD0[31:16] LBRD0[15:0] DMRR[31:16] DMRR[15:0] DMLBAM[31:16] DMLBAM[15:0] DMLBAI[31:16] DMLBAI[15:0] DMPBAM[31:16] DMPBAM[15:0] DMCFGA[31:16] DMCFGA[15:0] MSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 MSW of Mode/DMA Arbitration Register LSW of Mode/DMA Arbitration Register MSW of Serial EEPROM Write-Protected Address LSW of Local Miscellaneous Control Register / LSW of Local Bus Big/Little Endian Descriptor Register MSW of Range for PCI-to-Local Expansion ROM LSW of Range for PCI-to-Local Expansion ROM MSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM LSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM MSW of Bus Region Descriptors for PCI-to-Local Accesses LSW of Bus Region Descriptors for PCI-to-Local Accesses MSW of Range for PCI Initiator-to-PCI LSW of Range for PCI Initiator-to-PCI MSW of Local Base Address for PCI Initiator-to-PCI Memory LSW of Local Base Address for PCI Initiator-to-PCI Memory MSW of Local Bus Address for PCI Initiator-to-PCI I/O Configuration LSW of Local Bus Address for PCI Initiator-to-PCI I/O Configuration MSW of PCI Base Address (Remap) for PCI Initiator-to-PCI LSW of PCI Base Address (Remap) for PCI Initiator-to-PCI MSW of PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration LSW of PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 2-9 Section 2--M Bus Op www..com Section 2 M Mode Bus Operation Serial EEPROM 2.4.2.2 Extra Long Serial EEPROM Load significant bit ([15]). Therefore, the PCI 9054 loads Device ID, Vendor ID, class code, and so forth. The serial EEPROM values can be programmed using a Data I/O programmer. The values can also be programmed using the PCI 9054 VPD function or through the Serial EEPROM Control register (CNTRL). Values should be programmed in the order listed in Table 2-21. The 44 16-bit words listed in Table 2-20 and Table 2-21 should be stored sequentially in the serial EEPROM. The registers listed in the Local Address Space 0/ Expansion ROM Bus Region Descriptor register (LBRD0) are loaded from serial EEPROM after a reset is de-asserted if the Serial EEPROM Extra Long Load bit is set (LBRD0[25]=1). The serial EEPROM is organized in words (16 bit). The PCI 9054 first loads the Most Significant Word bits ([31:16]), starting from the most significant bit ([31]). It then loads the Least Significant Word bits ([15:0]), restarting from the most Table 2-21. Extra Long Serial EEPROM Load Registers Serial EEPROM Offset 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h Subsystem ID Subsystem Vendor ID Description Register Bits Affected PCISID[15:0] PCISVID[15:0] LAS1RR[31:16] LAS1RR[15:0] LAS1BA[31:16] LAS1BA[15:0] LBRD1[31:16] LBRD1[15:0] Reserved HS_NEXT[7:0] / HS_CNTL[7:0] MSW of Range for PCI-to-Local Address Space 1 (1 MB) LSW of Range for PCI-to-Local Address Space 1 (1 MB) MSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 MSW of Bus Region Descriptors (Space 1) for PCI-to-Local Accesses LSW of Bus Region Descriptors (Space 1) for PCI-to-Local Accesses MSW of Hot Swap Control/Status LSW of Hot Swap Control / Hot Swap Next Capability Pointer 2.4.2.3 New Capabilities Function Support 2.4.2.4 Recommended Serial EEPROMs The New Capabilities Function Support includes PCI Power Management, Hot Swap, and VPD features, as listed in Table 2-22. Table 2-22. New Capabilities Function Support Features New Capability Function First (Power Management) The PCI 9054 is designed to use either a 2K bit (NM93CS56L or compatible) or 4K bit (NM93CS66L or compatible) device. Note: The PCI 9054 does not support serial EEPROMs that do not support sequential reads and writes (such as the NM93C56L). PCI Register Offset Location 40'h, if the New Capabilities Function Support bit (PCISR[4]) is enabled (PCISR[4] is enabled, by default). 48'h, which is pointed to from PMNEXT[7:0]. 4C'h, which is pointed to from HS_NEXT[7:0]. Because PVPD_NEXT[7:0] defaults to zero, this indicates that VPD is the last New Capability Function Support feature of the PCI 9054. Second (Hot Swap) Third (VPD) PCI 9054 Data Book v2.1 2-10 (c) PLX Technology, Inc. All rights reserved. www..com Serial EEPROM Section 2 M Mode Bus Operation 4096 100h PCI Bus Master Local Bus Master 2048 80h PCI 9054 PCI Configuration Registers VPD 1536 60h (PROT_AREA register default) 2Ch Empty 704 Local Configuration Registers DMA Registers Mailbox Registers Extra Long PCI Interrupt Set Clear Long Load 0 0 PCI-to-Local Doorbell Register Local-to-PCI Doorbell Register Messaging Queue Registers Power Management Registers Set # of bits # of words Figure 2-5. Serial EEPROM Memory Map 2.4.2.5 Serial EEPROM Initialization Hot Swap Registers VPD Registers During serial EEPROM initialization, the PCI 9054 responds to PCI Target accesses with a Retry. During serial EEPROM initialization, the PCI 9054 responds to a Local processor access by delaying acknowledgement of the cycle (TA#). Figure 2-6. PCI 9054 Internal Register Access 2.4.3.1 PCI Bus Access to Internal Registers 2.4.3 Internal Register Access The PCI 9054 provides several internal registers, which allow for maximum flexibility in the bus interface design and performance. These registers are accessible from the PCI and Local Buses and include the following: * PCI and Local Configuration registers * DMA registers * Mailbox registers * PCI-to-Local and Local-to-PCI Doorbell registers * Messaging Queue registers (I2O) * Power Management registers * Hot Swap registers * VPD registers Figure 2-6 accessed. illustrates how these registers are The PCI 9054 PCI Configuration registers can be accessed from the PCI Bus with a Configuration Type 0 cycle. All other PCI 9054 internal registers can be accessed by a Memory cycle, with the PCI Bus address that matches the base address specified in PCI Base Address 0 (PCIBAR0[31:8]) for the PCI 9054 MemoryMapped Configuration register. These registers can also be accessed by an I/O cycle, with the PCI Bus address matching the base address specified in PCI Base Address 1 for the PCI 9054 I/O-Mapped Configuration register (PCIBAR1). All PCI Read or Write accesses to the PCI 9054 registers can be Byte, Word, or Lword accesses. All PCI Memory accesses to the PCI 9054 registers can be Burst or Non-Burst accesses. The PCI 9054 responds with a PCI disconnect for all Burst I/O accesses (PCIBAR1[31:8]) to the PCI 9054 Internal registers. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 2-11 Local Interrupt 544 22h Clear Section 2--M Bus Op www..com Section 2 M Mode Bus Operation Serial EEPROM 2.4.3.2 Local Bus Access to Internal Registers Address Mode Pin PCI 9054 CCS# (PCI 9054 Chip Select) The Local processor can access all PCI 9054 internal registers through an external chip select. The PCI 9054 responds to a Local Bus access when the PCI 9054 Configuration Chip Select input (CCS#) is asserted low. Figure 2-7 illustrates how the Configuration Chip Select logic works. Notes: CCS# must be decoded while TS# is low. Accesses must be for a 32-bit non-pipelined bus. Local Read or Write accesses to the PCI 9054 internal registers can be Byte, Word, or Lword accesses. Local accesses to the PCI 9054 internal registers can be Burst or Non-Burst accesses. The PCI 9054 TA# signal indicates that Data transfer is complete. PCI 9054 Internal Register Chip Select Figure 2-7. Address Decode Mode PCI 9054 Data Book v2.1 2-12 (c) PLX Technology, Inc. All rights reserved. www..com Serial EEPROM Section 2 M Mode Bus Operation 2.4.4 Serial EEPROM Timing Diagrams 0us 5us 10us 15us 20us 25us 30us EESK LRESETo# EEDI EEDO 0 1 1 0 0 0 0 0 0 0 0 0 INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----| 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] CONFIGURATION REGISTER 0 HEX EESK EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 BITS [15:0] CONFIGURATION REGISTER 0 HEX BITS [31:16] OF CONFIGURATION REGISTER 8 HEX CONTINUES EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LAST WORD CONTINUES EESK, EEDO, EECS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ Timing Diagram 2-1. Initialization from Serial EEPROM (2K Bit) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 2-13 Section 2--M Bus Op EECS www..com Section 2 M Mode Bus Operation Serial EEPROM 0us 5us 10us 15us 20us 25us 30us EESK LRESETo# EECS EEDI EEDO 0 1 1 0 0 0 0 0 0 0 0 0 INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----| 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] CONFIGURATION REGISTER 0 HEX EESK EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 BITS [15:0] CONFIGURATION REGISTER 0 HEX BITS [31:16] OF CONFIGURATION REGISTER 8 HEX CONTINUES EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LAST WORD CONTINUES EESK, EEDO, EECS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ Timing Diagram 2-2. Initialization from Serial EEPROM (4K Bit) 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=B Data BE Timing Diagram 2-3. PCI Configuration Write to PCI Configuration Register PCI 9054 Data Book v2.1 2-14 (c) PLX Technology, Inc. All rights reserved. www..com Serial EEPROM Section 2 M Mode Bus Operation 0ns 50ns 100ns 150ns 200ns 250ns 300n CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=A Data Read BE Timing Diagram 2-4. PCI Configuration Read to PCI Configuration Register 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=7 Data BE Timing Diagram 2-5. PCI Memory Write to Local Configuration Register PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 2-15 Section 2--M Bus Op www..com Section 2 M Mode Bus Operation Serial EEPROM 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=6 BE Data Read Timing Diagram 2-6. PCI Memory Read to Local Configuration Register 0ns 100ns 200ns 300ns 400ns 500n CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR DATA CMD BE INTA# RESPONSE ON THE PCI BUS LCLK LINT# Timing Diagram 2-7. Local Interrupt Asserting PCI Interrupt PCI 9054 Data Book v2.1 2-16 (c) PLX Technology, Inc. All rights reserved. www..com 3 M MODE FUNCTIONAL DESCRIPTION 3.3 RESPONSE TO FIFO FULL OR EMPTY The functional operation described in this chapter can be modified through the PCI 9054 programmable internal registers. 3.1 3.1.1 RESET OPERATION PCI Bus Input RST# Table 3-1 lists the PCI 9054 response to full and empty FIFOs. 3.4 DIRECT DATA TRANSFER MODES PCI Bus RST# input pin is a PCI Host reset. It causes all PCI Bus outputs to float, resets the entire PCI 9054 and causes the Local reset LRESETo# signal to be asserted. The PCI 9054 supports three direct transfer modes: * PCI InitiatorLocal CPU accesses PCI memory or I/O * PCI TargetPCI Master accesses Local memory or I/O * DMAPCI 9054 DMA controller reads/writes PCI memory to/from Local memory 3.1.2 Software Reset A Host on the PCI Bus can set the PCI Adapter Software Reset bit (CNTRL[30]=1) to reset the PCI 9054 and assert LRESETo# output. All Local Configuration registers are reset; however, the PCI Configuration DMA and Shared Runtime registers and the Local Init Status bit (LMISC[2]) are not reset. When the Software Reset bit (CNTRL[30]) is set, the PCI 9054 responds to PCI accesses, but not to Local Bus accesses. The PCI 9054 remains in this reset condition until the PCI Host clears the bit. The serial EEPROM is reloaded if the Reload Configuration Registers bit is set (CNTRL[29]=1). Note: The Local Bus cannot clear this reset bit because the Local Bus is in a reset state, even if the Local processor does not use LRESETo# to reset. The PCI 9054 supports a direct access of the PCI Bus by the Local processor or an intelligent controller. Master mode must be enabled in the PCI Command register. The following registers define Local-to-PCI accesses: * PCI Initiator Memory and I/O Range (DMRR) * Local Base Address for PCI Initiator-to-PCI Memory (DMLBAM) * Local Base Address for PCI Initiator-to-PCI I/O and Configuration (DMLBAI) * PCI Base Address (DMPBAM) * PCI Initiator Configuration (DMCFGA) * PCI Initiator PCI Dual Address Cycles (DMDAC) * Master Enable (PCICR) * PCI Command Code (CNTRL) 3.2 PCI 9054 INITIALIZATION The PCI 9054 Configuration registers can be programmed by an optional serial EEPROM and/or by a Local processor, as listed in Table 2-19. The serial EEPROM can be reloaded by setting the Reload Configuration Registers bit (CNTRL[29]). The PCI 9054 retries all PCI cycles until the Local Init Status bit is set to "done" (LMISC[2]=1). Note: The PCI Host processor can also access Internal Configuration registers after the Local Init Status bit is set. If a PCI Host is present, the Master Enable, Memory Space, and I/O Space bits (PCICR[2:0]) are programmed by that Host after initialization completes (LMISC[2]=1). PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-1 Section 3--M Func Desc 3.4.1 PCI Initiator Operation (Local Master-to-PCI Target) www..com Section 3 M Mode Functional Description Direct Data Transfer Modes Table 3-1. Response to FIFO Full or Empty Mode PCI Initiator Write Direction Local-to-PCI FIFO Full Empty Full Empty Full Empty Full Empty Full Empty Full Empty Normal PCI Bus De-assert REQ# (off the PCI Bus) De-assert REQ# or throttle Normal Disconnect or throttle TRDY#3 Normal Normal Throttle TRDY# Normal De-assert REQ# De-assert REQ# Normal 3 Local Bus De-assert TA#, RETRY#1 Normal Normal De-assert TA# Normal De-assert BB#4 De-assert BB#4 Normal De-assert BB#4 Normal Normal De-assert BB#4 IRDY#2 PCI Initiator Read PCI-to-Local PCI Target Write PCI-to-Local PCI Target Read Local-to-PCI Local-to-PCI DMA PCI-to-Local 1. Issue RETRY# depends upon the PCI Initiator Write FIFO Almost Full RETRY# Output Enable bit (LMISC[6]). 2. Throttle IRDY# depends upon the PCI Initiator PCI Read Mode bit (DMPBAM[4]). 3. Throttle TRDY4 depends upon the PCI Target Write Mode bit (LBRD0[27]). 4. BB# de-assert depends upon the Local Bus PCI Target Release Bus Mode bit (MARBR[21]). PCI 9054 Data Book v2.1 3-2 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 3 M Mode Functional Description PCI Bus Master Local Processor 1 Initialize Local PCI Initiator Access Registers Local Range for PCI Initiator-to-PCI Local Base Address for PCI Initiator-to-PCI Memory PCl Base Address (Remap) for PCI Initiator-to-PCI Local Base Address for PCI Initiator-to-PCI I/O Configuration I/O or Configuration 0 = I/O 1 = Configuration PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration PCI Command Register 3 PCI Bus Access 2 FIFOs 32-Lword Deep Write 16-Lword Deep Read Local Base Address for PCI Initiatorto-PCI Memory Space Local Bus Access Local Memory PCI Address Space PCI Base Address Memory Command Range Local Base Address for PCI Initiator-toPCI I/O Configuration I/O Command Range Figure 3-1. PCI Initiator Access of the PCI Bus 3.4.1.1 PCI Initiator Memory and I/O Decode The Range register and the Local Base Address specifies the Local Address bits to use for decoding a Local-to-PCI access (PCI Initiator). The range of Memory or I/O space must be a power of 2 and the Range register value must be the inverse of the range value. In addition, the Local Base Address must be a multiple of the range value. Any Local Master Address starting from the PCI Initiator Local Base Address (Memory or I/O) to the range value is recognized as a PCI Initiator access by the PCI 9054. All PCI Initiator cycles are then decoded as PCI Memory, I/O, or Configuration Type 0 or 1. Moreover, a PCI Initiator Memory or I/O cycle is remapped according to the Remap register value. The Remap Register value must be a multiple of the PCI Initiator Range value (not the Range register value). The PCI 9054 can only accept Memory cycles from a Local processor. The Local Base Address and/or the range determine whether PCI Memory or PCI I/O transactions occur. 3.4.1.2 PCI Initiator FIFOs For PCI Initiator Memory access to the PCI Bus, the PCI 9054 has a 32-Lword (128-byte) Write FIFO and a 16-Lword (64-byte) Read FIFO. The FIFOs enable the Local Bus to operate independent of the PCI Bus and PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-3 Section 3--M Func Desc www..com Section 3 M Mode Functional Description Direct Data Transfer Modes allows high-performance bursting on the PCI and Local Buses. In a PCI Initiator write, the Local processor (Master) writes data to the PCI Bus (Slave). In a PCI Initiator read, the Local processor (Master) reads data from the PCI Bus (Slave). The FIFOs that function during a PCI Initiator write and read are illustrated in Figure 3-2 and Figure 3-3. Slave Master Slave LA, TS#, TSIZ, LD, RD/WR#, BURST#, BI#, BDIP# Master Transactions are initiated by the MPC850 or MPC860 (a Local Bus Master) when the memory address on the Local Bus matches the Memory space decoded for PCI Initiator operations. Upon a Local Bus Read, the PCI 9054 becomes a PCI Bus Master, arbitrates for the PCI Bus, and reads data from the PCI Target directly into the PCI Initiator Read FIFO. When sufficient data is placed into the FIFO, it asserts the Transfer Acknowledge (TA#) signal onto the Local Bus to indicate that the requested data is on the Local Bus. The Local processor can read or write to PCI memory. The PCI 9054 converts the Local Read/Write access. The Local Address space starts from PCI Initiator Local Base Address up to the range. Remap (PCI Base Address) defines PCI starting address. An MPC850 or MPC860 Single cycle causes a SingleCycle PCI transaction. An MPC850 or MPC860 Burst cycle asserts a Burst PCI Cycle transaction. Bursts are limited to 16 bytes (four Lwords) in the MPC850 or MPC860. The PCI 9054 supports bursts beyond the 16-byte boundary (Continuous Burst) when the BDIP# input signal remains asserted beyond a 16-byte boundary by an external Local Bus Master. To finish, continuing burst and the external Master should de-assert the BDIP# signal on the last Data phase. Writes--Upon a Local Bus Write, the Local Bus Master writes data to the PCI Initiator Write FIFO. When the first data is in the FIFO, the PCI 9054 becomes the PCI Bus Master, arbitrates for the PCI Bus, and writes data to the PCI Target device. The PCI 9054 continues to accept writes and returns TA# until the Write FIFO is full. It then holds off TA# until space becomes available in the Write FIFO. A programmable PCI Initiator "almost full" status output is provided (MDREQ#/DMPAF/EOT#). The PCI 9054 asserts RETRY# whenever the PCI Initiator Write FIFO is full, implying that the Local Master can relinquish the bus and finish the Write operation at a later time (LMISC[6]). Reads--The PCI 9054 holds off TA# while gathering an Lword from the PCI Bus. Programmable Prefetch modes are available if prefetch is enabled: prefetch, 4, 8, 16, or continuous until the PCI Initiator cycle ends. The Read cycle is terminated when the Local BDIP# input is de-asserted. Unused Read data is flushed from the FIFO. REQ# TA# PCI Bus GNT# FRAME#, C/BE# AD (addr) IRDY# DEVSEL#, TRDY# AD (data) PCI 9054 RETRY#, TEA# (Optional) Figure 3-2. PCI Initiator Write Slave Master Slave TS#, BI#, RD/WR#, TSIZ, BURST#, BDIP# Master REQ# GNT# IRDY# DEVSEL#, TRDY#, AD (data) PCI 9054 LD, TA# RETRY#, TEA# (Optional) Figure 3-3. PCI Initiator Read Note: The figures represent a sequence of Bus cycles. 3.4.1.3 PCI Initiator Memory Access The MPC850 or MPC860 transfers data through a Single or Burst Read/Write Memory transaction, or through SDMA channels to the PCI 9054 and PCI Bus. The MPC850 or MPC860 IDMA/SDMA accesses to the PCI 9054 appear as PCI Initiator operations. (Refer to Section 3.4.2 for further information.) Local Bus PCI Bus FRAME#, C/BE#, AD (addr) Local Bus PCI 9054 Data Book v2.1 3-4 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 3 M Mode Functional Description The PCI 9054 does not prefetch Read data for single cycle PCI Initiator reads (Local BURST# input is not asserted during the first Data phase). In this case, the PCI 9054 reads a single PCI Lword unless PCI Initiator Read Ahead mode is enabled. For PCI Initiator Single-Cycle reads, the PCI 9054 sets the corresponding PCI Bus byte enables from the Local Bus address and the TSIZ[0:1] signal. For Burst-Cycle reads, the PCI 9054 reads entire Lwords (all PCI Bus byte enables are asserted). If the PCI Initiator Prefetch Limit bit is enabled (DMPBAM[11]=1), the PCI 9054 does not prefetch past a 4 KB boundary. Also, the Local Bus must not cross a 4 KB boundary during a Burst read. The PCI 9054 never prefetches beyond the region specified for PCI Initiator accesses. 3.4.1.6 RETRY# Capability 3.4.1.6.1 PCI Initiator Write FIFO Full The PCI 9054 supports the PCI Initiator Write FIFO full condition. When enabled (LMISC[6]=1), the PCI 9054 asserts the RETRY# signal to the Local Bus Master to relinquish ownership of the bus and return to finish the initial write at a later time. In a PCI Initiator Write FIFO full condition, the PCI 9054 asserts the RETRY# signal. Otherwise, the PCI Initiator Write transfer goes through successfully. 3.4.1.6.2 PCI Initiator Delayed Read The PCI 9054 supports Deferred PCI Initiator Read transactions. When the M Mode PCI Initiator Deferred Read Enable bit is set (LMISC[4]=1), the PCI 9054 asserts RETRY# and prefetches Read data every time the Local Master requests a read. During a PCI data prefetch, the Local Master is capable of doing other transactions and free to return for requested data at a later time. When Deferred PCI Initiator Read mode is disabled, the Local Master must "keep" the Local Bus and wait for the requested data (TA# is not asserted until data is available to the Local Bus). 3.4.1.4 PCI Initiator I/O Configuration Access When a Local PCI Initiator I/O access to the PCI Bus occurs, the PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration Enable bit (DMCFGA[31]) determines whether an I/O or Configuration access is to be made to the PCI Bus. Local Burst accesses are broken into single PCI I/O (address/data) cycles. The PCI 9054 does not prefetch Read data for I/O and configuration reads. For PCI Initiator I/O or Configuration cycles, the PCI 9054 asserts the same PCI Bus byte enables as set on the Local Bus. 3.4.1.7 PCI Initiator Configuration (PCI Configuration Type 0 or Type 1 Cycles) 3.4.1.5 PCI Initiator I/O If the Configuration Enable bit is cleared (DMCFGA[31]=0), a single I/O access is made to the PCI Bus. The Local Address, Remapped Decode Address Bits, and Local byte enables are encoded to provide the address and are output with an I/O read or write command during a PCI Address cycle. When the I/O Remap Select bit is set (DMPBAM[13]=1), the PCI Address bits [31:16] are forced to 0 for the 64 KB I/O address limit. For writes, data is loaded into the Write FIFO and TA# is returned to the Local Bus. For reads, the PCI 9054 holds off TA# while receiving an Lword from the PCI Bus. If the Configuration Enable bit (DMCFGA[31]) is set, a Configuration access is made to the PCI Bus. In addition to enabling configuration of this bit, the user must provide all register information. The Register Number and Device Number bits (DMCFGA[7:2] and DMCFGA[15:11], respectively) must be modified and a new Configuration Read/Write cycle must be performed before accessing other registers or devices. If the PCI Configuration Address register selects a Type 0 command, bits [10:0] of the register are copied to address bits [10:0]. Bits [15:11] (device number) are translated into a single bit being set in the PCI Address bits [31:11]. The PCI Address bits [31:11] can be used as a device select. For a Type 1 command, bits [23:0] are copied from the register to bits [23:0] of the PCI address. The PCI Address bits [31:24] are set to 0. A configuration read or write command code is output with the address during the PCI Address cycle (refer to the DMCFGA register). PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-5 Section 3--M Func Desc www..com Section 3 M Mode Functional Description Direct Data Transfer Modes For writes, Local data is loaded into the Write FIFO and TA# is returned. For reads, the PCI 9054 holds off TA# while gathering an Lword from the PCI Bus. 3.4.1.7.1 PCI Initiator Configuration Cycle Example To perform a Type 0 Configuration cycle to PCI device on AD[21]: 1. The PCI 9054 must be configured to allow PCI Initiator access to the PCI Bus. The PCI 9054 must also be set to respond to I/O Space accesses. These bits must be set (PCICR[2:0]=111b). In addition, PCI Initiator memory and I/O access must be enabled (DMPBAM[1:0]=11). 2. The Local Memory map selects the PCI Initiator range. For this example, use a range of 1 MB: 1 MB = 220 = 000FFFFFh 3. The value to program into the Range register is the inverse of 000FFFFFh (FFF00000h): DMRR = FFF00000h 4. The Local Memory map determines the Local Base Address for the PCI Initiator-to-PCI I/O Configuration register. For this example, use 40000000h: DMLBAI = 40000000h 5. The PCI Address (Remap) for PCI Initiator-to-PCI Memory register must enable the PCI Initiator I/O access. The PCI Initiator I/O Access Enable bit must be set (DMPBAM[1]=1). The user must know which PCI device and PCI Configuration register the PCI Configuration cycle is accessing. This example assumes the IDSEL signal of the Target PCI device is connected to AD[21] (logical device #10=0Ah). Also access PCIBAR0 (the fourth register, counting from 0; use Table 11-2 for reference). Set DMCFGA[31, 23:0] as follows: Bit 1:0 After these registers are configured, a simple Local Master Memory cycle to the I/O base address is necessary to generate a PCI Configuration Read or Write cycle. Offset to the base address is not necessary because the register offset for the read or write is specified in the Configuration register. The PCI 9054 takes the Local Bus Master Memory cycle and checks for the Configuration Enable bit (DMCFGA[31]). If set, the PCI 9054 converts the current cycle to a PCI Configuration cycle, using the DMCFGA register and the Write/Read signal (RD/WR#). The Register Number and Device Number bits (DMCFGA[7:2] and DMCFGA[15:11], respectively) must be modified and a new Configuration Read/ Write cycle must be performed before accessing other registers or devices. 3.4.1.8 PCI Initiator PCI Dual Address Cycle 6. The PCI 9054 supports PCI Dual Address Cycle (DAC) when it is a PCI Bus Master using the DMDAC register for PCI Initiator transactions. The DAC command is used to transfer a 64-bit address to devices that support 64-bit addressing when the address is not in the low 4-GB Address space. The PCI 9054 performs the address portion of a DAC in two PCI clock periods, where the first PCI address is a Lo-Addr with the command (C/BE[3:0]#) "D" and the second PCI address will be a Hi-Addr with the command (C/BE[3:0]#) "6" or "7", depending upon it being a PCI Read or a PCI Write cycle. Whenever the DMDAC register contains a value of 0x00000000, the PCI 9054 performs a Single Address Cycle (SAC) on the PCI Bus. (Refer to Figure 3-4.) Description Configuration Type 0. Register Number. Fourth register. Must program a "4" into this value, beginning with bit 2. Function Number. Device Number n-11, where n is the value in AD[n]=21-11 = 10. Bus Number. Configuration Enable. Value 00b 7:2 000100b 10:8 15:11 23:16 31 000b 01010b 00000000b 1 PCI 9054 Data Book v2.1 3-6 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 3 M Mode Functional Description Set DMA Mode to Block Mode Register PCI Host Memory Set up Transfer Parameters Single Address--PCI Address Register Dual Address--PCI Addresses Register Local Address Register Transfer Size (byte count) Register Descriptor Pointer Register (set direction only) Memory Block to Transfer Local Memory Memory Block to Transfer Command/Status Register Figure 3-4. Block DMA Mode Initialization (Single Address or Dual Address PCI) 3.4.1.9 PCI Initiator/Target Abort The PCI 9054 PCI Initiator/Target Abort logic enables a Local Bus Master to perform a PCI Initiator Bus poll of devices to determine whether devices exist (typically when the Local Bus performs Configuration cycles to the PCI Bus). When a PCI Master device attempts to access and does not receive DEVSEL# within six PCI clocks, it results in a Master Abort. The Local Bus Master must clear the Received Master Abort bit or Target Abort bit (PCISR[13 or 11]=0, respectively) and continue by processing the next task. If a PCI Master/Target Abort, or Retry Time-Out is encountered during a transfer, the PCI 9054 asserts TEA# if enabled [(INTCSR[1:0]=1), which can be used as a Non-Maskable Interrupt (NMI)]. If a Local Bus Master is waiting for TA#, it is asserted along with TEA#. The interrupt handler of the Local Bus Master can take the appropriate application-specific action. It can then clear the Target Abort bit (PCISR[11]) to clear the TEA# interrupt and re-enable PCI Initiator transfers. If a Local Bus Master is attempting a Burst read from a nonresponding PCI device (Master/Target Abort), it receives TA# for the first cycle only. In addition, the PCI 9054 asserts TEA# if the Enable Local Bus TEA# bits are enabled (INTCSR[1:0], which can be used as an NMI). If the Local processor cannot terminate its Burst cycle, it may cause the Local processor to hang. The Local Bus must then be reset from the PCI Bus. If the Local Bus Master cannot terminate its cycle with TEA# output, it should not perform Burst cycles when attempting to determine whether a PCI device exists. 3.4.1.10 PCI Initiator Memory Write and Invalidate The PCI 9054 can be programmed to perform Memory Write and Invalidate cycles to the PCI Bus for PCI Initiator transfers, as well as DMA transfers (refer to Section 3.5.4). The PCI 9054 supports Memory Write and Invalidate transfers for cache line sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or 16 is specified, the PCI 9054 performs Write transfers rather than Memory Write and Invalidate transfers. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-7 Section 3--M Func Desc Set Enable and Go Bits in DMA Command/Status Registers (DMACSR0 and DMACSR1) to Initiate DMA Transfer www..com Section 3 M Mode Functional Description Direct Data Transfer Modes PCI Initiator Memory Write and Invalidate transfers are enabled when the Invalidate Enable and the Memory Write and Invalidate Enable bits are set (DMPBAM[9]) and (PCICR[4]), respectively. In Memory Write and Invalidate mode, if the start address of the PCI Initiator transfer is on a cache line boundary, the PCI 9054 waits until the number of Lwords required for the specified cache line size are written from the Local Bus before starting a PCI Memory Write and Invalidate access. This ensures a complete cache line write can complete in one PCI Bus ownership. If the start address is not on a cache line boundary, the PCI 9054 starts a normal PCI Write access (PCI command code = 7h). The PCI 9054 terminates a cycle at a cache line boundary if it is performing a normal write or if it is performing a Memory Write and Invalidate cycle and another cache line of data is not available. If an entire cache line is available by the time PCI 9054 regains use of the PCI Bus, the PCI 9054 resumes Memory Write and Invalidate cycles. Otherwise, it continues with a normal write. If a Target disconnects before a cache line is completed, the PCI 9054 completes the remainder of that cache line, using normal writes. Figure 3-5. Dual Address Timing PCI 9054 Data Book v2.1 3-8 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 3 M Mode Functional Description 3.4.2 3.4.2.1 IDMA/SDMA Operation IDMA Operation 3.4.2.2 SDMA Operation Note: The PCI Initiator Write FIFO Retry Enable bit (LMISC[6]) can be disabled to prevent assertion of the RETRY# signal. In IDMA reads (PCI 9054 to the Local Bus), the MDREQ# signal is always asserted (indicating data is available), although the Read FIFO is empty. Any Local Bus read of the PCI Bus causes the PCI 9054 to become a PCI Bus Master and fill the PCI Initiator Read FIFO buffer. When sufficient data is in the FIFO, the PCI 9054 completes the Local Bus cycle by asserting Transfer Acknowledge (TA#). After the IDMA has transferred all required bytes (MPC850 or MPC860 Byte counter decrements to zero), the MPC850 or MPC860 generate an internal interrupt, which in turn should execute the code to disable the IDMA channel (the MDREQ# input signal may still be asserted by the PCI 9054). The SDACK[1:0] signal from the MPC850 or MPC860 is not used by the PCI 9054 (no connection). Refer to Section 3.4.1 for more information about PCI Initiator Data transfers. * Space 0 * Space 1 * Expansion ROM space Expansion ROM space is intended to support a bootable ROM device for the Host. For Single-Cycle PCI Target reads, the PCI 9054 reads a single Local Bus Lword or partial Lword. The PCI 9054 disconnects after one transfer for all PCI Target I/O accesses. For the highest data-transfer rate, the PCI 9054 supports posted writes and can be programmed to prefetch data during a PCI Burst read. The Prefetch size, when enabled, can be from one to 16 Lwords or until the PCI Bus stops requesting. When the PCI 9054 prefetches, if enabled, it drops the Local Bus after reaching the prefetch counter. In Continuous Prefetch mode, the PCI 9054 prefetches as long as FIFO space is available and stops prefetching when the PCI Bus terminates the request. If Read prefetching is disabled, the PCI 9054 disconnects after one Read transfer. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-9 Section 3--M Func Desc The PCI 9054 supports the MPC850 or MPC860 Independent DMA (IDMA) mode, using the MDREQ# signal and operating in PCI Initiator mode. In M mode, this signal is connected to the MPC850 or MPC860 DREQ[1:0] input pins. After programming the MPC850 or MPC860 IDMA channel, the PCI 9054 uses PCI Initiator mode to transfer data between the PCI Bus and the MPC850 or MPC860 internal dual-port RAM (or external memory). The data count is controlled by the IDMA Byte counter and throttled by the PCI 9054 MDREQ# signal. When the PCI 9054 FIFO is nearly full, MDREQ# is de-asserted to the MPC850 or MPC860, indicating that it should inhibit transferring further data (the FIFO threshold count in the PCI 9054 must be set to a value of at least five Lwords below the full capacity of the FIFO--27 Lwords) (DMPBAM[10, 8:5]). The Retry function can be used to communicate to the Local Bus Master that it should relinquish ownership of the Local Bus. The PCI 9054 supports the MPC850 or MPC860 Serial DMA (SDMA) mode, using PCI Initiator mode. No handshake signals are required to perform the SDMA operation. The Retry function can be used to communicate to the Local Bus Master it should relinquish ownership of the Local Bus. The PCI Initiator Write FIFO Retry Enable bit (LMISC[6]) can be disabled to prevent assertion of the RETRY# signal. Note: The PCI Initiator Write FIFO can be programmed to identify the full status condition (DMPBAM[10, 8:5]). The FIFO Full Status Flag is in MARBR[30]. 3.4.3 PCI Target Operation (PCI Master-to-Local Bus Access) The PCI 9054 supports both Burst Memory-Mapped Transfer accesses and I/O-Mapped, Single-Transfer accesses to the Local Bus from the PCI Bus through a 16-Lword (64-byte) PCI Target Read FIFO and a 32-Lword (128-byte) PCI Target Write FIFO. The PCI Base Address registers are provided to set up the location of the adapter in the PCI memory and the I/O space. In addition, Local mapping registers allow address translation from the PCI Address Space to the Local Address Space. Three spaces are available: www..com Section 3 M Mode Functional Description Direct Data Transfer Modes In addition to Prefetch mode, the PCI 9054 supports Read Ahead mode (refer to Section 3.4.3.3). Each Local space can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width. The PCI 9054 has an internal wait state generator and external wait state input, TA#. TA# can be disabled or enabled with the Internal Configuration registers. With or without wait state(s), the Local Bus, independent of the PCI Bus, can: * Burst as long as data is available (Continuous Burst mode) * Burst four Lwords at a time (recommended) * Perform a Continuous Single cycle A Burst cycle from the PCI Bus through the PCI 9054 asserts an MPC850 or MPC860 Burst transaction if the following is true: * The address is quad-Lword aligned, * A FIFO contains at least four Lwords, and * All PCI Bus byte enables are set for writes only and ignored for reads PCI Bus PCI 9054 Local Bus PCI Read request PCI 9054 instructs PCI Host to "Retry" Read cycle later PCI Bus is free to perform other cycles during this time PCI Host returns to fetch Read data again Read data is now ready for host Spec v2.1 mode is set in Internal Registers PCI 9054 requests Read data from Local Bus Local memory returns requested data to PCI 9054 Data is stored in 16-Lword Internal FIFO PCI 9054 returns prefetched data immediately Figure 3-6. PCI Target PCI v2.1 Delayed Reads Note: The figure represents a sequence of Bus cycles. 3.4.3.3 PCI Target PCI Read Ahead Mode 3.4.3.1 PCI Target Lock The PCI 9054 supports direct PCI-to-Local-Bus exclusive accesses (locked atomic operations). A PCIlocked operation to the Local Bus results in the entire address Space 0, Space 1, and Expansion ROM space being locked until they are released by the PCI Bus Master. Locked operations are enabled or disabled with the PCI Target LOCK# Enable bit (MARBR[22]) for PCI-to-Local accesses. The PCI 9054 also supports Read Ahead mode, where prefetched data can be read from the internal FIFO of the PCI 9054 instead of from the Local Bus. The address must be subsequent to the previous address and 32-bit aligned (next address = current address + 4). Read Ahead mode functions with or without PCI Delayed Read mode. PCI Bus PCI Read request PCI 9054 Read Ahead mode is set in Internal Registers Local Bus PCI 9054 prefetches data from Local Bus device 3.4.3.2 PCI Target PCI v2.1 Delayed Read Mode Read data PCI Bus Master Read returns with "Sequential Address" Prefetched data is stored in the internal FIFO PCI 9054 returns prefetched data immediately from internal FIFO without reading again from the Local Bus The PCI 9054 can be programmed through the PCI Specification v2.1 Mode bit (MARBR[24]=1) to perform delayed reads, as specified in PCI Specification v2.1. In addition to delayed reads, the PCI 9054 supports the following PCI Specification v2.1 functions: * No write while a read is pending (PCI Retry for writes) * Write and flush pending read PCI 9054 prefetches more data if FIFO space is available Read data PCI 9054 prefetches more data from Local memory Figure 3-7. PCI Target PCI 9054 Read Ahead Mode Note: The figure represents a sequence of Bus cycles. PCI 9054 Data Book v2.1 3-10 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 3 M Mode Functional Description 3.4.3.4 PCI Target Transfer Master Slave FRAME#, C/BE#, AD (addr) IRDY#, AD (data) Master Slave A PCI Bus Master addressing the Memory space decoded for the Local Bus initiates transactions. Upon a PCI Read/Write, the PCI 9054 becomes a Local Bus Master and arbitrates for the Local Bus. The PCI 9054 then reads data into the PCI Target Read FIFO or writes data to the Local Bus. The PCI Target or PCI Initiator preempts DMA; however, the PCI Target does not preempt the PCI Initiator (refer to Section 3.4.4.1). The PCI 9054 can be programmed to "keep" the PCI Bus by generating a wait state(s) and de-asserting TRDY# if the Write FIFO becomes full. The PCI 9054 can also be programmed to "keep" the Local Bus and continue asserting BB# if the PCI Target Write FIFO becomes empty or the PCI Target Read FIFO becomes full. In either case, the Local Bus is dropped when the Local Bus Latency Timer is enabled and expires (MARBR[7:0]). For PCI Target writes, the PCI Bus writes data to the Local Bus. PCI Target is the "Command from the PCI Host," which has the highest priority. For PCI Target reads, the PCI Bus Master reads data from the Local Bus Slave. The PCI 9054 supports on-the-fly Endian conversion for Space 0, Space 1, and Expansion ROM space. The Local Bus can be Big/Little Endian (Address/Data Invariance) by using the programmable internal register configuration. Note: The PCI Bus is always Little Endian. PCI Bus PCI 9054 BR# BG# BB#, LA, TS#, RD/WR# LD, BURST# TA# Figure 3-8. PCI Target Write Master FRAME#, C/BE#, AD (addr) IRDY# Slave Master Slave Local Bus DEVSEL#, TRDY# PCI 9054 TRDY#, AD (data) BR# BG# BB#, LA, TS#, RD/WR# , BURST# TA#, LD Figure 3-9. PCI Target Read Note: The figures represent a sequence of Bus cycles. During PCI Target transactions, the MPC850 or MPC860 user has the option to use the PCI 9054 for maximum Burst transfers, using the BTERM# Input Enable bit(s) (LBRD0[23,7], LBRD1[7], and DMAMODE0[7]). In PCI Target transfers, each PCI Target space (Space 0, Space 1, and Expansion ROM) has its own BTERM# Input Enable bit (the BTERM# input signal becomes the BI# signal in M mode). Space 0 is in LBRD0[7], Space 1 is in LBRD1[7], and Expansion ROM is in LBRD0[23]. When the Bterm Mode bit is enabled, the PCI 9054 continues to burst on the Local Bus until the BI# signal is asserted for one CLK cycle any time after the first Data phase, implying a new Address cycle (TS#) is needed if there is more data to transfer. If the BI# signal is asserted on the first Data phase, the Burst transfer is broken into Single-Cycle transactions. When the Bterm Mode bit is enabled and the BI# signal asserted for one CLK cycle any time after the First data phase, this implies that a new Address cycle (TS#) is needed for more data to transfer. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-11 Local Bus PCI Bus DEVSEL# Section 3--M Func Desc www..com Section 3 M Mode Functional Description Direct Data Transfer Modes Regardless of the Bterm mode setting, if the BI# signal is asserted on the first Data phase, Single-Cycle transfers are performed until the quad-word boundary is reached. Table 3-2. PCI Target Burst Mode Cycle Detection Burst Enable Bit BTERM# Input Enable Bit 3.4.3.5 Note: PCI Target PCI-to-Local Address Mapping Not applicable in I2O mode. BI# Signal Result Burst 16 bytes (MPC850 or MPC860 compatible) Single cycle Burst until BI# is asserted for one CLK cycle Single cycle Three Local Address spaces--Space 0, Space 1, and Expansion ROM--are accessible from the PCI Bus. Each is defined by a set of three registers: * Local Address Range (LAS0RR, LAS1RR, and/or EROMRR) * Local Base Address (LAS0BA, LAS1BA, and/or EROMBA) * PCI Base Address (PCIBAR2, PCIBAR3, and/or PCIERBAR) A fourth register, the Bus Region Descriptor register for PCI-to-Local Accesses (LBRD0 and/or LBRD1), defines the Local Bus characteristics for the PCI Target regions (refer to Figure 3-10). Each PCI-to-Local Address space is defined as part of reset initialization, as described in Section 3.4.3.5.1. These Local Bus characteristics can be modified at any time before actual data transactions. 1 0 Not asserted 1 0 Asserted during first Data phase Asserted after first Data phase X 1 0 1 X Caution: The MPC850 and MPC860 do not support bursting more than 16 bytes. The BTERM# Input Enable bits should be set only for Local Bus Masters that support continuous bursting. Note: "X" is "Don't Care." The PCI 9054 supports Local Bus error conditions using TEA#. TEA# may be asserted by a device on the Local Bus, either before or simultaneously with TA#. In either case, the PCI 9054 tries to complete the current transaction by transferring data and then asserting TS# for every address that follows, waiting for another TA# or TEA# to be issued (used to flush PCI Target FIFOs). After acknowledging TEA# is asserted, the PCI 9054 asserts PCI SERR# and sets an error flag, using the Signaled System Error bit (PCISR[14]=1). When set, this indicates a catastrophic error occurred on the Local Bus. SERR# may be masked off by resetting the TEA# Input Interrupt Mask bit (LMISC[5]=0). The PCI 9054 Local Bus Latency Timer (MARBR[7:0]) can be used to better utilize the Local Bus. 3.4.3.5.1 PCI Target Local Bus Initialization Range--Specifies which PCI Address bits to use for decoding a PCI access to Local Bus space. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0 to all others. Remap PCI-to-Local Addresses into a Local Address Space--Bits in this register remap (replace) the PCI Address bits used in decode as the Local Address bits. Local Bus Region Descriptor--Specifies the Local Bus characteristics. 3.4.3.5.2 PCI Target PCI Initialization After a PCI reset, the software determines how much address space is required by writing all ones (1) to a PCI Base Address register and then reading back the value. The PCI 9054 returns zeroes (0) in the Don't Care Address bits, effectively specifying the address space required. The PCI software then maps the Local Address space into the PCI Address space by programming the PCI Base Address register. (Refer to Figure 3-10.) PCI 9054 Data Book v2.1 3-12 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 3 M Mode Functional Description PCI Bus Master Local Processor 1 Initialize Local Direct Access Registers 2 Initialize PCI Base Address Registers Range for PCI-to-Local Address Space 0/1 Local Base Address (Remap) for PCI-to-Local Address Space 0/1 Bus Region Descriptors for PCI-to-Local Accesses Range for PCI-to-Local Expansion ROM Local Base Address (Remap) for PCI-to-Local Expansion ROM Bus Region Descriptors for PCI-to-Local Accesses Local Bus Hardware Characteristics PCI Base Address to Local Address Space 0/1 PCI Base Address to Local Expansion ROM 3 PCI Bus Access 4 FIFOs 32-Lword Deep Write 16-Lword Deep Read Local Bus Access PCI Address Space PCI Base Address Local Base Address Local Memory Range Figure 3-10. Local Bus PCI Target Access PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-13 Section 3--M Func Desc www..com Section 3 M Mode Functional Description Direct Data Transfer Modes 3.4.3.5.3 PCI Target Transfer Size The TSIZ[0:1] pins correspond to the data-transfer size on the Local Bus. Table 3-3. Data Bus TSIZ[0:1] Contents for Single Write Cycles Address LA30 1 1 1 1 0 0 0 0 0 1 1 0 1 0 Transfer Size 0 Byte 0 0 0 Word Lword 1 1 0 TSIZ [0:1] External Data Bus Pattern For 32-, 16-, and 8-Bit Port Sizes LD[0:7] OP0 OP1 OP2 OP3 OP0 OP2 OP0 LA31 0 1 0 1 0 0 0 LD[8:15] -- OP1 -- OP3 OP1 OP3 OP1 LD[16:23] -- -- OP2 -- -- OP2 OP2 LD[24:31] -- -- -- OP3 -- OP3 OP3 Table 3-4. Data Bus TSIZ[0:1] Requirements for Single Read Cycles Address LA30 0 0 1 1 0 1 0 Transfer Size TSIZ [0:1] 0 1 1 1 1 0 0 0 0 0 0 32-Bit Port Size LD[0:7] OP0 -- -- -- OP0 -- OP0 16-Bit Port Size LD[24:31] -- -- -- OP3 -- OP3 OP3 8-Bit Port Size LD[0:7] OP0 OP1 OP2 OP3 OP0 OP2 OP0 LA31 0 1 0 1 0 0 0 LD[8:15] -- OP1 -- -- OP1 -- OP1 LD[16:23] -- -- OP2 -- -- OP2 OP2 LD[0:7] OP0 -- OP2 -- OP0 OP2 OP0 LD[8:15] -- OP1 -- OP3 OP1 OP3 OP1 Byte Word Lword 1 1 0 3.4.3.5.3.1 PCI Target Example A 1 MB Local Address Space, 12300000h through 123FFFFFh, is accessible from the PCI Bus at PCI addresses 78900000h through 789FFFFFh. a. Local initialization software sets the Range and Local Base Address registers as follows: * * Range--FFF00000h (1 MB, decode the upper 12 PCI Address bits) Local Base Address (Remap)--123XXXXXh (Local Base Address for PCI-to-Local accesses [Space Enable bit(s) must be set to be recognized by the PCI Host (LAS0BA[0]=1, LAS1BA[0]=1)] b. PCI Initialization software writes all ones to the PCI Base Address, then reads it back again. * The PCI 9054 returns a value of FFF00000h. The PCI software then writes to the PCI Base Address register(s). PCI Base Address--789XXXXXh (PCI Base Address for Access to the Local Address Space registers, PCIBAR2 and PCIBAR3). * For a PCI Direct access to the Local Bus, the PCI 9054 has a 32-Lword (128-byte) Write FIFO and a 16-Lword (64-byte) Read FIFO. The FIFOs enable the Local Bus to operate independent of the PCI Bus. The PCI 9054 can be programmed to return a Retry response or to throttle TRDY# for any PCI Bus transaction attempting to write to the PCI 9054 Local Bus when the FIFO is full. PCI 9054 Data Book v2.1 3-14 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 3 M Mode Functional Description For PCI Read transactions from the Local Bus, the PCI 9054 holds off TRDY# while gathering data from the Local Bus. For Read accesses mapped to PCI Memory space, the PCI 9054 prefetches up to 16 Lwords (has Continuous Prefetch mode) from the Local Bus. Unused Read data is flushed from the FIFO. For Read accesses mapped to PCI I/O space, the PCI 9054 does not prefetch Read data. Rather, it breaks each read of a Burst cycle into a Single Address/Data cycle on the Local Bus. The PCI Target Retry Delay Clocks bits (LBRD0[31:28]) can be used to program the period of time in which the PCI 9054 holds off TRDY#. The PCI 9054 issues a Retry to the PCI Bus Transaction Master when the programmed time period expires. This occurs when the PCI 9054 cannot gain control of the Local Bus and return TRDY# within the programmed time period. 3.4.4 Deadlock Conditions Deadlock can occur when a PCI Bus Master must access the PCI 9054 Local Bus at the same time a Master on the PCI 9054 Local Bus must access the PCI Bus. There are two types of deadlock: * Partial Deadlock--A Local Bus Master is performing a Direct Bus Master access to a PCI Bus device other than the PCI Bus device concurrently trying to access the Local Bus * Full Deadlock--A Local Bus Master is performing a Direct Bus Master access to the same PCI Bus device concurrently trying to access the Local Bus This applies only to PCI Initiator and PCI Target accesses through the PCI 9054. Deadlock does not occur in transfers through the PCI 9054 DMA channels or the PCI 9054 internal registers (such as mailboxes). For partial deadlock, the PCI access to the Local Bus times out (the PCI Target Retry Delay Clock (LBRD0[31:28]), which is programmable through the Local Bus Region Descriptor register) and the PCI 9054 responds with a PCI Retry. The PCI Specification requires that a PCI Master release its request for the PCI Bus (de-assert REQ#) for a minimum of two PCI clocks after receiving a Retry. This allows the PCI Bus arbiter to grant the PCI Bus to the PCI 9054 so that it can complete its PCI Initiator access and free up the Local Bus. Possible solutions are described in the following sections for cases in which the PCI Bus arbiter does not function as described (PCI Bus architecture dependent), waiting for a time out is undesirable, or a full deadlock condition exists. When a full deadlock occurs, the only solution is to backoff the Local Bus Master. Section 3--M Func Desc 3.4.3.6 PCI Target Priority PCI Target accesses have a higher priority than DMA accesses, thereby preempting DMA transfers. During a DMA transfer, if the PCI 9054 detects a pending PCI Target access, it releases the Local Bus within two Data transfers. The PCI 9054 resumes operation after the PCI Target access completes. When the PCI 9054 DMA controller owns the Local Bus, its BR# output and BG# input are asserted. When a PCI Target access occurs, the PCI 9054 releases the Local Bus within two Lword transfers by de-asserting BB# and floating the Local Bus outputs. After the PCI 9054 acknowledges that BG# is de-asserted, it requests the Local Bus for a PCI Target transfer by asserting BR#. When the PCI 9054 receives BG#, it drives the bus and performs the PCI Target transfer. Upon completing a PCI Target transfer, the PCI 9054 releases the Local Bus by de-asserting BB# and floating the Local Bus outputs. After the PCI 9054 acknowledges that BG# is de-asserted and the Local Bus Pause Timer is set to zero, it requests a DMA transfer from the Local Bus by re-asserting BR#. When it receives BG#, it drives the bus and continues the DMA transfer. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-15 www..com Section 3 M Mode Functional Description DMA Operation 3.4.4.1 Backoff A new PCI read is performed if the resumed Local Bus cycle is not the same as the Backed Off cycle. The PCI 9054 Local RETRY# signal indicates whether a possible deadlock condition exists. The PCI 9054 starts the Backoff timer (programmable through registers) when it detects one of the following conditions: * A PCI Bus Master is attempting to access memory or an I/O device on the Local Bus and is not gaining access (for example, BG# is not received). * A Local Bus Master is performing a Direct Bus Master Read access to the PCI Bus. Or, a Local Bus Master is performing a Direct Bus Master Write access to the PCI Bus and the PCI 9054 PCI Initiator Write FIFO cannot accept another Write cycle. If the Local Bus Backoff Enable bit is enabled (EROMBA[4]=1), the Backoff Timer expires, and the PCI 9054 has not received BG#, the PCI 9054 asserts RETRY#. External bus logic can use this signal to perform backoff. The Backoff cycle is device/bus architecture dependent. The external logic (arbiter) can assert the necessary signals to cause the Local Bus Master to release the Local Bus (backoff). After the Local Bus Master backs off, it can grant the bus to the PCI 9054 by asserting BG#. Once RETRY# is asserted, TA# for current Data cycle is never asserted (the Local Bus Master must perform a backoff). When the PCI 9054 detects BG#, it proceeds with the PCI Master-to-Local-Bus access. When this access completes and the PCI 9054 releases the Local Bus, external logic can then release the backoff and the Local Bus Master can resume the cycle interrupted by the Backoff cycle. The PCI 9054 Write FIFO retains all data acknowledged (that is, last data for which TA# was asserted). After the backoff condition ends, the Local Bus Master restarts the last cycle with TS#. For writes, data following TS# should be the data the PCI 9054 did not acknowledge prior to the Backoff cycle (for example, the last data for which TA# is not asserted). All PCI Read cycles completed before the Local Bus was backed off remain in the PCI Initiator Read FIFO. Therefore, if the Local Bus Master returns with the same last cycle, the cycle is acknowledged with the data currently in the FIFO (the FIFO data is not read twice). 3.4.4.1.1 Software/Hardware Solution for Systems without Backoff Capability For adapters that do not support backoff, a possible deadlock solution is as follows. PCI Host software, external Local Bus hardware, general-purpose output USERo and general-purpose input USERi can be used to prevent deadlock. USERo can be asserted to request that the external arbiter not grant the bus to any Local Bus Master except the PCI 9054. Status output from the Local arbiter can be connected to the general purpose input USERi to indicate that no Local Bus Master owns the Local Bus, or the PCI Host to determine that no Local Bus Master that currently owns the Local Bus can read input. The PCI Host can then perform PCI Target access. When the Host finishes, it de-asserts USERo. 3.4.4.1.2 Preempt Solution For devices that support preempt, USERo can be used to preempt the current Local Bus Master device. When USERo is asserted, the current Local Bus Master device completes its current cycle and releases the Local Bus, de-asserting BB#. 3.4.4.2 Software Solutions to Deadlock Both PCI Host and Local Bus software can use a combination of mailbox registers, doorbell registers, interrupts, direct Local-to-PCI accesses and direct PCI-to-Local accesses to avoid deadlock. 3.5 DMA OPERATION The PCI 9054 supports two independent DMA channels capable of transferring data from the: * Local-to-PCI Bus * PCI-to-Local Bus Each channel consists of a DMA controller and a dedicated, bidirectional FIFO. Both channels support Block transfers, and Scatter/Gather transfers, with or without End of Transfer (EOT#). Only DMA Channel 0 supports Demand mode DMA transfers. Master mode must be enabled with the Master Enable bit (PCICR[2]) before the PCI 9054 can become a PCI PCI 9054 Data Book v2.1 3-16 (c) PLX Technology, Inc. All rights reserved. www..com DMA Operation Section 3 M Mode Functional Description Bus Master. In addition, both DMA channels can be programmed to: * Operate in 8-, 16-, or 32-bit Local Bus width * Use zero to 15 internal wait states (Local Bus) * Enable/disable internal wait states (Local Bus) * Enable/disable Local Bus Burst capability * Limit Local Bus bursts to four (BTERM# enable/ disable) * Hold Local address constant (Local Target is FIFO) or increment * Perform PCI Memory Write and Invalidate (command code = Fh) or normal PCI Memory Write (command code = 7h) * Pause Local transfer with/without BLAST# (DMA Fast/Slow termination) * Assert PCI interrupt (INTA#) or Local interrupt (LINT#) when DMA transfer is complete or Terminal Count is reached during Scatter/Gather DMA mode transfers * Operate in DMA Clear Count mode (only if the descriptor is in Local memory) The PCI 9054 also supports PCI Dual Address with the upper 32-bit registers (DMADAC0 and DMADAC1). The Local Bus Latency Timer determines the number of Local clocks the PCI 9054 can burst data before relinquishing the Local Bus. The Local Pause Timer sets how soon the DMA channel can request the Local Bus. 3.5.2 Block DMA Mode The Host processor or the Local processor sets the Local and PCI starting addresses, transfer byte count, and transfer direction. The Host or Local processor then sets the DMA Start bit to initiate a transfer. The PCI 9054 requests the PCI and Local Buses and transfers data. Once the transfer completes, the PCI 9054 sets the Channel Done bit(s) (DMACSR0[4]=1 and/or DMACSR1[4]=1) and, if enabled, asserts an interrupt(s) (DMAMODE0[10] and/or DMAMODE1[10]) to the Local processor or the PCI Host (programmable). The Channel Done bit(s) can be polled, instead of interrupt generation, to indicate the DMA transfer status. DMA registers are accessible from the PCI and Local Buses (refer to Figure 3-4 on page 3-7). During DMA transfers, the PCI 9054 is a Master on both the PCI and Local Buses. For simultaneous access, PCI Target or PCI Initiator has a higher priority than DMA. The PCI 9054 releases the PCI Bus if one of the following conditions occur (refer to Figure 3-11 on page 3-18 and Figure 3-12 on page 3-18): * FIFO is full (PCI-to-Local Bus) * FIFO is empty (Local-to-PCI Bus) * Terminal count is reached * PCI Bus Latency Timer expires (PCILTR[7:0])-- normally programmed by the Host PCI BIOS--and PCI GNT# de-asserts * PCI Host asserts STOP# The PCI 9054 releases the Local Bus if one of the following conditions occurs: * FIFO is empty (PCI-to-Local Bus) * FIFO is full (Local-to-PCI Bus) * Terminal count is reached * Local Bus Latency Timer is enabled and expires (MARBR[7:0]) * Special cycle BI# input is asserted * PCI Target request is pending During DMA transactions, users have the option of using the Burst Forever BTERM# Input Enable bit(s) (DMAMODE0[7] and/or DMAMODE1[7]) if the External Memory Controller is provided. Used in conjunction with the Fast/Slow Terminate Mode Select bit(s) (DMAMODE0[15] and/or DMAMODE1[15]). 3.5.1 DMA PCI Dual Address Cycle The PCI 9054 supports PCI Dual Address Cycle (DAC) when it is a PCI Bus Master using the DMADAC0 and DMADAC1 registers for Block DMA transactions. Scatter/Gather DMA can utilize the DAC function via the DMADAC0 and DMADAC1 registers or DMAMODE0[18] and DMAMODE1[18]. The DAC command is used to transfer a 64-bit address to devices that support 64-bit addressing when the address is above the 4-GB Address space. The PCI 9054 performs a DAC within two PCI clock periods, when the first PCI address is a Lo-Addr, with the command (C/BE[3:0]#) "D", and the second PCI address is a Hi-Addr, with the command (C/BE[3:0]#) "6" or "7", depending upon whether it is a PCI Read or PCI Write cycle. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-17 Section 3--M Func Desc www..com Section 3 M Mode Functional Description DMA Operation Table 3-5. DMA Slave DMA Start (DMALADR1 & DMASIZ1) Master Master DMA Start Slave (DMALADR1 & DMASIZ1) REQ# GNT# FRAME#, C/BE#, AD (addr) IRDY# DEVSEL#, TRDY#, AD (data) BTERM# Input Enable Bit(s) Enabled (1) Fast/Slow Terminate Mode Select Bit(s) Disabled (1) PCI 9054 BDIP# Output BDIP# is not asserted. Burst forever or until BI# asserts for one CLK cycle. BDIP# is asserted on the last data transfer, or until BI# asserts for one CLK cycle. (Refer to Section 2.2.5.2.1.) BDIP# is not asserted. Burst forever. BDIP# is asserted by the PCI 9054. Burst up to 16 bytes (MPC850 or MPC860 compatible). PCI 9054 Local Bus PCI Bus Enabled (1) Enabled (0) BR# BG# BB#, LA, TS#, RD/WR#, BURST# Disabled (0) TA# Disabled (1) Enabled (0) Disabled (0) Figure 3-11. DMA, PCI-to-Local Bus Slave DMA Start Master (DMALADR1 & DMASIZ1) Master DMA Start (DMALADR1 & DMASIZ1) Slave Table 3-6. Normal DMA with EOT Function BTERM# Enable Bit(s) Fast/Slow Terminate Mode Select Bit(s) Disabled (1) Enabled (0) Disabled (1) Enabled (0) BR# BG# BB#, LA, TS#, RD/WR# PCI 9054 BDIP# Output BDIP# is not asserted. Immediate transfer terminated by EOT#. BDIP# is asserted by the PCI 9054. Transfers up to the nearest 16-byte boundary, then terminates (MPC850 or MPC860 compatible). PCI Bus REQ# GNT# IRDY# DEVSEL#, TRDY# AD (addr & data) PCI 9054 LD, TA# Local Bus Enabled (1) Enabled (1) Disabled (0) Disabled (0) Figure 3-12. DMA, Local-to-PCI Bus Note: The figures represent a sequence of Bus cycles. Note: If the Burst Enable bit is set to 0, the PCI 9054 performs Single-Cycle transfers on the Local Bus. Figure 3-13. Dual Address Timing PCI 9054 Data Book v2.1 3-18 (c) PLX Technology, Inc. All rights reserved. www..com DMA Operation Section 3 M Mode Functional Description 3.5.2.1 Block DMA PCI Dual Address Cycle The PCI 9054 supports the DAC feature in Block DMA mode. Whenever the DMADAC0 or DMADAC1 registers contain a value of 0x00000000, the PCI 9054 performs a Single Address Cycle (SAC) on the PCI Bus. Any other value causes a Dual Address to appear on the PCI Bus. (Refer to Figure 3-13.) Notes: In Scatter/Gather DMA mode, the descriptor includes the PCI and Local Address Space, transfer size, and next descriptor pointer. It also includes a DAC value if DMADPR0[18] and/or DMAMODE1[I8] is enabled. Otherwise, the register (DMADAC0 and DMADAC1) values are used. The Descriptor Pointer register(s) (DMADPR0 and/or DMADPR1) contains end of chain (bit 1), direction of transfer (bit 3), next descriptor address (bits [31:4]), interrupt after terminal count (bit 2), and next descriptor location (bit 0) bits. The Local Bus width must be the same as Local Memory bus width. A DMA descriptor can be on the Local memory or the PCI memory, or both (for example, one descriptor on Local memory, another descriptor on PCI memory and vice-versa). 3.5.3 Scatter/Gather DMA Mode PCI Bus Local Bus Set up Scatter/Gather DMA for PCI-to-Local PCI 9054 retrieves Scatter/Gather data from Local memory PCI 9054 writes data to Local Bus In Scatter/Gather DMA mode, the Host processor or Local processor sets up descriptor blocks in Local or Host memory composed of PCI and Local addresses, transfer count, transfer direction, and address of next descriptor block (refer to Figure 3-14 and Figure 3-15). The Host or Local processor then: * Enables the Scatter/Gather mode bit(s) (DMAMODE0[9]=1 and/or DMAMODE1[9]=1) * Sets up the address of initial descriptor block in the PCI 9054 Descriptor Pointer register(s) (DMADPR0 and/or DMADPR1) * Initiates the transfer by setting a control bit(s) (DMACSR0[1:0] and/or DMACSR1[1:0]) The PCI 9054 loads the first descriptor block and initiates the Data transfer. The PCI 9054 continues to load descriptor blocks and transfer data until it detects the End of Chain bit(s) (DMADPR0[1] and/or DMADPR1[1]) is set (these bits are part of each descriptor). When the End of Chain bit(s) is detected, the PCI 9054 completes the current descriptor block and sets the DMA Done bit(s) (DMACSR0[4] and/or DMACSR1[4]). If the End of Chain bit(s) is detected, the PCI 9054 asserts a PCI interrupt (INTA#) and/or Local interrupt (LINT#). The PCI 9054 can also be programmed to assert PCI or Local interrupts after each descriptor is loaded, then finish transferring. If Scatter/Gather descriptors are in Local memory, the DMA controller can be programmed to clear the transfer size at completion of each DMA, using the DMA Clear Count Mode bit(s) (DMAMODE0[16] and/ or DMAMODE1[16]). PCI 9054 initiates read from PCI Bus PCI 9054 initiates read from PCI Bus PCI 9054 initiates read from PCI Bus PCI 9054 initiates read from PCI Bus PCI 9054 retrieves Scatter/Gather data from Local memory PCI 9054 writes data to Local Bus PCI 9054 writes data to Local Bus Read and Write cycles continue... Figure 3-14. Scatter/Gather DMA Mode from PCI-to-Local Bus (Control Access from the Local Bus) PCI Bus Set up Scatter/Gather DMA for Local-to-PCI PCI 9054 retrieves Scatter/Gather data from PCI memory PCI 9054 writes data to PCI Bus PCI 9054 writes data to PCI Bus PCI 9054 retrieves S catter/Gather data from PCI memory PCI 9054 writes data to PCI Bus PCI 9054 writes data to PCI Bus Local Bus PCI 9054 initiates read from Local Bus PCI 9054 PCI 9054 initiates read from Local Bus PCI 9054 initiates read from Local Bus PCI 9054 initiates read from Local Bus Read and Write cycles continue... Figure 3-15. Scatter/Gather DMA Mode from Local-to-PCI Bus (Control Access from the PCI Bus) Note: The figures represent a sequence of Bus cycles. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-19 Section 3--M Func Desc PCI 9054 PCI 9054 writes data to Local Bus www..com Section 3 M Mode Functional Description DMA Operation 3.5.3.1 Scatter/Gather DMA PCI Dual Address Cycle 16 is specified, the PCI 9054 performs Write transfers rather than Memory Write and Invalidate transfers. DMA Memory Write and Invalidate transfers are enabled when the DMA controller Memory Write and Invalidate Enable bit(s) (DMAMODE0[13] and/or DMAMODE1[13]) and the Memory Write and Invalidate Enable bit (PCICR[4]) are set. In Memory Write and Invalidate mode, the PCI 9054 waits until the number of Lwords required for specified cache line size are read from the Local Bus before starting the PCI access. This ensures a complete cache line write can complete in one PCI Bus ownership. If a Target disconnects before a cache line completes, the PCI 9054 completes the remainder of that cache line, using normal writes before resuming Memory Write and Invalidate transfers. If a Memory Write and Invalidate cycle is in progress, the PCI 9054 continues to burst if another cache line is read from the Local Bus before the cycle completes. Otherwise, the PCI 9054 terminates the burst and waits for the next cache line to be read from the Local Bus. If the final transfer is not a complete cache line, the PCI 9054 completes the DMA transfer, using normal writes. The PCI 9054 supports the DAC feature in Scatter/ Gather DMA mode for Data transfers only. The descriptor blocks should reside below the 4-GB Address space. The PCI 9054 offers three different options of how PCI DAC Scatter/Gather DMA is utilized. Assuming the descriptor blocks are located on the PCI Bus: * DMADAC0 and/or DMADAC1 contain(s) a non-zero value. DMAMODE0[18] and/or DMAMODE1[18] is set to 0. The PCI 9054 performs a Single Address Cycle (SAC) four-Lword descriptor block load from PCI memory and DMA transfer with DAC on the PCI Bus. (Refer to Figure 3-16.) * DMADAC0 and/or DMADAC1 contain(s) an 0x00000000 value. DMAMODE0[18] and/or DMAMODE1[18] is set to 1. The PCI 9054 performs a SAC five-Lword descriptor block load from PCI memory and DMA transfer with DAC on the PCI Bus. (Refer to Figure 3-17.) * DMADAC0 and/or DMADAC1 contain(s) a non-zero value. DMAMODE0[18] and/or DMAMODE1[18] is set to 1. The PCI 9054 performs a SAC five-Lword descriptor block load from PCI memory and DMA transfer with DAC on the PCI Bus. The fifth descriptor overwrites the value of the DMADAC0 and/or DMADAC1 register. (Refer to Figure 3-17.) 3.5.4.1 DMA Abort DMA transfers can be aborted, in addition to the EOT# signal, as follows: 1. 2. 3. Clear the DMA Channel Enable bit(s) (DMACSR0[0]=0 and/or DMACSR1[0]=0). Abort DMA by setting the Channel Abort bit(s) (DMACSR0[2]=1 and/or DMACSR1[2]=1). Wait until the Channel Done bit(s) is set (DMACSR0[4]=1 and/or DMACSR1[4]=1). 3.5.3.2 DMA Clear Count Mode The PCI 9054 supports DMA Clear Count mode (Write-Back feature, DMAMODE0[16] and DMAMODE1[16]). This feature allows users to control the data transfer blocks during Scatter/Gather DMA operations. The PCI 9054 clears the Transfer Size descriptor to zero by writing to a descriptor-memory location at the end of each transfer chain. This feature works only if DMA descriptors are on the Local Bus. Note: One to two Data transfers occur after the Abort bit is set. Aborting when no DMA cycles are in progress causes the next DMA to abort. 3.5.5 3.5.4 DMA Memory Write and Invalidate The PCI 9054 can be programmed to perform Memory Write and Invalidate cycles to the PCI Bus for DMA transfers, as well as PCI Initiator transfers (refer to Section 3.4.1.10). The PCI 9054 supports Memory Write and Invalidate transfers for cache line sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or DMA Priority The DMA Channel Priority bit (MARBR[20:19]) can be used to specify the following priorities: * Rotating (MARBR[20:19]=00) * DMA Channel 0 (MARBR[20:19]=01) * DMA Channel 1 (MARBR[20:19]=10) PCI 9054 Data Book v2.1 3-20 (c) PLX Technology, Inc. All rights reserved. www..com DMA Operation Section 3 M Mode Functional Description 1 Set DMA Mode to Scatter/Gather 3 First PCI Address First Local Address Local or Host Memory PCI Memory Mode Register 2 Set up First Descriptor Pointer Register (Required only for the first Descriptor Pointer) Memory Descriptor Block(s) First Transfer Size (byte count) Next Descriptor Pointer First Memory Block to Transfer PCI Address Local Address Transfer Size (byte count) Next Descriptor Pointer Command/Status Register Next Memory Block to Transfer End of Chain Specification Bit Local Memory 4 Set Enable and Go Bits in DMA Command/Status Register (DMACSR0 and DMACSR1) to Initiate DMA Transfer First Memory Block to Transfer Next Memory Block to Transfer Figure 3-16. Scatter/Gather DMA Mode Descriptor Initialization [PCI SAC/DAC PCI Address (DMADAC0, DMADAC1) Register Dependent] Local or Host Memory PCI Memory 1 Set DMA Mode to Scatter/Gather 3 PCI Address Low First Local Address Mode Register 2 Set up First Descriptor Pointer Register (Required only for the first Descriptor Pointer) Memory Descriptor Block(s) First Transfer Size (byte count) Next Descriptor Pointer PCI Address High First Memory Block to Transfer PCI Address Low Local Address Transfer Size (byte count) Next Descriptor Pointer Next Memory Block to Transfer Command/Status Register PCI Address High Local Memory 4 Set Enable and Go Bits in DMA Command/Status Register (DMACSR0 and DMACSR1) to Initiate DMA Transfer End of Chain Specification Bit First Memory Block to Transfer Next Memory Block to Transfer Figure 3-17. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address (DMAMODE0[18], DMAMODE1[18]) Descriptor Dependent (PCI Address High Added) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-21 Section 3--M Func Desc www..com Section 3 M Mode Functional Description DMA Operation 3.5.6 DMA Channel 0/1 Interrupts A DMA channel can assert a PCI Bus or Local Bus interrupt when done (transfer complete) or after a transfer is complete for the current descriptor in Scatter/ Gather DMA mode. The DMA Channel Interrupt Select bit(s) determine whether to assert a PCI (DMAMODE0[17]=1 and/or DMAMODE1[17]=1) or Local (DMAMODE0[17]=0 and/or DMAMODE1[17]=0) interrupt. The Local or PCI processor can read the DMA Channel 0 Interrupt Active bits to determine whether a DMA Channel 0 (INTCSR[21]) or DMA Channel 1 (INTCSR[22]) interrupt is pending. The Channel Done bit(s) (DMACSR0[4] and/or DMACSR1[4]) can be used to determine whether an interrupt is: * DMA Done interrupt * Transfer complete for current descriptor interrupt The Done Interrupt Enable bit(s) (DMAMODE0[10] and/or DMAMODE1[10]) enable a Done interrupt. In Scatter/Gather DMA mode, a bit in the Next Descriptor Pointer register of the channel (loaded from Local memory) specifies whether to assert an interrupt at the end of the transfer for the current descriptor. A DMA Channel interrupt is cleared by the Channel Clear Interrupt bit(s) (DMACSR0[3]=1 and/or DMACSR1[3]=1). 3.5.7 DMA Data Transfers The PCI 9054 DMA controller can be programmed to transfer data from the Local-to-PCI Bus or from the PCI-to-Local Bus. PCI 9054 Data Book v2.1 3-22 (c) PLX Technology, Inc. All rights reserved. www..com DMA Operation Section 3 M Mode Functional Description 3.5.7.1 Local-to-PCI Bus DMA Transfer PCI Interrupt Generation (Programmable) Local Interrupt Generation (Programmable) * Done Unload FIFO with PCI Bus Write Cycles * Done FIFO PCI Bus Arbitration Local Bus Arbitration Load FIFO with Local Bus Read Cycles PCI Bus Arbitration: Local Bus Arbitration: * Releases control of PCI Bus whenever FIFO becomes empty, PCI Bus Latency Timer expires and PCI GNT# de-asserts, PCI disconnect is received, or Direct Local-to-PCI Bus request is pending. GNT# Rearbitrates for control of PCI Bus when preprogrammed number of entries in FIFO becomes available, or after two PCI clocks if disconnect is received. REQ# BG# BR#, BB# * Releases control of Local Bus whenever FIFO becomes full, terminal count is reached, Local Bus Latency Timer is enabled and expires, or Direct PCI-to-Local Bus request is pending. Rearbitrates for control of Local Bus when preprogrammed number of empty entries in FIFO becomes available. If Local Bus Latency Timer is enabled and expires, waits until Local Bus Pause Timer expires. * * Figure 3-18. Local-to-PCI Bus DMA Data Transfer Operation Section 3--M Func Desc 3-23 3.5.7.2 PCI-to-Local Bus DMA Transfer Local Interrupt Generation (Programmable) PCI Interrupt Generation (Programmable) * Done Load FIFO with PCI Bus Read Cycles * Done FIFO PC Bus Arbitration Local Bus Arbitration Unload FIFO with Local Bus Write Cycles PCI Bus Arbitration: Local Bus Arbitration: * Releases control of PCI Bus whenever FIFO becomes full, terminal count is reached, PCI Latency Timer expires and PCI GNT# de-asserts, PCI disconnect is received, or Direct Local-to-PCI Bus request is pending. Rearbitrates for control of PCI Bus when preprogrammed number of empty entries in FIFO becomes available, or after two PCI clocks if disconnect is received. GNT# REQ# BG# BR#, BB# * Releases control of Local Bus whenever FIFO becomes empty, Local Bus Latency Timer is enabled and expires, or Direct PCI-to-Local Bus request is pending. Rearbitrates for control of Local Bus when preprogrammed number of entries becomes available in FIFO or PCI terminal count is reached. IfLocal Bus Latency Timer is enabled and expires, waits until Local Bus Pause Timer expires * * Figure 3-19. PCI-to-Local Bus DMA Data Transfer Operation PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. www..com Section 3 M Mode Functional Description DMA Operation 3.5.7.3 DMA Local Bus Error Condition The PCI 9054 supports Local Bus error conditions with the TEA# signal. TEA# may be asserted by a device on the Local Bus, either before or simultaneously with TA#. In either case, the PCI 9054 attempts to finish the current transaction by transferring data and then asserting TS# for every address that follows, waiting for another TA# or TEA# to be issued to flush the FIFOs. After sensing TEA# is asserted, the PCI 9054 asserts PCI SERR# and sets the Signaled System Error bit (PCISR[14], indicating a catastrophic error occurred on the Local Bus. SERR# may be masked by resetting the TEA# Input Interrupt Mask bit (LMISC[5]=0). The PCI 9054 Local Bus Latency Timer (MARBR[7:0]), as well as the Local Bus Pause Timer (MARBR[15:8]), can be used to better utilize the Local Bus. If BDIP# output must be de-asserted before the last Lword of the DMA transfer (bit [15]=0), the DMA controller continues transferring data up to the nearest 16-byte boundary. If DREQ0# is de-asserted during the Address phase of the first transfer in PCI 9054 Local Bus ownership (TS#, BG# asserted), the DMA controller completes a 16-byte transfer. If DREQ0# is de-asserted during a Data-Transfer phase, one Lword before the last 16-byte transfer, the PCI 9054 finishes the transfer and performs an additional 16-byte transfer to satisfy BDIP# de-assertion protocol. (Refer to Table 3-7.) Table 3-7. Demand Mode DMA, Channel 0 BTERM# Input Enable Bit(s) Enabled (1) Enabled (1) Disabled (0) Fast/Slow Terminate Mode Select Bit(s) Disabled (1) Enabled (0) Disabled (1) Enabled (0) PCI 9054 BDIP# Output BDIP# is not asserted. Immediate transfer terminated by EOT#. BDIP# asserted by the PCI 9054. Transfers up to the nearest 16-byte boundary, then terminates (MPC850 or MPC860 compatible). 3.5.7.4 DMA Unaligned Transfers For unaligned Local-to-PCI transfers, the PCI 9054 reads a partial Lword from the Local Bus. It continues to perform a Single-Cycle read (Lwords) from the Local Bus until the nearest 16-byte boundary. If the Burst Mode bit is enabled, the PCI 9054 bursts thereafter. Lwords are assembled, aligned to the PCI Bus address, and loaded into the FIFO until the nearest 16-byte boundary. For PCI-to-Local transfers, Lwords are read from the PCI Bus and loaded into the FIFO. On the Local Bus, Lwords are assembled from the FIFO, aligned to the Local Bus address and single cycle written to the Local Bus until the nearest 16-byte boundary. If burst functionality is enabled, the PCI 9054 bursts thereafter. Disabled (0) 3.5.9 End of Transfer (EOT#) Input The DMA EOT# Enable bit(s) (DMAMODE0[14] and DMAMODE1[14]) determines the number of Lwords to transfer after a DMA controller asserts EOT# input. EOT# input should be asserted only when the PCI 9054 owns a bus. (Refer to Table 3-8.) If BDIP# output is not required to be de-asserted before the last Lword of the DMA transfer (DMAMODE0[15]=1 and/or DMAMODE1[15]=1), and the DMA EOT# Enable bit(s) is set (DMAMODE0[14]=1 and/or DMAMODE1[14]=1), the DMA controller releases the data bus and terminates DMA after receiving an external TA# signal. Or, the internal wait state counter decrements to 0 for the current Lword when EOT# is asserted. If BDIP# output must be de-asserted before the last Lword of the DMA transfer (DMAMODE0[15]=0 and/or DMAMODE1[15]=0), the DMA controller transfers data up to the nearest 16-byte boundary if EOT# is asserted and enabled (DMAMODE0[14]=1 and/or DMAMODE1[14]=1). 3.5.8 Demand Mode DMA, Channel 0 The Fast/Slow Terminate Mode Select bit(s) (DMAMODE0[15] and/or DMAMODE1[15]) determines the number of Lwords to transfer after the DMA controller DREQ0# input is de-asserted. If BDIP# output is not required to be de-asserted before the last Lword of a DMA transfer (bit [15]=1), the DMA controller releases the data bus after it receives an external TA# or the internal wait state counter decrements to 0 for the current Lword. If the DMA controller is currently bursting data, which is not the last Data phase for the burst, BDIP# is not asserted before the last Lword of the DMA transfer. PCI 9054 Data Book v2.1 3-24 (c) PLX Technology, Inc. All rights reserved. www..com DMA Operation Section 3 M Mode Functional Description When the BTERM# Enable bit is disabled, Fast/Slow Terminate is enabled, and EOT# is asserted during the Data-Transfer phase of the last four bytes of a 16-byte transfer, the PCI 9054 completes the transfer and performs an additional 16-byte transfer to satisfy the BDIP# de-assertion protocol. Otherwise, it completes the current 16-byte transfer. When the BTERM# Enable bit is enabled, or the BTERM# Enable bit is disabled and Fast/Slow Terminate is disabled, the DMA controller terminates a transfer on an Lword boundary after EOT# is asserted. For an 8-bit bus, the PCI 9054 terminates after transferring the last byte for the Lword. For a 16-bit bus, the PCI 9054 terminates after transferring the last word for the Lword. In Single-Cycle mode (burst disabled), the transfer is terminated at the next Lword boundary after EOT# occurs. The exception to this is when EOT# occurs on the last four bytes of the Transfer Count setting. During the descriptor loading on the Local Bus, assertion of EOT# causes a complete descriptor load and no subsequent Data transfer; however, this is not recommended. This has no effect when the descriptor is loaded from the PCI Bus. Table 3-8. Any DMA Transfer Channel 0/1 with EOT Functionality BTERM# Enable Bit(s) Enabled (1) Enabled (1) Disabled (0) 3.5.10 DMA Arbitration The PCI 9054 asserts BR# when it needs to be the Local Bus Master. Upon receiving BG#, the PCI 9054 waits for BB# to be de-asserted. The PCI 9054 then asserts BB# at the next rising edge of the Local clock after sensing that BB# is de-asserted (no other device is acting as Local Bus Master). The PCI 9054 continues to assert BB# while acting as the Local Bus Master (that is, it holds the bus until instructed to release BB#) under the following conditions: * Local Bus Latency Timer is enabled and expires (MARBR[7:0]) * PCI Target access is pending * EOT# input is received (if enabled) The DMA controller releases control of the PCI Bus when one of the following conditions occurs: * PCI Bus Latency Timer expires (PCILTR[7:0])--and loses the PCI GNT# signal * Target disconnect response is received The DMA controller de-asserts its PCI Bus request (REQ#) for a minimum of two PCI clocks. Section 3--M Func Desc * FIFOs are full or empty Fast/Slow Terminate Mode Select Bit(s) Disabled (1) Enabled (0) Disabled (1) 3.5.11 Local Bus Latency and Pause Timers The Local Bus Latency and Pause Timers are programmable with the Mode/DMA Arbitration register (MARBR[7:0, 15:8]). If the Local Bus Latency Timer is enabled and expires (MARBR[7:0]), the PCI 9054 completes an Lword transfer up to the nearest 16-byte boundary and releases the Local Bus, de-asserting BB#. After the programmable Pause Timer expires (MARBR[15:8]), it arbitrates for the bus by asserting BR#. When it receives BG#, it asserts BB# and continues to transfer until the FIFO is empty for a Local-to-PCI transfer or full for a PCI-to-Local transfer. The DMA transfer can be paused by writing a 0 to the Channel Enable bit. To acknowledge the disable, the PCI 9054 gets at least one data from the bus before it stops. However, this is not recommended during a burst. The DMA Local Bus Timer starts after the Local Bus is granted to the PCI 9054 and the Local Pause Timer starts after BB# is de-asserted. PCI 9054 BDIP# Output BDIP# is not asserted. Transfer is immediately terminated by EOT# or paused by DREQ# at Lword boundary. BDIP# asserted by the PCI 9054. Transfers up to the nearest 16-byte boundary, then terminates (MPC850 or MPC860 compatible). Disabled (0) Enabled (0) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-25 www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 3.6 M MODE TIMING DIAGRAMS 0ns 250ns 500ns LCLK BR# BG# BB# Other Local Bus Master drives Local Bus PCI 9054 asserts BB# to drives Local Bus and de-asserts BB# to end cycle PCI 9054 requests Local Bus Timing Diagram 3-1. Local Bus Arbitration (BR#, BG#, BB#, and so forth) PCI 9054 Data Book v2.1 3-26 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 3.6.1 M Mode PCI Initiator 0ns 250ns 500ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A 7 0 D0 LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 00 A0 Timing Diagram 3-2. PCI Initiator Single Write Cycle, Zero Wait States PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-27 Section 3--M Func Desc www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 6 A 0 D0 LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# WAIT# D0 00 A0 Timing Diagram 3-3. PCI Initiator Single Read Cycle, One Wait State (WAIT# Asserted for One Clock) PCI 9054 Data Book v2.1 3-28 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# Section 3--M Func Desc 00 D0 D1 D2 D3 A 7 D0 D1 D2 0 D3 TRDY# LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-4. PCI Initiator Burst Write Cycle of Four Lwords, Zero Wait States A0 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-29 www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A 6 D0 D1 0 D2 D3 LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-5. PCI Initiator Burst Read Cycle of Four Lwords, Zero Wait States D0 D1 D2 D3 00 A0 PCI 9054 Data Book v2.1 3-30 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# Section 3--M Func Desc D0 A 6 0 D0 LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# RETRY# 00 00 A0 A0 Timing Diagram 3-6. PCI Initiator Deferred Read Mode (RETRY#) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-31 www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A 6 D0 D1 D2 D3 D4 D5 D6 D7 0 LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-7. PCI Initiator Burst Read with Read Ahead Mode (Prefetch Counter Set to Eight Lwords) D0 D1 D2 D3 D4 D5 D6 D7 00 A0 A4 PCI 9054 Data Book v2.1 3-32 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns LCLK LA[0:31] CCS# RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# It takes a minimum of five clocks for the PCI 9054 to assert TA# D0 00 A0 Timing Diagram 3-8. Local Configuration Write to Configuration Register 0ns 250ns 500ns LCLK LA[0:31] CCS# RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# It takes a minimum of five clocks for the PCI 9054 to assert TA# D0 00 A0 Timing Diagram 3-9. Local Configuration Read from Configuration Register PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-33 Section 3--M Func Desc www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A 7 D0 D1 D2 0 D3 D4 D5 LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 D4 D5 00 A0 Timing Diagram 3-10. PCI Initiator Burst Write of Six Lwords beyond MPC860 Protocol PCI 9054 Data Book v2.1 3-34 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns 7 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A 6 D0 D1 D2 0 D3 D4 D5 LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 D4 D5 00 A0 Timing Diagram 3-11. PCI Initiator Burst Read of Six Lwords beyond MPC860 Protocol PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-35 Section 3--M Func Desc www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 3.6.2 M Mode PCI Target 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A 7 D0 0 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 00 A0 Timing Diagram 3-12. PCI Target Single Write Cycle, Zero Wait States PCI 9054 Data Book v2.1 3-36 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A 7 D0 0 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 00 A0 Timing Diagram 3-13. PCI Target Single Write Cycle, One Wait State by Delaying TA# PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-37 Section 3--M Func Desc www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns 750ns LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# LD[0:31] TA# Timing Diagram 3-14. Local Bus Single Write Cycle, Zero Wait States, Burst Enabled, 16-Bit Local Bus D D 10 10 A A+2 PCI 9054 Data Book v2.1 3-38 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns 750ns LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# LD[0:31] TA# Timing Diagram 3-15. Local Bus Single Write Cycle, One Wait State, Burst Disabled, 8-Bit Local Bus D D D D 01 01 01 01 A A+1 A+2 A+3 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-39 Section 3--M Func Desc www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 6 0 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 00 A0 Timing Diagram 3-16. PCI Target Single Read Cycle, Zero Wait States PCI 9054 Data Book v2.1 3-40 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 6 0 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 00 A0 Timing Diagram 3-17. PCI Target Single Read Cycle, One Wait State Using TA# PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-41 Section 3--M Func Desc www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 0 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D A A+2 10 10 D Timing Diagram 3-18. PCI Target Single Read Cycle, Zero Wait States, 16-Bit Bus PCI 9054 Data Book v2.1 3-42 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns 750ns LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# LD[0:31] TA# Timing Diagram 3-19. PCI Target Single Read Cycle, One Wait State, Burst Disabled, 8-Bit Local Bus D D D D 01 A A+1 A+2 A+3 0ns 250ns 500ns 750ns LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 00 A0 A1 A2 A3 Timing Diagram 3-20. PCI Target Burst Write Cycle of Four Lwords, Bterm Disabled, Burst Enabled PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-43 Section 3--M Func Desc www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns 750ns LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 00 A0 A1 A2 A3 Timing Diagram 3-21. PCI Target Burst Read Cycle of Four Lwords, Bterm Disabled, Burst Enabled 0ns 250ns 500ns 750ns LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 D4 D5 D6 D7 00 00 A0 A1 A2 A3 A4 A5 A6 A7 Timing Diagram 3-22. PCI Target Burst Write Cycle of Eight Lwords, Bterm Disabled, Burst Enabled PCI 9054 Data Book v2.1 3-44 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns 750ns LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 D4 D5 D6 D7 00 00 A0 A1 A2 A3 A4 A5 A6 A7 Timing Diagram 3-23. PCI Target Burst Read Cycle of Eight Lwords, Bterm Disabled, Burst Enabled 0ns 250ns 500ns 750ns LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 00 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Timing Diagram 3-24. PCI Target Burst Write Cycle of 10 Lwords, Zero Wait States beyond MPC860 Protocol, Bterm Enabled, Burst Enabled PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-45 Section 3--M Func Desc www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns 750ns LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 00 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Timing Diagram 3-25. PCI Target Burst Read Cycle of 10 Lwords, Zero Wait States beyond MPC860 Protocol, Bterm Enabled, Burst Enabled PCI 9054 Data Book v2.1 3-46 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0us 5us 10us 15us 20us 25us 30us EESK LRESETo# EECS EEDI EEDO 0 1 1 0 0 0 0 0 0 0 0 0 INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----| 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] CONFIGURATION REGISTER 0 HEX EESK EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 CONTINUES EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LAST WORD CONTINUES EESK, EEDO, EECS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ Timing Diagram 3-26. Initialization from Serial EEPROM (2K Bit) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-47 Section 3--M Func Desc BITS [15:0] CONFIGURATION REGISTER 0 HEX BITS [31:16] OF CONFIGURATION REGISTER 8 HEX www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0us 5us 10us 15us 20us 25us 30us EESK LRESETo# EECS EEDI EEDO 0 1 1 0 0 0 0 0 0 0 0 0 INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----| 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] CONFIGURATION REGISTER 0 HEX EESK EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 BITS [15:0] CONFIGURATION REGISTER 0 HEX BITS [31:16] OF CONFIGURATION REGISTER 8 HEX CONTINUES EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LAST WORD CONTINUES EESK, EEDO, EECS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ Timing Diagram 3-27. Initialization from Serial EEPROM (4K Bit) 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=B Data BE Timing Diagram 3-28. PCI Configuration Write to PCI Configuration Register PCI 9054 Data Book v2.1 3-48 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 50ns 100ns 150ns 200ns 250ns 300n CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=A Data Read BE Timing Diagram 3-29. PCI Configuration Read to PCI Configuration Register 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=7 Data BE Timing Diagram 3-30. PCI Memory Write to Local Configuration Register PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-49 Section 3--M Func Desc www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=6 BE Data Read Timing Diagram 3-31. PCI Memory Read to Local Configuration Register 0ns 100ns 200ns 300ns 400ns 500n CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR DATA CMD BE INTA# RESPONSE ON THE PCI BUS LCLK LINT# Timing Diagram 3-32. Local Interrupt Asserting PCI Interrupt PCI 9054 Data Book v2.1 3-50 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 3.6.3 M Mode DMA 0ns 250ns 500ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# Section 3--M Func Desc 00 LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# TEA# A0 Timing Diagram 3-33. Master Abort Condition During PCI Initiator Read Cycle Causes TEA# PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-51 www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 D1 D2 D3 D4 D5 D6 D7 E 00 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 D4 D5 D6 D7 00 00 A0 A1 A2 A3 A4 A5 A6 A7 Timing Diagram 3-34. DMA PCI-to-Local, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords PCI 9054 Data Book v2.1 3-52 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 D1 D2 D3 D4 D5 D6 D7 7 00 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 D4 D5 D6 D7 00 00 A0 A1 A2 A3 A4 A5 A6 A7 Timing Diagram 3-35. DMA Local-to-PCI, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-53 Section 3--M Func Desc www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A 7 D0 D1 D2 D3 D4 D5 00 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Example: Starting Local Address = 1008h, Starting PCI Address = 1000h D0 D1 D2 D3 D4 D5 00 A A A Timing Diagram 3-36. DMA Local-to-PCI, Address Unaligned, Bterm Disabled, Burst Enabled, Transfer Size = Six Lwords PCI 9054 Data Book v2.1 3-54 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 D1 D2 D3 D4 D5 D6 D7 D8 8 E 0111 00 LCLK BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Example: Starting PCI Address = 1003h, Starting Local Address = 1000h D0 D1 D2 D3 D4 D5 D6 D7 00 00 A0 A1 A2 A3 A4 A5 A6 A7 Timing Diagram 3-37. DMA PCI-to-Local, Address Unaligned, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-55 Section 3--M Func Desc BR# www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 D1 D2 D3 7 00 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# EOT# D0 D1 D2 D3 00 A0 A1 A2 A3 Timing Diagram 3-38. DMA Local-to-PCI, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts in the Middle of the Quad-Lword of Data PCI 9054 Data Book v2.1 3-56 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 D1 D2 D3 D4 D5 D6 D7 7 00 LCLK BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# EOT# D0 D1 D2 D3 D4 D5 D6 D7 00 00 A0 A1 A2 A3 A4 A5 A6 A7 Timing Diagram 3-39. DMA Local-to-PCI, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at the Last Data of the First Quad-Lword PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-57 Section 3--M Func Desc BR# www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 D1 D2 D3 D4 D5 D6 D7 E 00 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# EOT# D0 D1 D2 D3 00 A0 A1 A2 A3 Timing Diagram 3-40. DMA PCI-to-Local, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts in the Middle of the First Quad-Lword of Data PCI 9054 Data Book v2.1 3-58 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 D1 D2 D3 D4 D5 D6 D7 E 00 LCLK BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# EOT# D0 D1 D2 D3 D4 D5 D6 D7 00 00 A0 A1 A2 A3 A4 A5 A6 A7 Timing Diagram 3-41. DMA PCI-to-Local, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at the Last Data of the First Quad-Lword PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-59 Section 3--M Func Desc BR# www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 D1 D2 D3 D4 7 00 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# EOT# D0 D1 D2 D3 D4 00 A0 A1 A2 A3 A4 Timing Diagram 3-42. DMA Local-to-PCI, Bterm Enabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at End of Third Local Data beyond MPC860 Protocol PCI 9054 Data Book v2.1 3-60 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 D1 D2 D3 D4 D5 D6 D7 E LCLK BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# EOT# D0 D1 D2 D3 D4 00 A0 A1 A2 A3 A4 Timing Diagram 3-43. DMA PCI-to-Local, Bterm Enabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at End of Third Local Data beyond MPC860 Protocol PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-61 Section 3--M Func Desc BR# www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns 750ns LCLK BR# Local Bus Pause Timer expires, Resume DMA operation BG# Kick off Local Bus Latency Timer BB# Kick off Local Bus Pause Timer TS# Local Bus Latency Timer expires --> PCI 9054 releases Local Bus after last data transferred (or up to Quad-Lword boundary during burst) TA# R/W# Timing Diagram 3-44. Local Bus Latency Timer (Eight Clocks) and Pause Timer (Four Clocks) in DMA Operation 0ns 250ns 500ns 750ns LCLK BR# Local Bus Pause Timer expires, resume DMA operation BG# (BG#) Kick off Local Bus Latency Timer BB# (BB# de-asserts) Kick off Pause Timer TS# Local Bus Latency Timer expires --> PCI 9054 finishes current data and one more data is transferred before releasing the Local Bus (de-asserts BB#) TA# R/W# Timing Diagram 3-45. Local Bus Latency Timer (Eight Clocks) and Pause Timer (Four Clocks) in DMA Operation beyond MPC860 Protocol PCI 9054 Data Book v2.1 3-62 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 E 00 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 00 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Timing Diagram 3-46. DMA PCI-to-Local, Bterm Enabled, Burst Enabled, Transfer Size = 10 Lwords, beyond MPC860 Protocol PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 3-63 Section 3--M Func Desc www..com Section 3 M Mode Functional Description M Mode Timing Diagrams 0ns 250ns 500ns 750ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 7 LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 00 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Timing Diagram 3-47. DMA Local-to-PCI, Bterm Enabled, Burst Enabled, Transfer Size = 10 Lwords, beyond MPC860 Protocol PCI 9054 Data Book v2.1 3-64 (c) PLX Technology, Inc. All rights reserved. www..com M Mode Timing Diagrams Section 3 M Mode Functional Description 0ns 250ns 500ns 750ns LCLK MDREQ# LA[0:31] TS# RD/WR# LD[0:31] TA# SDACK[1:0]# Section 3--M Func Desc 3-65 User must clear the IDMA Enable bit when the MPC850 or MPC860 is done (monitor interrupt) with the IDMA cycle. D0 Timing Diagram 3-48. IDMA Single Write Cycle Notes: The PCI 9054 treats the IDMA function from the MPC850 or MPC860 the same as a PCI Initiator cycle. The MPC850 or MPC860 starts IDMA cycle when the IDMA Enable bit is set in the MPC850 or MPC860 respective register. The PCI 9054 does not look at SDACK[1:0]# because the pins do not exist in the PCI 9054 (not connected). PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. www..com www..com 4 4.1 C AND J MODES BUS OPERATION PCI BUS CYCLES 4.1.2.1 DMA Master Command Codes DMA controllers of the PCI 9054 can assert the Memory cycles listed in Table 4-2. Table 4-2. DMA Master Command Codes Command Type Memory Read Memory Write Memory Read Multiple PCI Dual Address Cycle The PCI 9054 is compliant with PCI Specification v2.2. Refer to PCI Specification v2.2 for specific PCI Bus functions. 4.1.1 PCI Target Command Codes Code (C/BE[3:0]#) 0110 (6h) 0111 (7h) 1100 (Ch) 1101 (Dh) 1110 (Eh) 1111 (Fh) As a Target, the PCI 9054 allows access to the PCI 9054 internal registers and the Local Bus, using the commands listed in Table 4-1. All Read or Write accesses to the PCI 9054 can be Byte, Word, or Lword (longword) accesses, defined as 32 bit. All memory commands are aliased to basic memory commands. All I/O accesses to the PCI 9054 are decoded to an Lword boundary. Byte enables are used to determine which bytes are read or written. An I/O access with illegal byte enable combinations is terminated with a Target Abort. Table 4-1. PCI Target Command Codes Command Type I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple PCI Dual Address Cycle Memory Read Line Memory Write and Invalidate Memory Read Line Memory Write and Invalidate 4.1.2.2 Direct Local-to-PCI Command Codes For direct Local-to-PCI Bus accesses, the PCI 9054 asserts the cycles listed in Table 4-3 through Table 4-5. Table 4-3. Local-to-PCI Memory Access Command Type Memory Read Memory Write Memory Read Multiple PCI Dual Address Cycle Memory Read Line Memory Write and Invalidate Code (C/BE[3:0]#) 0010 (2h) 0011 (3h) 0110 (6h) 0111 (7h) 1010 (Ah) 1011 (Bh) 1100 (Ch) 1101 (Dh) 1110 (Eh) 1111 (Fh) Code (C/BE[3:0]#) 0110 (6h) 0111 (7h) 1100 (Ch) 1101 (Dh) 1111 (Fh) Table 4-4. Local-to-PCI I/O Access Command Type I/O Read I/O Write Code (C/BE[3:0]#) 0010 (2h) 0011 (3h) 4.1.2 PCI Master Command Codes The PCI 9054 can access the PCI Bus to perform DMA or PCI Initiator Local-to-PCI Bus transfers. During a PCI Initiator or DMA transfer, the command code assigned to the PCI 9054 internal register location (CNTRL[15:0]) is used as the PCI command code (except for Memory Write and Invalidate mode for DMA cycles where (DMPBAM[9]=1). Table 4-2 through Table 4-5 lists various PCI Master Command codes. Notes: Programmable internal registers determine PCI command codes when the PCI 9054 is the Master. DMA cannot perform I/O or configuration accesses. Table 4-5. Local-to-PCI Configuration Access Command Type Configuration Memory Read Configuration Memory Write Code (C/BE[3:0]#) 1010 (Ah) 1011 (Bh) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 4-1 Section 4--C, J Bus Op 1110 (Eh) www..com Section 4 C and J Modes Bus Operation Local Bus Cycles 4.1.3 PCI Arbitration 4.2.1 Local Bus Arbitration The PCI 9054 asserts REQ# to request the PCI Bus. The PCI 9054 can be programmed using the PCI Request Mode bit (MARBR[23]) to de-assert REQ# when it asserts FRAME# during a Bus Master cycle, or to keep REQ# asserted for the entire Bus Master cycle. The PCI 9054 always de-asserts REQ# for a minimum of two PCI clocks between Bus Master ownership that includes a Target disconnect. The PCI Initiator Write Delay bits (DMPBAM[15:14]) can be programmed to delay the PCI 9054 from asserting PCI REQ# during a PCI Initiator Write cycle. DMPBAM can be programmed to wait 0, 4, 8, or 16 PCI Bus clocks after the PCI 9054 has received its first Write data from the Local Bus Master and is ready to begin the PCI Write transaction. This function is useful in applications where a Local Master is bursting and a Local Bus clock is slower than the PCI Bus clock. This allows Write data to accumulate in the PCI 9054 PCI Initiator Write FIFO, which provides for better use of the PCI Bus. The PCI 9054 asserts LHOLD to request the Local Bus. It owns the Local Bus when LHOLD and LHOLDA are asserted. When the PCI 9054 acknowledges BREQi assertion during DMA or PCI Target Write transfers, it releases the Local Bus within two Lword transfers by de-asserting LHOLD and floating the Local Bus outputs if either of the following conditions exist: * BREQi is asserted and enabled * Gating is enabled and the Local Bus Latency Timer is enabled and expires (MARBR[27, 7:0]) The Local Arbiter can now grant the Local Bus to another Local Master. After the PCI 9054 acknowledges that LHOLDA is de-asserted and the Local Bus Pause Timer is zero, it re-asserts LHOLD to request the Local Bus. When the PCI 9054 receives LHOLDA, it drives the bus and continues the transfer. Note: The Local Bus Pause Timer applies only to DMA operation. It does not apply to PCI Target operation. 4.2 LOCAL BUS CYCLES 4.2.2 PCI Initiator The PCI 9054 interfaces a PCI Host bus to several Local Bus types, as listed in Table 4-6 and Table 4-7. It operates in one of three modes, selected through MODE[1:0] (PQFP--Pins 157 and 156; PBGA--Pins B7 and E8), corresponding to three bus types--M, J, and C. Table 4-6. Local Bus Types (176-Pin PQFP) Pin 157 1 1 0 0 Pin 156 1 0 1 0 Mode M Reserved J C -- Bus Type 32-bit non-multiplexed 32-bit multiplexed 32-bit non-multiplexed Local Bus cycles can be Single or Burst cycles. The BLAST# signal is used to determine if a Single or Burst cycle is to be performed. If BLAST# is asserted at the beginning of the first Data phase, on which the PCI 9054 performs a Single PCI Bus cycle. Otherwise, the PCI 9054 performs a Burst PCI Bus cycle and BLAST# is used to end the cycle. As a Local Bus Target, the PCI 9054 allows access to the PCI 9054 internal registers and the PCI Bus. Non-32- bit PCI Initiator accesses to the PCI 9054 require simple external logic (latch array to combine data into a 31-bit bus). Local Bus PCI Initiator accesses to the PCI 9054 must be for a 32-bit non-pipelined bus. Table 4-7. Local Bus Types (225-Pin PBGA) Pin B7 1 1 0 0 Pin E8 1 0 1 0 Mode M Reserved J C -- Bus Type 32-bit non-multiplexed 4.2.3 PCI Target 32-bit multiplexed 32-bit non-multiplexed The PCI Bus Master reads from and writes to the Local Bus (the PCI 9054 is a PCI Bus Target and a Local Bus Master). PCI 9054 Data Book v2.1 4-2 (c) PLX Technology, Inc. All rights reserved. www..com Local Bus Cycles Section 4 C and J Modes Bus Operation 4.2.4 Wait State Control PCI Bus Local Bus Accessing PCI 9054 from Local Bus [5:2]) can be used to program the number of internal wait states between the first address-to-data (and subsequent data-to-data in Burst mode). During PCI Initiator accesses, WAIT# signal must be asserted during the ADS phase for the PCI 9054 to sample the wait state phase. In PCI Target and DMA modes, the READY# signal has no effect until the wait state counter--(LBRD0[21:18, 5:2]), (LBRD1[5:2]), (DMAMODE0[5:2]), and/or (DMAMODE1[5:2])--reaches zero. READY# then controls the number of wait states by being de-asserted in the middle of the data transaction. Accessing PCI 9054 from PCI Bus PCI 9054 de-asserts TRDY# when waiting on the Local Bus PCI Bus de-asserts IRDY# or simply ends the cycle when it's not ready PCI 9054 accessing PCI Bus PCI 9054 can be programmed to de-assert IRDY# when its PCI Initiator Read FIFO is full PCI Bus de-asserts TRDY# when it's not ready PCI 9054 generates READY# when data is valid on the following clock edge Local Processor generates wait states with WAIT# PCI 9054 PCI 9054 accessing Local Bus PCI 9054 generates wait states with WAIT# (programmable) Local Bus can respond to PCI 9054 requests with READY# 4.2.4.2 Wait States--PCI Bus Figure 4-1. Wait States Note: The figure represents a sequence of Bus cycles. The PCI Bus Master throttles IRDY# and the PCI Bus Slave throttles TRDY# to assert PCI Bus wait state(s). 4.2.5 If READY# mode is disabled, the external READY# input signal has no effect on wait states for a Local access. Wait states between Data cycles are asserted internally by a wait state counter. The wait state counter is initialized with its Configuration register value at the start of each data access. If READY# mode is enabled, it has no effect until the wait state counter reaches 0. READY# then controls the number of additional wait states. BTERM# input is not sampled until the wait state counter reaches 0. BTERM# overrides READY# when BTERM# is enabled and asserted. Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode) Note: In the following sections, Bterm refers to the PCI 9054 internal register bit and BTERM# refers to the PCI 9054 external signal. 4.2.5.1 Burst and Bterm Modes Table 4-8. Burst and Bterm on the Local Bus Mode Single Cycle Single Cycle Burst-4 Burst 0 0 1 Bterm 0 1 0 Result One ADS# per data (default). One ADS# per data. One ADS# per four data (recommended for i960 and PPC401 family). One ADS# per BTERM# (refer to Section 4.2.5.2.1). 4.2.4.1 Wait States--Local Bus Burst Forever 1 1 In PCI Initiator mode and when accessing the PCI 9054 registers, the PCI 9054 acts as a Local Bus Slave. The PCI 9054 asserts wait states by delaying the READY# signal. The Local processor asserts wait states with the WAIT# signal. In PCI Target and DMA modes, the PCI 9054 acts as a Local Bus Master. The PCI 9054 inserts internal wait states with the WAIT# signal. The Local processor asserts external wait states by delaying the READY# signal. The Internal Wait State bit(s) (LBRD0[21:18, 5:2], (LBRD1[5:2]), DMAMODE0[5:2], and/or DMAMODE1 On the Local Bus, BLAST# and BTERM# perform the following: * If the Burst Mode bit is enabled, but the Bterm Mode bit is disabled, then the PCI 9054 bursts (up to a quad word boundary) four Lwords. BLAST# is asserted at the beginning of the fourth Lword Data phase (LA[3:2]=11) and a new ADS# is asserted at the first Lword (LA[3:2]=00) of the next burst. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 4-3 Section 4--C, J Bus Op www..com Section 4 C and J Modes Bus Operation Local Bus Cycles * If BTERM# is enabled and asserted, the PCI 9054 terminates the Burst cycle of the end of the current Data phase without generating BLAST#. The PCI 9054 generates a new burst transfer starting with a new ADS#, terminating it normally using BLAST#. * BTERM# input is valid only when the PCI 9054 is Master of the Local Bus (PCI Target or DMA modes). * As an input, BTERM# is asserted by external logic. It instructs the PCI 9054 to break up a Burst cycle. * BTERM# is used to indicate a memory access is crossing a page boundary or requires a new Address cycle. Notes: If Address Increment is disabled, the DMA transfer bursts beyond four Lwords. If the Bterm Mode bit is disabled, the PCI 9054 performs the following: * * * 32-bit Local Bus--Bursts up to four Lwords 16-bit Local Bus--Bursts up to two Lwords 8-bit Local Bus--Bursts up to one Lword enabled and the BTERM# signal is asserted, the PCI 9054 asserts BLAST# only if its Read FIFO is full, its Write FIFO is empty, or if a transfer is complete. 4.2.5.3 Partial Lword Accesses Lword accesses in which not all byte enables asserted will be broken into Single-Cycle accesses. Burst start addresses can be any Lword boundary. If the Burst Start Address in a PCI Target or DMA transfer is not aligned to an Lword boundary, the PCI 9054 first performs a Single cycle. It then starts to burst on the Lword boundary if there is remaining data that is not a whole Lword during DMA (for example, it will result in a Single cycle at the end). 4.2.6 Recovery States (J Mode Only) In every case, it performs four transactions. 4.2.5.2 Burst-4 Lword Mode In J mode, the PCI 9054 inserts one recovery state between the last Data transfer and the next Address cycle. Note: The PCI 9054 does not support the i960J function that uses READY# input to add recovery states. No additional recovery states are added if READY# input remains asserted during the last Data cycle. If the Burst Mode bit is enabled and the Bterm Mode bit is disabled, bursting can start on any Lword boundary and continue up to a 16-byte address boundary. After data up to the boundary is transferred, the PCI 9054 asserts a new Address cycle (ADS#). Table 4-9. Burst-4 Lword Mode Bus Width 32 bit 16 bit 8 bit 4.2.7 Local Bus Read Accesses Burst Four Lwords or up to a quad-Lword boundary (LA3, LA2 = 11) Four words or up to a quad-word boundary (LA2, LA1 = 11) Four bytes or up to a quad-byte boundary (LA1, LA0 = 11) For all Single-Cycle Local Bus Read accesses, the PCI 9054 reads only bytes corresponding to byte enables requested by the PCI Initiator. For all Burst Read cycles, the PCI 9054 passes all the bytes and can be programmed to: * Prefetch * Perform Read Ahead mode * Generate internal wait states * Enable external wait control (READY# input) * Enable type of Burst mode to perform 4.2.5.2.1 Continuous Burst Mode (Bterm "Burst Terminate" Mode) If both the Burst and Bterm Mode bits are enabled, the PCI 9054 can operate beyond the Burst-4 Lword mode. Bterm mode enables PCI 9054 to perform long bursts to devices that can accept bursts of longer than four Lwords. The PCI 9054 asserts one Address cycle and continues to burst data. If a device requires a new Address cycle (ADS#), it can assert BTERM# input to cause the PCI 9054 to assert a new Address cycle. BTERM# input acknowledges current Data transfer and requests that a new Address cycle be asserted (ADS#). The new address is for the next Data transfer. If the Bterm Mode bit is 4.2.8 Local Bus Write Accesses For Local Bus writes, only bytes specified by a PCI Bus Master or the PCI 9054 DMA controller are written. 4.2.9 PCI Target Accesses to 8- or 16-Bit Local Bus Direct PCI access to an 8- or 16-bit Local Bus results in the PCI Bus Lword being broken into multiple Local Bus transfers. For each transfer, byte enables are encoded as in the i960C to provide Local Address bits LA[1:0]. PCI 9054 Data Book v2.1 4-4 (c) PLX Technology, Inc. All rights reserved. www..com Big Endian/Little Endian Section 4 C and J Modes Bus Operation 4.2.10 Local Bus Data Parity Generation or use of Local Bus data parity is optional. Signals on the data parity pins do not affect operation of the PCI 9054. The PCI Bus parity checking and generation is independent of the Local Bus parity checking and generation. PCI Bus parity checking may result in assertion of PERR#, a PCI Bus system error (SERR#), or other means of PCI Bus transfer termination as a result of the parity error on the PCI data address, command code, and byte enables. The Local Bus Parity Check is passive and only provides parity information to the Local processor during PCI Initiator, PCI Target, and DMA transfers. There is one data parity pin for each byte lane of the PCI 9054 data bus (DP[3:0]). "Even data parity" is asserted for each lane during Local Bus reads from the PCI 9054 and during PCI 9054 Master writes to the Local Bus. Even data parity is checked during Local Bus writes to the PCI 9054 and during PCI 9054 reads from the Local Bus. Parity is checked for each byte lane with an asserted byte enable. If a parity error is detected, LSERR# is asserted in the Clock cycle following the data being checked. Parity is checked for PCI Target reads, PCI Initiator writes, and DMA Local Bus reads. The PCI 9054 sets a status bit and asserts an interrupt (LSERR#) in the clock cycle following data being checked if a parity error is detected. However, the Data Parity Error Status bit and interrupt are never set or asserted unless the READY# signal is active and asserted low. This applies only when the READY# signal is disabled in the PCI 9054 register. A workaround for this is to disable the READY# Enable bit and externally pull READY# low. Table 4-10. PCI Bus Little Endian Byte Lanes Byte Number 0 1 2 3 Byte Lane AD[7:0] AD[15:8] AD[23:16] AD[31:24] 4.3.2 Local Bus Big/Little Endian Mode The PCI 9054 Local Bus can be programmed to operate in Big or Little Endian mode. Table 4-11. Byte Number and Lane Cross-Reference Byte Number Mode Big Endian 3 C 2 1 0 3 J 2 1 0 Little Endian 0 1 2 3 0 1 2 3 Byte Lane LD[7:0] LD[15:8] LD[23:16] LD[31:24] LAD[7:0] LAD[15:8] LAD[23:16] LAD[31:24] Table 4-12. Big/Little Endian Program Mode BIGEND# Pin 0 0 1 1 0 1 0 1 Big Big Little Big Table 4-13 lists registers for information about the following cycles. Table 4-13. Cycles Reference Tables Cycles Register Bits BIGEND[0] BIGEND[1] BIGEND[2], Space 0, and BIGEND[3], Expansion ROM 4.3 4.3.1 BIG ENDIAN/LITTLE ENDIAN PCI Bus Little Endian Mode Local access to the Configuration registers PCI Initiator, Memory, and I/O PCI Target PCI Bus is a Little Endian bus (that is, the address is invariant and data is Lword-aligned to the lowermost byte lane). In Big Endian mode, the PCI 9054 transposes data byte lanes. Data is transferred as listed in Table 4-14 through Table 4-19. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 4-5 Section 4--C, J Bus Op BIGEND Register (1=Big, 0=Little) Endian Mode www..com Section 4 C and J Modes Bus Operation Big Endian/Little Endian 4.3.2.1 32-Bit Local Bus--Big Endian Mode 31 BYTE 3 Little Endian BYTE 2 BYTE 1 First Cycle 0 BYTE 0 Data is Lword aligned to uppermost byte lane (Data Invariance). Table 4-14. Upper Lword Lane Transfer Burst Order Byte Lane Byte 0 appears on Local Data [31:24] First transfer Byte 1 appears on Local Data [23:16] Byte 2 appears on Local Data [15:8] Byte 3 appears on Local Data [7:0] Second Cycle 15 BYTE 0 15 16 BYTE 0 15 Big Endian Figure 4-3. Big/Little Endian--16-Bit Local Bus 0 BYTE 1 0 Big Endian 31 BYTE 1 0 Little Endian 31 BYTE 3 BYTE 2 BYTE 1 BYTE 0 0 4.3.2.3 8-Bit Local Bus--Big Endian Mode For an 8-bit Local Bus, the PCI 9054 can be programmed to use upper or lower byte lanes. Table 4-17. Upper Byte Lane Transfer 31 BYTE 0 BYTE 1 BYTE 2 BYTE 3 0 Burst Order First transfer Second transfer Byte Lane Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [31:24] Byte 2 appears on Local Data [31:24] Byte 3 appears on Local Data [31:24] Big Endian Figure 4-2. Big/Little Endian--32-Bit Local Bus Third transfer Fourth transfer Table 4-18. Lower Byte Lane Transfer 4.3.2.2 16-Bit Local Bus--Big Endian Mode Burst Order First transfer Second transfer Third transfer Fourth transfer Byte Lane Byte 0 appears on Local Data [7:0] Byte 1 appears on Local Data [7:0] Byte 2 appears on Local Data [7:0] Byte 3 appears on Local Data [7:0] For a 16-bit Local Bus, the PCI 9054 can be programmed to use upper or lower word lanes. Table 4-15. Upper Word Lane Transfer Burst Order First transfer Byte Lane Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [23:16] Byte 2 appears on Local Data [31:24] Byte 3 appears on Local Data [23:16] 31 BYTE 3 Little Endian BYTE 2 BYTE 1 Second Cycle 0 BYTE 0 First Cycle Second transfer Fourth Cycle Third Cycle 7 BYTE 0 0 0 15 23 Table 4-16. Lower Word Lane Transfer Burst Order First transfer Byte Lane Byte 0 appears on Local Data [15:8] Byte 1 appears on Local Data [7:0] Byte 2 appears on Local Data [15:8] Byte 3 appears on Local Data [7:0] 16 7 BYTE 0 31 24 7 0 BYTE 0 Big Endian 7 0 8 7 BYTE 0 0 Second transfer Figure 4-4. Big/Little Endian--8-Bit Local Bus PCI 9054 Data Book v2.1 4-6 (c) PLX Technology, Inc. All rights reserved. www..com Serial EEPROM Section 4 C and J Modes Bus Operation 4.3.2.4 Local Bus Big/Little Endian Mode Accesses 4.4.1.2 Local Initialization For each of the following transfer types, the PCI 9054 Local Bus can be independently programmed to operate in Little Endian or Big Endian mode: * Local Bus accesses to the PCI 9054 Configuration registers * PCI Target PCI accesses to Local Address Space 0 * PCI Target PCI accesses to Local Address Space 1 * PCI Target PCI accesses to the Expansion ROM * DMA Channel 0 accesses to the Local Bus * DMA Channel 1 accesses to the Local Bus * PCI Initiator accesses to the PCI Bus For Local Bus accesses to the Internal Configuration registers and PCI Initiator accesses, use BIGEND# to dynamically change the Endian mode. Notes: The PCI Bus is always Little Endian. Only byte lanes are swapped, not individual bits. The PCI 9054 issues a Retry to all PCI accesses until the Local Init Status bit (LMISC[2]) is set. This bit can be programmed three different ways: 1. 2. By the Local processor, through the Local Configuration register. By the serial EEPROM, during a serial EEPROM load, if the Local processor does not set this bit or if this bit is missing. If the Local processor and/or the serial EEPROM are missing, the serial EEPROM remains blank and the PCI 9054 reverts to the default values and sets this bit (refer to Table 4-19. on page 4-8). 3. 4.4.2 Serial EEPROM Operation 4.4 SERIAL EEPROM Functional operation described can be modified through the PCI 9054 programmable internal registers. 4.4.1 Vendor and Device ID Registers * PCIIDR--Contains normal Device and Vendor IDs. Can be loaded from the serial EEPROM or Local processor(s). * PCISVID--Contains Subsystem and Subvendor IDs. Can be loaded from the serial EEPROM or Local processor(s). * PCIHIDR--Contains hardcoded PLX Vendor and Device IDs. The 3.3V serial EEPROM clock (EESK) is derived from the PCI clock. The PCI 9054 generates the serial EEPROM clock by internally dividing the PCI clock by 132. The serial EEPROM can be read or written from the PCI or Local Buses. The Serial EEPROM Control Register bits (CNTRL[28:24]) control the PCI 9054 pins that enable reading or writing of serial EEPROM data bits. (Refer to manufacturer's data sheet for the particular serial EEPROM being used.) The PCI 9054_AB revision, provides the ability to manually access the serial EEPROM. This may be accomplished by using bits 24 through 27 of the CNTRL register (EESK, EECS, and EEDI/EEDO controlled by software). Bit 24 is used to generate EESK (clock), bit 25 controls the chip select, and bit 26 sets/clears EEDO. Bit 27, when read, returns the value of EEDI. 4.4.1.1 Serial EEPROM Initialization During serial EEPROM initialization, the PCI 9054 responds to PCI Target accesses with a Retry. During serial EEPROM initialization, the PCI 9054 responds to a Local processor access by delaying acknowledgment of the cycle (READY#). PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 4-7 Section 4--C, J Bus Op Three Vendor and Device ID registers are supported: After reset, the PCI 9054 attempts to read the serial EEPROM to determine its presence. An active Start bit set to 0 indicates a serial EEPROM is present. The PCI 9054 supports 93CS56L (2K bits) or 93CS66L (4K bits). (Refer to manufacturer's data sheet for the particular serial EEPROM being used.) The first Lword is then checked to verify that the serial EEPROM is programmed. If the first Lword (33 bits) is all ones, a blank serial EEPROM is present. If the first Lword (33 bits) is all zeros, no serial EEPROM is present. For both conditions, the PCI 9054 reverts to the default values. (Refer to Table 4-19.) CNTRL[28] is set to 1 if programmed (real or random data if a serial EEPROM is detected). www..com Section 4 C and J Modes Bus Operation Serial EEPROM Setting bits 24, 25, and 26 to 1, causes the output to go high. A pull-up resistor is required on EEDO to go high when bit 26 is set. When reading the EEPROM, bit 26 must be set to a 1. To perform the read, the basic approach is to set the EECS and EEDO bits (bits 25 and 26) to the desired level and then toggle EESK high and low until done. For example, reading the serial EEPROM at location 0 involves the following steps: Table 4-19. Serial EEPROM Guidelines Local Processor None Serial EEPROM None System Boot Condition The PCI 9054 uses default values. The EEDI/EEDO pin must be pulled low--a 1 K-ohm resistor is required (rather than pulled high, which is typically done for this pin). If the PCI 9054 detects all zeros, it reverts to default values. None 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Clear EESK, EEDO and EECS bits. Toggle EESK high, then low. Set EECS high. Toggle EESK high, then low. Set EEDO bit high (start bit). Toggle EESK high, then low. Repeat step 6. Clear EEDO. Toggle EESK bit high, then low eight times (clock in Local Address 0). Set EEDO to float the EEDO pin for reading. Toggle EESK high, then low 16 times (clock in one word from serial EEPROM). After each clock pulse, read bit 27 and save. Clear EECS bit. Toggle EESK high, then low. Read is now complete. Present Present None Present Programmed Boot with serial EEPROM values. The Local Init Status bit (LMISC[2]) must be set by the serial EEPROM. Blank None The PCI 9054 detects a blank device and reverts to default values. The Local processor programs the PCI 9054 registers, then sets the Local Init Status bit (LMISC[2]=done). Note: Some systems may hang if PCI Target reads and writes take too long (during initialization, the PCI Host also performs PCI Target accesses). The value of the PCI Target Retry Delay Clocks (LBRD0[31:28]) may resolve this. Programmed Load serial EEPROM, but the Local processor can reprogram the PCI 9054. Either the Local processor or the serial EEPROM must set the Local Init Status bit (LMISC[2]=done). Blank The PCI 9054 detects a blank serial EEPROM and reverts to default values. Notes: In some systems, the Local processor may be too late to reconfigure the PCI 9054 registers before the BIOS configures them. The serial EEPROM can be programmed through the PCI 9054 after the system boots in this condition. The serial EEPROM can also be read or written, using the VPD function (refer to Section 10). The PCI 9054 has two serial EEPROM load options: * Long Load Mode--Default. The PCI 9054 loads 17 Lwords from the Serial EEPROM and the Extra Long Load bit (LBRD0[25]) * Extra Long Load Mode--The PCI 9054 loads 22 Lwords if the Serial EEPROM and the Extra Long Load bit (LBRD0[25]) is set to 1 during a Long Load 4.4.2.1 Long Serial EEPROM Load The registers listed in Table 4-20 are loaded from the serial EEPROM after a reset is de-asserted if the Serial EEPROM Extra Long Load bit is not set (LBRD0[25]=0). The serial EEPROM is organized in words (16 bit). The PCI 9054 first loads the Most Significant Word bits (MSW[31:16]), starting from the most significant bit [31]). The PCI 9054 then loads the Least Significant Word bits (LSW[15:0]), starting again from the most significant bit [15]. Therefore, the PCI 9054 loads the Device ID, Vendor ID, class code, and so forth. PCI 9054 Data Book v2.1 4-8 (c) PLX Technology, Inc. All rights reserved. www..com Serial EEPROM Section 4 C and J Modes Bus Operation The serial EEPROM values can be programmed using a Data I/O programmer. The values can also be programmed using the PCI 9054 VPD function (refer to Section 10) or through the Serial EEPROM Control register (CNTRL). The CNTRL register allows programming of the serial EEPROM, one bit at a time. To read back the value from the serial EEPROM, the CNTRL[27] bit (refer to Table 4-20. Long Serial EEPROM Load Registers Serial EEPROM Offset 0h 2h 4h 6h 8h Ah Ch Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h Device ID Vendor ID Class Code Class Code / Revision Maximum Latency / Minimum Grant Interrupt Pin / Interrupt Line Routing MSW of Mailbox 0 (User Defined) LSW of Mailbox 0 (User Defined) MSW of Mailbox 1 (User Defined) LSW of Mailbox 1 (User Defined) MSW of Range for PCI-to-Local Address Space 0 LSW of Range for PCI-to-Local Address Space 0 Section 4.4.2) or the VPD function should be utilized. With full utilization of VPD, the designer can perform reads and writes from/to the serial EEPROM, 32 bits at a time. Values should be programmed in the order listed in Table 4-20. The 34, 16-bit words listed in the table are stored sequentially in the serial EEPROM. Description Register Bits Affected PCIIDR[31:16] PCIIDR[15:0] PCICCR[23:8] PCICCR[7:0] / PCIREV[7:0] PCIMLR[7:0] / PCIMGR[7:0] PCIIPR[7:0] / PCIILR[7:0] MBOX0[31:16] MBOX0[15:0] MBOX1[31:16] MBOX1[15:0] LAS0RR[31:16] LAS0RR[15:0] LAS0BA[31:16] LAS0BA[15:0] MARBR[31:16] MARBR[15:0] PROT_AREA[15:0] LMISC[7:0] / BIGEND[7:0] EROMRR[31:16] EROMRR[15:0] EROMBA[31:16] EROMBA[15:0] LBRD0[31:16] LBRD0[15:0] DMRR[31:16] DMRR[15:0] DMLBAM[31:16] DMLBAM[15:0] DMLBAI[31:16] DMLBAI[15:0] DMPBAM[31:16] DMPBAM[15:0] DMCFGA[31:16] DMCFGA[15:0] MSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 MSW of Mode/DMA Arbitration Register LSW of Mode/DMA Arbitration Register MSW of Serial EEPROM Write-Protected Address LSW of Local Miscellaneous Control Register / LSW of Local Bus Big/Little Endian Descriptor Register MSW of Range for PCI-to-Local Expansion ROM LSW of Range for PCI-to-Local Expansion ROM MSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM LSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM MSW of Bus Region Descriptors for PCI-to-Local Accesses LSW of Bus Region Descriptors for PCI-to-Local Accesses MSW of Range for PCI Initiator-to-PCI LSW of Range for PCI Initiator-to-PCI MSW of Local Base Address for PCI Initiator-to-PCI Memory LSW of Local Base Address for PCI Initiator-to-PCI Memory MSW of Local Bus Address for PCI Initiator-to-PCI I/O Configuration LSW of Local Bus Address for PCI Initiator-to-PCI I/O Configuration MSW of PCI Base Address (Remap) for PCI Initiator-to-PCI LSW of PCI Base Address (Remap) for PCI Initiator-to-PCI MSW of PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration LSW of PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 4-9 Section 4--C, J Bus Op www..com Section 4 C and J Modes Bus Operation Serial EEPROM 4.4.2.2 Extra Long Serial EEPROM Load significant bit [15]. Therefore, the PCI 9054 loads Device ID, Vendor ID, class code, and so forth. The serial EEPROM values can be programmed using a Data I/O programmer. The values can also be programmed using the PCI 9054 VPD function or through the Serial EEPROM Control register (CNTRL). Values should be programmed in the order listed in Table 4-21. The 44 16-bit words listed in Table 4-20 and Table 4-21 should be stored sequentially in the serial EEPROM. The registers listed in the Local Address Space 0/ Expansion ROM Bus Region Descriptor register (LBRD0) are loaded from serial EEPROM after a reset is de-asserted if the Serial EEPROM Extra Long Load bit is set (LBRD0[25]=1). The serial EEPROM is organized in words (16 bit). The PCI 9054 first loads the Most Significant Word bits [31:16], starting from the most significant bit [31]. It then loads the Least Significant Word bits [15:0], restarting from the most Table 4-21. Extra Long Serial EEPROM Load Registers Serial EEPROM Offset 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h Subsystem ID Subsystem Vendor ID Description Register Bits Affected PCISID[15:0] PCISVID[15:0] LAS1RR[31:16] LAS1RR[15:0] LAS1BA[31:16] LAS1BA[15:0] LBRD1[31:16] LBRD1[15:0] Reserved HS_NEXT[7:0] / HS_CNTL[7:0] MSW of Range for PCI-to-Local Address Space 1 (1 MB) LSW of Range for PCI-to-Local Address Space 1 (1 MB) MSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 MSW of Bus Region Descriptors (Space 1) for PCI-to-Local Accesses LSW of Bus Region Descriptors (Space 1) for PCI-to-Local Accesses MSW of Hot Swap Control LSW of Hot Swap Control / Hot Swap Next Capability Pointer PCI 9054 Data Book v2.1 4-10 (c) PLX Technology, Inc. All rights reserved. www..com Serial EEPROM Section 4 C and J Modes Bus Operation 4.4.2.3 New Capabilities Function Support 4.4.2.5 Serial EEPROM Initialization The New Capabilities Function Support includes PCI Power Management, Hot Swap, and VPD features, as listed in Table 4-22. Table 4-22. New Capabilities Function Support Features New Capability Function PCI Register Offset Location 40'h, if the New Capabilities Function Support bit (PCISR[4]) is enabled (PCISR[4] is enabled, by default). 48'h, which is pointed to from PMNEXT[7:0]. 4C'h, which is pointed to from HS_NEXT[7:0]. Because PVPD_NEXT[7:0] defaults to zero, this indicates that VPD is the last New Capability Function Support feature of the PCI 9054. During serial EEPROM initialization, the PCI 9054 responds to PCI Target accesses with a Retry. During serial EEPROM initialization, the PCI 9054 responds to a Local processor access by delaying acknowledgment of the cycle (READY#). 4.4.3 Internal Register Access First (Power Management) Second (Hot Swap) The PCI 9054 provides several internal registers, which allow for maximum flexibility in the bus-interface design and performance. These registers are accessible from the PCI and Local Buses and include the following: * PCI and Local Configuration registers * DMA registers * Mailbox registers * PCI-to-Local and Local-to-PCI Doorbell registers * Messaging Queue registers (I2O) * Power Management registers * Hot Swap registers * VPD registers Figure 4-6 illustrates how these registers are accessed. Local Bus Master Third (VPD) 4.4.2.4 Recommended Serial EEPROMs The PCI 9054 is designed to use either a 2K bit (NM93CS56L or compatible) or 4K bit (NM93CS66L or compatible) device. Note: The PCI 9054 does not support serial EEPROMs that do not support sequential reads and writes (such as the NM93C56L). PCI Bus Master PCI 9054 PCI Configuration Registers 4096 100h Local Configuration Registers 2048 80h DMA Registers Mailbox Registers VPD Set Clear PCI-to-Local Doorbell Register Local-to-PCI Doorbell Register Messaging Queue Registers Power Management Registers Hot Swap Registers VPD Registers Empty 704 2Ch Set Extra Long 544 22h Long Load 0 0 # of bits # of words Figure 4-5. Serial EEPROM Memory Map Figure 4-6. PCI 9054 Internal Register Access PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. Local Interrupt 1536 PCI Interrupt 60h (PROT_AREA register default) Clear 4-11 Section 4--C, J Bus Op www..com Section 4 C and J Modes Bus Operation Serial EEPROM 4.4.3.1 PCI Bus Access to Internal Registers 4.4.3.2 Local Bus Access to Internal Registers The PCI 9054 PCI Configuration registers can be accessed from the PCI Bus with a Configuration Type 0 cycle. All other PCI 9054 internal registers can be accessed by a Memory cycle, with the PCI Bus address that matches the base address specified in PCI Base Address 0 (PCIBAR0[31:8]) for the PCI 9054 MemoryMapped Configuration register. These registers can also be accessed by an I/O cycle, with the PCI Bus address matching the base address specified in PCI Base Address 1 for the PCI 9054 I/O-Mapped Configuration register. All PCI Read or Write accesses to the PCI 9054 registers can be Byte, Word, or Lword accesses. All PCI Memory accesses to the PCI 9054 registers can be Burst or Non-Burst accesses. The PCI 9054 responds with a PCI disconnect for all Burst I/O accesses (PCIBAR1[31:8]) to the PCI 9054 Internal registers. The Local processor can access all PCI 9054 internal registers through an external chip select. The PCI 9054 responds to a Local Bus access when the PCI 9054 Configuration Chip Select input (CCS#) is asserted low. Figure 4-7 illustrates how the Configuration Chip Select logic works. Notes: CCS# must be decoded while ADS# is low. Accesses must be for a 32-bit non-pipelined bus. Local Read or Write accesses to the PCI 9054 internal registers can be Byte, Word, or Lword accesses. Local accesses to the PCI 9054 internal registers can be Burst or Non-Burst accesses. The PCI 9054 READY# signal indicates that Data transfer is complete. Address Mode Pin PCI 9054 CCS# (PCI 9054 Chip Select) PCI 9054 Internal Register Chip Select Figure 4-7. Address Decode Mode PCI 9054 Data Book v2.1 4-12 (c) PLX Technology, Inc. All rights reserved. www..com Serial EEPROM Section 4 C and J Modes Bus Operation 4.4.4 Serial EEPROM Timing Diagrams 0us 5us 10us 15us 20us 25us 30us EESK LRESETo# EECS EEDI EEDO 0 1 1 0 0 0 0 0 0 0 0 0 INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----| 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] CONFIGURATION REGISTER 0 HEX EESK EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 BITS [15:0] CONFIGURATION REGISTER 0 HEX BITS [31:16] OF CONFIGURATION REGISTER 8 HEX CONTINUES EESK(continues) EECS LAST WORD CONTINUES EESK, EEDO, EECS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ Timing Diagram 4-1. Initialization from Serial EEPROM (2K Bit) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 4-13 Section 4--C, J Bus Op EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 www..com Section 4 C and J Modes Bus Operation Serial EEPROM 0us 5us 10us 15us 20us 25us 30us EESK LRESETo# EECS EEDI EEDO 0 1 1 0 0 0 0 0 0 0 0 0 INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----| 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] CONFIGURATION REGISTER 0 HEX EESK EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 BITS [15:0] CONFIGURATION REGISTER 0 HEX BITS [31:16] OF CONFIGURATION REGISTER 8 HEX CONTINUES EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LAST WORD CONTINUES EESK, EEDO, EECS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ Timing Diagram 4-2. Initialization from Serial EEPROM (4K Bit) 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=B Data BE Timing Diagram 4-3. PCI Configuration Write to PCI Configuration Register PCI 9054 Data Book v2.1 4-14 (c) PLX Technology, Inc. All rights reserved. www..com Serial EEPROM Section 4 C and J Modes Bus Operation 0ns 50ns 100ns 150ns 200ns 250ns 300n CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=A Data Read BE Timing Diagram 4-4. PCI Configuration Read to PCI Configuration Register 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=7 Data BE Timing Diagram 4-5. PCI Memory Write to Local Configuration Register PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 4-15 Section 4--C, J Bus Op www..com Section 4 C and J Modes Bus Operation Serial EEPROM 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=6 BE Data Read Timing Diagram 4-6. PCI Memory Read to Local Configuration Register 0ns 100ns 200ns 300ns 400ns 500n CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR DATA CMD BE INTA# RESPONSE ON THE PCI BUS LCLK LINT# Timing Diagram 4-7. Local Interrupt Asserting PCI Interrupt PCI 9054 Data Book v2.1 4-16 (c) PLX Technology, Inc. All rights reserved. www..com 5 C AND J MODES FUNCTIONAL DESCRIPTION 5.3 RESPONSE TO FIFO FULL OR EMPTY The functional operation described can be modified through the PCI 9054 programmable internal registers. 5.1 5.1.1 RESET OPERATION PCI Bus Input RST# Table 5-1 lists the response of the PCI 9054 to full and empty FIFOs. 5.4 DIRECT DATA TRANSFER MODES PCI Bus RST# input pin is a PCI Host reset. It causes all PCI Bus outputs to float, resets the entire PCI 9054 and causes the Local reset LRESETo# signal to be asserted. The PCI 9054 supports three direct transfer modes: * PCI InitiatorLocal CPU accesses PCI memory or I/O * PCI TargetPCI Master accesses Local memory or I/O * DMAPCI 9054 DMA controller reads/writes PCI memory to/from Local memory 5.1.2 Software Reset A Host on the PCI Bus can set the PCI Adapter Software Reset bit (CNTRL[30]=1) to reset the PCI 9054 and assert LRESETo# output. All Local Configuration registers are reset; however, the PCI Configuration DMA and Shared Runtime registers and the Local Init Status bit (LMISC[2]) are not reset. When the Software Reset bit (CNTRL[30]) is set, the PCI 9054 responds to PCI accesses, but not to Local Bus accesses. The PCI 9054 remains in this reset condition until the PCI Host clears the bit. The serial EEPROM is reloaded if the Reload Configuration Registers bit is set (CNTRL[29]=1). Note: The Local Bus cannot clear this reset bit because the Local Bus is in a reset state, even if the Local processor does not use LRESETo# to reset. 5.4.1 PCI Initiator Operation (Local Master-to-PCI Target) The PCI 9054 supports a direct access of the PCI Bus by the Local processor or an intelligent controller. Master mode must be enabled in the PCI Command register. The following registers define Local-to-PCI accesses: * PCI Initiator Memory and I/O Range (DMRR) * Local Base Address for PCI Initiator to PCI Memory (DMLBAM) * Local Base Address for PCI Initiator to PCI I/O and Configuration (DMLBAI) * PCI Base Address (DMPBAM) * PCI Initiator Configuration (DMCFGA) * PCI Initiator PCI Dual Address Cycles (DMDAC) * Master Enable (PCICR) * PCI Command Code (CNTRL) 5.2 PCI 9054 INITIALIZATION The PCI 9054 Configuration registers can be programmed by an optional serial EEPROM and/or by a Local processor, as listed in Table 4-19. The serial EEPROM can be reloaded by setting the Reload Configuration Registers bit (CNTRL[29]). The PCI 9054 retries all PCI cycles until the Local Init Status bit is set to "done" (LMISC[2]=1). Note: The PCI Host processor can also access Internal Configuration registers after the Local Init Status bit is set. If a PCI Host is present, the Master Enable, Memory Space, and I/O Space bits (PCICR[2:0]) are programmed by that Host after initialization completes (LMISC[2]=1). PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-1 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description Direct Data Transfer Modes Table 5-1. Response to FIFO Full or Empty Mode PCI Initiator Write Direction Local-to-PCI FIFO Full Empty Full Empty Full Empty Full Empty Full Empty Full Empty Normal PCI Bus De-assert REQ# (off PCI Bus) De-assert REQ# or throttle IRDY#1 Normal Disconnect or throttle TRDY#2 Normal Normal Throttle TRDY# Normal De-assert REQ# De-assert REQ# Normal 2 Local Bus De-assert READY# Normal Normal De-assert READY# Normal De-assert LHOLD, assert BLAST#3 De-assert LHOLD, assert BLAST#3 Normal De-assert LHOLD, assert BLAST#3 Normal Normal De-assert LHOLD, assert BLAST#3 PCI Initiator Read PCI-to-Local PCI Target Write PCI-to-Local PCI Target Read Local-to-PCI Local-to-PCI DMA PCI-to-Local 1. Throttle IRDY# depends on the PCI Initiator PCI Read Mode bit (DMPBAM[4]). 2. Throttle TRDY# depends on the PCI Target Write Mode bit (LBRD0[27]). 3. LHOLD de-assert depends upon the Local Bus PCI Target Release Bus Mode bit (MARBR[21]). PCI 9054 Data Book v2.1 5-2 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 5 C and J Modes Functional Description PCI Bus Master Local Processor 1 Initialize Local PCI Initiator Access Registers Local Range for PCI Initiator-to-PCI Local Base Address for PCI Initiator-to-PCI Memory PCl Base Address (Remap) for PCI Initiator-to-PCI Local Base Address for PCI Initiator-to-PCI I/O Configuration I/O or Configuration 0 = I/O 1 = Configuration PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration PCI Command Register 3 PCI Bus Access 2 FIFOs 32-Lword Deep Write 16-lword Deep Read Local Base Address for PCI Initiatorto-PCI Memory Space Local Bus Access Local Memory PCI Address Space PCI Base Address Memory Command Range Local Base Address for PCI Initiator-toPCI I/O Configuration I/O Command Range Figure 5-1. PCI Initiator Access of the PCI Bus PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-3 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description Direct Data Transfer Modes 5.4.1.1 PCI Initiator Memory and I/O Decode Slave Master Slave LA, ADS#, LBE#, LD/LAD, LW/R#, BLAST# Master The Range register and the Local Base Address specifies the Local Address bits to use for decoding a Local-to-PCI access (PCI Initiator). The range of memory or I/O space must be a power of 2 and the Range register value must be the inverse of the Range value. In addition, the Local Base Address must be a multiple of the range value. Any Local Master Address starting from the PCI Initiator Local Base Address (Memory or I/O) to the range value is recognized as a PCI Initiator access by the PCI 9054. All PCI Initiator cycles are then decoded as PCI Memory, I/O, or Configuration Type 0 or 1. Moreover, a PCI Initiator memory or I/O cycle is remapped according to the Remap register value. The Remap Register value must be a multiple of the PCI Initiator Range value (not the Range register value). The PCI 9054 can only accept Memory cycles from the Local processor. The Local Base Address and/or the range determine whether PCI Memory or PCI I/O transactions occur. REQ# READY# PCI Bus GNT# FRAME#, C/BE# AD (addr) IRDY# DEVSEL#, TRDY# AD (data) PCI 9054 Figure 5-2. PCI Initiator Write Slave Master Slave LA, ADS#, LW/R# Master REQ# GNT# IRDY# DEVSEL#, TRDY#, AD (data) PCI 9054 LD/LAD, READY# BLAST# 5.4.1.2 PCI Initiator FIFOs For PCI Initiator Memory access to the PCI Bus, the PCI 9054 has a 32-Lword (128-byte) Write FIFO and a 16-Lword (64-byte) Read FIFO. The FIFOs enable the Local Bus to operate independent of the PCI Bus and allows high-performance bursting on the PCI and Local Buses. In a PCI Initiator write, the Local processor (Master) writes data to the PCI Bus (Slave). In a PCI Initiator read, the Local processor (Master) reads data from the PCI Bus (Slave). The FIFOs that function during a PCI Initiator write and read are illustrated in Figure 5-2 and Figure 5-3. Figure 5-3. PCI Initiator Read Note: The figures represent a sequence of Bus cycles. 5.4.1.3 PCI Initiator Memory Access The Local processor can read or write to the PCI memory. The PCI 9054 converts the Local Read/Write access. The Local Address space starts from the PCI Initiator Local Base Address up to the range. Remap (PCI Base Address) defines the PCI starting address. Writes--PCI 9054 continues to accept writes and returns READY# until the Write FIFO is full. It then holds off READY# until space becomes available in the Write FIFO. A programmable PCI Initiator FIFO "almost full" status output is provided (DMPAF). PCI 9054 Data Book v2.1 5-4 (c) PLX Technology, Inc. All rights reserved. Local Bus PCI Bus FRAME#, C/BE#, AD (addr) Local Bus www..com Direct Data Transfer Modes Section 5 C and J Modes Functional Description Reads--PCI 9054 holds off READY# while gathering an Lword from the PCI Bus. Programmable prefetch modes are available if prefetch is enabled: prefetch, 4, 8, 16, or continuous until the PCI Initiator cycle ends. The Read cycle is terminated when the Local BLAST# input is asserted. Unused Read data is flushed from the FIFO. The PCI 9054 does not prefetch Read data for SingleCycle PCI Initiator reads (Local BLAST# input asserted during the first Data phase). In this case, the PCI 9054 reads a single PCI Lword unless PCI Initiator Read Ahead mode is enabled. For PCI Initiator Single-Cycle reads, the PCI 9054 sets the same PCI Bus byte enables as set on the Local Bus. For Burst-Cycle reads, the PCI 9054 reads entire Lwords (all PCI Bus byte enables are asserted). If the PCI Initiator Prefetch Limit bit is enabled (DMPBAM[11]=1), the PCI 9054 does not prefetch past a 4 KB boundary. Also, the Local Bus must not cross a 4 KB boundary during a Burst read. The PCI 9054 never prefetches beyond the region specified for PCI Initiator accesses. 5.4.1.5 PCI Initiator I/O If the Configuration Enable bit is cleared (DMCFGA[31]=0), a Single I/O access is made to the PCI Bus. The Local Address, Remapped Decode Address bits, and Local byte enables are encoded to provide the address and are output with an I/O Read or Write command during a PCI Address cycle. When the I/O Remap Select bit is set (DMPBAM[13]=1), the PCI Address bits [31:16] are forced to 0 for the 64 KB I/O address limit. For writes, data is loaded into the Write FIFO and READY# is returned to the Local Bus. For reads, the PCI 9054 holds off READY# while receiving an Lword from the PCI Bus. 5.4.1.6 PCI Initiator Configuration (PCI Configuration Type 0 or Type 1 Cycles) 5.4.1.4 PCI Initiator I/O Configuration Access When a Local PCI Initiator I/O access to the PCI Bus occurs, the PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration Enable bit (DMCFGA[31]) determines whether an I/O or Configuration access is to be made to the PCI Bus. Local Burst accesses are broken into single PCI I/O (address/data) cycles. The PCI 9054 does not prefetch Read data for I/O and configuration reads. For PCI Initiator I/O or Configuration cycles, the PCI 9054 asserts the same PCI Bus byte enables as set on the Local Bus. If the Configuration Enable bit (DMCFGA[31]) is set, a Configuration access is made to the PCI Bus. In addition to enabling configuration of this bit, the user must provide all register information. The Register Number and Device Number bits (DMCFGA[7:2] and DMCFGA[15:11], respectively) must be modified and a new Configuration Read/Write cycle must be performed before accessing other registers or devices. If the PCI Configuration Address register selects a Type 0 command, bits [10:0] of the register are copied to address bits [10:0]. Bits [15:11] (device number) are translated into a single bit being set in the PCI Address bits [31:11]. The PCI Address bits [31:11] can be used as a device select. For a Type 1 command, bits [23:0] are copied from the register to bits [23:0] of the PCI address. The PCI Address bits [31:24] are set to 0. A Configuration Read or Write command code is output with the address during the PCI Address cycle (refer to the DMCFGA register). For writes, Local data is loaded into the Write FIFO and READY# is returned. For reads, the PCI 9054 holds off READY# while gathering an Lword from the PCI Bus. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-5 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description Direct Data Transfer Modes 5.4.1.6.1 PCI Initiator Configuration Cycle Example To perform a Type 0 Configuration cycle to PCI device on AD[21]: 1. The PCI 9054 must be configured to allow PCI Initiator access to the PCI Bus. The PCI 9054 must also be set to respond to I/O space accesses. These bits must be set (PCICR[2:0]=111b). In addition, PCI Initiator memory and I/O access must be enabled (DMPBAM[1:0]=11). 2. The Local memory map selects the PCI Initiator range. For this example, use a range of 1 MB: 1 MB = 220 = 000FFFFFh The value to program into the Range register is the inverse of 000FFFFFh (FFF00000h): DMRR = FFF00000h 3. The Local memory map determines the Local Base Address for the PCI Initiator-to-PCI I/O Configuration register. For this example, use 40000000h: DMLBAI = 40000000h 4. The PCI Address (Remap) for PCI Initiator-to-PCI Memory register must enable the PCI Initiator I/O access. The PCI Initiator I/O Access Enable bit must be set (DMPBAM[1]=1). The user must know which PCI device and PCI Configuration register the PCI Configuration cycle is accessing. This example assumes the IDSEL signal of the Target PCI device is connected to AD[21] (logical device #10=0Ah). Also access PCIBAR0 (the fourth register, counting from 0; use Table 11-2 for reference). Set DMCFGA[31, 23:0] as follows: Bit 1:0 7:2 10:8 15:11 23:16 31 or Write cycle. Offset to the base address is not necessary because the register offset for the read or write is specified in the Configuration register. The PCI 9054 takes the Local Bus Master Memory cycle and checks for the Configuration Enable bit (DMCFGA[31]). If set, the PCI 9054 converts the current cycle to a PCI Configuration cycle, using the DMCFGA register and the Write/Read signal (LW/R#). The Register Number and Device Number bits (DMCFGA[7:2] and DMCFGA[15:11], respectively) must be modified and a new Configuration Read/ Write cycle must be performed before accessing other registers or devices. 5.4.1.7 PCI Initiator PCI Dual Address Cycle 5. The PCI 9054 supports PCI Dual Address Cycle (DAC) when it is a PCI Bus Master using the DMDAC register for PCI Initiator transactions. The DAC command is used to transfer a 64-bit address to devices that support 64-bit addressing when the address is not in the low 4-GB Address space. The PCI 9054 performs the address portion of a DAC in two PCI clock periods, where the first PCI address is a Lo-Addr with the command (C/BE[3:0]#) "D" and the second PCI address will be a Hi-Addr with the command (C/BE[3:0]#) "6" or "7", depending upon it being a PCI Read or a PCI Write cycle. Whenever the DMDAC register contains a value of 0x00000000, the PCI 9054 performs a Single Address Cycle (SAC) on the PCI Bus. (Refer to Figure 5-4.) 5.4.1.8 PCI Initiator/Target Abort Description Configuration Type 0. Register Number. Fourth register. Must program a "4" into this value, beginning with bit 2. Function Number. Device Number n-11, where n is the value in AD[n]=21-11 = 10. Bus Number. Configuration Enable. Value 00b 000100b 000b 01010b 00000000b 1 The PCI 9054 PCI Initiator/Target Abort logic enables a Local Bus Master to perform a PCI Initiator Bus poll of devices to determine whether devices exist (typically when the Local Bus performs Configuration cycles to the PCI Bus). When a PCI Master device attempts to access and does not receive DEVSEL# within six PCI clocks, it results in a Master Abort. The Local Bus Master must clear the Received Master Abort bit or Target Abort bit (PCISR[13 or 11]=0, respectively) and continue by processing the next task. After these registers are configured, a simple Local Master Memory cycle to the I/O base address is necessary to generate a PCI Configuration Read PCI 9054 Data Book v2.1 5-6 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 5 C and J Modes Functional Description Set DMA Mode to Block Mode Register PCI Host Memory Memory Block to Transfer Set up Transfer Parameters Single Address-- PCI Address Register Dual Address--PCI Addresses Register Local Address Register Transfer Size (byte count) Register Descriptor Pointer Register (set direction only) Local Memory Memory Block to Transfer Command/Status Register Set Enable and Go Bits in DMA Command/Status Registers (DMACSR0 and DMACSR1) to Initiate DMA Transfer Figure 5-4. Block DMA Mode Initialization (Single Address or Dual Address PCI) Figure 5-5. Dual Address Timing PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-7 Section 5--C, J Func Desc If a PCI Master/Target Abort, or Retry Time-Out is encountered during a transfer, the PCI 9054 asserts LSERR# if enabled [(INTCSR[1:0]=1), which can be used as an NMI]. If a Local Bus Master is waiting for READY#, it is asserted along with BTERM#. The Local Master's interrupt handler can take the appropriate application-specific action It can then clear the Target Abort bit (PCISR[11]) to de-assert the LSERR# interrupt and re-enable PCI Initiator transfers. If a Local Bus Master is attempting a Burst read from a nonresponding PCI device (Master/Target Abort), it receives READY# and BTERM# for the first cycle only. In addition, the PCI 9054 asserts LSERR# if the Enable Local Bus LSERR# bits are enabled (INTCSR[1:0], which can be used as an NMI). If the Local processor cannot terminate its Burst cycle, it may cause the Local processor to hang. The Local Bus must then be reset from the PCI Bus. If a Local Bus Master cannot terminate its cycle with BTERM# output, it should not perform Burst cycles when attempting to determine whether a PCI device exists. www..com Section 5 C and J Modes Functional Description Direct Data Transfer Modes 5.4.1.9 PCI Initiator Memory Write and Invalidate space. In addition, Local mapping registers allow address translation from the PCI Address Space to the Local Address Space. Three spaces are available: * Space 0 * Space 1 * Expansion ROM space Expansion ROM space is intended to support a bootable ROM device for the Host. For Single-Cycle PCI Target reads, the PCI 9054 reads a single Local Bus Lword or partial Lword. The PCI 9054 disconnects after one transfer for all PCI Target I/O accesses. For the highest data-transfer rate, the PCI 9054 supports posted writes and can be programmed to prefetch data during a PCI Burst Read. The Prefetch size, when enabled, can be from one to 16 Lwords or until the PCI Bus stops requesting. When the PCI 9054 prefetches, if enabled, it drops the Local Bus after reaching the prefetch counter. In Continuous Prefetch mode, the PCI 9054 prefetches as long as FIFO space is available and stops prefetching when the PCI Bus terminates the request. If Read prefetching is disabled, the PCI 9054 disconnects after one Read transfer. In addition to Prefetch mode, the PCI 9054 supports Read Ahead mode (refer to Section 5.4.2.3). Each Local space can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width. The PCI 9054 has an internal wait state generator and external wait state input, READY#. READY# can be disabled or enabled with the Internal Configuration registers. With or without wait state(s), the Local Bus, independent of the PCI Bus, can: * Burst as long as data is available (Continuous Burst mode) * Burst four Lwords at a time (recommended) * Perform a continuous Single cycle The PCI 9054 can be programmed to perform Memory Write and Invalidate cycles to the PCI Bus for PCI Initiator transfers, as well as DMA transfers (refer to Section 5.5.4). The PCI 9054 supports Memory Write and Invalidate transfers for cache line sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or 16 is specified, the PCI 9054 performs Write transfers rather than Memory Write and Invalidate transfers. PCI Initiator Memory Write and Invalidate transfers are enabled when the Invalidate Enable and the Memory Write and Invalidate Enable bits are set (DMPBAM[9] and PCICR[4], respectively). In Memory Write and Invalidate mode, if the start address of the PCI Initiator transfer is on a cache line boundary, the PCI 9054 waits until the number of Lwords required for the specified cache line size are written from the Local Bus before starting a PCI Memory Write and Invalidate access. This ensures a complete cache line write can complete in one PCI Bus ownership. If the start address is not on a cache line boundary, the PCI 9054 starts a normal PCI Write access (PCI command code = 7h). The PCI 9054 terminates a cycle at a cache line boundary if it is performing a normal write or if it is performing a Memory Write and Invalidate cycle and another cache line of data is not available. If an entire cache line is available by the time PCI 9054 regains use of the PCI Bus, the PCI 9054 resumes Memory Write and Invalidate cycles. Otherwise, it continues with a normal write. If a Target disconnects before a cache line is completed, the PCI 9054 completes the remainder of that cache line, using normal writes. 5.4.2 PCI Target Operation (PCI Master-to-Local Bus Access) The PCI 9054 supports both Burst Memory-Mapped Transfer accesses and I/O-Mapped, Single-Transfer accesses to the Local Bus from the PCI Bus through a 16-Lword (64-byte) PCI Target Read FIFO and a 32-Lword (128-byte) PCI Target Write FIFO. The PCI Base Address registers are provided to set up the location of the adapter in the PCI memory and the I/O PCI 9054 Data Book v2.1 5-8 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 5 C and J Modes Functional Description 5.4.2.1 PCI Target Lock The PCI 9054 supports direct PCI-to-Local-Bus Exclusive accesses (locked atomic operations). A PCIlocked operation to the Local Bus results in the entire address Space 0, Space 1, and Expansion ROM space being locked until they are released by the PCI Bus Master. Locked operations are enabled or disabled with the PCI Target LOCK# Enable bit (MARBR[22]) for PCI-to-Local accesses. address and 32-bit aligned (next address = current address + 4). Read Ahead mode functions with or without PCI Delayed Read mode. PCI Bus PCI Read request PCI 9054 Read Ahead mode is set in Internal Registers Local Bus PCI 9054 prefetches data from Local Bus device Read data 5.4.2.2 PCI Target PCI v2.1 Delayed Read Mode PCI Bus Master Read returns with "Sequential Address" Prefetched data is stored in the internal FIFO PCI 9054 returns prefetched data immediately from internal FIFO without reading again from the Local Bus The PCI 9054 can be programmed through the PCI Specification v2.1 Mode bit (MARBR[24]=1) to perform delayed reads, as specified in PCI Specification v2.1. PCI 9054 prefetches more data if FIFO space is available Read data PCI 9054 prefetches more data from Local memory PCI Bus PCI 9054 Local Bus Figure 5-7. PCI Target PCI 9054 Read Ahead Mode Note: The figure represents a sequence of Bus cycles. PCI Read request PCI 9054 instructs PCI Host to "Retry" Read cycle later PCI Bus is free to perform other cycles during this time PCI Host returns to fetch Read data again Read data is now ready for Host Spec v2.1 mode is set in Internal Registers PCI 9054 requests Read data from Local Bus Local memory returns requested data to PCI 9054 5.4.2.4 PCI Target Transfer Data is stored in 16-Lword Internal FIFO PCI 9054 returns prefetched data immediately A PCI Bus Master addressing the Memory space decoded for the Local Bus initiates transactions. Upon a PCI Read/Write, the PCI 9054 becomes a Local Bus Master and arbitrates for the Local Bus. The PCI 9054 then reads data into the PCI Target Read FIFO or writes data to the Local Bus. The PCI Target or PCI Initiator preempts DMA; however, the PCI Target does not preempt the PCI Initiator (refer to Section 5.4.3.1). The PCI 9054 can be programmed to "keep" the PCI Bus by generating a wait state(s) and de-asserting TRDY# if the Write FIFO becomes full. The PCI 9054 can also be programmed to "keep" the Local Bus and continue asserting LHOLD if the PCI Target Write FIFO becomes empty or the PCI Target Read FIFO becomes full. In either case, the Local Bus is dropped when the Local Bus Latency Timer is enabled and expires (MARBR[7:0]). For PCI Target writes, the PCI Bus writes data to the Local Bus. The PCI Target is the "Command from the PCI Host," which has highest priority. For PCI Target reads, the PCI Bus Master reads data from the Local Bus Slave. Figure 5-6. PCI Target PCI v2.1 Delayed Reads Note: The figure represents a sequence of Bus cycles. In addition to delayed reads, the PCI 9054 supports the following PCI Specification v2.1 functions: * No write while a read is pending (PCI Retry for writes) * Write and flush pending read 5.4.2.3 PCI Target PCI Read Ahead Mode The PCI 9054 also supports Read Ahead mode, where prefetched data can be read from the internal FIFO of the PCI 9054 instead of from the Local Bus. The address must be subsequent to the previous PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-9 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description Direct Data Transfer Modes The PCI 9054 supports on-the-fly Endian conversion for Space 0, Space 1, and Expansion ROM space. The Local Bus can be Big/Little Endian by using the programmable internal register configuration. Note: The PCI Bus is always Little Endian. 5.4.2.5 Note: PCI Target PCI-to-Local Address Mapping Not applicable in I2O mode. Master FRAME#, C/BE#, AD (addr) IRDY#, AD (data) Slave Master Slave Three Local Address spaces--Space 0, Space 1, and Expansion ROM--are accessible from the PCI Bus. Each is defined by a set of three registers: * Local Address Range (LAS0RR, LAS1RR, and/or EROMRR) * Local Base Address (LAS0BA, LAS1BA, and/or EROMBA) * PCI Base Address (PCIBAR2, PCIBAR3, and/or PCIERBAR) A fourth register, the Bus Region Descriptor register for PCI-to-Local Accesses (LBRD0 and/or LBRD1), defines the Local Bus characteristics for the PCI Target regions (refer to Figure 5-10). Each PCI-to-Local Address space is defined as part of reset initialization, as described in Section 5.4.2.5.1. These Local Bus characteristics can be modified at any time before actual data transactions. PCI 9054 LHOLD LHOLDA LA, ADS#, LW/R# LD/LAD, BLAST# READY# Figure 5-8. PCI Target Write Master FRAME#, C/BE#, AD (addr) IRDY# Slave Master Slave Local Bus PCI Bus DEVSEL#, TRDY# 5.4.2.5.1 PCI Target Local Bus Initialization LHOLD LHOLDA LA, ADS#, LW/R#, BLAST# READY#, LD/LAD PCI 9054 TRDY#, AD (data) Local Bus PCI Bus DEVSEL# Range--Specifies which PCI Address bits to use for decoding a PCI access to Local Bus space. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0 to all others. Remap PCI-to-Local Addresses into a Local Address Space--Bits in this register remap (replace) the PCI Address bits used in decode as the Local Address bits. Local Bus Region Descriptor--Specifies the Local Bus characteristics. Figure 5-9. PCI Target Read Note: The figures represent a sequence of Bus cycles. 5.4.2.5.2 PCI Target PCI Initialization After a PCI reset, the software determines how much address space is required by writing all ones (1) to a PCI Base Address register and then reading back the value. The PCI 9054 returns zeroes (0) in the Don't Care Address bits, effectively specifying the address space required. The PCI software then maps the Local Address space into the PCI Address space by programming the PCI Base Address register. (Refer to Figure 5-10.) PCI 9054 Data Book v2.1 5-10 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 5 C and J Modes Functional Description PCI Bus Master Local Processor 1 Initialize Local Direct Access Registers 2 Initialize PCI Base Address Registers Range for PCI-to-Local Address Space 0/1 Local Base Address (Remap) for PCI-to-Local Address Space 0/1 Bus Region Descriptors for PCI-to-Local Accesses Range for PCI-to-Local Expansion ROM Local Base Address (Remap) for PCI-to-Local Expansion ROM Bus Region Descriptors for PCI-to-Local Accesses Local Bus Hardware Characteristics PCI Base Address to Local Address Space 0/1 PCI Base Address to Local Expansion ROM 3 PCI Bus Access 4 FIFOs 32-Lword Deep Write 16-Lword Deep Read Local Bus Access PCI Address Space PCI Base Address Local Base Address Local Memory Range Figure 5-10. Local Bus PCI Target Access PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-11 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description Direct Data Transfer Modes 5.4.2.5.3 PCI Target Byte Enables (C Mode) During a PCI Target transfer, each of three spaces (Space 0, Space 1, and Expansion ROM spaces) can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width by encoding the Local Byte Enables (LBE[3:0]#). LBE[3:0]# (PQFP--Pins 91-94; PBGA--Pins P15, N14, L11, and M13) are encoded, based on the configured bus width, as follows: 32-Bit Bus--The four-byte enables indicate which of the four bytes are active during a Data cycle: * BE3# Byte Enable 3--LD[31:24] * BE2# Byte Enable 2--LD[23:16] * BE1# Byte Enable 1--LD[15:8] * BE0# Byte Enable 0--LD[7:0] 16-Bit Bus--BE3#, BE1# and BE0# are encoded to provide BHE#, LA1, and BLE#, respectively: * BE3# Byte High Enable (BHE#)--LD[15:8] * BE2# not used * BE1# Address bit 1 (LA1) * BE0# Byte Low Enable (BLE#)--LD[7:0] 8-Bit Bus--BE1# and BE0# are encoded to provide LA1 and LA0, respectively: * BE3# not used * BE2# not used * BE1# Address bit 1 (LA1) * BE0# Address bit 0 (LA0) * BE0# Byte Enable 0--LAD[7:0] 16-Bit Bus--BE3#, BE1# and BE0# are encoded to provide BHE#, LAD1, and BLE#, respectively: * BE3# Byte High Enable (BHE#)--LAD[15:8] * BE2# not used * BE1# Address bit 1 (LAD1) * BE0# Byte Low Enable (BLE#)--LAD[7:0] 8-Bit Bus--BE1# and BE0# are encoded to provide LAD1 and LAD0, respectively: * BE3# not used * BE2# not used * BE1# Address bit 1 (LAD1) * BE0# Address bit 0 (LAD0) 5.4.2.5.4.1 PCI Target Example A 1 MB Local Address Space, 12300000h through 123FFFFFh, is accessible from the PCI Bus at PCI addresses 78900000h through 789FFFFFh. a. Local initialization software sets the Range and Local Base Address registers as follows: * * Range--FFF00000h (1 MB, decode the upper 12 PCI Address bits) Local Base Address (Remap)--123XXXXXh (Local Base Address for PCI-to-Local accesses) [Space Enable bit(s) must be set to be recognized by the PCI Host (LAS0BA[0]=1, LAS1BA[0]=1)] b. PCI Initialization software writes all ones to the PCI Base Address, then reads it back again. * The PCI 9054 returns a value of FFF00000h. The PCI software then writes to the PCI Base Address register(s). PCI Base Address--789XXXXXh (PCI Base Address for Access to the Local Address Space registers, PCIBAR2 and PCIBAR3). 5.4.2.5.4 PCI Target Byte Enables (J Mode) During a PCI Target transfer, each of three spaces (Space 0, Space 1, and Expansion ROM spaces) can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width by encoding the Local Byte Enables (LBE[3:0]#). LBE[3:0]# (PQFP--Pins 91-94; PBGA--Pins P15, N14, L11, and M13) are encoded, based on the configured bus width, as follows: 32-Bit Bus--The four-byte enables indicate which of the four bytes are active during a Data cycle: * BE3# Byte Enable 3--LAD[31:24] * BE2# Byte Enable 2--LAD[23:16] * BE1# Byte Enable 1--LAD[15:8] * For a PCI Direct access to the Local Bus, the PCI 9054 has a 32-Lword (128-byte) Write FIFO and a 16-Lword (64-byte) Read FIFO. The FIFOs enable the Local Bus to operate independent of the PCI Bus. The PCI 9054 can be programmed to return a Retry response or to throttle TRDY# for any PCI Bus transaction attempting to write to the PCI 9054 Local Bus when the FIFO is full. For PCI Read transactions from the Local Bus, the PCI 9054 holds off TRDY# while gathering data from the Local Bus. For Read accesses mapped to PCI Memory space, the PCI 9054 prefetches up to 16 PCI 9054 Data Book v2.1 5-12 (c) PLX Technology, Inc. All rights reserved. www..com Direct Data Transfer Modes Section 5 C and J Modes Functional Description Lwords (has Continuous Prefetch mode) from the Local Bus. Unused Read data is flushed from the FIFO. For Read accesses mapped to PCI I/O space, the PCI 9054 does not prefetch Read data. Rather, it breaks each read of a Burst cycle into a Single Address/Data cycle on the Local Bus. The PCI Target Retry Delay Clocks bits (LBRD0[31:28]) can be used to program the period of time in which the PCI 9054 holds off TRDY#. The PCI 9054 issues a Retry to the PCI Bus Transaction Master when the programmed time period expires. This occurs when the PCI 9054 cannot gain control of the Local Bus and return TRDY# within the programmed time period. There are two types of deadlock: * Partial Deadlock--A Local Bus Master is performing a Direct Bus Master access to a PCI Bus device other than the PCI Bus device concurrently trying to access the Local Bus * Full Deadlock--A Local Bus Master is performing a Direct Bus Master access to the same PCI Bus device concurrently trying to access the Local Bus This applies only to PCI Initiator and PCI Target accesses through the PCI 9054. Deadlock does not occur in transfers through the PCI 9054 DMA channels or the PCI 9054 internal registers (such as mailboxes). For partial deadlock, the PCI access to the Local Bus times out (the PCI Target Retry Delay Clock (LBRD0[31:28]), which is programmable through the Local Bus Region Descriptor register) and the PCI 9054 responds with a PCI Retry. The PCI Specification requires that a PCI Master release its request for the PCI Bus (de-assert REQ#) for a minimum of two PCI clocks after receiving a Retry. This allows the PCI Bus arbiter to grant the PCI Bus to the PCI 9054 so that it can complete its PCI Initiator access and free up the Local Bus. Possible solutions are described in the following sections for cases in which the PCI Bus arbiter does not function as described (PCI Bus architecture dependent), waiting for a time out is undesirable, or a full deadlock condition exists. When a full deadlock occurs, the only solution is to backoff the Local Bus Master. 5.4.2.6 PCI Target Priority PCI Target accesses have a higher priority than DMA accesses, thereby preempting DMA transfers. During a DMA transfer, if the PCI 9054 detects a pending PCI Target access, it releases the Local Bus within two Data transfers. The PCI 9054 resumes operation after the PCI Target access completes. When the PCI 9054 DMA controller owns the Local Bus, its LHOLD output and LHOLDA input are asserted. When a PCI Target access occurs, the PCI 9054 releases the Local Bus within two Lword transfers by de-asserting LHOLD and floating the Local Bus outputs. After the PCI 9054 acknowledges that LHOLDA is de-asserted, it requests the Local Bus for a PCI Target transfer by asserting LHOLD. When the PCI 9054 receives LHOLDA, it drives the bus and performs the PCI Target transfer. Upon completing a PCI Target transfer, the PCI 9054 releases the Local Bus by de-asserting LHOLD and floating the Local Bus outputs. After the PCI 9054 samples LHOLDA is de-asserted and the Local Bus Pause Timer is set to zero, it requests a DMA transfer from the Local Bus by re-asserting LHOLD. When it receives LHOLDA, it drives the bus and continues the DMA transfer. 5.4.3.1 Backoff The PCI 9054 BREQo signal indicates whether a possible deadlock condition exists. The PCI 9054 starts the Backoff Timer (programmable through registers) when it detects the following conditions: Section 5--C, J Func Desc * A PCI Bus Master is attempting to access memory or an I/O device on the Local Bus and is not gaining access (for example, LHOLDA is not received). * A Local Bus Master is performing a Direct Bus Master Read access to the PCI Bus. Or, a Local Bus Master is performing a Direct Bus Master Write access to the PCI Bus and the PCI 9054 PCI Initiator Write FIFO cannot accept another Write cycle. If the Local Bus Backoff Enable bit is enabled (EROMBA[4]=1), the Backoff Timer expires, and the PCI 9054 has not received LHOLDA, the PCI 9054 5.4.3 Deadlock Conditions Deadlock can occur when a PCI Bus Master must access the PCI 9054 Local Bus at the same time a Master on the PCI 9054 Local Bus must access the PCI Bus. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-13 www..com Section 5 C and J Modes Functional Description DMA Operation asserts BREQo. External bus logic can use this signal to perform backoff. The Backoff cycle is device/bus architecture dependent. External logic (an arbiter) can assert the necessary signals necessary to cause a Local Bus Master to release a Local Bus (backoff). After the Local Bus Master backs off, it can grant the bus to the PCI 9054 by asserting LHOLDA. Once BREQo is asserted, READY# for the current Data cycle is never asserted (the Local Bus Master must perform backoff). When the PCI 9054 detects LHOLDA, it proceeds with the PCI Master-to-Local-Bus access. When this access completes and the PCI 9054 releases the Local Bus, external logic can release the backoff and the Local Bus Master can resume the cycle interrupted by the Backoff cycle. The PCI 9054 Write FIFO retains all data it acknowledged (that is, the last data for which READY# was asserted). After the backoff condition ends, the Local Bus Master restarts the last cycle with ADS#. For writes, data following ADS# should be the data the PCI 9054 did not acknowledge prior to the Backoff cycle (for example, the last data for which READY# is not asserted). If a PCI Read cycle completes when the Local Bus is backed off, the Local Bus Master receives that data if the Local Master restarts the same last cycle (data is not read twice). A new read is performed if the resumed Local Bus cycle is not the same as the Backed Off cycle. 5.4.3.1.2 Preempt Solution For devices that support preempt, USERo can be used to preempt the current Bus Master device. When USERo is asserted, the current Local Bus Master device completes its current cycle and releases the Local Bus, de-asserting LHOLD. 5.4.3.2 Software Solutions to Deadlock Both PCI Host and Local Bus software can use a combination of mailbox registers, doorbell registers, interrupts, direct Local-to-PCI accesses and direct PCI-to-Local accesses to avoid deadlock. 5.5 DMA OPERATION The PCI 9054 supports two independent DMA channels capable of transferring data from the: * Local-to-PCI Bus * PCI-to-Local Bus Each channel consists of a DMA controller and a dedicated bidirectional FIFO. Both channels support Block transfers, Scatter/Gather transfers, with or without End of Transfer (EOT#). Only DMA Channel 0 supports Demand mode DMA transfers. Master mode must be enabled with the Master Enable bit (PCICR[2]) before the PCI 9054 can become a PCI Bus Master. In addition, both DMA channels can be programmed to: * Operate in 8-, 16-, or 32-bit Local Bus width * Use zero to 15 internal wait states (Local Bus) * Enable/disable internal wait states (Local Bus) * Enable/disable Local Bus Burst capability * Limit Local Bus bursts to four (BTERM# enable/ disable) * Hold Local address constant (Local Target is FIFO) or increment * Perform PCI Memory Write and Invalidate (command code = Fh) or normal PCI Memory Write (command code = 7h) * Pause Local transfer with/without BLAST# (DMA Fast/Slow termination) * Assert PCI interrupt (INTA#) or Local interrupt (LINT#) when DMA transfer is complete or Terminal Count is reached during Scatter/Gather DMA mode transfers * Operate in DMA Clear Count mode (only if the descriptor is in Local memory) PCI 9054 Data Book v2.1 5.4.3.1.1 Software/Hardware Solution for Systems without Backoff Capability For adapters that do not support backoff, a possible deadlock solution is as follows. The PCI Host software can use PCI Host software, external Local Bus hardware, general purpose output USERo and general purpose input USERi to prevent deadlock. USERo can be asserted to request that the external arbiter not grant the bus to any Local Bus Master except the PCI 9054. Status output from the Local arbiter can be connected to the general purpose input USERi to indicate that no Local Bus Master owns the Local Bus, or the PCI Host to determine that no Local Bus Master that currently owns the Local Bus can read input. The PCI Host can then perform PCI Target access. When the Host finishes, it de-asserts USERo. 5-14 (c) PLX Technology, Inc. All rights reserved. www..com DMA Operation Section 5 C and J Modes Functional Description The PCI 9054 also supports PCI Dual Address with the upper 32-bit registers (DMADAC0 and DMADAC1). The Local Bus Latency Timer determines the number of Local clocks the PCI 9054 can burst data before relinquishing the Local Bus. The Local Pause Timer sets how soon the DMA channel can request the Local Bus. The PCI 9054 releases the PCI Bus if one of the following conditions occur (refer to Figure 5-11 and Figure 5-12): * FIFO is full (PCI-to-Local Bus) * FIFO is empty (Local-to-PCI Bus) * Terminal count is reached * PCI Bus Latency Timer expires (PCILTR[7:0])--normally programmed by the Host PCI BIOS--and PCI GNT# de-asserts * PCI Host asserts STOP# The PCI 9054 releases the Local Bus if one of the following conditions occurs: * FIFO is empty (PCI-to-Local Bus) * FIFO is full (Local-to-PCI Bus) * Terminal count is reached * Local Bus Latency Timer is enabled and expires (MARBR[7:0]) * Special cycle BREQi# is asserted * PCI Target request is pending 5.5.1 DMA PCI Dual Address Cycle The PCI 9054 supports PCI Dual Address Cycle (DAC) when it is a PCI Bus Master, using the DMADAC0 and DMADAC1 registers for Block DMA transactions. Scatter/ Gather DMA can utilize the DAC function via the DMADAC0 and DMADAC1 registers or DMAMODE0[18] and DMAMODE1[18]. The DAC command is used to transfer a 64-bit address to devices that support 64-bit addressing when the address is above the 4-GB Address space. The PCI 9054 performs a DAC within two PCI clock periods, where the first PCI address is a Lo-Addr, with the command (C/BE[3:0]#) "D", and the second PCI address is a Hi-Addr, with the command (C/BE[3:0]#) "6" or "7", depending upon whether it is a PCI Read or PCI Write cycle. Slave DMA Start Master (DMALADR1 & DMASIZ1) Master DMA Start Slave (DMALADR1 & DMASIZ1) 5.5.2 Block DMA Mode PCI Bus REQ# GNT# FRAME#, C/BE#, AD (addr) IRDY# DEVSEL#, TRDY#, AD (data) DMA registers are accessible from the PCI and Local Buses (refer to Figure 5-4 on page 5-7). During DMA transfers, the PCI 9054 is a Master on both the PCI and Local Buses. For simultaneous access, PCI Target or PCI Initiator has a higher priority than DMA. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-15 Section 5--C, J Func Desc The Host processor or the Local processor sets the Local and PCI starting addresses, transfer byte count, and transfer direction. The Host or Local processor then sets the DMA Start bit to initiate a transfer. The PCI 9054 requests the PCI and Local Buses and transfers data. Once the transfer completes, the PCI 9054 sets the Channel Done bit(s) (DMACSR0[4]=1 and/or DMACSR1[4]=1) and, if enabled, asserts an interrupt(s) (DMAMODE0[10] and/or DMAMODE1[10]) to the Local processor or the PCI Host (programmable). The Channel Done bit(s) can be polled, instead of interrupt generation, to indicate the DMA transfer status. PCI 9054 LHOLD LHOLDA LA, LD/LAD, ADS#, LW/R#, BLAST# READY# Figure 5-11. DMA, PCI-to-Local Bus Note: The figure represents a sequence of Bus cycles. Local Bus www..com Section 5 C and J Modes Functional Description DMA Operation Slave DMA Start Master (DMALADR1 & DMASIZ1) Master DMA Start Slave 5.5.2.1 Block DMA PCI Dual Address Cycle (DMALADR1 & DMASIZ1) LHOLD LHOLDA LA, ADS#, LW/R# BLAST# REQ# GNT# IRDY# DEVSEL#, TRDY# AD (addr & data) PCI 9054 LD/LAD, READY# The PCI 9054 supports the DAC feature in Block DMA mode. Whenever the DMADAC0 or DMADAC1 registers contain a value of 0x00000000, the PCI 9054 performs a Single Address Cycle (SAC) on the PCI Bus. Any other value causes a Dual Address to appear on the PCI Bus. (Refer to Figure 5-13.) PCI Bus Local Bus 5.5.3 Scatter/Gather DMA Mode Figure 5-12. DMA, Local-to-PCI Bus Note: The figure represents a sequence of Bus cycles. In Scatter/Gather DMA mode, the Host processor or Local processor sets up descriptor blocks in Local or Host memory composed of PCI and Local addresses, transfer count, transfer direction, and address of next descriptor block (refer to Figure 5-14 and Figure 5-15). The Host or Local processor then: * Enables the Scatter/Gather mode bit(s) (DMAMODE0[9]=1 and/or DMAMODE1[9]=1) Table 5-2. DMA Local Burst Mode Burst Enable Bit 0 1 BTERM# Enable Bit X 0 Result Single cycle Burst up to four Data cycles Burst forever (terminate when BTERM# is asserted or transfer is completed) * Sets up the address of initial descriptor block in the PCI 9054 Descriptor Pointer register(s) (DMADPR0 and/or DMADPR1) * Initiates the transfer by setting a control bit(s) (DMACSR0[1:0] and/or DMACSR1[1:0]) The PCI 9054 loads the first descriptor block and initiates the Data transfer. The PCI 9054 continues to load descriptor blocks and transfer data until it detects the End of Chain bit(s) (DMADPR0[1] and/or DMADPR1[1]) is set (these bits are part of each descriptor). When the End of Chain bit(s) is detected, the PCI 9054 completes the current descriptor block and sets the DMA Done bit(s) (DMACSR0[4] and/or DMACSR1[4]). If the End of Chain bit(s) is detected, the PCI 9054 asserts a PCI interrupt (INTA#) and/or Local interrupt (LINT#). The PCI 9054 can also be programmed to assert PCI or Local interrupts after each descriptor is loaded, then finish transferring. If Scatter/Gather descriptors are in Local memory, the DMA controller can be programmed to clear the transfer size at completion of each DMA, using the DMA Clear Count Mode bit(s) (DMAMODE0[16] and/ or DMAMODE1[16]). 1 Note: 1 "X" is "Don't Care." PCI 9054 Data Book v2.1 5-16 (c) PLX Technology, Inc. All rights reserved. www..com DMA Operation Section 5 C and J Modes Functional Description Figure 5-13. Dual Address Timing Notes: In Scatter/Gather DMA mode, the descriptor includes the PCI and Local Address Space, transfer size, and next descriptor pointer. It also includes a DAC value if DMADPR0[18] and/or DMAMODE1[I8] is enabled. Otherwise, the register (DMADAC0 and DMADAC1) values are used. The Descriptor Pointer register(s) (DMADPR0 and/or DMADPR1) contains end of chain (bit 1), direction of transfer (bit 3), next descriptor address (bits [31:4]), interrupt after terminal count (bit 2), and next descriptor location (bit 0) bits. The Local Bus width must be the same as Local Memory bus width. A DMA descriptor can be on the Local memory or the PCI memory, or both (for example, one descriptor on Local memory, another descriptor on PCI memory and vice-versa). PCI Bus Local Bus Set up Scatter/Gather DMA for PCI-to-Local PCI 9054 retrieves Scatter/Gather data from Local memory PCI 9054 writes data to Local Bus PCI 9054 writes data to Local Bus PCI 9054 retrieves Scatter/Gather data from Local memory PCI 9054 writes data to Local Bus PCI 9054 writes data to Local Bus PCI Bus Set up Scatter/Gather DMA for Local-to-PCI PCI 9054 retrieves Scatter/Gather data from PCI memory PCI 9054 writes data to PCI Bus PCI 9054 writes data to PCI Bus PCI 9054 retrieves Scatter/Gather data from PCI memory PCI 9054 writes data to PCI Bus PCI 9054 writes data to PCI Bus Local Bus PCI 9054 initiates read from PCI Bus PCI 9054 initiates read from PCI Bus PCI 9054 initiates read from Local Bus PCI 9054 PCI 9054 PCI 9054 initiates read from Local Bus PCI 9054 initiates read from PCI Bus PCI 9054 initiates read from PCI Bus PCI 9054 initiates read from Local Bus PCI 9054 initiates read from Local Bus Read and Write cycles continue... Read and Write cycles continue... Figure 5-14. Scatter/Gather DMA Mode from PCI-toLocal Bus (Control Access from the Local Bus) Note: The figures represent a sequence of Bus cycles. Figure 5-15. Scatter/Gather DMA Mode from Localto-PCI Bus (Control Access from the PCI Bus) Section 5--C, J Func Desc 5-17 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. www..com Section 5 C and J Modes Functional Description DMA Operation 5.5.3.1 Scatter/Gather DMA PCI Dual Address Cycle The PCI 9054 supports the PCI DAC feature in Scatter/Gather DMA mode for Data transfers only. The descriptor blocks should reside below the 4-GB Address space. The PCI 9054 offers three different options of how PCI DAC Scatter/Gather DMA is utilized. Assuming the descriptor blocks are located on the PCI Bus: * DMADAC0 and/or DMADAC1 contain(s) a non-zero value. DMAMODE0[18] and/or DMAMODE1[18] is set to 0. The PCI 9054 performs a Single Address Cycle (SAC) four-Lword descriptor block load from PCI memory and DMA transfer with DAC on the PCI Bus. (Refer to Figure 5-16.) * DMADAC0 and/or DMADAC1 contain(s) an 0x00000000 value. DMAMODE0[18] and/or DMAMODE1[18] is set to 1. The PCI 9054 performs a SAC five-Lword descriptor block load from PCI memory and DMA transfer with PCI DAC on the PCI Bus. (Refer to Figure 5-17.) * DMADAC0 and/or DMADAC1 contain(s) a non-zero value. DMAMODE0[18] and/or DMAMODE1[18] is set to 1. The PCI 9054 performs a SAC five-Lword descriptor block load from PCI memory and DMA transfer with DAC on the PCI Bus. The fifth descriptor overwrites the value of the DMADAC0 and/or DMADAC1 register. (Refer to Figure 5-17.) 5.5.3.2 DMA Clear Count Mode The PCI 9054 supports DMA Clear Count mode (WriteBack feature, DMAMODE0[16] and DMAMODE1[16]). This feature allows users to control the data transfer blocks during Scatter/Gather DMA operations. The PCI 9054 clears the Transfer Size descriptor to zero by writing to a descriptor-memory location at the end of each transfer chain. This feature works only if DMA descriptors are on the Local Bus. PCI 9054 Data Book v2.1 5-18 (c) PLX Technology, Inc. All rights reserved. www..com DMA Operation Section 5 C and J Modes Functional Description 1 Set DMA Mode to Scatter/Gather 3 First PCI Address First Local Address Local or Host Memory PCI Memory Mode Register 2 Set up First Descriptor Pointer Register (Required only for the first Descriptor Pointer) Memory Descriptor Block(s) First Transfer Size (byte count) Next Descriptor Pointer First Memory Block to Transfer PCI Address Local Address Transfer Size (byte count) Next Descriptor Pointer Command/Status Register Next Memory Block to Transfer End of Chain Specification Bit Local Memory 4 Set Enable and Go Bits in DMA Command/Status Register (DMACSR0 and DMACSR1) to Initiate DMA Transfer First Memory Block to Transfer Next Memory Block to Transfer Figure 5-16. Scatter/Gather DMA Mode Descriptor Initialization [PCI SAC/DAC PCI Address (DMADAC0, DMADAC1) Register Dependent] 1 Set DMA Mode to Scatter/Gather 3 PCI Address Low First Local Address Local or Host Memory PCI Memory Mode Register 2 Set up First Descriptor Pointer Register (Required only for the first Descriptor Pointer) Memory Descriptor Block(s) First Transfer Size (byte count) Next Descriptor Pointer PCI Address High First Memory Block to Transfer PCI Address Low Local Address Transfer Size (byte count) Next Descriptor Pointer Next Memory Block to Transfer Command/Status Register PCI Address High Local Memory 4 Set Enable and Go Bits in DMA Command/Status Register (DMACSR0 and DMACSR1) to Initiate DMA Transfer End of Chain Specification Bit First Memory Block to Transfer Next Memory Block to Transfer Figure 5-17. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address (DMAMODE0[18], DMAMODE1[18]) Descriptor Dependent] (PCI Address High Added) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-19 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description DMA Operation 5.5.4 DMA Memory Write and Invalidate 5.5.5 DMA Priority The PCI 9054 can be programmed to perform Memory Write and Invalidate cycles to the PCI Bus for DMA transfers, as well as PCI Initiator transfers (refer to Section 5.4.1.9). The PCI 9054 supports Memory Write and Invalidate transfers for cache line sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or 16 is specified, the PCI 9054 performs Write transfers rather than Memory Write and Invalidate transfers. DMA Memory Write and Invalidate transfers are enabled when the DMA controller Memory Write and Invalidate Enable bit(s) (DMAMODE0[13] and/or DMAMODE1[13]) and the Memory Write and Invalidate Enable bit (PCICR[4]) are set. In Memory Write and Invalidate mode, the PCI 9054 waits until the number of Lwords required for specified cache line size are read from the Local Bus before starting the PCI access. This ensures a complete cache line write can complete in one PCI Bus ownership. If a Target disconnects before a cache line completes, the PCI 9054 completes the remainder of that cache line, using normal writes before resuming Memory Write and Invalidate transfers. If a Memory Write and Invalidate cycle is in progress, the PCI 9054 continues to burst if another cache line is read from the Local Bus before the cycle completes. Otherwise, the PCI 9054 terminates the burst and waits for the next cache line to be read from the Local Bus. If the final transfer is not a complete cache line, the PCI 9054 completes the DMA transfer, using normal writes. The DMA Channel Priority bit (MARBR[20:19]) can be used to specify the following priorities: * Rotating (MARBR[20:19]=00) * DMA Channel 0 (MARBR[20:19]=01) * DMA Channel 1 (MARBR[20:19]=10) 5.5.6 DMA Channel 0/1 Interrupts A DMA channel can assert a PCI Bus or Local Bus interrupt when done (transfer complete) or after a transfer is complete for the current descriptor in Scatter/ Gather DMA mode. The DMA Channel Interrupt Select bit(s) determine whether to assert a PCI (DMAMODE0[17]=1 and/or DMAMODE1[17]=1) or Local (DMAMODE0[17]=0 and/or DMAMODE1[17]=0) interrupt. The Local or PCI processor can read the DMA Channel 0 Interrupt Active bits to determine whether a DMA Channel 0 (INTCSR[21]) or DMA Channel 1 (INTCSR[22]) interrupt is pending. The Channel Done bit(s) (DMACSR0[4] and/or DMACSR1[4]) can be used to determine whether an interrupt is: * DMA Done interrupt * Transfer complete for current descriptor interrupt The Done Interrupt Enable bit(s) (DMAMODE0[10] and/or DMAMODE1[10]) enable a Done interrupt. In Scatter/Gather DMA mode, a bit in the Next Descriptor Pointer register of the channel (loaded from Local memory) specifies whether to assert an interrupt at the end of the transfer for the current descriptor. A DMA Channel interrupt is cleared by the Channel Clear Interrupt bit(s) (DMACSR0[3]=1 and/or DMACSR1[3]=1). 5.5.4.1 DMA Abort DMA transfers can be aborted, in addition to the EOT# signal, as follows: 1. 2. 3. Clear the DMA Channel Enable bit(s) (DMACSR0[0]=0 and/or DMACSR1[0]=0). Abort DMA by setting the Channel Abort bit(s) (DMACSR0[2]=1 and/or DMACSR1[2]=1). Wait until the Channel Done bit(s) is set (DMACSR0[4]=1 and/or DMACSR1[4]=1). 5.5.7 DMA Data Transfers The PCI 9054 DMA controller can be programmed to transfer data from the Local-to-PCI Bus or from the PCI-to-Local Bus. Note: One to two Data transfers occur after the Abort bit is set. Aborting when no DMA cycles are in progress causes the next DMA to abort. PCI 9054 Data Book v2.1 5-20 (c) PLX Technology, Inc. All rights reserved. www..com DMA Operation Section 5 C and J Modes Functional Description 5.5.7.1 Local-to-PCI Bus DMA Transfer PCI Interrupt Generation (Programmable) * Done Unload FIFO with PCI Bus Write Cycles Local Interrupt Generation (Programmable) * Done FIFO PCI Bus Arbitration Local Bus Arbitration Load FIFO with Local Bus Read Cycles PCI Bus Arbitration: Local Bus Arbitration: * Releases control of PCI Bus whenever FIFO becomes empty, PCI Bus Latency Timer expires and PCI GNT# de-asserts, PCI disconnect is received, or Direct Local-to-PCI Bus request is pending. Rearbitrates for control of PCI Bus when preprogrammed number of entries in FIFO becomes available, or after two PCI clocks if disconnect is received. * Releases control of Local Bus whenever FIFO becomes full, terminal count is reached, Local Bus Latency Timer is enabled and expires, BREQi is asserted, or Direct PCI-to-Local Bus request is pending. * GNT# REQ# LHOLDA LHOLD * Rearbitrates for control of Local Bus when preprogrammed number of empty entries in FIFO becomes available. If Local Bus Latency Timer is enabled and expires, waits until Local Bus Pause Timer expires. Figure 5-18. Local-to-PCI Bus DMA Data Transfer Operation 5.5.7.2 PCI-to-Local Bus DMA Transfer PCI Interrupt Generation (Programmable) Local Interrupt Generation (Programmable) * Done Load FIFO with PCI Bus Read Cycles * Done FIFO PCI Bus Arbitration Local Bus Arbitration Unload FIFO with Local Bus Write Cycles PCI Bus Arbitration: Local Bus Arbitration: * Releases control of PCI Bus whenever FIFO becomes full, terminal count is reached, PCI Latency Timer expires and PCI GNT# de-asserts, PCI disconnect is received, or Direct Local-to-PCI Bus request is pending. Rearbitrates for control of PCI Bus when preprogrammed number of empty entries in FIFO becomes available, or after two PCI clocks if disconnect is received. GNT# REQ# LHOLDA LHOLD * Releases control of Local Bus whenever FIFO becomes empty, Local Bus Latency Timer is enabled and expires, BREQi is asserted, or Direct PCI-to-Local Bus request is pending. Rearbitrates for control of Local Bus when preprogrammed number of entries becomes available in FIFO or PCI terminal count is reached. If Local Bus Latency Timer is enabled and expires, waits until Local Bus Pause Timer expires. * * Figure 5-19. PCI-to-Local Bus DMA Data Transfer Operation PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-21 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description DMA Operation 5.5.7.3 DMA Unaligned Transfers For unaligned Local-to-PCI transfers, the PCI 9054 reads a partial Lword from the Local Bus. It continues to read Lwords from the Local Bus. Lwords are assembled, aligned to the PCI Bus address, and loaded into the FIFO. For PCI-to-Local transfers, Lwords are read from the PCI Bus and loaded into the FIFO. On the Local Bus, Lwords are assembled from the FIFO, aligned to the Local Bus address and written to the Local Bus. On both the PCI and Local Buses, the byte enables for writes determine LA[1:0] for the start of a transfer. For the last transfer, byte enables specify the bytes to be written. DREQ0# controls only the number of Lword transfers. For an 8-bit bus, the PCI 9054 releases the bus after transferring the last byte for the Lword. For a 16-bit bus, the PCI 9054 releases the bus after transferring the last word for the Lword. (Refer to the timing diagrams in Section 5.6 for C mode or Section 5.7 for J mode.) 5.5.9 End of Transfer (EOT#) Input The DMA EOT# Enable bit(s) (DMAMODE0[14] and/or DMAMODE1[14]) determines the number of Lwords to transfer after a DMA controller asserts EOT# input. EOT# input should be asserted only when the PCI 9054 owns a bus. If BLAST# output is not required for the last Lword of the DMA transfer (DMAMODE0[15]=1 and/or DMAMODE1[15]=1), the DMA controller releases the data bus and terminates DMA after it receives an external READY#. Or, the internal wait state counter decrements to 0 for the current Lword. If the DMA controller is currently bursting data that is not the last Data phase for the burst, BLAST# output is not asserted. If BLAST# output is required for last Lword of the DMA transfer (DMAMODE0[15]=0 and/or DMAMODE1[15]=0), the DMA controller transfers one or two Lwords, depending on the Local Bus width. If EOT# is asserted, the DMA controller completes the current Lword and one additional Lword (this allows BLAST# output to be asserted during the final Lword). If the DMA FIFO is full or empty after the Data phase in which EOT# is asserted, the second Lword is not transferred. The DMA controller terminates a transfer on an Lword boundary after EOT# is asserted. For an 8-bit bus, the PCI 9054 terminates after transferring the last byte for the Lword. For a 16-bit bus, the PCI 9054 terminates after transferring the last word for the Lword. During the descriptor loading on the Local Bus, assertion of EOT# causes a complete descriptor load and no subsequent Data transfer; however, this is not recommended. This has no effect when the descriptor is loaded from the PCI Bus. 5.5.8 Demand Mode DMA, Channel 0 The Fast/Slow Terminate Mode Select bit(s) (DMAMODE0[15] and/or DMAMODE1[15]) determines the number of Lwords to transfer after the DMA controller DREQ0# input is de-asserted. If BLAST# output is not required for the last Lword of a DMA transfer (bit [15]=1), the DMA controller releases the data bus after it receives an external READY# or the internal wait state counter decrements to 0 for the current Lword. If the DMA controller is currently bursting data, which is not the last Data phase for the Burst, BLAST# is not asserted. If BLAST# output is required for the last Lword of the DMA transfer (bit [15]=0), the DMA controller transfers one or two Lwords. If DREQ0# is de-asserted during the Address phase of the first transfer in the PCI 9054 Local Bus ownership (ADS#, LHOLDA asserted), the DMA controller completes current Lword. If DREQ0# is de-asserted during any phase other than the Address phase of the first transfer in the PCI 9054 Local Bus ownership, the DMA controller completes the current Lword, and one additional Lword (this allows BLAST# output to be asserted during the final Lword). If the DMA FIFO is full or empty after the Data phase in which DREQ0# is de-asserted, the second Lword is not transferred. PCI 9054 Data Book v2.1 5-22 (c) PLX Technology, Inc. All rights reserved. www..com DMA Operation Section 5 C and J Modes Functional Description 5.5.10 DMA Arbitration The PCI 9054 DMA controller releases control of the Local Bus (de-asserts LHOLD) when one of the following conditions occur: * Local Bus Latency Timer is enabled and expires (MARBR[7:0]) * BREQi is asserted (BREQi can be enabled or disabled, or gated with a Local Bus Latency Timer before the PCI 9054 releases the Local Bus) * PCI Target access is pending * EOT# input is received (if enabled) The DMA controller releases control of the PCI Bus when one of the following conditions occurs: * FIFOs are full or empty * PCI Bus Latency Timer expires (PCILTR [7:0])--and loses the PCI GNT# signal * Target disconnect response is received The DMA controller de-asserts its PCI Bus request (REQ#) for a minimum of two PCI clocks. 5.5.11 Local Bus Latency and Pause Timers The Local Bus Latency and Pause Timers are programmable with the Mode/DMA Arbitration register (MARBR[7:0, 15:8]). If the Local Bus Latency Timer is enabled and expires (MARBR[7:0]), the PCI 9054 completes the current Lword transfer and releases LHOLD. After its programmable Pause Timer expires (MARBR[7:0]), it reasserts LHOLD. It continues to transfer when it receives LHOLDA. The PCI Bus transfer continues until the FIFO is empty for a Localto-PCI transfer or full for a PCI-to-Local transfer. The DMA transfer can be paused by writing a 0 to the Channel Enable bit. To acknowledge the disable, the PCI 9054 gets at least one data from the bus before it stops. However, this is not recommended during a burst. The DMA Local Bus Timer starts after the Local Bus is granted to the PCI 9054 and the Local Pause Timer starts after LHOLDA is de-asserted. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-23 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 5.6 C MODE TIMING DIAGRAMS 0ns 250ns 500ns LCLK LHOLD |--- CAN GO HIGH WILL NOT BE RE-ASSERTED UNTIL LHOLDA GOES LOW LHOLDA MUST REMAIN HIGH UNTIL LHOLD GOES LOW Local Bus PCI 9054 DRIVES BUS Timing Diagram 5-1. Local Bus Arbitration (LHOLD and LHOLDA) PCI 9054 Data Book v2.1 5-24 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 5.6.1 C Mode PCI Initiator 0ns 100ns 200ns 300ns 400ns LCLK ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (output) A LBE D0 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# A0 D0 CMD BE Timing Diagram 5-2. PCI Initiator Single Write PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-25 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 100ns 200ns 300ns 400ns LCLK ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (output) A LBE D0 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# A0 D0 CMD BE Timing Diagram 5-3. PCI Initiator Single Read PCI 9054 Data Book v2.1 5-26 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns 75 LCLK ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (output) WAIT# (input) A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 CMD BE Timing Diagram 5-4. PCI Initiator Memory Write of 12 Lwords with WAIT# Input PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-27 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns 750ns LCLK ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (output) WAIT# (input) A D0 D1 D2 D3 D4 D5 D6 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# A CMD BE Timing Diagram 5-5. PCI Initiator Burst Read of Seven Lwords with WAIT# Input PCI 9054 Data Book v2.1 5-28 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns 750ns LCLK ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (output) A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# CMD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 BE Timing Diagram 5-6. PCI Initiator Memory Read of 12 Lwords with Prefetch Counter Set to 16 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-29 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns 750ns 1000ns LCLK ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (output) A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# A CMD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 BE Timing Diagram 5-7. Memory Write and Invalidate with Cache Line Size of Eight PCI 9054 Data Book v2.1 5-30 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns 750ns 1000ns 1250ns 1500ns LCLK ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (output) WAIT# (input) A D0D1 D2 D3D4 D5 D6 D7 D8 D9 D10 D12 13 D11 D D14D16 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# De-assert IRDY# and Keep Bus A CMD D0 D1 D2 BE TRDY# Timing Diagram 5-8. PCI Initiator Memory Read with Keep Bus Mode PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-31 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns 750ns 1000ns 1250ns 1500ns LCLK ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (output) WAIT# (input) A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9D10D11 D13 D15 D12 D14 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Drop Bus BE Timing Diagram 5-9. PCI Initiator Memory Read with Drop Bus Mode PCI 9054 Data Book v2.1 5-32 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns LCLK ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (output) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 BE ADDR D0 D1 D2 D3 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RA D0 D1 D2 D3 CMD BE Timing Diagram 5-10. PCI Bus Request (REQ#) Delay During Direct Master Write (Eight-PCI Clock Delay) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-33 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns 750ns LCLK ADS# BLAST# LW/R# UNLOCK --> LLOCK# LA[31:2] LD[31:0] READY# (output) <-- LOCK KEEP LOCK --> RA WA WD D0 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# LOCK# R-RA CMD D0 0 R-WA WD CMD Timing Diagram 5-11. PCI Initiator Locked Read Followed by Write and Release (LLOCK# and LOCK#) PCI 9054 Data Book v2.1 5-34 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns 750ns CLK FRAME# PCI TARGET READ AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# REQ# ADDR D0 D1 D2 CMD BYTE ENABLES PCI Initiator does not gain PCI Bus until the PCI Target access completes (GNT# asserted, FRAME# de-asserted, IRDY# de-asserted) LCLK LHOLD LHOLDA PCI TARGET PROCEEDS <-- PCI TARGET BACKOFF TIMER STARTS ADS# LA[31:2] LD[31:0] READY# (output) READY# (input) NO PCI INITIATOR READY ADDR D0 D1 D2 D3 BREQo Backoff Timer expires and asserts BREQo to indicate a potential deadlock condition. Refer to PCI 9054 Data Book for a description of deadlock. Note: For partial deadlock, PCI Target Retry Delay Clock bits (LBRD0[31:28]) can be used to issue Retrys to the PCI Master attempting the PCI Target access. Timing Diagram 5-12. BREQo and Deadlock PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-35 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 100ns 200ns 300ns 400ns LCLK CCS# ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (output) First READY# output will be delayed for at least five clocks for access to shared registers. DATA 0 DATA 1 Timing Diagram 5-13. Local Bus Write to Configuration Register 0ns 100ns 200ns 300ns 400ns LCLK CCS# ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] DP[3:0] READY# (output) First READY# output will be delayed at least five clocks for access to shared registers. DATA 0 DATA 1 DP0 DP1 Timing Diagram 5-14. Local Bus Read to Configuration Register PCI 9054 Data Book v2.1 5-36 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns 750ns LCLK ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (output) D1 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# A0 D0 0 CMD Timing Diagram 5-15. PCI Initiator Configuration Read--Type 1 or Type 0 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-37 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns LCLK ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (output) A D1 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# A0 CMD D0 0 Timing Diagram 5-16. PCI Initiator Configuration Write--Type 1 or Type 0 PCI 9054 Data Book v2.1 5-38 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0us 5us 10us 15us 20us 25us 30us EESK LRESETo# EECS EEDI EEDO 0 1 1 0 0 0 0 0 0 0 0 0 INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----| 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] CONFIGURATION REGISTER 0 HEX EESK EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 BITS [15:0] CONFIGURATION REGISTER 0 HEX BITS [31:16] OF CONFIGURATION REGISTER 8 HEX CONTINUES EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LAST WORD CONTINUES EESK, EEDO, EECS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ Timing Diagram 5-17. Initialization from Serial EEPROM (2K Bit) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-39 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0us 5us 10us 15us 20us 25us 30us EESK LRESETo# EECS EEDI EEDO 0 1 1 0 0 0 0 0 0 0 0 0 INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----| 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] CONFIGURATION REGISTER 0 HEX EESK EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 BITS [15:0] CONFIGURATION REGISTER 0 HEX BITS [31:16] OF CONFIGURATION REGISTER 8 HEX CONTINUES EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LAST WORD CONTINUES EESK, EEDO, EECS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ Timing Diagram 5-18. Initialization from Serial EEPROM (4K Bit) PCI 9054 Data Book v2.1 5-40 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=B Data BE Timing Diagram 5-19. PCI Configuration Write to PCI Configuration Register 0ns 50ns 100ns 150ns 200ns 250ns 300n CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=A Data Read BE Timing Diagram 5-20. PCI Configuration Read to PCI Configuration Register PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-41 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=7 Data BE Timing Diagram 5-21. PCI Memory Write to Local Configuration Register 0ns 50ns 100ns 150ns 200ns 250ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR CMD=6 BE Data Read Timing Diagram 5-22. PCI Memory Read to Local Configuration Register PCI 9054 Data Book v2.1 5-42 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 100ns 200ns 300ns 400ns 500n CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR DATA CMD BE INTA# RESPONSE ON THE PCI BUS LCLK LINT# Timing Diagram 5-23. Local Interrupt Asserting PCI Interrupt PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-43 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 5.6.2 C Mode PCI Target 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR Data CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) ADDR Data LBE Timing Diagram 5-24. PCI Target Single Write (32-Bit Local Bus) PCI 9054 Data Book v2.1 5-44 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 100ns 200ns 300ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[15:0] READY# (input) A 0 2 D D Timing Diagram 5-25. PCI Target Burst Cycle Write (16-Bit Local Bus) 0ns 100ns 200ns 300ns 400ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LD[7:0]# LW/R# LA[31:2] READY# (input) A 0 1 2 3 D D D D Timing Diagram 5-26. PCI Target Burst Cycle Write (8-Bit Local Bus) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-45 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 100ns 200ns 300ns 400ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADDR DATA CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (input) ADDR DATA Timing Diagram 5-27. PCI Target Single-Cycle Read (32-Bit Local Bus) PCI 9054 Data Book v2.1 5-46 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 100ns 200ns 300ns 400ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADDR DATA CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) ADDR DATA LBE Timing Diagram 5-28. PCI Target Single Read with One Wait State Using READY# Input (32-Bit Local Bus) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-47 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 100ns 200ns 300ns 400ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 14 ADDR DATA CMD BE LCLK LHOLD LHOLDA ADS# LW/R# BLAST# LA[31:2] LD[31:0] ADDR DATA Timing Diagram 5-29. PCI Target Single Read with One Wait State Using Internal Wait State (32-Bit Local Bus) PCI 9054 Data Book v2.1 5-48 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR D0 D1 BE D2 CMD LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] BTERM# (input) READY# (input) ADDR LBE +4 D1 +8 D2 D0 Timing Diagram 5-30. PCI Target Non-Burst Write (32-Bit Local Bus) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-49 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 100ns 200ns 300ns 400ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[7:0] BTERM# (input) READY# (input) D D A C D E F D D Timing Diagram 5-31. PCI Target Non-Burst Write (8-Bit Local Bus) PCI 9054 Data Book v2.1 5-50 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 14 ADDR D0 D1 D2 CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] BTERM# (input) READY# (input) ADDR D0 +4 D1 +8 D2 LBE Timing Diagram 5-32. PCI Target Non-Burst Local Bus Read PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-51 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] BTERM# (input) READY# (input) Eight Lword Burst, no wait states, Bterm enabled, Burst enabled, 32-bit Local Bus. Note: If Bterm is disabled, a new ADS# cycle starts every quad-Lword boundary. A A+4 A+8 A+C A+10 A+14 A+18 A+1C A+20 A+24 A+28 LBE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Bterm FORCES NEW ADS# --> Timing Diagram 5-33. PCI Target Burst Write with Bterm Enabled (32-Bit Local Bus) PCI 9054 Data Book v2.1 5-52 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 100ns 200ns 300ns 400ns 500ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] BTERM# (input) READY# (input) No wait states, Bterm disabled, Burst enabled, 32-bit Local Bus. Unaligned Transfer results in new ADS#. Note: Not all byte enables asserted or a quad boundary LA[3:2]=11 results in a new ADS#. ADDR A+4 A+8 A+C A+10 A+14 A+18 A+1C A+20 0001 LBE = 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 Timing Diagram 5-34. PCI Target Burst Write with Bterm Disabled (32-Bit Local Bus) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-53 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR D0 D1 D2 D3 D4 CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) ADDR D0 +4 D1 +8 D2 +12 D3 +16 D4 LBE +20 +24 +28 D5 D6 D7 Timing Diagram 5-35. PCI Target Burst Read with Prefetch Counter Set to 8 (32-Bit Local Bus) PCI 9054 Data Book v2.1 5-54 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR D0 D1 D2 D3 D4 CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) ADDR D0 +4 D1 +8 D2 +C D3 +10 D4 LBE Timing Diagram 5-36. PCI Target Burst Read with Prefetch Counter Set to 5 (32-Bit Local Bus) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-55 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR DO D1 D3 D4 CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) Five Lwords, one external wait state, Bterm enabled, Burst enabled. A +4 +8 +C +10 LBE D0 D1 D2 D3 D4 Timing Diagram 5-37. PCI Target Burst Write (32-Bit Local Bus) PCI 9054 Data Book v2.1 5-56 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 100ns 200ns 300ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[15:0] READY# (input) Two Lword Burst Write, no wait states, Bterm enabled. A A+4 4 6 4 6 D D D D Timing Diagram 5-38. PCI Target Burst Write (16-Bit Local Bus) 0ns 100ns 200ns 300ns 400ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[7:0] BTERM# (input) READY# (input) D D A C D E F D D Timing Diagram 5-39. PCI Target Burst Write with External Wait States (8-Bit Local Bus) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-57 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns 750ns 1000ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# Retry Retry A CMD A CMD A CMD D0 D1 D2 D3 D4 D5 D6 D7 D8 BE ADDR CMD D0 BE BE STOP# Delayed Read Retries Write Is Not Allowed During Delayed Read Reads Data Write Retries and Completes LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) Disconnect immediately for a read. Does not effect pending reads when a Write cycle occurs, nor flush the Read FIFO if the PCI Read cycle completes. When a read is pending, force Retry on a write. De-assert TRDY# until space is available in the Direct Slave Write FIFO. ADDR +4 +8 +C +10 +14 +18 +1C +20 +24 +28 +2C +30 +34 +38 +3C D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 LBE Timing Diagram 5-40. Delayed Read Transaction PCI Specification v2.1 PCI 9054 Data Book v2.1 5-58 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns 750ns 1000ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR D0 AddrD1 D2 D3 D4 D5 D6 CMD BE CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) ADDR +4 +8 +C +10 +14 +18 +1C +20 +24 +28 +2C +30 +34 +38 +3C +40 ADDR LBE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D0 Timing Diagram 5-41. PCI Target Read No Flush Mode (Read Ahead Mode), Prefetch Enabled, Prefetch Count Disabled PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-59 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] BTERM# (input) READY# (input) BREQi No wait states, Bterm enabled, Burst enabled, 32-bit Local Bus. Owned by the Local Processor or other Bus Master. DMA continues transferring data. A +4 +8 +C +10 +14 +18 +1C +20 +24 DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS# D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Timing Diagram 5-42. PCI Target Burst Write Suspended by BREQi PCI 9054 Data Book v2.1 5-60 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns 750ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# LOCK# <-- CAN BE DE-ASSERTED AFTER LAST DAT ADDR D0 D1 W-A W-DATA R BYTE ENABLES W BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) LLOCKo# DE-ASSERTED AFTER DETECTING PCI UNLOCK ---> ADDR +4 +8 +12 +16 +20 +24 +28 +32 W-ADDR LBE LBE D0 D1 D2 D3 D4 D5 D6 D7 D8 W-DATA Timing Diagram 5-43. Locked PCI Target Read Followed by Write and Release (LLOCKo#) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-61 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 100ns 200ns 300ns 400ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR Data= AABBCCDD 01234567 CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] BIGEND# READY# (input) ADDR LBE DDCCBBAA 67452301 Timing Diagram 5-44. PCI Target in BIGEND Local Bus with BIGEND# Input PCI 9054 Data Book v2.1 5-62 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 5.6.3 C Mode DMA 0ns 250ns 500ns 750ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR D0 D1 D2 D3 D4 D5 D6 D7 CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) ADDR D0 +4 D1 +8 +C +10 +14 +18 +1C LBE D2 D3 D4 D5 D6 D7 Timing Diagram 5-45. DMA Aligned PCI Address to Aligned Local Address, Bterm Enabled, Burst Enabled PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-63 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns 750ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR D0 D1 D2 D3 D4 D5 D6 D7 CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) BTERM# (input) No wait states, Bterm disabled, Burst enabled, 32-bit Bus. ADDR +4 +8 +C +10 +14 +18 +1C LBE D0 D1 D2 D3 D4 D5 D6 D7 Timing Diagram 5-46. DMA Aligned PCI Address to Aligned Local Address, Bterm Disabled, Burst Enabled PCI 9054 Data Book v2.1 5-64 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) First Address A are Next Descriptor Address bits (DMADPR0[31:4] and/or DMADPR1[31:4]). D0: PCI start address D1: Local start address D2: Transfer count (bytes) D3: Next descriptor pointer ADDR LBE <--- PCI 9054 DRIVES BUS +4 D1 +8 D2 +C D3 D0 Timing Diagram 5-47. Scatter/Gather DMA with Descriptor on Local Bus PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-65 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns 750ns CLK Reading from the Descriptor FRAME# AD[31:0] C/BE[3:0]# ADDR D0 D1 D2 D3 ADDR(D0) d0 d1 d2 d3 CMD BE Local-to-PCI Transfer CMD BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) ADDR +4 +8 +12 +16 LBE D0 D1 D2 D3 Timing Diagram 5-48. Scatter/Gather DMA from Local-to-PCI with Descriptor on PCI Bus PCI 9054 Data Book v2.1 5-66 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 50ns 100ns 150ns 200ns 250ns 300ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] DREQ0# DACK0# READY# (input) No wait states, Bterm enabled, Burst enabled, 32-bit Local Bus. A A+4 LBE D0 D1 DREQ0# MUST BE DE-ASSERTED AFTER LHOLD IS DE-ASSERTED Timing Diagram 5-49. Demand DMA, Terminate with BLAST# (Local-to-PCI) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-67 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR D0 D1 D2 D3 D4 D5 CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) EOT# The Fast/Slow Terminate Mode Select bit is not set. If this bit is set, there is no BLAST# and D5 is not transferred (see DMAMODE[15] and/or DMAMODE1[15]). ADDR +4 +8 +C +10 +14 +18 LBE D0 D1 D2 D3 D4 D5 Timing Diagram 5-50. DMA Local-to-PCI, Terminate with EOT# PCI 9054 Data Book v2.1 5-68 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR D0 D1 D2 D3 D4 D5 D6 D7 CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) EOT# ADDR +4 +8 LBE D0 D1 The Fast/Slow Terminate Mode Select bit is not set. If this bit is set, there is no BLAST# and D1 is not transferred (see DMAMODE[15] and/or DMAMODE1[15]). Timing Diagram 5-51. DMA PCI-to-Local, Terminate with EOT# PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-69 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 250ns 500ns 750ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CMD BE LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) D0 +4 +8 +C +10 +14 +18 +1C +20 +24 LBE D1 D2 D3 D4 D5 D6 D7 D8 D9 Local Bus Latency Timer = 7 CLK, Local Bus Pause Timer = 4 CLK. The PCI 9054 has internally added another clock to the Local Bus Pause Timer. The Local Bus Latency Timer starts after ADS# is active. The Local Bus Pause Timer starts after LHOLDA is de-asserted. Timing Diagram 5-52. DMA PCI-to-Local with Local Bus Pause and Latency Timers PCI 9054 Data Book v2.1 5-70 (c) PLX Technology, Inc. All rights reserved. www..com C Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 100ns 200ns 300ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] A D0 DREQ0# MUST BE DE-ASSERTED TO PREVENT BURST ------------------------------> DREQ0# DACK0# READY# (input) Timing Diagram 5-53. Single-Cycle Demand DMA Mode (PCI-to-Local) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-71 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description C Mode Timing Diagrams 0ns 100ns 200ns 300ns 400ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] A A+4 D0 CURRENT DATA + LAST DATA TRANSFERRED AFTER DREQ0# IS DE-ASSERTED D1 DREQ0# DACK0# READY# (input) No wait states, Bterm enabled, Burst enabled, 32-bit Local Bus. Timing Diagram 5-54. Multiple-Cycle Demand DMA Mode (PCI-to-Local) PCI 9054 Data Book v2.1 5-72 (c) PLX Technology, Inc. All rights reserved. www..com J Mode Timing Diagrams Section 5 C and J Modes Functional Description 5.7 5.7.1 J MODE TIMING DIAGRAMS J Mode PCI Initiator 0ns 100ns 200ns 300ns 400ns LCLK ADS# ALE BLAST# LBE[3:0]# LW/R# LAD[31:0] DT/R# DEN# READY# (output) A Data LBE CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# A0 CMD D0 BE Timing Diagram 5-55. PCI Initiator Single Write Section 5--C, J Func Desc PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-73 www..com Section 5 C and J Modes Functional Description J Mode Timing Diagrams 0ns 100ns 200ns 300ns 400ns LCLK ADS# ALE BLAST# LBE[3:0]# LW/R# LAD[31:0] DT/R# DEN# READY# (output) A Data LBE CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# A0 D0 CMD BE Timing Diagram 5-56. PCI Initiator Single Read PCI 9054 Data Book v2.1 5-74 (c) PLX Technology, Inc. All rights reserved. www..com J Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 250ns 500ns 750ns LCLK ADS# ALE BLAST# LBE[3:0]# LW/R# LAD[31:0] DT/R# DEN# READY# (output) A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 LBE CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 CMD 0 Timing Diagram 5-57. PCI Initiator Burst Write of 10 Lwords, Zero Wait States Section 5--C, J Func Desc PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-75 www..com Section 5 C and J Modes Functional Description J Mode Timing Diagrams 0ns 250ns 500ns 750ns LCLK ADS# ALE BLAST# LBE[3:0]# LW/R# LAD[31:0] DT/R# DEN# READY# (output) A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 LBE CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# ADDR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 CMD BE Timing Diagram 5-58. PCI Initiator Burst Read of 10 Lwords, Zero Wait States PCI 9054 Data Book v2.1 5-76 (c) PLX Technology, Inc. All rights reserved. www..com J Mode Timing Diagrams Section 5 C and J Modes Functional Description 5.7.2 J Mode PCI Target 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 ADDR Data CMD BE LCLK LHOLD LHOLDA ADS# ALE BLAST# LBE[3:0]# LW/R# LAD[31:0] DT/R# DEN# READY# (input) A LBE Data Timing Diagram 5-59. PCI Target Single Write (32-Bit Local Bus) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-77 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description J Mode Timing Diagrams 0ns 100ns 200ns 300ns 400ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# 1 2 3 4 5 6 7 8 14 ADDR Data CMD BE LCLK LHOLD LHOLDA ADS# ALE BLAST# LW/R# LBE[3:0]# LAD[31:0] DT/R# DEN# READY# (input) A LBE Data Timing Diagram 5-60. PCI Target Single Read (32-Bit Local Bus) PCI 9054 Data Book v2.1 5-78 (c) PLX Technology, Inc. All rights reserved. www..com J Mode Timing Diagrams Section 5 C and J Modes Functional Description 0ns 100ns 200ns 300ns 400ns 500ns LCLK LHOLD LHOLDA ADS# ALE BLAST# LBE[3:0]# LW/R# LAD[31:0] DT/R# DEN# BTERM# (input) READY# (input) Eight Lword Burst, no wait states, BTERM# (input) enabled, Burst enabled, 32-bit Local Bus. Note: If BTERM# (input) is disabled, a new ADS# cycle starts every quad-Lword boundary. BTERM# (input) replaces READY# (input) when asserted. A D0 D1 D2 D3 D4 A+14 D5 D6 D7 DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS# Timing Diagram 5-61. PCI Target Burst Write with Bterm Enabled (32-Bit Local Bus) PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-79 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description J Mode Timing Diagrams 0ns 250ns 500ns 750ns 1000ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# ADDR D0 D1 D2 D3 D4 D5 D6 D7 CMD BE LCLK LHOLD LHOLDA ADS# ALE BLAST# LAD[31:0] LBE[3:0]# LW/R# DTR# DEN# READY# (input) A D0 D1 D2 D3 D4 D5 D6 D7 LBE Timing Diagram 5-62. PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus), Prefetech Counter Set to 8 PCI 9054 Data Book v2.1 5-80 (c) PLX Technology, Inc. All rights reserved. www..com J Mode Timing Diagrams Section 5 C and J Modes Functional Description 5.7.3 J Mode DMA 0ns 100ns 200ns 300ns 400ns 500ns LCLK LHOLD LHOLDA ADS# ALE BLAST# LBE[3:0]# LW/R# LAD[31:0] DT/R# DEN# BTERM# (input) READY# (input) Eight Lword burst, no wait states, BTERM# (input) enabled, Burst enabled, 32-bit Local Bus. Note: If BTERM# (input) is disabled, a new ADS# cycle starts every quad-Lword boundary. A D0 D1 D2 D3 D4 A+14 D5 D6 D7 DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS# Timing Diagram 5-63. DMA Aligned PCI Address to Aligned Local Address, Bterm Enabled, Burst Enabled PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 5-81 Section 5--C, J Func Desc www..com Section 5 C and J Modes Functional Description J Mode Timing Diagrams 0ns 250ns 500ns LCLK LHOLD LHOLDA ADS# ALE BLAST# LBE[3:0]# LW/R# LAD[31:0] DT/R# DEN# BTERM# (input) READY# (input) Eight Lword Burst, no wait states, BTERM# (input) enabled, Burst enabled, 32-bit Local Bus. Note: If BTERM# (input) is disabled, a new ADS# cycle starts every quad-Lword boundary. A D0 D1 D2 D3 D4 A+14 DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS# D5 D6 D7 Timing Diagram 5-64. DMA Aligned Local Address to Aligned PCI Address, Bterm Enabled, Burst Enabled PCI 9054 Data Book v2.1 5-82 (c) PLX Technology, Inc. All rights reserved. www..com 6 6.1 PCI LOCAL INTERRUPTS AND USER I/O INTERRUPTS Parity Error Master Abort 256 Retrys Target Abort Local Parity Check Messaging Queue (outbound overflow) DMA Ch 0 Done DMA Ch 0 Terminal Count Doorbells Master Abort 256 Retrys Target Abort LINT# (input) Messaging Queue (outbound not empty) DMA Ch 1 Done DMA Ch 1 Terminal Count X6 OR X7 X8 [12] OR [10] X2 OR X3 X4 [6] [12] OR [0] [1] DMA Ch 0 Done DMA Ch 0 Terminal Count Doorbells X2 OR X3 X4 OR TEA#/ LSERR# [17] Mailboxes X1 [7] BIST Power Management Messaging Queue (inbound not empty) [9] [4] OR [16] LINT# (output) X5 DMA Ch 1 Done DMA Ch 1 Terminal Count OR [11] [8] X6 OR X7 X8 INTA# The numbers represent bit numbers in the INTCSR register X9 X1 = X2 = X3 = X4 = X5 = X6 = X7 = X8 = X9 = Outbound Free Queue Overflow Interrupt Full and Mask bits (QSR[7:6]) Channel 0 Done Interrupt Enable bit (DMAMODE0[10]) Channel 0 Interrupt after Terminal Count bit (DMADPR0[2]) Local DMA Channel 0 Interrupt Enable bit (INTCSR[18]) and DMA Channel 0 Interrupt Select bit (DMAMODE0[17]) Inbound Post Queue Interrupt Not Empty and Inbound Post Queue Interrupt Mask bits (QSR[5:4]) Channel 1 Done Interrupt Enable bit (DMAMODE1[10]) Channel 1Interrupt after Terminal Count bit (DMADPR1[2]) Local DMA Channel 1 Interrupt Enable bit (INTCSR[19]) and DMA Channel 1 Interrupt Select bit (DMAMODE1[17]) Outbound Post Queue Interrupt bit (OPQIS[3]) and Outbound Post Queue Interrupt Mask bit (OPQIM[3]) For X4 and X8, if bit 17='0', then LINT# is asserted and if bit 17='1', then INTA# is asserted. Figure 6-1. Interrupt and Error Sources 6.1.1 PCI Interrupts (INTA#) A PCI 9054 PCI Interrupt (INTA#) can be asserted by one of the following: * Local-to-PCI Doorbell register * Local Interrupt input * Master/Target Abort Status condition * DMA Ch 0/Ch 1 Done * DMA Ch 0/Ch 1 Terminal Count is reached * Messaging Outbound Post Queue not empty * 256 consecutive PCI Retrys INTA#, or individual sources of an interrupt, can be enabled or disabled with the PCI 9054 Interrupt Control/Status register (INTCSR). This register also provides the interrupt status of each interrupt source. The PCI 9054 PCI Bus interrupt is a level output. Disabling an interrupt enable bit or clearing the cause(s) of the interrupt can clear an interrupt. 6.1.2 Local Interrupt Input (LINT#) Asserting the Local Bus input LINT# can assert a PCI Bus interrupt. The PCI Host processor can read the PCI 9054 Interrupt Control/Status register (INTCSR) to determine whether an interrupt is pending as a result of LINT# being asserted (INTCSR[15]). The interrupt remains asserted as long as LINT# input is asserted and the Local Interrupt input is enabled. The PCI Host processor can take adapter-specific action to cause the Local Bus to release LINT#. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 6-1 Section 6--Interrupts, I/O www..com Section 6 PCI Local Interrupts and User I/O Interrupts If the PCI Interrupt Enable bit is cleared (INTCSR[8]=0), the PCI interrupt (INTA#) is de-asserted; however, the Local interrupts (LINT#) and the status bit remain active. 6.1.5 Mailbox Registers 6.1.3 Local Interrupt Output (LINT#) The PCI 9054 has eight 32-bit Mailbox registers that can be written to and read from both the PCI and Local Buses. These registers can be used to pass command and status information directly between the PCI and Local Bus devices. A Local interrupt can be asserted, if enabled (INTCSR[3] and INTCSR[16]), when the PCI Host writes to one of the first four Mailbox registers (MBOX0, MBOX1, MBOX2, or MBOX3). To clear the Mailbox registry, the destination bus should read the values currently in the Mailbox registers. The PCI 9054 Local Interrupt (LINT#) output can be asserted by one of the following: * PCI-to-Local Doorbell/Mailbox register access * PCI BIST interrupt * DMA Ch 0/Ch 1 Done interrupt * DMA Ch 0/Ch 1 Terminal Count is reached * DMA Abort Interrupt or Messaging Outbound Post Queue is not empty LINT#, or individual sources of an interrupt, can be enabled or disabled with the PCI 9054 Interrupt Control/Status register (INTCSR). This register also provides interrupt status for each interrupt source. The PCI 9054 Local interrupt is a level output. Interrupts can be cleared by disabling the Interrupt Enable bit of a source or by clearing the cause of an interrupt. The Local Interrupt Input Enable bit must be disabled (INTCSR[11]=0) when LINT# output is active; otherwise, the PCI interrupt becomes active. This could result in an unwanted PCI interrupt. 6.1.6 Doorbell Registers The PCI 9054 has two 32-bit Doorbell Interrupt/Status registers. One is assigned to the PCI Bus interface. The other is assigned to the Local Bus interface. A Local processor can assert a PCI Bus interrupt by writing any number other than all zeroes to the Local-to-PCI Doorbell register bits (P2LDBELL[31:0]). A PCI Host can assert a Local Bus interrupt by writing any number other than all zeroes to the PCI-to-Local Doorbell register bits (L2PDBELL[31:0]). The PCI Interrupt and Local Interrupt remain asserted until all bits are cleared to zero. 6.1.4 Master/Target Abort Interrupt PCI Bus Local Bus PCI Bus Local Bus The PCI 9054 sets the Received Master Abort or Target Abort bit (PCISR[13, 11]=1, respectively) when it detects a Master or Target Abort. These status bits cause the PCI INTA# to be asserted if interrupts are enabled. Interrupt remains set as long as the Receive Master Abort or Target Abort bits remain set and the Master/ Target Abort interrupt is enabled. Use PCI Type 0 Configuration or Local accesses to clear the Received Master Abort and Target Abort interrupt bits (PCISR[13, 11]=0, respectively). The Interrupt Control/Status Register bit(s) (INTCSR[26:24]) are latched at the time of a Master or Target Abort interrupt. These bits provide information such as which device was the Master when an abort occurred. The PCI 9054 updates these bits only when an abort occurs. Mailbox registers can be read and/or written from both sides Mailbox 0 Mailbox 1 Mailbox 2 Mailbox 3 Mailbox 4 Mailbox 5 Mailbox 6 Mailbox 7 Set Doorbell registers set and clear interrupts PCI-to-Local Local-to-PCI LINT# (Interrupt) INTA# Set Used for Passing * Commands * Pointers * Status Figure 6-2. Mailbox and Doorbell Message Passing PCI 9054 Data Book v2.1 6-2 (c) PLX Technology, Inc. All rights reserved. www..com 6.1.6.1 Local-to-PCI Doorbell Interrupt A Local Bus Master can assert a PCI Bus interrupt by writing to the Local-to-PCI Doorbell Register bit(s) (L2PDBELL[31:0]). The PCI Host processor can read the PCI Doorbell Interrupt Active bit to determine whether a PCI Doorbell interrupt is pending (INTCSR[13]), and if so, read the PCI 9054 Local-toPCI Doorbell register. Each bit in the Local-to-PCI Doorbell register is individually controlled. The Local Bus can only set bits in the Local-to-PCI Doorbell register. From Local Bus, writing 1 to any bit position sets that bit and writing 0 has no effect. Bits in the Local-to-PCI Doorbell register can only be cleared from the PCI Bus. From the PCI Bus, writing 1 to any bit position clears that bit and writing 0 has no effect. Interrupts remain set as long as any Local-to-PCI Doorbell register bits are set and the PCI Doorbell Interrupt Enable bit (INTCSR[9]) is set. Each bit in the PCI-to-Local Doorbell register is individually controlled. The PCI Bus only sets bits in the PCI-to-Local Doorbell register. From the PCI Bus, writing 1 to any bit position sets that bit and writing 0 to a bit position has no effect. Bits in the PCI-to-Local Doorbell register can only be cleared from the Local Bus. From the Local Bus, writing 1 to any bit position clears that bit and writing 0 has no effect. Note: If the Local Bus cannot clear a Doorbell Interrupt, do not use the PCI-to-Local Doorbell register. Interrupts remain set as long as any PCI-to-Local Doorbell register bits are set and the Local Doorbell Interrupt Enable bit is set (INTCSR[17]=1). To prevent race conditions when the Local Bus is accessing the PCI-to-Local Doorbell register (or any Configuration register), the PCI 9054 automatically issues a Retry to the PCI Bus. 6.1.7 Built-In Self Test Interrupt (BIST) 6.1.6.1.1 M Mode Local-to-PCI Doorbell Interrupt To prevent race conditions from occurring when the PCI Bus is accessing the Local-to-PCI Doorbell register (or any Configuration register), the PCI 9054 automatically de-asserts TA# output to prevent Local Bus configuration accesses. A PCI Bus Master can assert a Local Bus interrupt by performing a PCI Type 0 Configuration write to a bit in the PCI BIST register. A Local processor can read the BIST Interrupt Active bit (INTCSR[23]) to determine whether a BIST interrupt is pending. Interrupts remain set as long as the bit is set and the PCI BIST Interrupt Enable bit is set (PCIBISTR[6]=1). The Local Bus then resets the bit when BIST completes. The PCI Host software may fail the device if the bit is not reset after two seconds. Note: The PCI 9054 does not have an internal BIST. 6.1.6.1.2 C and J Modes Local-to-PCI Doorbell Interrupt To prevent race conditions from occurring when the PCI Bus is accessing the Local-to-PCI Doorbell register (or any Configuration register), the PCI 9054 automatically de-asserts READY# output to prevent Local Bus configuration accesses. 6.1.8 DMA Channel 0/1 Interrupts 6.1.6.2 PCI-to-Local Doorbell Interrupt A PCI Bus Master can assert a Local Bus interrupt by writing to the PCI-to-Local Doorbell Register bit(s) (P2LDBELL[31:0]). The Local processor can read the Local Doorbell Interrupt Active bit to determine whether a Local doorbell interrupt is pending (P2LDBELL[20]), and if so, read the PCI 9054 PCI-toLocal Doorbell register. A DMA channel can assert a PCI Bus or Local Bus interrupt when done (transfer complete) or after a transfer is complete for the current descriptor in Scatter/ Gather DMA mode. The DMA Channel Interrupt Select bit(s) determine whether to assert a PCI (DMAMODE0[17]=1 and/or DMAMODE1[17]=1) or Local (DMAMODE0[17]=0 and/or DMAMODE1[17]=0) interrupt. The Local or PCI processor can read the DMA Channel 0 Interrupt Active bits to determine whether a DMA Channel 0 (INTCSR[21]) or DMA Channel 1 (INTCSR[22]) interrupt is pending. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 6-3 Section 6--Interrupts, I/O Interrupts Section 6 PCI Local Interrupts and User I/O www..com Section 6 PCI Local Interrupts and User I/O Interrupts The Channel Done bit(s) (DMACSR0[4] and/or DMACSR1[4]) can be used to determine whether an interrupt is one of the following: * DMA Done interrupt * Transfer complete for current descriptor interrupt The Done Interrupt Enable bit(s) (DMAMODE0[10] and/or DMAMODE1[10]) enable a Done interrupt. In Scatter/Gather DMA mode, a bit in the Next Descriptor Pointer register of the channel (loaded from Local memory) specifies whether to assert an interrupt at the end of the transfer for the current descriptor. A DMA Channel interrupt is cleared by the Channel Clear Interrupt bit(s) (DMACSR0[3]=1 and/or DMACSR1[3]=1). The PCI 9054 sets the Detected Parity Error bit (PCISR[15]=1) if it detects one of the following conditions: * The PCI 9054 detected a parity error during a PCI Address phase * The PCI 9054 detected a data parity error when it was the Target of a write * The PCI 9054 detected a data parity error when performing Master Read operation 6.1.12 M Mode Local TEA# (Local NMI) A TEA# interrupt is asserted if the following occurs: * PCI Bus Target Abort bit is set (PCISR[11]=1) or Received Master Abort bit is set (PCISR[13]=1) * Detected Parity Error bit is set (PCISR[15]=1) * PCI Initiator Local Data Parity Check Error Status bit is set (INTCSR[7]=1) * Messaging Outbound Free queue overflows The Enable Local Bus TEA# bit (INTCSR[0]) can be used to enable or disable TEA# for an abort or parity error. TEA# is a level output that remains asserted as long as the Abort or Parity Error Status bits are set. The PCI 9054 tolerates TEA# input assertion only during PCI Target or DMA transactions. The PCI 9054 does not sample TEA# assertion during PCI Initiator transactions. 6.1.9 All Modes PCI SERR# (PCI NMI) The PCI 9054 asserts an SERR# pulse if parity checking is enabled (PCICR[6]=1) and it detects an address or 1 is written to the Generate PCI Bus SERR# Interrupt bit (INTCSR[2]) with a current value of 0. SERR# output can be enabled or disabled with the SERR# Enable bit (PCICR[8]). 6.1.10 M Mode PCI SERR# The PCI 9054 also asserts SERR# if the Local Bus responds with TEA# to the PCI 9054. The TEA# Input Interrupt Mask bit (LMISC[5]) masks out the SERR# interrupt assertion process. 6.1.13 C and J Modes Local LSERR# (Local NMI) An LSERR# interrupt is asserted if the following conditions occur: * PCI Bus Target Abort bit is set (PCISR[11]=1) or Received Master Abort bit is set (PCISR[13]=1) * Detected Parity Error bit is set (PCISR[15]=1) * PCI Initiator Local Data Parity Check Error Status bit is set (INTCSR[7]=1) * Messaging Outbound Free queue overflows The Enable Local Bus LSERR# bit (INTCSR[0]) can be used to enable or disable LSERR# for an abort or parity error. LSERR# is a level output that remains asserted as long as the Abort or Parity Error Status bits are set. 6.1.11 Local NMI If the Parity Error Response bit is set (PCICR[6]=1), the PCI 9054 sets the Master Data Parity Error Detected bit (PCISR[8]=1) when the following three conditions are met: * The PCI 9054 asserted PERR# or acknowledged PERR# was asserted * The PCI 9054 was the Bus Master for the operation in which the error occurred * The Parity Error Response bit is set (PCICR[6]=1) PCI 9054 Data Book v2.1 6-4 (c) PLX Technology, Inc. All rights reserved. www..com 6.2 USER INPUT AND OUTPUT The PCI 9054 supports user input and output pins, USERi and USERo (PQFP--pins 159-158; PBGA-- pins C7 and A7), respectively. Both are multiplexed with other functional pins. The default PCI 9054 condition are the USERi and USERo functions. USERi is selected when CNTRL[18]=1. USERo is selected when CNTRL[19]=1. User output data can be logged by writing to the General Purpose Output bit (CNTRL[16]). User input data can be read from the General Purpose Input bit (CNTRL[17]). PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 6-5 Section 6--Interrupts, I/O User Input and Output Section 6 PCI Local Interrupts and User I/O www..com www..com 7 7.1 INTELLIGENT I/O (I2O) I2O-COMPATIBLE MESSAGE UNIT FIFOs implemented in Local memory. The Inbound Free List FIFO holds the message frame addresses (MFA) of available message frames in Local memory. The Inbound Post Queue FIFO holds the MFA of all currently posted messages. External PCI agents, through the Inbound Queue Port location in PCI Address space access inbound circular FIFOs. The Inbound Queue Port, when read by an external PCI agent, returns the Inbound Free List FIFO MFA. The external PCI agent places a message frame into the Inbound Post Queue FIFO by writing its MFA to the Inbound Queue Port location. The I2O-compatible Messaging Unit supplies two paths for messages, two inbound FIFOs to receive messages from the primary PCI Bus, and two outbound FIFOs to pass messages to the primary PCI Bus. Refer to I2O Architecture Specification v1.5 for details. Figure 7-1 and Figure 7-2 illustrate I2O architecture. No Hardware Changes Required on the Host Side Host System Memory Message Frames Host Local Bus Host PCI Interface Host CPU Inbound Queue Port PCI Bus Outbound Queue Port 7.1.2 Outbound Messages IOP Must Have CPU * Memory * Messaging * IOP Local Memory Message Queues PCI 9054 IO Messaging 2 Unit Message Frames IOP Local Bus I/O Chip I/O Chip Figure 7-1. Typical I2O Server/Adapter Card Design Outbound messages reside in a pool of message frames (minimum 64-byte frames) allocated in the shared PCI Bus (Host System) memory. The Outbound message queue is comprised of a pair of rotating FIFOs implemented in Local memory. The Outbound Free List FIFO holds the message frame addresses (MFA) of available message frames in system memory. The Outbound Post Queue FIFO holds the MFA of all currently posted messages. External PCI agents, through the Outbound Queue Port location in PCI Address space access outbound circular FIFOs. The Outbound Queue Port, when read by an external PCI agent, returns the Outbound Post Queue FIFO MFA. The External PCI agent places free message frames into the Outbound Free List FIFO by writing the free MFA into the Outbound Queue Port location. Memory for the circular FIFOs themselves must be allocated in Local (IOP) memory. The base address of the queue is contained in the Queue Base Address bits (QBAR[31:20]). Each FIFO entry is a 32-bit data value. Each read and write of the queue must be a single 32-bit access. Circular FIFOs range in size from 4-KB to 64-KB entries. All four FIFOs must be the same size and contiguous. Therefore, the total amount of Local memory needed for circular FIFOs ranges from 64 KB to 1 MB. A FIFO size is specified in the Circular Queue Size bits (MQCR[5:1]). Present Architecture API for I/O Commands OSM (I2O Shell) Messaging Layer I2O Architecture OS-Specific Module (I2O Shell) Hardware Device Module Optional (I2O Shell) DDM Hardware Hardware Figure 7-2. Driver Architecture Compared 7.1.1 Inbound Messages Inbound messages reside in a pool of message frames (minimum 64-byte frames) allocated in the shared Local Bus (IOP) memory. The inbound message queue is comprised of a pair of rotating PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 7-1 Section 7--I2O www..com Section 7 Intelligent I/O (I2O) I2O-Compatible Message Unit The starting address of each FIFO is based on the Queue Base Address and the FIFO Size, as listed in Table 7-1. Table 7-1. Queue Starting Address FIFO Inbound Free List Inbound Post List Outbound Post List Outbound Free List Starting Address QBAR QBAR + (1 * FIFO Size) QBAR + (2 * FIFO Size) QBAR + (3 * FIFO Size) 7.1.3 I2O Pointer Management The FIFOs always reside in shared Local (IOP) memory and are allocated and initialized by the IOP. Before setting the Queue Enable bit (MQCR[0]=1), the Local processor must initialize the following registers, with the initial offset according to the configured FIFO size: * Inbound Post and Free Head Pointer registers (IPHPR) * Inbound Post and Free Tail Pointer registers (IPTPR) * Outbound Post and Free Head Pointer registers (OFHPR) * Outbound Post and Free Tail Pointer registers (OFTPR) The Messaging Unit automatically adds the Queue Base Address to offset in each head and tail pointer register. The software can then enable I2O. After initialization, the Local software should not write to the pointers managed by the MU hardware. Empty flags are set if the queues are disabled (MQCR[0]=0) or head and tail pointers are equal. This occurs independent of how the head and tail pointers are set. An empty flag is cleared, signifying not empty, only if the queues are enabled and pointers become not equal. If an empty flag is cleared and the queues are enabled, the empty flag is set only if the tail pointer is incremented and the head and tail pointers become equal. Full flags are always cleared when the queues are disabled or the head and tail pointers are not equal. A full flag is set when the queues are enabled, the head pointer is incremented, and the head and tail pointers become equal. Each circular FIFO has a head pointer and a tail pointer, which are offsets from the Queue Base Address. Writes to a FIFO occur at the head of the FIFO and reads occur from the tail. Head and tail pointers are incremented by either the Local processor or the MU hardware. The unit that writes to the FIFO also maintains the pointer. Pointers are incremented after a FIFO access. Both pointers wrap around to the first address of the circular FIFO when they reach the FIFO size, so that the head and tail pointers continuously "chase" each other around in the circular FIFO. The MU wraps the pointers automatically for the pointers that it maintains. IOP software must wrap the pointers that it maintains. Whenever they are equal, the FIFO is empty. To prevent overflow conditions, I2O specifies that the number of message frames allocated should be less than or equal to the number of entries in a FIFO. (Refer to Figure 7-3.) Each inbound MFA is specified by I2O as the offset from the start of shared Local (IOP) memory region 0 to the start of the message frame. Each outbound MFA is specified as the offset from Host memory location 0x00000000h to the start of the message frame in shared Host memory. Because the MFA is an actual address, the message frames need not be contiguous. IOP allocates and initializes inbound message frames in shared IOP memory using any suitable memory allocation technique. Host allocates and initializes outbound message frames in shared Host memory using any suitable memory allocation technique. Message frames are a minimum of 64 bytes in length. I2O uses a "push" (write preferred) memory model. That means the IOP writes messages and data to the shared Host memory, and the Host writes messages and data to shared IOP memory. Software should make use of Burst and DMA transfers whenever possible to ensure efficient use of the PCI Bus for message passing. Additional information on message passing implementation may be found in I2O Architecture Specification v1.5. 7.1.4 Inbound Free List FIFO The Local processor allocates inbound message frames in its shared memory and can place the address of a free (available) message frame into the Inbound Free List FIFO by writing its MFA into the PCI 9054 Data Book v2.1 7-2 (c) PLX Technology, Inc. All rights reserved. www..com I2O-Compatible Message Unit Section 7 Intelligent I/O (I2O) FIFO location pointed to by the Queue Base register + Inbound Free Head Pointer register. The Local processor must then increment the Inbound Free Head Pointer register. A PCI Master (Host or another IOP) can obtain the MFA of a free message frame by reading the Inbound Queue Port Address (40h of the first PCI Memory Base Address register). If the FIFO is empty (no free inbound message frames are currently available, head and tail pointers are equal), the MU returns -1 (FFFFFFFFh). If the FIFO is not empty (head and tail pointers are not equal), the MU reads the MFA pointed to by the Queue Base register + Inbound Free Tail Pointer register, returns its value and increments the Inbound Free Tail Pointer register. If the Inbound Free Queue is not empty, and the Inbound Free Queue Prefetch Enable bit is set (QSR[3]=1), the next entry in the FIFO is read from the Local Bus into a prefetch register. The prefetch register then provides the data for the next PCI read from this queue, thus reducing the number of PCI wait states. (Refer to Figure 7-3.) FIFO is empty. The Inbound Post Queue FIFO Interrupt Mask bit (QSR[4]) can mask the interrupt. To prevent racing between the time the PCI Write transaction is received until the data is written in Local memory and the Inbound Post Head Pointer register is incremented, any PCI Target access to the PCI 9054 is issued a Retry. 7.1.6 Outbound Post Queue FIFO Section 7--I2O A Local Master (IOP) can write a message into an available message frame in shared Host memory. It can then post that message by writing the Message Frame Address (MFA) to the Outbound Post Queue FIFO location pointed to by the Queue Base register + Outbound Post Head Pointer register + (2 * FIFO Size). The Local processor should then increment the Outbound Post Head Pointer register. A PCI Master can obtain the MFA of the oldest posted message by reading the Outbound Queue Port Address (44h of the first PCI Memory Base Address register). If the FIFO is empty (no more outbound messages are posted, head and tail pointers are equal), the MU returns -1 (FFFFFFFFh). If the Outbound Post Queue FIFO is not empty (head and tail pointers are not equal), the MU reads the MFA pointed to by the Queue Base register + (2 * FIFO Size) + outbound Post Tail Pointer register, returns its value and increments the Outbound Post Tail Pointer register. The PCI 9054 asserts a PCI Interrupt when the Outbound Post Head Pointer register is not equal to the Outbound Post Tail Pointer register. The Outbound Post Queue FIFO Interrupt bit of the Outbound Post Queue Interrupt Status register (OPQIS) indicates the interrupt status. When the pointers become equal, both the interrupt and the Outbound Post Queue FIFO interrupt bit are automatically cleared. Pointers become equal when a PCI Master (Host or another IOP) reads sufficient FIFO entries to empty the FIFO. The Outbound Post Queue FIFO Interrupt Mask register (OPLFIM) can mask the Interrupt. 7.1.5 Inbound Post Queue FIFO A PCI Master (Host or another IOP) can write a message into an available message frame in the shared Local (IOP) memory. It can then post that message by writing the Message Frame Address (MFA) to the Inbound Queue Port Address, IQP (40h of the first PCI Memory Base Address register). When the port is written, the MU writes the MFA to the Inbound Post Queue FIFO location pointed to by the Queue Base register + FIFO Size + Inbound Post Head Pointer register. After the MU writes the MFA to the Inbound Post Queue FIFO, it increments the Inbound Post Head Pointer register. The Inbound Post Tail Pointer register points to the Inbound Post Queue FIFO location, which holds the MFA of the oldest posted message. The Local processor maintains the tail pointer. After a Local processor reads the oldest MFA, it can remove the MFA from the Inbound Post Queue FIFO by incrementing the Inbound Post Tail Pointer register. The PCI 9054 asserts a Local Interrupt when the Inbound Post Queue FIFO is not empty. The Inbound Post Queue FIFO Interrupt bit in the Queue Status/ Control register (QSR[5]) indicates the interrupt status. The interrupt clears when the Inbound Post Queue PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 7-3 www..com Section 7 Intelligent I/O (I2O) I2O-Compatible Message Unit High Address Local Memory Write External PCI Agent Read Outbound Queue Port Outbound Free List FIFO Incremented by Local Processor Incremented by PCI 9054 Hardware (outbound free list) Head Pointer Tail Pointer Local Processor Read Write Outbound Post List FIFO Incremented by PCI 9054 Hardware Incremented by Local Processor (outbound post list) Outbound Queue Head Pointer Tail Pointer Write External PCI Agent Read Inbound Queue Port Inbound Post List FIFO Incremented by Local Processor Incremented by PCI 9054 Hardware (inbound post list) Head Pointer Tail Pointer Local Processor Read Write Inbound Free List FIFO Incremented by PCI 9054 Hardware Incremented by Local Processor (inbound free list) Inbound Queue Head Pointer Tail Pointer Low Address Local Memory Figure 7-3. Circular FIFO Operation PCI 9054 Data Book v2.1 7-4 (c) PLX Technology, Inc. All rights reserved. www..com I2O-Compatible Message Unit Section 7 Intelligent I/O (I2O) 7.1.7 Outbound Post Queue To reduce read latency, prefetching from the tail of the queue occurs whenever the queue is not empty and the tail pointer is incremented (queue has been read from), or when the queue is empty and the head pointer is incremented (queue has been written to). When the Host CPU reads the Outbound Post Queue, the data is immediately available. equal to the number of entries in a FIFO. The MU also checks for overflows of the Outbound Free List FIFO. When the head pointer is incremented and becomes equal to the tail pointer, the Outbound Free List FIFO is full, and the MU asserts a Local TEA#/LSERR# (NMI) interrupt. The interrupt is recorded in the Queue Status/Control register (QSR). From the time the PCI Write transaction is received until the data is written into Local memory and the Outbound Free Head Pointer register is incremented, any PCI Target access to the PCI 9054 is issued a Retry. 7.1.8 Inbound Free Queue To reduce read latency, prefetching from the tail of the queue occurs whenever the queue is not empty and the tail pointer is incremented (queue has been read from), or when the queue is empty and the head pointer is incremented (queue has been written to). When the Host CPU reads the Inbound Free Queue, the data is immediately available. 7.1.10 I2O Enable Sequence To enable I2O, the Local processor should perform the following: * Initialize Space 1 address and range * Initialize all FIFOs and Message Frame memory * Set the PCI Base Class Code bits (PCICCR[23:16]) to be an I2O device with programming interface 01h * Set the I2O Decode Enable bit (QSR[0]) * Set Local Init Status bit to "done" (LMISC[2]=1) Note: The serial EEPROM must not set the Local Init Status bit so that the PCI 9054 issues retries to all PCI accesses until the Local Init Status bit is set to "done" by the Local processor. 7.1.9 Outbound Free List FIFO The PCI Bus Master (Host or other IOP) allocates outbound message frames in its shared memory. The PCI Bus Master can place the address of a free (available) message frame into the Outbound Free List FIFO by writing a Message Frame Address (MFA) to the Outbound Queue Port Address (44h of the first PCI Memory Base Address register). When the port is written, the MU writes the MFA to the Outbound Free List FIFO location pointed to by the Queue Base register + (3 * FIFO Size) + Outbound Free Head Pointer register. After the MU writes the MFA to the Outbound Free List FIFO, it increments the Outbound Free Head Pointer register. When the IOP needs a free outbound message frame, it must first check whether any free frames are available. If the Outbound Free List FIFO is empty (outbound free head and tail pointers are equal), the IOP must wait for the Host to place additional outbound free message frames in the Outbound Free List FIFO. If the Outbound Free List FIFO is not empty (head and tail pointers are not equal), the IOP can obtain the MFA of the oldest free outbound message frame by reading the location pointed to by the Queue Base register + (3 * FIFO Size) + Outbound Free Tail Pointer register. After the IOP reads the MFA, it must increment the Outbound Free Tail Pointer register. To prevent overflow conditions, I2O specifies the number of message frames allocated should be less than or The I2O Decode Enable bit (QSR[0]) causes remapping of resources for use in I2O mode. When set, all Memory-Mapped Configuration registers (for example, queue ports 40h and 44h) and Space 1 share the PCIBAR0 register. PCI accesses to offset 00h-FFh of PCIBAR0 result in accesses to the PCI 9054 Internal Configuration registers. Accesses above offset FFh of PCIBAR0 result in Local Space accesses, beginning at offset 100h from the Remap PCI Address to Local Address Space 1 into the Local Address Space bit(s) (LAS1BA[31:4]). Therefore, space located at offset 00h-FFh from LAS1BA is not addressable from the PCI Bus using PCIBAR0. Note: Because PCI accesses to offset 00h-FFh of PCIBAR0 result in internal configuration accesses, the Inbound Free MFAs must be greater than FFh. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 7-5 Section 7--I2O www..com Section 7 Intelligent I/O (I2O) I2O-Compatible Message Unit Table 7-2. Circular FIFO Summary FIFO Name Inbound Free List FIFO Inbound Pos List FIFO Outbound Post List FIFO Outbound Free List FIFO PCI Port Inbound Queue Port (Host read) Inbound Queue Port (Host write) Outbound Queue Port (Host read) Outbound Queue Port (Host write) Generate PCI Interrupt No Generate Local Interrupt No Yes, when Port is written No Yes, (TEA#/LSERR#) when FIFO is full Head Pointer Maintained By Local processor Tail Pointer Maintained By MU hardware No Yes, when FIFO is not empty No MU hardware Local processor Local processor MU hardware MU hardware Local processor PCI 9054 Data Book v2.1 7-6 (c) PLX Technology, Inc. All rights reserved. www..com 8 8.1 PCI POWER MANAGEMENT OVERVIEW * B1--Intermediate power management state. Full power with clock frequency, PCI v2.1 compliant. PME Event driven bus activity. Vcc is applied to all devices on the bus, and no transactions are allowed to occur on the bus. * B2--Intermediate power management state. Full power clock frequency stopped, PCI v2.1 compliant (in the low state). PME Event-driven bus activity. Vcc is applied to all devices on the bus; however, the clock is stopped and held in the Low state. * B3 (Off)--Power to the bus is switched off. PME Event-driven bus activity. Vcc is removed from all devices on the PCI Bus. All system PCI Buses have an originating device, which can support one or more power states. In most cases, this creates a bridge (such as a Host-Bus-toPCI-Bus or a PCI-to-PCI bridge). Function States must be at the same or lower energy state than the bus on which they reside. The PCI Bus Power Management Interface Specification provides a standard mechanism for operating systems to control add-in cards for power management. The Specification defines four PCI functional power states--D0, D1, D2, and D3. States D0 and D3 are required, while states D1 and D2 are optional. State D0 represents the highest power consumption and state D3 the least. * D0 (Uninitialized)--Enters this state from Power-On Reset or from state D3hot. Supports PCI Target PCI transactions only. * D0 (Active)--All functions active. * D1--Uses less power than State D0, and more than state D2. Light sleep state. * D2--Uses very little power. The functional states are defined by the allowed activities of the add-in card with the PCI 9054. The function supports PCI Configuration cycles to function if clock is running (Memory, I/O, Bus Mastering, and Interrupts are disabled). It also supports the Wakeup Event from function, but not standard PCI interrupts. * D3hot--Uses lower power than any other state. Supports PCI Configuration cycles to function if clock is running. Supports Wakeup Event from function, but not standard PCI interrupts. When programmed for state D0, an internal soft reset occurs. The PCI Bus drivers must be disabled. PME# context must be retained during this soft reset. * D3cold--No power. Supports Bus reset only. All context is lost in this state. From a power management perspective, the PCI Bus can be characterized at any point in time by one of four power management states--B0, B1, B2, and B3: * B0 (Fully On)--Bus is fully usable with full power and clock frequency, PCI v2.1 compliant. Fully operational bus activity. This is the only Power Management state in which data transactions can occur. 8.1.1 PCI Power Management Functional Description The PCI 9054 passes power management information and has no inherent power-saving feature. The PCI Status register (PCISR) and the New Capability Pointer register (CAP_PTR) indicate whether a new capability (the Power Management function) is available. The New Capability Functions Support bit (PCISR[4]) enables a PCI BIOS to identify a New Capability function support. This bit is executable for writes from the Local Bus, and reads from both the Local and PCI Buses. CAP_PTR provides an offset into PCI Configuration Space, the start location of the first item in a New Capabilities Linked List. The Power Management Capability ID register (PMCAPID) specifies the Power Management Capability ID, 01h, assigned by the PCI SIG. The Power Management Next Capability Pointer register (PMNEXT) points to the first location of the next item in the capabilities linked list. If Power Management is the last item in the list, then this register should be set to 0. The default value for the PCI 9054 is 48h (Hot Swap). For the PCI 9054 to change the power state and assert PME#, the Local Host or PCI Host should set PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 8-1 Section 8--Power Mgmt www..com Section 8 PCI Power Management Overview the PME#_En bit (PMCSR[8]=1). The Local Host then determines to which power state the backplane should change by reading the Power_State bits (PMCSR[1:0]). The Local Host sets up the following: * D2_Support and D1_Support bits (PMC[10:9]) are used by the Local Host to identify power state support * PME#_Support bits (PMC[14:11]) are used by the PCI 9054 to identify the PME# Support correspondent to a specific power state (PMCSR[1:0]) The Local Host then sets the PME#_Status bit (PMCSR[15]=1) and the PCI 9054 asserts PME#. To clear the PME#_Status bit, the PCI Host must write a 1 to the PME# Status bit (PMCSR[15]=1). To disable the PME# Interrupt signal, either Host can write a 0 to the PME#_En bit (PMCSR[8]=0). LINT# output is asserted every time the power state in the PMCSR register changes. Transmission from state 11 (D3hot) to state 00 (D0) causes a soft reset. A soft reset should only be initiated from the PCI Bus because the Local Bus interface is reset during a soft reset. The PCI 9054 issues LRESETo# and resets all its internal registers to their default values. In state D3hot, PCI Memory and I/O accesses are disabled, as well as PCI interrupts, and only configuration is allowed. Before making LINT# output work, set the Power Management Interrupt Enable bit (INTCSR[4]=1), and clear the interrupt by setting the Power Management Interrupt bit (INTCSR[5]=1). The Data_Scale bits (PMCSR[14:13]) indicate the scaling factor to use when interpreting the value of the Power Management Data bits (PMDATA[7:0]). The value and meaning of the bits depend upon the data value specified in the Data_Select bits (PMCSR[12:9]). The Data_Scale bit value is unique for each Data_Select bit. For Data_Select values from 8 to 15, the Data_Scale bits always return a zero (PMCSR[14:13]=0). PMDATA provides operating data, such as power consumed or heat dissipation. 8.1.2 1. 2. 3. System Changes Power Mode Example The Host writes to the PCI 9054 PMCSR register to change the power states. The PCI 9054 sends a local interrupt (LINT# output) to a Local CPU (LCPU). The LCPU has 200 s to read the power management information from the PCI 9054 PMCSR register to implement the power saving function. After the LCPU implements the power saving function, the PCI 9054 disables all PCI Target accesses and PCI Interrupt output (INTA#). In addition, the BIOS disables the PCI 9054 Master Access Enable bit (PCICR[2]). 4. Notes: In Power Saving mode, all PCI and Local Configuration cycles are granted. The PCI 9054 automatically performs a soft reset to a Local Bus on D3-to-D0 transitions. 8.1.3 1. 2. 3. 4. Wake-Up Request Example The add-in card (with a PCI 9054 chip installed) is in a powered-down state. The Local CPU performs a write to the PCI 9054 PMCSR register to request a wake-up procedure. As soon as the request is detected, the PCI 9054 drives PME# out to the PCI Bus. The PCI Host accesses the PCI 9054 PMCSR register to disable the PME# output signal and restores the PCI 9054 to the D0 power state. The PCI 9054 completes the power management task by issuing the Local interrupt (LINT# output) to the Local CPU, indicating that the power mode has changed. 5. PCI 9054 Data Book v2.1 8-2 (c) PLX Technology, Inc. All rights reserved. www..com 9 9.1 COMPACTPCI HOT SWAP HOT SWAP Hot Swap-Friendly silicon includes all the required Capable functions and adds some of the functions in the following list. These functions are possible to add externally to the device. The PCI 9054 has integrated them into the PCI silicon, thus reducing the amount of external circuitry that a user must add. * Incorporates Hot Swap Control/Status register (HS_CSR)--Contained within the configuration space. * Incorporates an Extended Capability Pointer (ECP) mechanism--Software must have a standard method of determining if a specific function is designed in accordance with the specification. The Capabilities Pointer is located within standard CSR space, using a bit in the PCI Status register (offset 04h). The PCI 9054 has additional resources for software control of the ENUM# ejector switch and the blue LED to indicate insertion/removal. The PCI 9054 is a Hot Swap-Friendly PCI silicon device. The PCI 9054 has incorporated all compliant functions defined by the CompactPCI Hot Swap specification. The PCI 9054 incorporates LEDon/ LEDin and ENUM# and Hot Swap Capabilities registers--HS_CNTL, HS_NEXT, and HS_CSR. The PCI 9054 is a CompactPCI Hot Swap-Friendlycompliant device. 9.1.1 Overview Hot Swap is used for CompactPCI applications. Hot Swap functionality allows the orderly insertion and removal of boards without adversely affecting system operation. This is done for repair of faulty boards or system reconfiguration. Additionally, Hot Swap provides programmatic access to Hot Swap services allowing system reconfiguration and fault recovery to occur with no system down time and minimum operator interaction. Control of adapter insertion/ removal logic resides on the individual adapters. The PCI 9054 uses two pins, ENUM# and LEDon/LEDin, to implement the hardware aspects of Hot Swap functionality. The PCI 9054 uses the Hot Swap Capabilities register to implement the software aspects of Hot Swap capabilities. To avoid confusion in the industry, Hot Swap defines three levels of compatibility: * Hot Swap-Capable devices contain the minimum requirements to operate in Hot Swap environment * Hot Swap-Friendly devices contain additional functions to ease the job of the user * Hot Swap-Ready devices contain all the necessary functions for Hot Swap Hot Swap-Capable requirements are mandatory for a device to be used in Hot Swap environment. These requirements are attributes for which a system user must compensate using external circuitry, as follows: * PCI Specification v2.1 compliant * Tolerate Vcc from early power * Tolerate precharge voltage * Limited I/O pin leakage at precharge voltage 9.1.2 The following sections are excerpts from CompactPCI Specification. Refer to the specification for more details. 9.1.2.1 Hardware Connection Control Hardware Control provides a means for the platform to control the hardware connection process. The signals listed in the following sections must be supported on all Hot Swap boards for interoperability. Implementations on different platforms may vary. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 9-1 Section 9--Hot Swap Controlling Connection Processes www..com Section 9 CompactPCI Hot Swap Hot Swap 9.1.2.1.1 Board Slot Control BD_SEL# is one of the shortest pins. It is driven low to enable power-on. For systems not implementing hardware control, it is grounded on the backplane. Systems implementing hardware control radially connect BD_SEL# to a Hot Swap Controller (HSC). The controller terminates the signal with a weak pull-down. The controller can detect board present when the board pull-up overrides the pull-down. HSC can then control the power-on process by driving BD_SEL# low. Platform | Board VIO 9.1.2.1.3 Platform Reset Reset (PCI_RST#), as defined by CompactPCI Specification, is a bused signal on the backplane, driven by the Host. Platforms may implement this signal as a radial signal from the Hot Swap Controller to further control the electrical connection process. To maintain function of the bused signal, platforms that do this must OR the Host reset signal with the slot-specific signal. Locally, boards must not come out of reset until the H1 State is reached (healthy), but they must also honor the backplane reset. The Local board reset (Local_PCI_RST#) must be the logical OR of these two conditions. Local_PCI_RST# is connected to the PCI 9054 RST# input pin. During a BIOS voltage precharge and platform reset, in insertion and extraction procedures, all PCI I/O buffers must be in a High Impedance state. The PCI 9054 supports this condition any time the Host RST# is asserted (PCI v2.1). To protect the Local board components from early power, the PCI 9054 floats the Local Bus I/Os. The TEST pin can be used to perform the High Impedance condition on the Local Bus. Both the RST# and TEST signals can be simultaneously asserted. The TEST signal is de-asserted some time before the Host RST# is de-asserted to ensure the PCI 9054 asserts the LRESETo# signal to complete a reset task of the Local board. Platform | Board PCI_RST# Platform | Board HSC PRESENT BD_SEL# PWR ON ON VIO BD_SEL# ON Power Circuitry Power Circuitry No Hardware Control Hardware Control Figure 9-1. Redirection of BD_SEL# 9.1.2.1.2 Board Healthy A second radial signal is used to acknowledge board health. It signals that a board is suitable to be released from reset and allowed onto the PCI Bus. Minimally, this signal must be connected to the board's power controller "power good" status line. Use of HEALTHY# can be expanded for applications requiring additional conditions to be met for the board to be considered healthy. On platforms that do not use Hardware Connection Control, this line is not monitored. Platforms implementing this signaling route these signals radially to a Hot Swap Controller. Platform | Board HSC Platform | Board VIO Platform | Board HOST HSC PCI_RST# LOCAL_ PCI_RST# HOST LOCAL_ PCI_RST# HEALTHY # HEALTHY # No Hardware Control Hardware Connection Control Figure 9-3. PCI Reset NC Power Circuitry HEALTHY HLTY Power Circuitry No Hardware Control Hardware Control Figure 9-2. Board Healthy PCI 9054 Data Book v2.1 9-2 (c) PLX Technology, Inc. All rights reserved. www..com Hot Swap Section 9 CompactPCI Hot Swap 9.1.2.2 Software Connection Control Software Connection Control provides a means to control the Software Connection Process. Resources on the hot swap board facilitate software Connection Control. Access to these resources occurs by way of the bus, using PCI protocol transfers (in-band). These resources consist of four elements: * ENUM# driven active indicates the need to change the state of the Hot Swap board * A switch, tied to the ejector, indicates the intent to remove a board * LED indicates the status of the software connection process * Control/Status register allows the software to interact with these resources an output, it drives the external LED. The LED state is driven from the LED Software On/Off Switch bit (HS_CSR[3]). When used as an input, it acknowledges the state of the ejector handle. With the implementation of TDM, this pin is usually driving the LED. A small portion of time is dedicated to acknowledging ejector status. 9.1.2.2.2 ENUM# ENUM# is provided to notify the Host CPU that a board has been freshly inserted or is about to be removed. This signal informs the CPU that configuration of the system has changed. The CPU then performs any necessary maintenance such as installing a device driver upon board insertion, or quiescing a device driver prior to board extraction. ENUM# is an open collector bused signal with a pull-up on the Host. It may drive an interrupt (preferred) or be polled by the system software at regular intervals. The CompactPCI Hot-Plug System Driver on the system Host manages the ENUM# sensing. Full Hot Swap Boards assert ENUM# until serviced by the Hot-Plug system driver. Regardless of switch status, when a board is inserted into the system and reset is complete, de-asserted, the PCI 9054 defaults the ENUM# Status Indicator for Board Insertion bit (HS_CSR[7]) to 1, causing the assertion of the ENUM# interrupt on the PCI Bus. Once the Host CPU has installed the proper drivers, it can logically include this board by clearing the interrupt. When a board is about to be removed, the PCI 9054 acknowledges the ejector switch is closed (ejector open), asserts ENUM# interrupt and sets the ENUM# Status Indicator for Board Removal bit (HS_CSR[6]). The Host then logically removes the board and turns on the LED. The operator can then remove the board completely. 9.1.2.2.1 Ejector Switch and Blue LED A microswitch (switch), located in the board-ejector mechanism of the Hot Swap CompactPCI board, is used to signal the impending removal of a board. This signal asserts ENUM#. The operator normally activates the switch, waits for the LED illumination to indicate it is okay to remove the board, and then removes the board. The PCI 9054 implements control logic for both the microswitch and the Blue LED in one pin (LEDon/LEDin). When the ejector is opened or closed, the switch bounces for a time. The PCI 9054 uses internal debounce circuitry to clean the signal before the remainder of Hot Swap logic acknowledges it. The state of the switch is acknowledged six times, at 1 ms intervals, before it is assumed closed or open. The Blue "Status" LED, located on the front of the Hot Swap CompactPCI board, is illuminated when it is permissible to remove a board. The hardware connection layer provides protection for the system during all insertions and extractions. This LED indicates the system software is in a state that tolerates board extraction. Upon insertion, the LED is automatically illuminated by the hardware until the hardware connection process completes. The LED remains OFF until the software uses it to indicate extraction is once again permitted. The PCI 9054 uses a tri-state I/O pin to drive the external LED. This pin is Time-Division Multiplexed (TDM) for input and output functionality. When used as PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 9.1.2.2.3 Hot Swap Control/Status Register (HS_CSR) The PCI 9054 supports Hot Swap directly, as a control/status register is provided in Configuration space. This register is accessed through the PCI Extended Capabilities Pointer (ECP) mechanism. The Hot Swap Control/Status register (HS_CSR) provides status read-back for the Hot-Plug System Driver to determine which board is driving ENUM#. This register is also used to control the Hot Swap 9-3 Section 9--Hot Swap www..com Section 9 CompactPCI Hot Swap Hot Swap Status LED on the front panel of the board, and to de-assert ENUM#. The PCI 9054 Hot Swap register (HS_CSR) is accessible for writes from the Local Bus. When a Local CPU is accessing the Hot Swap register (HS_CSR) from the Local Bus, it must take care to not write into the ENUM# status bits. Otherwise, the value might be overwritten prior to the PCI Hot Swap software acknowledging it. Table 9-1. Hot Swap Control Bit 23 22 21 20 19 18 17 16 Description ENUM# status--Insertion (1 = board is inserted). ENUM# status--Removal (1 = board is being removed). Not used. Not used. LED state (1 = LED on, 0 = LED off). Not used. ENUM# interrupt enable (1 = de-assert, 0 = enable interrupt). Not used. 9.1.2.2.4 Hot Swap Capabilities Register Bit Definition 31 24 23 Control 16 15 Next_Cap Pointer 8 7 0 Reserved Hot Swap ID Figure 9-4. Hot Swap Capabilities Register Bit Definition Hot Swap ID. Bits [7:0]. These bits are set to a default value of 0x06. Next_Cap Pointer. Bits [15:8]. These bits either point to the next New Capability structure, or are set to 0 if this is the last capability in the structure. Control. Bits [23:16]. This eight-bit control register is defined in the following table. PCI 9054 Data Book v2.1 9-4 (c) PLX Technology, Inc. All rights reserved. www..com 10 10.1 PCI VITAL PRODUCT DATA (VPD) OVERVIEW F. Bit 31. This bit sets a flag to indicate when a serial EEPROM data operation is complete. For Write cycles, the four bytes of data are first written into the VPD Data bits, after which the VPD Address is written at the same time the F flag is set to 1. The F flag clears when the serial EEPROM Data transfer completes. For Read cycles, the VPD Address is written at the same time the F flag is cleared to 0. The F flag is set when four bytes of data are read from the serial EEPROM. VPD Data. Bits [31:0]. The VPDDATA register is not a pure read/write register. Data read into the register depends upon the last Read operation performed in VPDDAD[15]. VPD data is written or read through this register. The least-significant byte corresponds to the VPD byte at the address specified by the VPD Address register. Four bytes are always transferred between the register and the serial EEPROM. 31 F 30 16 15 8 7 VPD ID (0x03) 0 The Vital Product Data (VPD) function in PCI Specification v2.2 defines a new location and access method. It also defines the Read Only and Read/Write bits. Currently Device ID, Vendor ID, Revision ID, Class Code, Subsystem ID, and Subsystem Vendor ID are required in the Configuration Space Header and are required for basic identification of the device and device configuration. Though this information allows a device to be configured, it is not sufficient to allow a device to be uniquely identified. With the addition of VPD, optional information is provided that allows a device to be uniquely identified and tracked. These additional bits enable current and/or future support tools and reduces the total cost of ownership of PCs and systems. This provides an alternate access method other than Expansion ROM for VPD. VPD is stored in an external serial EEPROM, which is accessed using the Configuration Space New Capabilities function. The VPD registers--PVPDCNTL, PVPD_NEXT, PVPDAD, and PVPDATA--are not accessible for reads from the Local Bus. It is recommended that the VPD function be exercised only from the PCI Bus. VPD Address Next_Cap Pointer (0X00) VPD Data Figure 10-1. VPD Capabilities Register 10.1.1 VPD Capabilities Register VPD ID. Bits [7:0]. The PCI SIG assigns these bits a value of 03h by. The VPD ID is hardcoded. Next_Cap Pointer. Bits [15:8]. These bits either point to the next New Capability structure, or are set to 0 if this is the last capability in the structure. The PCI 9054 defaults to 0x00. This value can be overwritten from the Local Bus. VPD Address. Bits [24:16]. These bits specify the byte address of the VPD to be accessed. All accesses are 32-bits wide; bits [17:16] must be 0, with the maximum serial EEPROM size being 4K bits. Bits [30:25] are ignored. 10.1.2 VPD Serial EEPROM Partitioning To support VPD, the serial EEPROM is partitioned into read only and read/write sections. 10.1.3 Sequential Read Only The first 1456 bits, 182 bytes of the serial EEPROM contain read-only information. The read-only portion of the serial EEPROM is loaded into the PCI 9054, using a sequential Read command to serial EEPROM and occurs once after power-on. Section 10--VPD 10-1 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. www..com Section 10 PCI Vital Product Data (VPD) Overview 10.1.4 Random Read and Write The PCI 9054 can read and write the read/write portion of serial EEPROM. The Serial EEPROM Starting at Lword Boundary for VPD Accesses bits (PROT_AREA[6:0]) designates this portion. This register is loaded upon power-on and can be written with a desired value starting at location 0. This provides the capability of writing the entire serial EEPROM. Writes to serial EEPROM are comprised of the following three commands: * Write Enable * Write Enable, followed by Write data * Write Disable This is done to ensure against accidental writes to the serial EEPROM. Random cycles allow VPD information to be written and read at any time. To perform a simple VPD write to the serial EEPROM, the following steps are necessary: 1. Change the write-protected serial EEPROM address in PROT_AREA[6:0] to the desired address. 0x0000000 makes the serial EEPROM removable from the beginning. Write desired data into the VPDDATA register. Write destination serial EEPROM address and flag of operation, value of 1. Probe a flag of operation until it changes to a 0 to ensure the write completes. To perform a simple VPD read from serial EEPROM, the following steps are necessary: 1. 2. 3. Write a destination serial EEPROM address and flag of operation, value of 0. Probe a flag of operation until it changes to a 1 to ensure the Read data is available. Read back the VPDDATA register to see the requested data. 2. 3. 4. PCI 9054 Data Book v2.1 10-2 (c) PLX Technology, Inc. All rights reserved. www..com 11 11.1 REGISTERS NEW REGISTER DEFINITIONS SUMMARY This section summarizes the new registers, as compared to the PCI 9080. Refer to the following sections for a full explanation of each register. Table 11-1. New Registers Definitions Summary (As Compared to the PCI 9080) PCI Offset Local Offset Register Bits Description WAIT# enable. In M mode, the bit lets WAIT# be rerouted to BIGEND#. In C and J modes, the bit has no effect. When set to 1, WAIT# function is selected. When set to 0, BIGEND# input function is selected. Write accessible Address Pointer in the serial EEPROM device for VPD support. I/O Base Address Register enable. I/O Base Address Register shift. Local Initialization Done. Serial EEPROM or Local Host sets bit. M-mode related. BDIP# input enabled during PCI Initiator accesses. M-mode related. Deferred PCI Initiator read. M-mode related. TEA# mask interrupt. M-mode related. PCI Initiator Write FIFO full RETRY# enable. Serial EEPROM starting at the Lword boundary for VPD accesses. Provides offset into PCI Configuration space for the location of the first item in the New Capability Linked List. Provides Power Management ID, Power Management Next Capability Pointer, and Power Management Capabilities. Provides Power Management Status, PMCSR Bridge Support Extensions, and Power Management Data. Hot Swap Control, Hot Swap Next Capability Pointer, and Hot Swap Control/Status Register. VPD ID, VPD Next Capability Pointer, and VPD Address Pointer. VPD Data. Local Data Parity Error Check. Bit 7 is the Parity Error Check Status bit. Bit 6 is the Enable bit. Bit 18 is a select bit between USERi and LLOCKi#. Bit 19 is a select bit between USERo and LLOCKo#. PCI Initiator PCI Dual Address Cycle. When set to 0, the PCI 9054 performs a 32-bit PCI Address cycle. The PCI 9054 does not support Demand Mode DMA by way of Channel 1. Reserved. DMA Channel 0 PCI Dual Address Cycle. When set to 0, the PCI 9054 performs a 32-bit PCI Address cycle. DMA Channel 1 PCI Dual Address Cycle. When set to 0, the PCI 9054 performs a 32-bit PCI Address cycle. 08h/ACh 88h/12Ch Mode/DMA Arbitration 31 22:16 0 1 2 3 4 5 6 0Dh 8Dh Local Miscellaneous Control 0Eh 8Eh Serial EEPROM Write-Protected Address Boundary New Capability Pointer Power Management Power Management CompactPCI Hot Swap PCI Vital Product Data PCI Vital Product Data Interrupt Control/Status USER I/O Control PCI Initiator PCI Dual Address Cycle DMA Channel 1 Mode DMA Channel 0 PCI Dual Address Cycle DMA Channel 1 PCI Dual Address Cycle 6:0 34h 40h 44h 48h 4Ch 50h 68h 6Ch 17Ch 94h B4h B8h 34h 180h 184h 188h 18Ch 190h E8h ECh FCh 114h 134h 138h 7:0 30:0 31:0 31:0 31:0 31:0 7:6 19:18 31:0 12 31:0 31:0 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-1 Section 11--Registers www..com Section 11 Registers Register Address Mapping 11.2 REGISTER ADDRESS MAPPING 11.2.1 PCI Configuration Registers Table 11-2. PCI Configuration Registers Local Access (Offset from Chip Select Addresss 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 180h Max_Lat BIST To ensure software compatibility with other versions of the PCI 9054 family and to ensure compatibility with future enhancements, write 0 to all unused bits. PCI Writable N Y N Y [7:0] Y Y Y Y Y Y N N Y Next_Cap Pointer Y [7:0] N Interrupt Pin Next_Cap Pointer Interrupt Line Capability ID Y [7:0] Y [31:8] Y [15, 12:8, 1:0] Y [23:16], Local [15:0] Y [31:16], Local [15:8] Y Serial EEPROM Writable Y N Y [31:8] N N N N N N N N Y N N N Y [15:8] N PCI Configuration Register Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 31 30 24 Status 23 16 15 8 7 0 Device ID Vendor ID Command Class Code Header Type PCI Bus Latency Timer Revision ID Cache Line Size PCI Base Address 0; used for Memory-Mapped Configuration Registers (PCIBAR0) PCI Base Address 1; used for I/O-Mapped Configuration Registers (PCIBAR1) PCI Base Address 2; used for Local Address Space 0 (PCIBAR2) PCI Base Address 3; used for Local Address Space 1 (PCIBAR3) PCI Base Address 4; used for Local Address Space 2 (PCIBAR4) PCI Base Address 5; used for Local Address Space 3 (PCIBAR5) Cardbus CIS Pointer (Not supported) Subsystem ID Subsystem Vendor ID PCI Base Address for Local Expansion ROM Reserved Reserved Min_Gnt Power Management Capabilities PMCSR Bridge Support Extensions Control/Status Register 44h 184h Data Power Management Control/Status Register N 48h 188h Reserved Next_Cap Pointer Next_Cap Pointer Capability ID Y [15:0] 4Ch 50h Note: 18Ch 190h F VPD Address VPD Data Capability ID N N Refer to PCI Specification v2.1 for definitions of these registers. PCI 9054 Data Book v2.1 11-2 (c) PLX Technology, Inc. All rights reserved. www..com 11.2.2 Local Configuration Registers Table 11-3. Local Configuration Registers Local Access (Offset from Chip Select Address 80h 84h 88h To ensure software compatibility with other versions of the PCI 9054 family and to ensure compatibility with future enhancements, write 0 to all unused bits. PCI/Local Writable Y Y Y Big/Little Endian Descriptor Serial EEPROM Writable Y Y Y PCI (Offset from Base Address) 00h 04h 08h 31 24 23 16 15 8 7 0 Range for PCI-to-Local Address Space 0 Local Base Address (Remap) for PCI-to-Local Address Space 0 Mode/DMA Arbitration Serial EEPROM Write-Protected Address Boundary Local Miscellaneous Control 0Ch 8Ch Reserved Y Y 10h 14h 18h 1Ch 20h 24h 28h 2Ch F0h F4h F8h FCh 90h 94h 98h 9Ch A0h A4h A8h ACh 170h 174h 178h 17Ch Range for PCI-to-Local Expansion ROM Local Base Address (Remap) for PCI-to-Local Expansion ROM and BREQo Control Local Bus Region Descriptors (Space 0 and Expansion ROM) for PCI-to-Local Accesses Range for PCI Initiator-to-PCI Local Base Address for PCI Initiator-to-PCI Memory Local Base Address for PCI Initiator-to-PCI I/O Configuration PCI Base Address (Remap) for PCI Initiator-to-PCI PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration Range for PCI-to-Local Address Space 1 Local Base Address (Remap) for PCI-to-Local Address Space 1 Local Bus Region Descriptor (Space 1) for PCI-to-Local Accesses PCI Base Dual Address Cycle (Remap) for PCI Initiator-to-PCI (Upper 32 bits) Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-3 Section 11--Registers Register Address Mapping Section 11 Registers www..com Section 11 Registers Register Address Mapping 11.2.3 Runtime Registers Table 11-4. Runtime Registers Local Access (Offset from Chip Select Address) C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h ECh F0h F4h C0h C4h To ensure software compatibility with other versions of the PCI 9054 family and to ensure compatibility with future enhancements, write 0 to all unused bits. Serial EEPROM Writable Y Y N N N N N N N N N N N N N N PCI (Offset from Base Address) 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 31 16 15 0 PCI/Local Writable Y Y Y Y Y Y Y Y Y Y Y Y N N Y Y Mailbox Register 0 (refer to Note) Mailbox Register 1 (refer to Note) Mailbox Register 2 Mailbox Register 3 Mailbox Register 4 Mailbox Register 5 Mailbox Register 6 Mailbox Register 7 PCI-to-Local Doorbell Register Local-to-PCI Doorbell Register Interrupt Control/Status Serial EEPROM Control, PCI Command Codes, User I/O Control, and Init Control Device ID Unused Vendor ID Revision ID Mailbox Register (refer to Note) Mailbox Register (refer to Note) Note: Mailbox registers 0 and 1 are always accessible at addresses 78h/C0h and 7Ch/C4. When the I2O function is disabled (QSR[0]=0), Mailbox registers 0 and 1 are also accessible at PCI addresses 40h and 44h for PCI 9060 compatibility. When the I2O function is enabled, the Inbound and Outbound Queue pointers are accessed at addresses 40h and 44h, replacing mailbox registers in PCI Address space. PCI 9054 Data Book v2.1 11-4 (c) PLX Technology, Inc. All rights reserved. www..com 11.2.4 DMA Registers Table 11-5. DMA Registers Local Access (Offset from Chip Select Address) 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h 12Ch 130h 134h 138h To ensure software compatibility with other versions of the PCI 9054 family and to ensure compatibility with future enhancements, write 0 to all unused bits. Serial EEPROM Writable N N N N N N N N N N N N N N N PCI (Offset from Base Address) 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h 31 16 15 8 7 0 PCI/Local Writable Y Y Y Y Y Y Y Y Y Y DMA Channel 0 Mode DMA Channel 0 PCI Address DMA Channel 0 Local Address DMA Channel 0 Transfer Byte Count DMA Channel 0 Descriptor Pointer DMA Channel 1 Mode DMA Channel 1 PCI Address DMA Channel 1 Local Address DMA Channel 1 Transfer Byte Count DMA Channel 1 Descriptor Pointer Reserved DMA Channel 1 Command/ Status Mode/DMA Arbitration DMA Threshold DMA Channel 0 PCI Dual Address Cycle (Upper 32 bits) DMA Channel 1 PCI Dual Address Cycle (Upper 32 bits) DMA Channel 0 Command/ Status Y Y Y Y Y PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-5 Section 11--Registers Register Address Mapping Section 11 Registers www..com Section 11 Registers Register Address Mapping 11.2.5 Messaging Queue Registers Table 11-6. Messaging Queue Registers Local Access (Offset from Chip Select Address) B0h B4h -- -- 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h 168h To ensure software compatibility with other versions of the PCI 9054 family and to ensure compatibility with future enhancements, write 0 to all unused bits. Serial EEPROM Writable N N N N N N N N N N N N N N N PCI (Offset from Base Address) 30h 34h 40h 44h C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h 31 Outbound Post Queue Interrupt Status Outbound Post Queue Interrupt Mask Inbound Queue Port Outbound Queue Port Messaging Unit Configuration Queue Base Address Inbound Free Head Pointer Inbound Free Tail Pointer Inbound Post Head Pointer Inbound Post Tail Pointer Outbound Free Head Pointer Outbound Free Tail Pointer Outbound Post Head Pointer Outbound Post Tail Pointer Queue Status/Control 0 PCI/Local Writable N Y PCI PCI Y Y Y Y Y Y Y Y Y Y Y Notes: When I2O messaging is enabled (QSR[0]= 1), the PCI Master (Host or another IOP) uses the Inbound Queue Port to read Message Frame Addresses (MFAs) from the Inbound Free List FIFO and to write MFAs to the Inbound Post Queue FIFO. The Outbound Queue Port reads MFAs from the Outbound Post Queue FIFO and writes MFAs to the Outbound Free List FIFO. Each Inbound MFA is specified by I2O as an offset from the PCI Base Address 0 (programmed in PCIBAR0) to the start of the message frame. This means that all inbound message frames should reside in PCI Base Address 0 Memory space. Each Outbound MFA is specified by I2O as an offset from system address 0x00000000h. Outbound MFA is a physical 32-bit address of the frame in shared PCI system memory. The Inbound and Outbound Queues may reside in Local Address Space 0 or 1 by programming QSR. The queues need not be in shared memory. PCI 9054 Data Book v2.1 11-6 (c) PLX Technology, Inc. All rights reserved. www..com 11.3 PCI CONFIGURATION REGISTERS All registers may be written to or read from in Byte, Word, or Lword accesses. Register 11-1. (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Bit 15:0 Description Vendor ID. Identifies manufacturer of device. Defaults to the PCI SIG-issued Vendor ID of PLX (10B5h) if blank or if no serial EEPROM is present. Device ID. Identifies particular device. Defaults to PLX part number for PCI interface chip (9054h) if blank or no serial EEPROM is present. Read Yes Write Local/ Serial EEPROM Local/ Serial EEPROM Value after Reset 10B5h or 0 9054h or 0 31:16 Yes Register 11-2. (PCICR; PCI:04h, LOC:04h) PCI Command Bit 0 Description I/O Space. Writing a 1 allows the device to respond to I/O space accesses. Writing a 0 disables the device from responding to I/O space accesses. Memory Space. Writing a 1 allows the device to respond to Memory Space accesses. Writing a 0 disables the device from responding to Memory Space accesses. Master Enable. Writing a 1 allows device to behave as a Bus Master. Writing a 0 disables device from generating Bus Master accesses. Special Cycle. Not supported. Memory Write and Invalidate Enable. Writing a 1 enables the Memory Write and Invalidate mode for PCI Initiator and DMA. (Refer to the DMA Mode register(s), DMAMODE0[13] and/or DMAMODE1[13].) VGA Palette Snoop. Not supported. Parity Error Response. Writing a 0 indicates parity error is ignored and the operation continues. Writing a 1 indicates parity checking is enabled. Wait Cycle Control. Controls whether a device does address/data stepping. Writing a 0 indicates the device never does stepping. Writing a 1 indicates the device always does stepping. Note: Hardcoded to 0. SERR# Enable. Writing a 1 enables SERR# driver. Writing a 0 disables SERR# driver. Fast Back-to-Back Enable. Indicates what type of fast back-to-back transfers a Master can perform on the bus. Writing a 1 indicates fast back-to-back transfers can occur to any agent on the bus. Writing a 0 indicates fast back-toback transfers can only occur to the same agent as in the previous cycle. Note: Hardcoded to 0. Reserved. Read Yes Write Yes Value after Reset 0 1 Yes Yes 0 2 3 4 5 6 Yes Yes Yes Yes Yes Yes No Yes No Yes 0 0 0 0 0 7 Yes No 0 8 Yes Yes 0 9 Yes No 0 15:10 Yes No 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-7 Section 11--Registers PCI Configuration Registers Section 11 Registers www..com Section 11 Registers PCI Configuration Registers Register 11-3. (PCISR; PCI:06h, LOC:06h) PCI Status Bit 3:0 Reserved. New Capability Functions Support. Writing a 1 supports New Capabilities Functions. If enabled, the first New Capability Function ID is located at PCI Configuration offset [40h]. Can be written only from the Local Bus. Read-only from the PCI Bus. Reserved. User Definable Functions. If set to 1, this device supports user definable functions. Can be written only from the Local Bus. Read-only from the PCI Bus. Fast Back-to-Back Capable. Writing a 1 indicates an adapter can accept fast back-to-back transactions. Note: Hardcoded to 1. Master Data Parity Error Detected. Set to 1 when three conditions are met: 1) PCI 9054 asserted PERR# or acknowledged PERR# asserted; 2) PCI 9054 was Bus Master for operation in which error occurred; 3) Parity Error Response bit is set (PCICR[6]=1). Writing a 1 clears this bit to 0. DEVSEL# Timing. Indicates timing for DEVSEL# assertion. Writing a 01 sets this bit to medium. Note: Hardcoded to 01. 11 12 13 14 Target Abort. When set to 1, indicates the PCI 9054 has signaled a Target abort. Writing a 1 clears this bit to 0. Received Target Abort. When set to 1, indicates the PCI 9054 has received a Target Abort signal. Writing a 1 clears this bit to 0. Received Master Abort. When set to 1, indicates the PCI 9054 has received a Master Abort signal. Writing a 1 clears this bit to 0. Signaled System Error. When set to 1, indicates the PCI 9054 has reported a system error on SERR#. Writing a 1 clears this bit to 0. Detected Parity Error. When set to 1, indicates the PCI 9054 has detected a PCI Bus parity error, even if parity error handling is disabled (the Parity Error Response bit in the Command register is clear). One of three conditions can cause this bit to be set: 1) PCI 9054 detected parity error during PCI Address phase; 2) PCI 9054 detected data parity error when it was the Target of a write; 3) PCI 9054 detected data parity error when performing Master Read operation. Writing a 1 clears this bit to 0. Yes Yes Yes Yes Yes/Clr Yes/Clr Yes/Clr Yes/Clr 0 0 0 0 Description Read Yes Write No Value after Reset 0h 4 Yes Local 1 5 6 Yes Yes No Local 0 0 7 Yes No 1 8 Yes Yes/Clr 0 10:9 Yes No 01 15 Yes Yes/Clr 0 Register 11-4. (PCIREV; PCI:08h, LOC:08h) PCI Revision ID Bit 7:0 Description Revision ID. Silicon revision of the PCI 9054. Read Yes Write Local/ Serial EEPROM Value after Reset Current Rev # PCI 9054 Data Book v2.1 11-8 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-5. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Bit 7:0 Description Register Level Programming Interface. None defined. Read Yes Write Local/ Serial EEPROM Local/ Serial EEPROM Local/ Serial EEPROM Value after Reset 0h 15:8 Subclass Code (Other Bridge Device). Yes 80h 23:16 Base Class Code (Bridge Device). Yes 06h Register 11-6. (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Bit 7:0 Description System Cache Line Size. Specified in units of 32-bit words (8 or 16 Lwords). If a size other than 8 or 16 is specified, the PCI 9054 performs Write transfers rather than Memory Write and Invalidate transfers. Read Yes Write Yes Value after Reset 0h Register 11-7. (PCILTR; PCI:0Dh, LOC:0Dh) PCI Bus Latency Timer Bit 7:0 Description PCI Bus Latency Timer. Specifies amount of time (in units of PCI Bus clocks) the PCI 9054, as a Bus Master, can burst data on the PCI Bus. Read Yes Write Yes Value after Reset 0h Register 11-8. (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Bit 6:0 Description Configuration Layout Type. Specifies layout of bits 10h through 3Fh in configuration space. Only one encoding, 0h, is defined. All other encodings are reserved. Header Type. Writing a 1 indicates multiple functions. Writing a 0 indicates single function. Read Yes Write Local Value after Reset 0h 7 Yes Local 0 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-9 Section 11--Registers PCI Configuration Registers Section 11 Registers www..com Section 11 Registers PCI Configuration Registers Register 11-9. (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Bit 3:0 5:4 Description BIST Pass/Fail. Writing 0h indicates a device passed its test. Non-0h values indicate a device failed its test. Device-specific failure codes can be encoded in a non-0h value. Reserved. PCI BIST Interrupt Enable. The PCI Bus writes 1 to enable BIST. Generates an interrupt to the Local Bus. The Local Bus resets this bit when BIST is complete. The software should fail device if BIST is not complete after two seconds. Refer to the Runtime registers for Interrupt Control/Status. BIST Support. Returns 1 if device supports BIST. Returns 0 if device is not BIST-compatible. Read Yes Yes Write Local No Value after Reset 0h 00 6 Yes Yes 0 7 Yes Local 0 Register 11-10. (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to Local, Runtime, and DMA Bit 0 Description Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. Note: Hardcoded to 0. Register Location. Values: 00--Locate anywhere in 32-bit Memory Address space 01--Locate below 1-MB Memory Address space 10--Locate anywhere in 64-bit Memory Address space 11--Reserved Note: Hardcoded to 00. Prefetchable. Writing a 1 indicates there are no side effects on reads. Does not affect operation of the PCI 9054. Note: Hardcoded to 0. Memory Base Address. Memory base address for access to Local, Runtime, and DMA registers (requires 256 bytes). Note: Hardcoded to 0h. Memory Base Address. Memory base address for access to Local, Runtime, and DMA registers. Read Yes Write No Value after Reset 0 2:1 Yes No 00 3 Yes No 0 7:4 Yes No 0h 31:8 Yes Yes 0h Note: For I2O, Inbound message frame pool must reside in address space pointed to by PCIBAR0. Message Frame Address (MFA) is defined by I2O as offset from this base address to start of message frame. PCI 9054 Data Book v2.1 11-10 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-11. (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local, Runtime, and DMA Bit 0 1 7:2 Description Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. Note: Hardcoded to 1. Reserved. I/O Base Address. Base Address for I/O access to Local, Runtime, and DMA registers (requires 256 bytes). Note: Hardcoded to 0h. I/O Base Address. Base Address for I/O access to Local, Runtime, and DMA registers. PCIBAR1 can be enabled or disabled by setting or clearing the Base Address Register 1 Enable bit (LMISC[0]). Read Yes Yes Yes Write No No No Value after Reset 1 0 0h 31:8 Yes Yes 0h Register 11-12. (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to Local Address Space 0 Bit 0 Description Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. (Specified in LAS0RR register.) Register Location (If Memory Space). Values: 00--Locate anywhere in 32-bit Memory Address space 01--Locate below 1-MB Memory Address space 10--Locate anywhere in 64-bit Memory Address space 11--Reserved (Specified in LAS0RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address. Prefetchable (If Memory Space). Writing a 1 indicates there are no side effects on reads. Reflects value of LAS0RR[3] and provides only status to the system. Does not affect operation of the PCI 9054. The associated Bus Region Descriptor register controls prefetching functions of this address space. (Specified in LAS0RR register.) If I/O Space, bit 3 is included in the base address. Memory Base Address. Memory base address for access to Local Address Space 0. PCIBAR2 can be enabled or disabled by setting or clearing the Space 0 Enable bit (LAS0BA[0]). Read Yes Write No Value after Reset 0 Mem: No Yes I/O: bit 1 no, bit 2 yes 00 2:1 3 Yes Mem: No I/O: Yes 0 31:4 Yes Yes 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-11 Section 11--Registers PCI Configuration Registers Section 11 Registers www..com Section 11 Registers PCI Configuration Registers Register 11-13. (PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses to Local Address Space 1 Bit 0 Description Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. (Specified in LAS1RR register.) Register Location. Values: 00--Locate anywhere in 32-bit Memory Address space 01--Locate below 1-MB Memory Address space 10--Locate anywhere in 64-bit Memory Address space 11--Reserved (Specified in LAS1RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address. Prefetchable (If Memory Space). Writing a 1 indicates there are no side effects on reads. Reflects value of LAS1RR[3] and only provides status to the system. Does not affect operation of the PCI 9054. The associated Bus Region Descriptor register controls prefetching functions of this address space. (Specified in LAS1RR register.) If I/O Space, bit 3 is included in base address. Memory Base Address. Memory base address for access to Local Address Space 1. PCIBAR3 can be enabled or disabled by setting or clearing the Space 1 Enable bit (LAS1BA[0]). If QSR[0]=1, PCIBAR3 returns 0h. Read Yes Write No Value after Reset 0 Mem: No Yes I/O: Bit 1 No, Bit 2 Yes 00 2:1 3 Yes Mem: No I/O: Yes 0 31:4 Yes Yes 0h Register 11-14. (PCIBAR4; PCI:20h, LOC:20h) PCI Base Address Bit 31:0 Reserved. Description Read Yes Write No Value after Reset 0h Register 11-15. (PCIBAR5; PCI:24h, LOC:24h) PCI Base Address Bit 31:0 Reserved. Description Read Yes Write No Value after Reset 0h Register 11-16. (PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer Bit 31:0 Description Cardbus Information Structure Pointer for PCMCIA. Not supported. Read Yes Write No Value after Reset 0h Register 11-17. (PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID Bit 15:0 Description Subsystem Vendor ID (unique add-in board Vendor ID). Read Yes Write Local/ Serial EEPROM Value after Reset 10B5h PCI 9054 Data Book v2.1 11-12 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-18. (PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID Bit 15:0 Description Subsystem ID (unique add-in board Device ID). Read Yes Write Local/ Serial EEPROM Value after Reset 9054h Register 11-19. (PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base Bit Description Address Decode Enable. Writing a 1 indicates a device accepts accesses to the Expansion ROM address. Writing a 0 indicates a device does not accept accesses to Expansion ROM space. Should be set to 0 if there is no Expansion ROM. Works in conjunction with EROMRR[0]. Reserved. Expansion ROM Base Address (upper 21 bits). Read Write Value after Reset 0 Yes Yes 0 10:1 31:11 Yes Yes No Yes 0h 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-13 Section 11--Registers PCI Configuration Registers Section 11 Registers www..com Section 11 Registers PCI Configuration Registers Register 11-20. (CAP_PTR; PCI:34h, LOC:34h) New Capability Pointer Bit 7:0 31:8 Description New Capability Pointer. Offset into PCI Configuration Space for the location of the first item in the New Capabilities Linked List. Reserved. Read Yes Yes Write Local No Value after Reset 40h 0h Register 11-21. (PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line Bit 7:0 Description Interrupt Line Routing Value. Value indicates which input of the system interrupt controller(s) is connected to each interrupt line of the device. Read Yes Write Yes Value after Reset 0h Register 11-22. (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Bit Description Interrupt Pin Register. Indicates which interrupt pin the device uses. The following values are decoded (the PCI 9054 supports only INTA#): 0 = No Interrupt pin 1 = INTA# 2 = INTB# 3 = INTC# 4 = INTD# Read Write Value after Reset 7:0 Yes Local/ Serial EEPROM 1h Register 11-23. (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Bit 7:0 Description Min_Gnt. Specifies how long a burst period device needs, assuming a clock rate of 33 MHz. Value is a multiple of 1/4 s increments. Read Yes Write Local/ Serial EEPROM Value after Reset 0h Register 11-24. (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat Bit 7:0 Description Max_Lat. Specifies how often the device must gain access to the PCI Bus. Value is a multiple of 1/4 s increments. Read Yes Write Local/ Serial EEPROM Value after Reset 0h Register 11-25. (PMCAPID; PCI:40h, LOC:180h) Power Management Capability ID Bit 7:0 Description Power Management Capability ID. Read Yes Write No Value after Reset 1h PCI 9054 Data Book v2.1 11-14 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-26. (PMNEXT; PCI:41h, LOC:181h) Power Management Next Capability Pointer Bit 7:0 Description Next_Cap Pointer. Points to the first location of the next item in the capabilities linked list. If power management is the last item in the list, then this register should be set to 0. Read Yes Write Local Value after Reset 48h Register 11-27. (PMC; PCI:42h, LOC:182h) Power Management Capabilities Bit 2:0 Description Version. Writing a 1 indicates this function complies with PCI Power Management Interface Specification v1.0. PCI Clock Required for PME# Signal. When set to 1, indicates a function relies on the presence of the PCI clock for PME# operation. The PCI 9054 does not require the PCI clock for PME#, so this bit should be set to 0. Auxiliary Power Source. Because the PCI 9054 does not support PME# while in a D3cold state, this bit is always set to 0. DSI. When set to 1, the PCI 9054 requires special initialization following a transition to a D0 uninitialized state before a generic class device driver is able to use it. Reserved. D1_Support. When set to 1, the PCI 9054 supports the D1 power state. D2_Support. When set to 1, the PCI 9054 supports the D2 power state. PME#_Support. Indicates power states in which the PCI 9054 may assert PME#. Value Description XXX1 PME# can be asserted from D0 XX1X PME# can be asserted from D1 X1XX PME# can be asserted from D2 1XXX PME# can be asserted from D3hot Reserved. Read Yes Write Local Value after Reset 001 3 Yes Local 0 4 Yes No 0 5 8:6 9 10 Yes Yes Yes Yes Local No Local Local 0 000 0 0 14:11 Yes Local 0h 15 Yes No 0 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-15 Section 11--Registers PCI Configuration Registers Section 11 Registers www..com Section 11 Registers PCI Configuration Registers Register 11-28. (PMCSR; PCI:44h, LOC:184h) Power Management Control/Status Bit Description Power State. Determines or changes the current power state. Value State 00 D0 01 D1 10 D2 11 D3hot Transition from a D3hot state to a D0 state causes a soft reset. Should only be initiated from the PCI Bus because the Local Bus interface is reset during a soft reset. In a D3hot state, PCI Memory and I/O accesses are disabled, as well as PCI interrupts, and only configuration is allowed. The same is true for the D2 state if the corresponding D2_Support pin is set. Reserved. PME#_En. Writing a 1 enables PME# to be asserted. Data_Select. Selects which data to report through the Data register and Data_Scale bits. Data_Scale. Indicates the scaling factor to use when interpreting the value of the Data register. Value and meaning of this bit depends on the data value selected by the Data_Select bit. When the Local CPU initializes the Data_Scale values, must use the Data_Select bit to determine which Data_Scale value it is writing. For Power Consumed and Power Dissipated data, the following scale factors are used. Unit values are in watts. Value Scale 0 Unknown 1 0.1x 2 0.01x 3 0.001x PME#_Status. Indicates PME# is being driven if the PME#_En bit is set (PMCSR[8]=1). Writing a 1 from the Local Bus sets this bit; writing a 1 from the PCI Bus clears this bit to 0. Depending on the current power state, set only if the appropriate PME#_Support bit(s) is set (PMC[15:11]=1). Read Write Value after Reset 1:0 Yes Yes 00 7:2 8 12:9 Yes Yes Yes No Yes Yes 0h 0 0h 14:13 Yes Local 00 15 Yes Local/ Set, PCI/Clr 0 Register 11-29. (PMCSR_BSE; PCI:46h, LOC:186h) PMCSR Bridge Support Extensions Bit 7:0 Reserved. Description Read Yes Write No Value after Reset 0h PCI 9054 Data Book v2.1 11-16 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-30. (PMDATA; PCI:47h, LOC:187h) Power Management Data Bit Description Power Management Data. Provides operating data, such as power consumed or heat dissipation. Data returned is selected by the Data_Select bit(s) (PMCSR[12:9]) and scaled by the Data_Scale bit(s) (PMCSR[14:13]). Data_Select Description 0 D0 Power Consumed 1 D1 Power Consumed 2 D2 Power Consumed 3 D3 Power Consumed 4 D0 Power Dissipated 5 D1 Power Dissipated 6 D2 Power Dissipated 7 D3hot Power Dissipated Read Write Value after Reset 7:0 Yes Local 0h Register 11-31. (HS_CNTL; PCI:48h, LOC:188h) Hot Swap Control Bit 7:0 Hot Swap ID. Description Read Yes Write Local/ Serial EEPROM Value after Reset 06h Register 11-32. (HS_NEXT; PCI:49h, LOC:189h) Hot Swap Next Capability Pointer Bit 7:0 Description Next_Cap Pointer. Points to the first location of the next item in the capabilities linked list. If Hot Swap is the last item in the list, then this register should be set to 0. Read Yes Write Local/ Serial EEPROM Value after Reset 4Ch Register 11-33. (HS_CSR; PCI:4Ah, LOC:18Ah) Hot Swap Control/Status Bit 0 1 2 3 4 5 6 7 15:8 Reserved. ENUM# Interrupt Clear. Writing a 0 enables the interrupt. Writing a 1 clears the interrupt. Reserved. LED Software On/Off Switch. Writing a 1 turns on the LED. Writing a 0 turns off the LED. Reserved. Reserved. Board Removal ENUM# Status Indicator. Writing a 1 reports the ENUM# assertion for removal process. Board Insertion ENUM# Status Indicator. Writing a 1 reports the ENUM# assertion for insertion process. Reserved. Description Read Yes Yes Yes Yes Yes Yes Yes Yes Yes Write No Yes/Clr No PCI No No Yes Yes No Value after Reset 0 0 0 0 0 0 0 1 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-17 Section 11--Registers PCI Configuration Registers Section 11 Registers www..com Section 11 Registers PCI Configuration Registers Register 11-34. (PVPDCNTL; PCI:4Ch, LOC:18Ch) PCI Vital Product Data Control Bit 7:0 Description VPD ID. Capability ID = 03h for VPD. Read PCI Write No Value after Reset 03h Register 11-35. (PVPD_NEXT; PCI:4Dh, LOC:18Dh) PCI Vital Product Data Next Capability Pointer Bit 7:0 Description Next_Cap Pointer. Points to first location of next item in the capabilities linked list. VPD is the last item in the capabilities linked list. This register is set to 0h. Read PCI Write Local Value after Reset 0h Register 11-36. (PVPDAD; PCI:4Eh, LOC:18Eh) PCI Vital Product Data Address Bit 14:0 Description VPD Address. Byte address of the VPD address to be accessed. Supports a 2K or 4K bit serial EEPROM. F. Flag used to indicate when the transfer of data between PVPDATA and the storage component is complete. Writing a 0 along with the VPD address causes a read of VPD information into PVPDATA. The hardware sets this bit to 1 when the VPD Data transfer is complete. Writing a 1 along with the VPD address causes a write of VPD information from PVPDATA into a storage component. The hardware sets this bit to 0 after the Write operation is complete. Read PCI Write Yes Value after Reset 0h 15 PCI Yes 0 Register 11-37. (PVPDATA; PCI:50h, LOC:190h) PCI VPD Data Bit 31:0 VPD Data Register. Description Read PCI Write Yes Value after Reset 0h PCI 9054 Data Book v2.1 11-18 (c) PLX Technology, Inc. All rights reserved. www..com 11.4 LOCAL CONFIGURATION REGISTERS Register 11-38. (LAS0RR; PCI:00h, LOC:80h) Local Address Space 0 Range Register for PCI-to-Local Bus Bit 0 Description Memory Space Indicator. Writing a 0 indicates Local Address Space 0 maps into PCI Memory space. Writing a 1 indicates Local Address Space 0 maps into PCI I/O space. When mapped into Memory space, encoding is as follows: 2/1 Meaning 00 Locate anywhere in 32-bit PCI Address space 01 Locate below 1 MB in PCI Address space 10 Locate anywhere in 64-bit PCI Address space 11 Reserved When mapped into I/O space, bit 1 must be set to 0.Bit 2 is included with bits [31:3] to indicate the decoding range. When mapped into Memory space, writing a 1 indicates reads are prefetchable (does not affect operation of the PCI 9054, but is used for system status). When mapped into I/O space, it is included with bits [31:2] to indicate the decoding range. Specifies which PCI Address bits to use for decoding a PCI access to Local Bus Space 0. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0 to all others (used in conjunction with PCIBAR2). Default is 1 MB. Notes: Range (not Range register) must be power of 2. "Range register value" is inverse of range. User should limit all I/O spaces to 256 bytes per PCI v2.1 spec. Read Yes Write Yes Value after Reset 0 2:1 Yes Yes 00 3 Yes Yes 0 31:4 Yes Yes FFF0000h Register 11-39. (LAS0BA; PCI:04h, LOC:84h) Local Address Space 0 Local Base Address (Remap) Bit 0 1 3:2 Description Space 0 Enable. Writing a 1 enables decoding of PCI addresses for PCI Target access to Local Bus Space 0. Writing a 0 disables decoding. Reserved. If Local Bus Space 0 is mapped into Memory space, bits are not used. When mapped into I/O space, included with bits [31:4] for remapping. Remap PCI Address to Local Address Space 0 into Local Address Space. Bits in this register remap (replace) PCI Address bits used in decode as Local Address bits. Note: Remap Address value must be a multiple of the Range (not the Range register). Read Yes Yes Yes Write Yes No Yes Value after Reset 0 0 00 31:4 Yes Yes 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-19 Section 11--Registers Local Configuration Registers Section 11 Registers www..com Section 11 Registers Local Configuration Registers Register 11-40. (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/DMA Arbitration Bit 7:0 Description Local Bus Latency Timer. Number of Local Bus clock cycles to occur before de-asserting HOLD and releasing the Local Bus. Local Bus Pause Timer. Number of Local Bus Clock cycles to occur before reasserting HOLD after releasing the Local Bus. The pause timer is valid only during DMA. Local Bus Latency Timer Enable. Writing a 1 enables the latency timer. Writing a 0 disables the latency timer. Local Bus Pause Timer Enable. Writing a 1 enables the pause timer. Writing a 0 disables the pause timer. Local Bus BREQ Enable. Writing a 1 enables the Local Bus BR#/BREQi. When BR#/BREQi is active, the PCI 9054 de-asserts HOLD and releases the Local Bus. DMA Channel Priority. Writing a 00 indicates a rotational priority scheme. Writing a 01 indicates Channel 0 has priority. Writing a 10 indicates Channel 1 has priority. Writing an 11 indicates reserved. Local Bus PCI Target Release Bus Mode. When set to 1, the PCI 9054 de-asserts HOLD and releases the Local Bus when the PCI Target Write FIFO becomes empty during a PCI Target Write or when the PCI Target Read FIFO becomes full during a PCI Target Read. PCI Target LOCK# Enable. Writing a 1 enables PCI Target locked sequences. Writing a 0 disables PCI Target locked sequences. PCI Request Mode. Writing a 1 causes the PCI 9054 to de-assert REQ# when it asserts FRAME during a Master cycle. Writing a 0 causes the PCI 9054 to leave REQ# asserted for the entire Bus Master cycle. Delayed Read Mode. When set to 1, the PCI 9054 operates in Delayed Transaction mode for PCI Target reads. The PCI 9054 issues a Retry to the PCI Host and prefetches Read data. PCI Read No Write Mode. Writing a 1 forces a Retry on writes if a read is pending. Writing a 0 allows writes to occur while a read is pending. PCI Read with Write Flush Mode. Writing a 1 submits a request to flush a pending Read cycle if a Write cycle is detected. Writing a 0 submits a request to not effect pending reads when a Write cycle occurs (PCI Specification v2.1 compatible). Gate Local Bus Latency Timer with BREQi. (C and J modes only.) PCI Read No Flush Mode. Writing a 1 submits a request to not flush the Read FIFO if the PCI Read cycle completes (Read Ahead mode). Writing a 0 submits a request to flush the Read FIFO if a PCI Read cycle completes. When set to 0, reads from the PCI Configuration Register address 00h returns Device ID and Vendor ID. When set to 1, reads from the PCI Configuration register address 00h returns Subsystem ID and Subsystem Vendor ID. FIFO Full Status Flag. When set to 1, the PCI Initiator Write FIFO is almost full. Reflects the value of the DMPAF pin. BIGEND#/WAIT# Input/Output Select (M mode only). Writing a 1 selects the wait functionality of the signal. Writing a 0 selects Big Endian input functionality. Read Yes Write Yes Value after Reset 0h 15:8 Yes Yes 0h 16 17 Yes Yes Yes Yes 0 0 18 Yes Yes 0 20:19 Yes Yes 00 21 Yes Yes 1 22 Yes Yes 0 23 Yes Yes 0 24 Yes Yes 0 25 Yes Yes 0 26 Yes Yes 0 27 28 Yes Yes Yes Yes 0 0 29 Yes Yes 0 30 Yes No 0 31 Yes Yes 0 PCI 9054 Data Book v2.1 11-20 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-41. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Bit Description Configuration Register Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for Local accesses to the Configuration registers. Writing a 0 specifies Little Endian ordering. Big Endian mode can be specified for Configuration register accesses by asserting BIGEND# during the Address phase of the access. PCI Initiator Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for PCI Initiator accesses. Writing a 0 specifies Little Endian ordering. Big Endian mode can be specified for PCI Initiator accesses by asserting BIGEND# input pin during the Address phase of the access. PCI Target Address Space 0 Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for PCI Target accesses to Local Address Space 0. Writing a 0 specifies Little Endian ordering. PCI Target Address Expansion ROM 0 Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for PCI Target accesses to Expansion ROM. Writing a 0 specifies Little Endian ordering. Big Endian Byte Lane Mode. Writing a 1 specifies that in any Endian mode, use the following byte lanes for the modes listed: M Mode [0:15] for a 16-bit Local Bus [0:7] for an 8-bit Local Bus C and J Modes [31:16] for a 16-bit Local Bus [31:24] for an 8-bit Local Bus Writing a 0 specifies that in any Endian mode, use the following byte lanes for the modes listed: M Mode [16:31] for a 16-bit Local Bus [24:31] for an 8-bit Local Bus C and J Modes [15:0] for a 16-bit Local Bus [7:0] for an 8-bit Local Bus PCI Target Address Space 1 Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for PCI Target accesses to Local Address Space 1. Writing a 0 specifies Little Endian ordering. DMA Channel 1 Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for DMA Channel 1 accesses to the Local Address space. Writing a 0 specifies Little Endian ordering. DMA Channel 0 Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for DMA Channel 0 accesses to the Local Address space. Writing a 0 specifies Little Endian ordering. Read Write Value after Reset 0 Yes Yes 0 1 Yes Yes 0 2 Yes Yes 0 3 Yes Yes 0 4 Yes Yes 0 5 Yes Yes 0 6 Yes Yes 0 7 Yes Yes 0 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-21 Section 11--Registers Local Configuration Registers Section 11 Registers www..com Section 11 Registers Local Configuration Registers Register 11-42. (LMISC; PCI:0Dh, LOC:8Dh) Local Miscellaneous Control Bit 0 Description Base Address Register 1 Enable. If set to 1, the Base Address 1 Register for I/O accesses to Configuration registers is enabled. If set to 0, the Base Address 1 Register for I/O accesses to Configuration registers is disabled. Base Address Register 1 Shift. If Base Address Register 1 Enable is low, and this bit is set to 0, then PCIBAR2 and PCIBAR3 remain at PCI Configuration addresses 18h and 1Ch. If Base Address Register 1 Enable is low, and this bit is set to 1, then PCIBAR2 (Local Address Space 0) and PCIBAR3 (Local Address Space 1) are shifted to become PCIBAR1 and PCIBAR2 at PCI Configuration addresses 14h and 18h. Set if a blank region in Base Address Register Space could not be accepted by system BIOS. Local Init Status. Writing a 1 indicates Local Init done. Responses to PCI accesses are Retrys until this bit is set. If the PCI 9054 has a blank serial EEPROM attached, the Local processor must set the Local Init Status bit to 1. Reserved. M Mode PCI Initiator Deferred Read Enable. Writing a 1 enables the PCI 9054 to operate in Delayed Transaction mode for PCI Initiator reads. The PCI 9054 issues a RETRY# to the M mode Master and prefetches Read data from the PCI Bus. M Mode TEA# Input Interrupt Mask. When set to 1, TEA# input causes SERR# output on the PCI Bus if enabled (PCICR[8]=1) and the Signaled System Error bit is set (PCISR[14]=1). Writing 0 masks the TEA# input to create SERR#. The SERR# Status bit is set in both cases. PCI Initiator Write FIFO Almost Full RETRY# Output Enable. When set to 1, the PCI 9054 issues a RETRY# to the MPC850 or MPC860. Reserved. Read Yes Write Yes Value after Reset 1 1 Yes Yes 0 2 3 Yes Yes Local/ Serial EEPROM No 0 0 4 Yes Yes 0 5 Yes Yes 0 6 7 Yes Yes Yes No 0 0 Register 11-43. (PROT_AREA; PCI:0Eh, LOC:8Eh) Serial EEPROM Write-Protected Address Boundary Bit Description Serial EEPROM Starting at Lword Boundary (48 Lwords = 192 bytes) for VPD Accesses. Any serial EEPROM address below this boundary is read-only. Note: Anything below the programmed address may contain the PCI 9054 Configuration data. Reserved. Read Write Value after Reset 6:0 Yes Yes 0110000 15:7 Yes No 0h PCI 9054 Data Book v2.1 11-22 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-44. (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range Bit 0 10:1 Description Address Decode Enable. Bit 0 can only be enabled from the serial EEPROM. To disable, set the PCI Expansion ROM Address Decode Enable bit to 0 (PCIERBAR[0]=0). Reserved. Specifies which PCI Address bits to use for decoding a PCI-to-Local Bus Expansion ROM. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0 to all others (used in conjunction with PCIERBAR). Default is 64 KB. Note: Range (not Range register) must be power of 2. "Range register value" is inverse of range. Read Yes Yes Write Serial EEPROM Only No Value after Reset 0 0h 31:11 Yes Yes FFFF00h Register 11-45. (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) and BREQo Control Bit Description M Mode: RETRY# Signal Assertion Delay Clocks. Number of Local Bus clocks in which a PCI Target BR# request is pending and a Local PCI Initiator access is in progress and not being granted the bus BG# before asserting RETRY#. Once asserted, RETRY# remains asserted until PCI 9054 samples de-assertion of BB# by the Local Arbiter (Least Significant Bit is 8 or 64 clocks). C and J Modes: Backoff Request Delay Clocks. Number of Local Bus clocks in which a PCI Target HOLD request is pending and a Local PCI Initiator access is in progress and not being granted the bus (LHOLDA) before asserting BREQo (Backoff Request Out). BREQo remains asserted until the PCI 9054 receives LHOLDA (Least Significant Bit is 8 or 64 clocks). Local Bus Backoff Enable (C, J, and M Modes). Writing a 1 enables the PCI 9054 to assert BREQo/RETRY#. Backoff Timer Resolution. Writing a 1 changes the Least Significant Bit of the Backoff Timer from 8 to 64 clocks. Reserved. Remap PCI Expansion ROM Space into Local Address Space. Bits in this register remap (replace) the PCI Address bits used in decode as Local Address bits. Note: Remap Address value must be a multiple of the Range (not the Range register). Read Write Value after Reset 3:0 Yes Yes 0h 4 5 10:6 Yes Yes Yes Yes Yes No 0 0 0h 31:11 Yes Yes 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-23 Section 11--Registers Local Configuration Registers Section 11 Registers www..com Section 11 Registers Local Configuration Registers Register 11-46. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor Bit 1:0 5:2 6 Description Memory Space 0 Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 or 11 indicates a 32-bit bus width. Memory Space 0 Internal Wait States (data-to-data; 0-15 wait states). Memory Space 0 TA#/READY# Input Enable. Writing a 1 enables TA#/READY# input. Writing a 0 disables TA#/READY# input. Memory Space 0 BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.5 for M mode or Section 4.2.5 for C and J modes. Memory Space 0 Prefetch Disable. When mapped into Memory space, writing a 0 enables Read prefetching. Writing a 1 disables prefetching. If prefetching is disabled, the PCI 9054 disconnects after each Memory read. Expansion ROM Space Prefetch Disable. Writing a 0 enables Read prefetching. Writing a 1 disables prefetching. If prefetching is disabled, the PCI 9054 disconnects after each Memory read. Prefetch Counter Enable. When set to 1 and Memory prefetching is enabled, the PCI 9054 prefetches up to the number of Lwords specified in prefetch count. When set to 0, the PCI 9054 ignores the count and continues prefetching until it is terminated by the PCI Bus. Prefetch Counter. Number of Lwords to prefetch during Memory Read cycles (0-15). A count of zero selects a prefetch of 16 Lwords. Reserved. Expansion ROM Space Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 or 11 indicates a 32-bit bus width. Expansion ROM Space Internal Wait States (data-to-data; 0-15 wait states). Expansion ROM Space TA#/READY# Input Enable. Writing a 1 enables TA#/READY# input. Writing a 0 disables TA#/READY# input. Expansion ROM Space BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.5 for M mode or to Section 4.2.5 for C and J modes. Memory Space 0 Burst Enable. Writing a 1 enables bursting. Writing a 0 disables bursting. Extra Long Load from Serial EEPROM. Writing a 1 loads the Subsystem ID and Local Address Space 1 registers. Writing a 0 indicates not to load them. Expansion ROM Space Burst Enable. Writing a 1 enables bursting. Writing a 0 disables bursting. PCI Target PCI Write Mode. Writing a 0 indicates the PCI 9054 should disconnect when the PCI Target Write FIFO is full. Writing a 1 indicates the PCI 9054 should de-assert TRDY# when the PCI Target Write FIFO is full. PCI Target Retry Delay Clocks. Contains the value (multiplied by 8) of the number of PCI Bus clocks after receiving a PCI-to-Local Read or Write access and not successfully completing a transfer. Pertains only to PCI Target writes when the PCI Target PCI Write Mode bit is set (LBRD0[27]=1). Read Yes Yes Yes Write Yes Yes Yes Value after Reset M = 11 J = 11 C = 11 0h 1 7 Yes Yes 0 8 Yes Yes 0 9 Yes Yes 0 10 Yes Yes 0 14:11 15 17:16 Yes Yes Yes Yes No Yes 0h 0 M = 11 J = 11 C = 11 0h 1 21:18 22 Yes Yes Yes Yes 23 Yes Yes 0 24 Yes Yes Serial EEPROM Only Yes 0 25 Yes 0 26 Yes 0 27 Yes Yes 0 31:28 Yes Yes 4h (32 clocks) PCI 9054 Data Book v2.1 11-24 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-47. (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for PCI Initiator-to-PCI Bit 15:0 Reserved (64-KB increments). Specifies which Local Address bits to use for decoding a Local-to-PCI Bus access. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0h to all others. Note: Range (not Range register) must be power of 2. "Range register value" is inverse of range. Description Read Yes Write No Value after Reset 0h 31:16 Yes Yes 0h Register 11-48. (DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for PCI Initiator-to-PCI Memory Bit 15:0 31:16 Reserved. Assigns a value to bits to use for decoding Local-to-PCI Memory accesses. Note: Local Base Address value must be a multiple of the Range (not the Range register). Yes Yes 0h Description Read Yes Write No Value after Reset 0h Register 11-49. (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for PCI Initiator-to-PCI I/O Configuration Bit 15:0 Reserved. Assigns a value to bits to use for decoding Local-to-PCI I/O or Configuration accesses. 31:16 Notes: Local Base Address value must be a multiple of the Range (not the Range register). Refer to DMPBAM[13] for the I/O Remap Address option. Yes Yes 0h Description Read Yes Write No Value after Reset 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-25 Section 11--Registers Local Configuration Registers Section 11 Registers www..com Section 11 Registers Local Configuration Registers Register 11-50. (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for PCI Initiator-to-PCI Memory Bit 0 Description PCI Initiator Memory Access Enable. Writing a 1 enables decode of PCI Initiator Memory accesses. Writing a 0 disables decode of PCI Initiator Memory accesses. PCI Initiator I/O Access Enable. Writing a 1 enables decode of PCI Initiator I/O accesses. Writing a 0 disables decode of PCI Initiator I/O accesses. PCI Initiator Cache Enable. Writing a 1 causes prefetch to occur infinitely. PCI Initiator Read Prefetch Size Control. Values: 00 = PCI 9054 continues to prefetch Read data from the PCI Bus until the PCI Initiator access is finished. This may result in an additional four unneeded Lwords being prefetched from the PCI Bus. 01 = Prefetch up to four Lwords from the PCI Bus. 10 = Prefetch up to eight Lwords from the PCI Bus. 11 = Prefetch up to 16 Lwords from the PCI Bus. PCI Initiator Burst reads should not exceed programmed limit. PCI Initiator PCI Read Mode. Writing a 0 indicates the PCI 9054 should release the PCI Bus when the Read FIFO becomes full. Writing a 1 indicates the PCI 9054 should keep the PCI Bus and de-assert IRDY# when the Read FIFO becomes full. Programmable Almost Full Flag. When the number of entries in the 32-word PCI Initiator Write FIFO exceeds this value, the MDREQ#/DMPAF signal is asserted high. Memory Write and Invalidate Mode. When set to 1, the PCI 9054 waits for 8 or 16 Lwords to be written from the Local Bus before starting a PCI access. In addition, all Memory Write and Invalidate cycles to the PCI Bus must be 8 or 16 Lword bursts. PCI Initiator Prefetch Limit. Writing a 1 causes the PCI 9054 to not prefetch past 4-KB boundaries. I/O Remap Select. Writing a 1 forces PCI Address bits [31:16] to all zeros. Writing a 0 uses bits [31:16] of this register as PCI Address bits [31:16]. PCI Initiator Write Delay. Delays PCI Bus request after PCI Initiator Burst Write cycle has started. Values: 00 = No delay; start cycle immediately 01 = Delay 4 PCI clocks 10 = Delay 8 PCI clocks 11 = Delay 16 PCI clocks Remap Local-to-PCI Space into PCI Address Space. Bits in this register remap (replace) Local Address bits used in decode as the PCI Address bits. Note: Remap Address value must be a multiple of the Range (not the Range register). Read Yes Write Yes Value after Reset 0 1 2 Yes Yes Yes Yes 0 0 12, 3 Yes Yes 00 4 Yes Yes 0 10, 8:5 Yes Yes 00000 9 Yes Yes 0 11 13 Yes Yes Yes Yes 0 0 15:14 Yes Yes 00 31:16 Yes Yes 0h PCI 9054 Data Book v2.1 11-26 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-51. (DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration Bit 1:0 7:2 10:8 15:11 23:16 30:24 Register Number. Function Number. Device Number. Bus Number. Reserved. Configuration Enable. Writing a 1 allows Local-to-PCI I/O accesses to be converted to a PCI Configuration cycle. Parameters in this table are used to assert the PCI Configuration address. Note: For more information, refer to the PCI Initiator Configuration Cycle example in Section 3.4.1.7 for M mode or Section 5.4.1.6.1 for C and J modes. Description Configuration Type (00=Type 0, 01=Type 1). Read Yes Yes Yes Yes Yes Yes Write Yes Yes Yes Yes Yes No Value after Reset 00 0 0 0 0h 0h 31 Yes Yes 0 Register 11-52. (LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI-to-Local Bus Bit 0 Description Memory Space Indicator. Writing a 0 indicates Local Address Space 1 maps into PCI Memory space. Writing a 1 indicates Address Space 1 maps into PCI I/O space. When mapped into Memory space, encoding is as follows: 2/1 Meaning 00 Locate anywhere in 32-bit PCI Address space 01 Locate below 1 MB in PCI Address space 10 Locate anywhere in 64-bit PCI Address space 11 Reserved When mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [31:3] to indicate the decoding range. When mapped into Memory space, writing a 1 indicates reads are prefetchable (does not affect operation of the PCI 9054, but is used for system status). When mapped into I/O space, included with bits [31:2] to indicate the decoding range. Specifies which PCI Address bits to use for decoding a PCI access to Local Bus Space 1. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0 to all others. (Used in conjunction with PCIBAR3.) Default is 1 MB. If QSR[0]=1, defines PCI Base Address 0. Notes: Range (not Range register) must be power of 2. "Range register value" is inverse of range. User should limit all I/O spaces to 256 bytes per PCI Specification v2.1. Read Yes Write Yes Value after Reset 0 2:1 Yes Yes 00 3 Yes Yes 0 31:4 Yes Yes FFF0000h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-27 Section 11--Registers Local Configuration Registers Section 11 Registers www..com Section 11 Registers Local Configuration Registers Register 11-53. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap) Bit 0 1 3:2 Description Space 1 Enable. Writing a 1 enables decoding of PCI addresses for PCI Target access to Local Bus Space 1. Writing a 0 disables decoding. Reserved. Not used if Local Bus Space 1 is mapped into Memory space. Included with bits [31:4] for remapping when mapped into I/O space. Remap PCI Address to Local Address Space 1 into Local Address Space. Bits in this register remap (replace) the PCI Address bits used in decode as Local Address bits. Note: Remap Address value must be a multiple of the Range (not the Range register). Read Yes Yes Yes Write Yes No Yes Value after Reset 0 0 00 31:4 Yes Yes 0h Register 11-54. (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor Bit 1:0 5:2 6 Description Memory Space 1 Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 or 11 indicates a 32-bit bus width. Memory Space 1 Internal Wait States (data-to-data; 0-15 wait states). Memory Space 1 TA#/READY# Input Enable. Writing a 1 enables TA#/READY# input. Writing a 0 disables TA#/READY# input. Memory Space 1 BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.5 for M mode or Section 4.2.5 for C and J modes. Memory Space 1 Burst Enable. Writing a 1 enables bursting. Writing a 0 disables bursting. Memory Space 1 Prefetch Disable. When mapped into Memory space, writing a 0 enables Read prefetching. Writing a 1 disables prefetching. If prefetching is disabled, the PCI 9054 disconnects after each Memory read. Read Prefetch Count Enable. When set to 1 and Memory prefetching is enabled, the PCI 9054 prefetches up to the number of Lwords specified in prefetch count. When set to 0, the PCI 9054 ignores the count and continues prefetching until it is terminated by the PCI Bus. Read Prefetch Count. Number of Lwords to prefetch during Memory Read cycles (0-15). Reserved. Read Yes Yes Yes Write Yes Yes Yes Value after Reset M = 11 J = 11 C = 11 0h 1 7 Yes Yes 0 8 Yes Yes 0 9 Yes Yes 0 10 Yes Yes 0 14:11 31:15 Yes Yes Yes No 0h 0h Register 11-55. (DMDAC; PCI:FCh, LOC:17Ch) PCI Initiator PCI Dual Address Cycle Bit 31:0 Description Upper 32 Bits of PCI Dual Address Cycle PCI Address during PCI Initiator Cycles. If set to 0, the PCI 9054 performs 32-bit PCI Initiator Address access. Read Yes Write Yes Value after Reset 0h PCI 9054 Data Book v2.1 11-28 (c) PLX Technology, Inc. All rights reserved. www..com 11.5 RUNTIME REGISTERS Register 11-56. (MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0 Bit 32-Bit Mailbox Register. 31:0 Note: Inbound Queue Port replaces Mailbox Register 0 when the I2O function is enabled (QSR[0]=1). Mailbox Register 0 is always accessible at PCI address 78h and Local address C0h. Yes Yes 0h Description Read Write Value after Reset Register 11-57. (MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1 Bit 32-Bit Mailbox Register. 31:0 Note: Mailbox Register 1 is replaced by Outbound Queue Port when the I2O function is enabled (QSR[0]=1). Mailbox Register 1 is always accessible at PCI address 7Ch and Local address C4h. Yes Yes 0h Description Read Write Value after Reset Register 11-58. (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2 Bit 31:0 32-Bit Mailbox Register. Description Read Yes Write Yes Value after Reset 0h Register 11-59. (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3 Bit 31:0 32-Bit Mailbox Register. Description Read Yes Write Yes Value after Reset 0h Register 11-60. (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4 Bit 31:0 32-Bit Mailbox Register. Description Read Yes Write Yes Value after Reset 0h Register 11-61. (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5 Bit 31:0 32-Bit Mailbox Register. Description Read Yes Write Yes Value after Reset 0h Register 11-62. (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6 Bit 31:0 32-Bit Mailbox Register. Description Read Yes Write Yes Value after Reset 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-29 Section 11--Registers Runtime Registers Section 11 Registers www..com Section 11 Registers Runtime Registers Register 11-63. (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7 Bit 31:0 32-Bit Mailbox Register. Description Read Yes Write Yes Value after Reset 0h Register 11-64. (P2LDBELL; PCI:60h, LOC:E0h) PCI-to-Local Doorbell Bit Description Doorbell Register. The PCI Bus Master can write to this register and assert a Local interrupt to the Local processor. The Local processor can then read this register to determine which doorbell bit was set. The PCI Bus Master sets the doorbell by writing a 1 to a particular bit. The Local processor can clear a doorbell bit by writing a 1 to that bit position. Read Write Value after Reset 31:0 Yes Yes/Clr 0h Register 11-65. (L2PDBELL; PCI:64h, LOC:E4h) Local-to-PCI Doorbell Bit Description Doorbell Register. The Local processor can write to this register and assert a PCI interrupt. The PCI Bus Master can then read this register to determine which doorbell bit was set. The Local processor sets the doorbell by writing a 1 to a particular bit. The PCI Bus Master can clear a doorbell bit by writing a 1 to that bit position. Read Write Value after Reset 31:0 Yes Yes/Clr 0h PCI 9054 Data Book v2.1 11-30 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-66. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Bit 0 Description Enable Local Bus TEA#/LSERR#. Writing a 1 enables PCI 9054 to assert TEA#/LSERR# interrupt when the PCI Bus Target Abort bit is set (PCISR[11]=1) or the Received Master Abort bit is set (PCISR[13]=1 or INTCSR[6]=1). Enable Local Bus TEA#/LSERR# when a PCI parity error occurs during a PCI 9054 Master Transfer or a PCI 9054 Slave access. Generate PCI Bus SERR# Interrupt. When set to 0, writing 1 asserts the PCI Bus SERR# interrupt. Mailbox Interrupt Enable. Writing a 1 enables a Local Interrupt to be asserted when the PCI Bus writes to MBOX0 through MBOX3. To clear a Local Interrupt, the Local Bus Master must read the Mailbox. Used in conjunction with the Local Interrupt Output Enable bit (INTCSR[16]). Power Management Interrupt Enable. Writing a 1 enables a Local Interrupt to be asserted when the Power Management Power State changes. Power Management Interrupt. When set to 1, indicates a Power Management interrupt is pending. A Power Management interrupt is caused by a change in the Power State register (PMCSR). Writing a 1 clears the interrupt. PCI Initiator Write/PCI Target Read Local Data Parity Check Error Enable. Writing a 1 enables a Local Data Parity error signal to be asserted through the LSERR#/TEA# pin. INTCSR[0] must be enabled for this to have an effect. PCI Initiator Write/PCI Target Read Local Data Parity Check Error Status. When set to 1, indicates the PCI 9054 has detected a Local Data Parity check error, even if the Check Parity Error bit is disabled. Writing 1 clears this bit to 0. PCI Interrupt Enable. Writing a 1 enables PCI interrupts. PCI Doorbell Interrupt Enable. Writing a 1 enablesDoorbell interrupts. Used in conjunction with the PCI Interrupt Enable bit (INTCSR[8]). Clearing the doorbell interrupt bits that caused the interrupt also clears the interrupt. PCI Abort Interrupt Enable. Values of 1 enables Master abort or Master detect of a Target abort to assert a PCI interrupt. Used in conjunction with the PCI Interrupt Enable bit (INTCSR[8]). Clearing the abort status bits also clears the PCI interrupt. Local Interrupt Input Enable. Writing a 1 enables a Local interrupt input to assert a PCI interrupt. Used in conjunction with the PCI Interrupt Enable bit (INTCSR[8]). Clearing the Local Bus cause of the interrupt also clears the interrupt. Retry Abort Enable. Writing a 1 enables the PCI 9054 to treat 256 Master consecutive Retrys to a Target as a Target abort. Writing a 0 enables the PCI 9054 to attempt Master Retrys indefinitely. PCI Doorbell Interrupt Active. When set to 1, indicates the PCI Doorbell interrupt is active. PCI Abort Interrupt Active. When set to 1, indicates the PCI Abort interrupt is active. Local Input Interrupt Active. When set to 1, indicates the Local Input interrupt is active. Local Interrupt Output Enable. Writing a 1 enables Local interrupt output. Used in conjunction with the Mailbox Interrupt Enable bit (INTCSR[3]). Local Doorbell Interrupt Enable. Writing a 1 enables Doorbell interrupts. Used in conjunction with the Local Interrupt Enable bit. Clearing the Local Doorbell Interrupt bits that caused the interrupt also clears the interrupt. Local DMA Channel 0 Interrupt Enable. Writing a 1 enables DMA Channel 0 interrupts. Used in conjunction with the Local Interrupt Enable bit. Clearing the DMA status bits also clears the interrupt. Read Yes Write Yes Value after Reset 0 1 2 Yes Yes Yes Yes 0 0 3 Yes Yes 0 4 Yes Yes 0 5 Yes Yes/Clr 0 6 Yes Yes 0 7 8 9 Yes Yes Yes Yes/Clr Yes Yes 0 1 0 10 Yes Yes 0 11 Yes Yes 0 12 Yes Yes 0 13 14 15 16 Yes Yes Yes Yes No No No Yes 0 0 0 1 17 Yes Yes 0 18 Yes Yes 0 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-31 Section 11--Registers Runtime Registers Section 11 Registers www..com Section 11 Registers Runtime Registers Register 11-66. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status (Continued) Bit 19 Description Local DMA Channel 1 Interrupt Enable. Writing a 1 enables DMA Channel 1 interrupts. Used in conjunction with the Local Interrupt Enable bit. Clearing the DMA status bits also clears the interrupt. Local Doorbell Interrupt Active. Reading a 1 indicates the Local Doorbell interrupt is active. DMA Channel 0 Interrupt Active. Reading a 1 indicates the DMA Channel 0 interrupt is active. DMA Channel 1 Interrupt Active. Reading a 1 indicates the DMA Channel 1 interrupt is active. BIST Interrupt Active. Reading a 1 indicates the BIST interrupt is active. The BIST (built-in self test) interrupt is asserted by writing a 1 to bit 6 of the PCI Configuration BIST register. Clearing bit 6 clears the interrupt. Refer to the PCIBISTR register for a description of the self test. Reading a 0 indicates the PCI Initiator was the Bus Master during a Master or Target abort. Reading a 0 indicates DMA CH 0 was the Bus Master during a Master or Target abort. Reading a 0 indicates DMA CH 1 was the Bus Master during a Master or Target abort. Reading a 0 indicates a Target abort was asserted by the PCI 9054 after 256 consecutive Master retries to a Target. Reading a 1 indicates the PCI Bus wrote data to MBOX0. Enabled only if the Mailbox Interrupt Enable bit is set (INTCSR[3]=1). Reading a 1 indicates the PCI Bus wrote data to MBOX1. Enabled only if the Mailbox Interrupt Enable bit is set (INTCSR[3]=1). Reading a 1 indicates the PCI Bus wrote data to MBOX2. Enabled only if the Mailbox Interrupt Enable bit is set (INTCSR[3]=1). Reading a 1 indicates the PCI Bus wrote data to MBOX3. Enabled only if the Mailbox Interrupt Enable bit is set (INTCSR[3]=1). Read Yes Write Yes Value after Reset 0 20 21 22 Yes Yes Yes No No No 0 0 0 23 Yes No 0 24 25 26 27 28 29 30 31 Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No 1 1 1 1 0 0 0 0 PCI 9054 Data Book v2.1 11-32 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-67. (CNTRL; PCI:6Ch, LOC:ECh) Serial EEPROM Control, PCI Command Codes, User I/O Control, and Init Control Bit 3:0 7:4 11:8 15:12 16 17 Description PCI Read Command Code for DMA. PCI Write Command Code for DMA. PCI Memory Read Command Code for PCI Initiator. PCI Memory Write Command Code for PCI Initiator. General Purpose Output. Writing a 1 causes USERo output to go high. Writing a 0 causes USERo output to go low. General Purpose Input. Reading a 1 indicates the USERi input pin is high. Reading a 0 indicates the USERi pin is low. Writing a 1 selects USERi to be an input to the chip. Writing a 0 selects LLOCKi# as an input. Enables the user to select between the USERi and LLOCKi# functions when USERi is chosen to be an input. DMAMODE0[12] and/or DMAMODE1[12] are select bit(s) for the pin. Writing a 1 selects USERo to be an output from the chip. Writing a 0 selects LLOCKo# as an output. Enables the user to select between the USERo and LLOCKo# functions when USERo is chosen to be an output. DMAMODE0[12] and/or DMAMODE1[12] are select bit(s) for the pin. Reserved. Serial EEPROM Clock for Local or PCI Bus Reads or Writes to Serial EEPROM. Toggling this bit asserts the serial EEPROM clock. (Refer to manufacturer's data sheet for particular serial EEPROM being used.) Serial EEPROM Chip Select. For Local or PCI Bus reads or writes to the serial EEPROM, setting this bit to 1 provides the serial EEPROM chip select. Write Bit to Serial EEPROM. For writes, this output bit is input to the serial EEPROM. Clocked into the serial EEPROM by the serial EEPROM clock. Read Bit from Serial EEPROM. (Refer to Sections 2.4.2 and 2.4.2.1 for M mode or Sections 4.4.2 and 4.4.2.1 for C and J modes.) Programmed Serial EEPROM Present. When set to 1, indicates that a programmed serial EEPROM is present. Reload Configuration Registers. When set to 0, writing a 1 causes the PCI 9054 to reload the Local Configuration registers from the serial EEPROM. PCI Adapter Software Reset. Writing a 1 holds the PCI 9054 Local Bus logic in a reset state, and asserts LRESETo# output. Contents of the PCI Configuration registers and the Shared Runtime registers are not reset. A software reset can only be cleared from the PCI Bus. Reserved. Read Yes Yes Yes Yes Yes Yes Write Yes Yes Yes Yes Yes No Value after Reset 1110 0111 0110 0111 1 -- 18 Yes Yes 1 19 Yes Yes 1 23:20 24 Yes Yes No Yes 0h 0 25 26 27 28 29 Yes Yes Yes Yes Yes Yes Yes No No Yes 0 0 -- 0 0 30 Yes Yes 0 31 Yes No 0 Register 11-68. (PCIHIDR; PCI:70h, LOC:F0h) PCI Hardcoded Configuration ID Bit 15:0 31:16 Description Vendor ID. Identifies manufacturer of device. Hardcoded to the PCI SIG-issued Vendor ID of PLX (10B5h). Device ID. Identifies particular device. Hardcoded to the PLX part number for PCI interface chip 9054h. Read Yes Yes Write No No Value after Reset 10B5h 9054h Register 11-69. (PCIHREV; PCI:74h, LOC:F4h) PCI Hardcoded Revision ID Bit 7:0 Description Revision ID. Hardcoded silicon revision of the PCI 9054. Read Yes Write No Value after Reset Current Rev # PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-33 Section 11--Registers Runtime Registers Section 11 Registers www..com Section 11 Registers DMA Registers 11.6 DMA REGISTERS Register 11-70. (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode Bit 1:0 5:2 6 7 8 Description Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 or 11 indicates a 32-bit bus width. Internal Wait States (data-to-data). TA#/READY# Input Enable. Writing a 1 enables TA#/READY# input. Writing a 0 disables TA#/READY# input. BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.5 for M mode or Section 4.2.5 for C and J modes. Local Burst Enable. Writing a 1 enables Local bursting. Writing a 0 disables Local bursting. Scatter/Gather Mode. Writing a 1 indicates Scatter/Gather mode is enabled. For Scatter/Gather mode, DMA source address, destination address, and byte count are loaded from memory in PCI or Local Address spaces. Writing a 0 indicates Block mode is enabled. Done Interrupt Enable. Writing a 1 enables an interrupt when done. Writing a 0 disables an interrupt when done. If DMA Clear Count mode is enabled, the interrupt does not occur until the byte count is cleared. Local Addressing Mode. Writing a 1 holds the Local Address bus constant. Writing a 0 indicates the Local Address is incremented. Demand Mode. Writing a 1 causes the DMA controller to operate in Demand mode, as well as to make USERo/DREQ0#/LLOCKo# an input (DREQ0#) and USERi/DACK0#/LLOCKi# an output (DACK0#). In Demand mode, the DMA controller transfers data when its DREQ0# input is asserted. Asserts DACK0# to indicate the current Local Bus transfer is in response to DREQ0# input. DMA controller transfers Lwords (32 bits) of data. This may result in multiple transfers for an 8- or 16-bit bus. Memory Write and Invalidate Mode for DMA Transfers. When set to 1, the PCI 9054 performs Memory Write and Invalidate cycles to the PCI Bus. The PCI 9054 supports Memory Write and Invalidate sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or 16 is specified, the PCI 9054 performs Write transfers rather than Memory Write and Invalidate transfers. Transfers must start and end at cache line boundaries. DMA EOT# Enable. Writing a 1 enables the EOT# input pin. Writing a 0 disables the EOT# input pin. Fast/Slow Terminate Mode Select. Writing a 0 sets PCI 9054 into the Slow Terminate mode. As a result in C or J modes, BLAST# is asserted on the last Data transfer to terminate DMA transfer. As a result in M mode, BDIP# is de-asserted at the nearest 16-byte boundary and stops the DMA transfer. Writing a 1 indicates that if EOT# is asserted or DREQ0# is de-asserted in Demand mode during DMA will immediately terminate the DMA transfer. In M mode, writing a 1 indicates BDIP# output is disabled. As a result, the PCI 9054 DMA transfer terminates immediately when EOT# is asserted or when DREQ0# is de-asserted in Demand mode. DMA Clear Count Mode. Writing a 1 clears the byte count in each Scatter/ Gather descriptor when the corresponding DMA transfer is complete. DMA Channel 0 Interrupt Select. Writing a 1 routes the DMA Channel 0 interrupt to the PCI Bus interrupt. Writing a 0 routes the DMA Channel 0 interrupt to the Local Bus interrupt. DAC Chain Load. When set to 1, enables the descriptor to load the PCI Dual Address Cycle value. Otherwise, it uses the contents of the register. Reserved. Read Yes Yes Yes Yes Yes Write Yes Yes Yes Yes Yes Value after Reset M = 11 J = 11 C = 11 0h 1 0 0 9 Yes Yes 0 10 11 Yes Yes Yes Yes 0 0 12 Yes Yes 0 13 Yes Yes 0 14 Yes Yes 0 15 Yes Yes 0 16 17 18 31:19 Yes Yes Yes Yes Yes Yes Yes No 0 0 0 0h PCI 9054 Data Book v2.1 11-34 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-71. (DMAPADR0; PCI:84h, LOC:104h) DMA Channel 0 PCI Address Bit 31:0 Description PCI Address Register. Indicates from where in PCI Memory space DMA transfers (reads or writes) start. Read Yes Write Yes Value after Reset 0h Register 11-72. (DMALADR0; PCI:88h, LOC:108h) DMA Channel 0 Local Address Bit 31:0 Description Local Address Register. Indicates from where in Local Memory space DMA transfers (reads or writes) start. Read Yes Write Yes Value after Reset 0h Register 11-73. (DMASIZ0; PCI:8Ch, LOC:10Ch) DMA Channel 0 Transfer Size (Bytes) Bit 22:0 31:23 Description DMA Transfer Size (Bytes). Indicates the number of bytes to transfer during a DMA operation. Reserved. Read Yes Yes Write Yes No Value after Reset 0h 0h Register 11-74. (DMADPR0; PCI:90h, LOC:110h) DMA Channel 0 Descriptor Pointer Bit 0 1 Description Descriptor Location. Writing a 1 indicates PCI Address space. Writing a 0 indicates Local Address space. End of Chain. Writing a 1 indicates end of chain. Writing a 0 indicates not end of chain descriptor. (Same as Block mode.) Interrupt after Terminal Count. Writing a 1 causes an interrupt to be asserted after the terminal count for this descriptor is reached. Writing a 0 disables interrupts from being asserted. Direction of Transfer. Writing a 1 indicates transfers from the Local Bus to the PCI Bus. Writing a 0 indicates transfers from the PCI Bus to the Local Bus. Next Descriptor Address. Qword aligned (bits [3:0]=0000). Read Yes Yes Write Yes Yes Value after Reset 0 0 2 Yes Yes 0 3 31:4 Yes Yes Yes Yes 0 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-35 Section 11--Registers DMA Registers Section 11 Registers www..com Section 11 Registers DMA Registers Register 11-75. (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode Bit 1:0 5:2 6 Description Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 or 11 indicates a 32-bit bus width. Internal Wait States (data-to-data). TA#/READY# Input Enable. Writing a 1 enables TA#/READY# input. Writing a 0 disables TA#/READY# input. BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.5 for M mode or Section 4.2.5 for C and J modes. Local Burst Enable. Writing a 1 enables Local bursting. Writing a 0 disables Local bursting. Scatter/Gather Mode. Writing a 1 indicates Scatter/Gather mode is enabled. For Scatter/Gather mode, the DMA source address, destination address, and byte count are loaded from memory in PCI or Local Address spaces. Writing a 0 indicates Block mode is enabled. Done Interrupt Enable. Writing a 1 enables interrupt when done. Writing a 0 disables the interrupt when done. If DMA Clear Count mode is enabled, the interrupt does not occur until the byte count is cleared. Local Addressing Mode. Writing a 1 holds the Local address bus constant. Writing a 0 indicates the Local address is incremented. Reserved. Memory Write and Invalidate Mode for DMA Transfers. When set to 1, the PCI 9054 performs Memory Write and Invalidate cycles to the PCI Bus. The PCI 9054 supports Memory Write and Invalidate sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or 16 is specified, the PCI 9054 performs Write transfers rather than Memory Write and Invalidate transfers. Transfers must start and end at cache line boundaries. DMA EOT# Enable. Writing a 1 enables the EOT# input pin. Writing a 0 disables the EOT# output pin. Fast/Slow Terminate Mode Select. Writing a 0 sets the PCI 9054 into Slow Terminate mode. As a result in C or J modes, BLAST# is asserted to terminate the DMA transfer. As a result in M mode, BDIP# is de-asserted at the nearest 16-byte boundary and stops the DMA transfer. Writing a 1 indicates that asserting EOT# during DMA will terminate the DMA transfer. In M mode, writing a 1 indicates BDIP# output is disabled. As a result, the PCI 9054 DMA transfer terminates immediately when EOT# is asserted. DMA Clear Count Mode. When set to 1, the byte count in each Scatter/ Gather descriptor is cleared when the corresponding DMA transfer is complete. DMA Channel 1 Interrupt Select. Writing a 1 routes the DMA Channel 1 interrupt to the PCI Bus interrupt. Writing a 0 routes the DMA Channel 1 interrupt to the Local Bus interrupt. DAC Chain Load. When set to 1, enables the descriptor to load the PCI Dual Address Cycle value. Otherwise, it uses the contents of the register. Reserved. Read Yes Yes Yes Write Yes Yes Yes Value after Reset M = 11 J = 11 C = 11 0h 1 7 Yes Yes 0 8 Yes Yes 0 9 Yes Yes 0 10 Yes Yes 0 11 12 Yes Yes Yes No 0 0 13 Yes Yes 0 14 Yes Yes 0 15 Yes Yes 0 16 Yes Yes 0 17 Yes Yes 0 18 31:19 Yes Yes Yes No 0 0h PCI 9054 Data Book v2.1 11-36 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-76. (DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address Bit 31:0 Description PCI Address Register. Indicates from where in PCI Memory space DMA transfers (reads or writes) start. Read Yes Write Yes Value after Reset 0h Register 11-77. (DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address Bit 31:0 Description Local Address Register. Indicates from where in Local Memory space DMA transfers (reads or writes) start. Read Yes Write Yes Value after Reset 0h Register 11-78. (DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes) Bit 22:0 31:23 Description DMA Transfer Size (Bytes). Indicates the number of bytes to transfer during a DMA operation. Reserved. Read Yes Yes Write Yes No Value after Reset 0h 0h Register 11-79. (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer Bit 0 1 Description Descriptor Location. Writing a 1 indicates PCI Address space. Writing a 0 indicates Local Address space. End of Chain. Writing a 1 indicates end of chain. Writing a 0 indicates not end of chain descriptor. (Same as Block mode.) Interrupt after Terminal Count. Writing a 1 causes an interrupt to be asserted after the terminal count for this descriptor is reached. Writing a 0 disables interrupts from being asserted. Direction of Transfer. Writing a 1 indicates transfers from the Local Bus to the PCI Bus. Writing a 0 indicates transfers from the PCI Bus to the Local Bus. Next Descriptor Address. Qword aligned (bits [3:0]=0000). Read Yes Yes Write Yes Yes Value after Reset 0 0 2 Yes Yes 0 3 31:4 Yes Yes Yes Yes 0 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-37 Section 11--Registers DMA Registers Section 11 Registers www..com Section 11 Registers DMA Registers Register 11-80. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Bit 0 Description Channel 0 Enable. Writing a 1 enables channel to transfer data. Writing a 0 disables the channel from starting a DMA transfer, and if in the process of transferring data, suspends the transfer (pause). Channel 0 Start. Writing a 1 causes the channel to start transferring data if the channel is enabled. Channel 0 Abort. Writing a 1 causes the channel to abort current transfer. Channel 0 Enable bit must be cleared (bit [0]=0). Sets Channel 0 Done (bit [4] = 1) when abort is complete. Channel 0 Clear Interrupt. Writing a 1 clears Channel 0 interrupts. Channel 0 Done. Reading a 1 indicates a channel transfer is complete. Reading a 0 indicates a channel transfer is not complete. Reserved. Read Yes Write Yes Value after Reset 0 1 No Yes/Set 0 2 3 4 7:5 No No Yes Yes Yes/Set Yes/Clr No No 0 0 1 000 Register 11-81. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Bit 0 Description Channel 1 Enable. Writing a 1 enables channel to transfer data. Writing a 0 disables the channel from starting a DMA transfer, and if in the process of transferring data, suspends the transfer (pause). Channel 1 Start. Writing a 1 causes channel to start transferring data if the channel is enabled. Channel 1 Abort. Writing a 1 causes channel to abort current transfer. Channel 1 Enable bit must be cleared (bit [0]=0). Sets Channel 1 Done (bit [4] = 1) when abort is complete. Channel 1 Clear Interrupt. Writing a 1 clears Channel 1 interrupts. Channel 1 Done. Reading a 1 indicates a channel transfer is complete. Reading a 0 indicates a channel transfer is not complete. Reserved. Read Yes Write Yes Value after Reset 0 1 No Yes/Set 0 2 3 4 7:5 No No Yes Yes Yes/Set Yes/Clr No No 0 0 1 000 PCI 9054 Data Book v2.1 11-38 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-82. (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration Same as "(MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/DMA Arbitration," on page 11-20. Register 11-83. (DMATHR; PCI:B0h, LOC:130h) DMA Threshold Bit 3:0 Description DMA Channel 0 PCI-to-Local Almost Full (C0PLAF). Number of full entries (divided by two, minus one) in the FIFO before requesting the Local Bus for writes. (C0PLAF+1) + (C0PLAE+1) should be a FIFO Depth of 32. DMA Channel 0 Local-to-PCI Almost Empty (C0LPAE). Number of empty entries (divided by two, minus one) in the FIFO before requesting the Local Bus for reads. (C0LPAF+1) + (C0LPAE+1) should be a FIFO depth of 32. DMA Channel 0 Local-to-PCI Almost Full (C0LPAF). Number of full entries (divided by two, minus one) in the FIFO before requesting the PCI Bus for writes. DMA Channel 0 PCI-to-Local Almost Empty (C0PLAE). Number of empty entries (divided by two, minus one) in the FIFO before requesting the PCI Bus for reads. DMA Channel 1 PCI-to-Local Almost Full (C1PLAF). Number of full entries, minus one, in the FIFO before requesting the Local Bus for writes. (C1PLAF+1) + (C1PLAE+1) should be a FIFO depth of 16. DMA Channel 1 Local-to-PCI Almost Empty (C1LPAE). Number of empty entries, minus one, in the FIFO before requesting the Local Bus for reads. (C1PLAF) + (C1PLAE) should be a FIFO depth of 16. DMA Channel 1 Local-to-PCI Almost Full (C1LPAF). Number of full entries, minus one, in the FIFO before requesting the PCI Bus for writes. DMA Channel 1 PCI-to-Local Almost Empty (C1PLAE). Number of empty entries, minus one, in the FIFO before requesting the PCI Bus for reads. Read Yes Write Yes Value after Reset 0h 7:4 Yes Yes 0h 11:8 Yes Yes 0h 15:12 Yes Yes 0h 19:16 Yes Yes 0h 23:20 Yes Yes 0h 27:24 31:28 Yes Yes Yes Yes 0h 0h Note: For DMA Channel 0 only, if number of entries needed is x, then the value is one less than half the number of entries (that is, x/2 - 1). Register 11-84. (DMADAC0; PCI:B4h, LOC:134h) DMA Channel 0 PCI Dual Address Cycle Address Bit 31:0 Description Upper 32 Bits of the PCI Dual Address Cycle PCI Address during DMA Channel 0 Cycles. If set to 0h, the PCI 9054 performs a 32-bit DMA Channel 0 Address access. Read Yes Write Yes Value after Reset 0h Register 11-85. (DMADAC1; PCI:B8h, LOC:138h) DMA Channel 1 PCI Dual Address Cycle Address Bit 31:0 Description Upper 32 Bits of the PCI Dual Address Cycle PCI Address during DMA Channel 1 Cycles. If set to 0h, the PCI 9054 performs a 32-bit DMA Channel 1 Address access. Read Yes Write Yes Value after Reset 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-39 Section 11--Registers DMA Registers Section 11 Registers www..com Section 11 Registers Messaging Queue Registers 11.7 MESSAGING QUEUE REGISTERS Register 11-86. (OPQIS; PCI:30h, LOC:B0h) Outbound Post Queue Interrupt Status Bit 2:0 3 31:4 Reserved. Outbound Post Queue Interrupt. Set when the Outbound Post Queue is not empty. Not affected by the Interrupt Mask bit. Reserved. Description Read Yes Yes Yes Write No No No Value after Reset 000 0 0h Register 11-87. (OPQIM; PCI:34h, LOC:B4h) Outbound Post Queue Interrupt Mask Bit 2:0 3 31:4 Reserved. Outbound Post Queue Interrupt Mask. Writing a 1 masks the interrupt. Reserved. Description Read Yes Yes Yes Write No Yes No Value after Reset 000 1 0h Register 11-88. (IQP; PCI:40h) Inbound Queue Port Bit Description Value written by the PCI Master is stored into the Inbound Post Queue, which is located in Local memory at the address pointed to by the Queue Base Address + Queue Size + Inbound Post Head Pointer. From the time of the PCI write until the Local Memory write and update of the Inbound Post Queue Head Pointer, further accesses to this register result in a Retry. A Local interrupt is asserted when the Inbound Post Queue is not empty. When the port is read by the PCI Master, the value is read from the Inbound Free Queue, which is located in Local memory at the address pointed to by the Queue Base Address + Inbound Free Tail Pointer. If the queue is empty, FFFFFFFh is returned. Read Write Value after Reset 31:0 PCI PCI 0h Register 11-89. (OQP; PCI:44h) Outbound Queue Port Bit Description Value written by the PCI Master is stored into the Outbound Free Queue, which is located in Local memory at the address pointed to by the Queue Base Address + 3*Queue Size + Outbound Free Head Pointer. From the time of the PCI write until the Local Memory write and update of the Outbound Free Queue Head Pointer, further accesses to this register result in a Retry. If the queue fills up, a Local NMI interrupt is asserted. When the port is read by the PCI Master, the value is read from the Outbound Post Queue, which is located in Local memory at the address pointed to by the Queue Base Address + 2*Queue Size + Outbound Post Tail Pointer. If the queue is empty, FFFFFFFh is returned. A PCI interrupt is asserted if the Outbound Post Queue is not empty. Read Write Value after Reset 31:0 PCI PCI 0h PCI 9054 Data Book v2.1 11-40 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-90. (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Bit 0 Description Queue Enable. Writing a 1 allows accesses to the Inbound and Outbound Queue ports. If cleared to 0, writes are accepted but ignored and reads return FFFFFFFFh. Circular Queue Size. Contains the size of one of the circular FIFO queues. Each of the four queues are the same size. Queue Size Encoding values: Bits [5:1] Number of entries Total size 00001 4-KB entries 64 KB 00010 8-KB entries 128 KB 00100 16-KB entries 256 KB 01000 32-KB entries 512 KB 10000 64-KB entries 1 MB Reserved. Read Yes Write Yes Value after Reset 0 5:1 Yes Yes 00001 31:6 Yes No 0h Register 11-91. (QBAR; PCI:C4h, LOC:144h) Queue Base Address Bit 19:0 31:20 Reserved. Queue Base Address. Local Memory base address of circular queues. Queues must be aligned on a 1-MB boundary. Description Read Yes Yes Write No Yes Value after Reset 0h 0h Register 11-92. (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Bit 1:0 19:2 31:20 Reserved. Inbound Free Head Pointer. Local Memory Offset for the Inbound Free Queue. Maintained by the Local CPU software. Queue Base Address. Description Read Yes Yes Yes Write No Yes No Value after Reset 00 0h 0h Register 11-93. (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Bit 1:0 19:2 31:20 Reserved. Inbound Free Tail Pointer. Local Memory offset for the Inbound Free Queue. Maintained by the hardware and incremented modulo the queue size. Queue Base Address. Description Read Yes Yes Yes Write No Yes No Value after Reset 00 0h 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-41 Section 11--Registers Messaging Queue Registers Section 11 Registers www..com Section 11 Registers Messaging Queue Registers Register 11-94. (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Bit 1:0 19:2 31:20 Reserved. Inbound Post Head Pointer. Local Memory offset for the Inbound Post Queue. Maintained by the hardware and incremented modulo the queue size. Queue Base Address. Description Read Yes Yes Yes Write No Yes No Value after Reset 00 0h 0h Register 11-95. (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Bit 1:0 19:2 31:20 Reserved. Inbound Post Tail Pointer. Local Memory offset for the Inbound Post Queue. Maintained by the Local CPU software. Queue Base Address. Description Read Yes Yes Yes Write No Yes No Value after Reset 00 0h 0h Register 11-96. (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Bit 1:0 19:2 31:20 Reserved. Outbound Free Head Pointer. Local Memory offset for the Outbound Free Queue. Maintained by the hardware and incremented modulo the queue size. Queue Base Address. Description Read Yes Yes Yes Write No Yes No Value after Reset 00 0h 0h Register 11-97. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Bit 1:0 19:2 31:20 Reserved. Outbound Free Tail Pointer. Local Memory offset for the Outbound Free Queue. Maintained by the Local CPU software. Queue Base Address. Description Read Yes Yes Yes Write No Yes No Value after Reset 00 0h 0h Register 11-98. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Bit 1:0 19:2 31:20 Reserved. Outbound Post Head Pointer. Local Memory offset for the Outbound Post Queue. Maintained by the Local CPU software. Queue Base Address. Description Read Yes Yes Yes Write No Yes No Value after Reset 00 0h 0h PCI 9054 Data Book v2.1 11-42 (c) PLX Technology, Inc. All rights reserved. www..com Register 11-99. (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Bit 1:0 19:2 31:20 Reserved. Outbound Post Tail Pointer. Local Memory offset for the Outbound Post Queue. Maintained by the hardware and incremented modulo the queue size. Queue Base Address. Description Read Yes Yes Yes Write No Yes No Value after Reset 00 0h 0h Register 11-100. (QSR; PCI:E8h, LOC:168h) Queue Status/Control Bit Description I2O Decode Enable. When set, replaces the MBOX0 and MBOX1 registers with the Inbound and Outbound Queue Port registers and redefines Space 1 as PCI Base Address 0 to be accessed by PCIBAR0. Former Space 1 registers F0, F4, and F8 should be programmed to configure their shared I2O Memory space, defined as PCI Base Address 0. Queue Local Space Select. When set to 0, use the Local Address Space 0 Bus Region descriptor for Queue accesses. When set to 1, use the Local Address Space 1 Bus Region descriptor for Queue accesses. Outbound Post Queue Prefetch Enable. Writing a 1 causes prefetching to occur from the Outbound Post Queue if it is not empty. Inbound Free Queue Prefetch Enable. Writing a 1 causes prefetching to occur from the Inbound Free Queue if it is not empty. Inbound Post Queue Interrupt Mask. Writing a 1 masks the interrupt. Inbound Post Queue Interrupt Not Empty. Set when the Inbound Post Queue is not empty. Not affected by the Interrupt Mask bit. Outbound Free Queue Overflow Interrupt Mask. When set to 0, masks the interrupt. Default is 1. Outbound Free Queue Overflow Interrupt Full. Set when the Outbound Free Queue becomes full. A Local TEA#/LSERR# (NMI) interrupt is asserted. Writing a 1 clears the interrupt. Unused. Read Write Value after Reset 0 Yes Yes 0 1 Yes Yes 0 2 3 4 5 6 Yes Yes Yes Yes Yes Yes Yes Yes No Yes 0 0 1 0 1 7 31:8 Yes Yes Yes/Clr No 0 0h PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 11-43 Section 11--Registers Messaging Queue Registers Section 11 Registers www..com www..com 12 12.1 PIN DESCRIPTION PIN SUMMARY Table 12-1 lists abbreviations used in this section to represent various pin types. Table 12-1. Pin Type Abbreviations Abbreviation I/O I O TS OC TP STS DTS Input pin only Output pin only Tri-state pin Open collector pin Totem pole pin Sustained tri-state pin, driven high for one CLK before float Driven tri-state pin, driven high for one-half CLK before float Tables in this section describe each PCI 9054 pin. Table 12-2 through Table 12-6 provide pin information common to all Local Bus modes of operation: * Power and Ground * Serial EEPROM Interface * PCI System Bus Interface * Local Bus Mode and Processor Independent Interface Pins in Table 12-7 through Table 12-9 correspond to the PCI 9054 Local Bus modes--M, C, and J: * M Bus Mode Interface Pin Description (32-bit address/32-bit data, non-multiplexed) * C Bus Mode Interface Pin Description (32-bit address/32-bit data, non-multiplexed) * J Bus Mode Interface Pin Description (32-bit address/32-bit data, multiplexed) For a visual view of the chip pinout, refer to Section 14, "Package, Signal, and Pinout Specs." The following pins have internal pull-ups: ADS#, BDIP#, BI#, BIGEND#/WAIT#, BLAST#, BTERM#, BURST#, CCS#, DMPAF/EOT#, DP[3:0]#, EEDI/EEDO, LA[31:30], LA[28:0], LAD[31:0], LBE[3:0]#, LINT#, LRESETo#, LSERR#, LW/R#, RD/WR#, MDREQ#/DMPAF/EOT#, MODE[1:0], READY#, TA#, TEA#, TS#, TSIZ[0:1], WAIT#. The TEST pin has an internal pull-down. Notes: Due to the complexity of pin multiplexing, LA[29] (C mode) or LA[2] (M mode) requires an external pull-up. In J mode, ALE requires a pull-down. M mode only: The BB# pin requires a 510 ohm external pull-up resistor for PCI 9054_AB revision. The BB# pin requires a weaker pull-up (4.7K or above) for PCI 9054_AB revision. Pin Type All Local Bus internal pull-ups go through a 100k-ohm resistor. All Local Bus internal pull-downs go through a 50k-ohm resistor. All Local I/O pins should have external pull-ups or pull-downs, which depend upon the application and pin polarity. (Use approximately 3k to 10k ohms.) This is recommended due to the weak value of the internal pull-ups and pull-downs. Unspecified pins are not connected (NC). Note for PCI Pins: DO NOT pull any pins up or down unless the PCI 9054 is being used in an embedded design. Refer to PCI Local Bus Specification, v2.1, page 123. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 12-1 Section 12--Pin Description Input and output pin www..com Section 12 Pin Description Pinout Common to All Bus Modes 12.2 PINOUT COMMON TO ALL BUS MODES Table 12-2. Power and Ground Pins (176-Pin PQFP) Total Pins 1 Symbol TEST Signal Name Test Pin Pin Type I PQFP Pin Number 155 Function Pulled high for test and low for normal operation. When pulled high: All outputs except USERo/DREQ0#/LLOCKo# and LEDon/ LEDin are placed in tri-state. USERo/DREQ0#/LLOCKo# provide NANDTREE output. Three-volt power supply pins for core and I/O buffers. Liberal .01 to .1 F decoupling capacitors should be placed near the PCI 9054. Ground pins. VDD Power (+3.3V) 15 I 1, 20, 28, 35, 45, 62, 70, 89, 99, 109, 116, 133, 141, 147, 162 19, 27, 44, 61, 69, 88, 108, 115, 132, 140, 161, 176 VSS Ground 12 I Note: The die contains 224 pads. Power and Grounds are double bounded in the PQFP package to meet proper drive strength of the buffers. Table 12-3. Power and Ground Pins (225-Pin PBGA) Total Die Pads 1 Symbol TEST Signal Name Test Pin Total Pins 1 Pin Type I PBGA Pin Number A8 Function Pulled high for test, low for normal operation. When pulled high: All outputs except USERo/DREQ0#/LLOCKo# and LEDon/LEDin are placed in tri-state. USERo/DREQ0#/ LLOCKo# provides NANDTREE output. VDD (Core) Power (+3.3V) 34 34 I A1, E2, G2, Three-volt power supply pins for core and I/O buffers. G5, H5, J4, Liberal .01 to .1 F decoupling capacitors should be J5, L2, K5, placed near the PCI 9054. R1, P5, R6, P7, L8, R9, P10, N11, R15, L13, K11, J13, J11, H12, G12, E15, A15, B12, C11, C10, D9, D8, A6, B6, D6 F8, G7, G8, Ground pins. G9, H6, H7, H8, H9, H10, J7, J8, J9, K8 VSS Ground 39 13 I PCI 9054 Data Book v2.1 12-2 (c) PLX Technology, Inc. All rights reserved. www..com Pinout Common to All Bus Modes Section 12 Pin Description Table 12-4. Serial EEPROM Interface Pins Symbol EECS Signal Name Serial EEPROM Chip Select Serial EEPROM Data IN/ Serial EEPROM Data OUT Serial Data Clock Total Pins 1 Pin Type O TP 6 mA I/O TP 6 mA O TP 6 mA PQFP Pin Number 164 PBGA Pin Number F7 Function Serial EEPROM Chip Select. EESK 1 165 B5 Serial EEPROM clock pin. Note: The serial EEPROM interface operates at core voltage (+3.3V). The PCI 9054 requires use of a serial EEPROM that can operate up to 1 MHz. Table 12-5. PCI System Bus Interface Pins Symbol AD[31:0] Signal Name Address and Data Total Pins 32 Pin Type I/O TS PCI PQFP Pin Number 173-175, 2-5, 8-15, 31-34, 36-40, 42-43, 46-51 PBGA Pin Number F6, A2, C3, D4, B1, C2, E5, D2, G6, D1, E3, F5, F4, F3, F2, J6, L1, K4, M1, M2, L4, N1, M3, N2, P1, N3, M4, R2, P3, L5, N4, R3 D3, G4, K3, K6 Function All multiplexed on the same PCI pins. The Bus transaction consists of an Address phase, followed by one or more Data phases. The PCI 9054 supports both Read and Write bursts. C/BE[3:0]# Bus Command and Byte Enables 4 I/O TS PCI 6, 16, 30, 41 All multiplexed on the same PCI pins. During the Address phase of a transaction, defines the bus command. During the Data phase, used as byte enables. Refer to the PCI spec for further details. When actively driven, indicates the driving device has decoded its address as Target of current access. As an input, indicates whether any device on the bus is selected. Interrupt output set when an adapter using the PCI 9054 is freshly inserted or ready to be removed from a PCI slot. Driven by the current Master to indicate the beginning and duration of an access. FRAME# is asserted to indicate the bus transaction is beginning. While FRAME# is asserted, Data transfers continue. When FRAME# is de-asserted, the transaction is in the final Data phase. Indicates to the agent that access to the bus is granted. Every Master has its own REQ# and GNT#. Used as a chip select during Configuration Read and Write transactions. DEVSEL# Device Select 1 I/O STS PCI O OC PCI I/O STS PCI 22 H1 ENUM# Enumeration 1 52 P4 FRAME# Cycle Frame 1 17 G3 GNT# Grant 1 I 171 C4 IDSEL Initialization Device Select 1 I 7 C1 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 12-3 Section 12--Pin Description EEDI/EEDO 1 166 C5 Multiplexed Write/Read data to a serial EEPROM pin. www..com Section 12 Pin Description Pinout Common to All Bus Modes Table 12-5. PCI System Bus Interface Pins (Continued) Symbol INTA# Signal Name Interrupt A Total Pins 1 Pin Type O OC PCI I/O STS PCI I/O STS PCI I/O TS PCI PQFP Pin Number 168 PBGA Pin Number B4 Function PCI Interrupt request. IRDY# Initiator Ready 1 18 G1 Indicates ability of the initiating agent (Bus Master) to complete the current Data phase of the transaction. Indicates an atomic operation that may require multiple transactions to complete. Even parity across AD[31:0] and C/BE[3:0]#. All PCI agents require parity generation. PAR is stable and valid one clock after the Address phase. For Data phases, PAR is stable and valid one clock after either IRDY# is asserted on a Write transaction or TRDY# is asserted on a Read transaction. Once PAR is valid, it remains valid until one clock after current Data phase completes. Provides timing for all transactions on PCI and is an input to every PCI device. The PCI 9054 operates up to 33 MHz. Reports data parity errors during all PCI transactions, except during a special cycle. Wake-up event interrupt. LOCK# Lock 1 24 J2 PAR Parity 1 29 K1 PCLK Clock 1 I 170 A3 PERR# Parity Error 1 I/O STS PCI O OC PCI O STS PCI I O OC PCI I/O STS PCI I/O STS PCI 25 J1 PME# Power Management Event Request 1 167 A4 REQ# 1 172 B3 Indicates to arbiter that this agent must use the bus. Every Master has its own GNT# and REQ#. Used to bring PCI-specific registers, sequencers, and signals to a consistent state. Reports address parity errors, data parity errors on the Special Cycle command, or any other system error where the result is catastrophic. Indicates the current Target is requesting that the Master stop the current transaction. Indicates ability of the Target agent (selected device) to complete the current Data phase of the transaction. RST# SERR# Reset Systems Error 1 1 169 26 D5 J3 STOP# Stop 1 23 H4 TRDY# Target Ready 1 21 H3 PCI 9054 Data Book v2.1 12-4 (c) PLX Technology, Inc. All rights reserved. www..com Pinout Common to All Bus Modes Section 12 Pin Description Table 12-6. Local Bus Mode and Processor Independent Interface Pins Symbol CCS# LCLK LEDon/ LEDin Signal Name Configuration Register Select Local Processor Clock LEDon/LEDin Total Pins 1 1 1 Pin Type I I I/O TS 24 mA O TP 6 mA I/O OC 12 mA PQFP Pin Number 160 142 53 PBGA Pin Number E7 D11 K7 Function Internal PCI 9054 registers are selected when CCS# is asserted low. Local clock input. As an output, acts as the Hot Swap board indicator LED. As an input, monitors the CompactPCI board latch status. Could be used to monitor PCI Bus activity. Available only on the PBGA package. As an input, when asserted low, causes PCI interrupt. As an output, a synchronous level output that remains asserted as long as an interrupt condition exists. If edge level interrupt is required, disabling and then enabling Local interrupts through INTCSR creates an edge if an interrupt condition still exists or a new interrupt condition occurs. Asserted when the PCI 9054 chip is reset. Can be used to drive RESET# input of a Local processor. Selects the PCI 9054 bus operation mode: Mode 0 Mode 1 Bus Mode 1 1 M 1 0 J 0 1 Reserved 0 0 C Multiplexed input/output pin. USERi: General-purpose input that can be read by way of the PCI 9054 Configuration registers. DACK0#: When a channel is programmed through the Configuration registers to operate in Demand mode, this output indicates a DMA transfer is being executed. DACK0# corresponds to PCI 9054 DMA Ch 0. LLOCKi#: Indicates an atomic operation that may require multiple transactions to complete. Used by the PCI 9054 for direct Local access to the PCI Bus. LFRAME# PCI Buffered FRAME# Signal Local Interrupt 1 -- G13 LINT# 1 154 B8 LRESETo# Local Bus Reset Out 1 O TP 12 mA I 152 A9 MODE[1:0] Bus Mode 2 157-156 B7, E8 1 USERi/ User Input I 159 C7 DACK0#/ Demand Mode DMA Acknowledge O TS 12 mA LLOCKi# Local Lock Input I 1 USERo/ User Output O TS 12 mA I 158 A7 Multiplexed input/output pin. USERo: General-purpose output controlled from the PCI 9054 Configuration registers. DREQ0#: When a channel is programmed through the Configuration registers to operate in Demand mode, this input serves as a DMA request. DREQ0# corresponds to the PCI 9054 DMA Ch 0. LLOCKo#: Indicates an atomic operation for a PCI Target PCI-to-Local Bus access may require multiple transactions to complete. DREQ0#/ Demand DMA Request LLOCKo# Local Lock Output O PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 12-5 Section 12--Pin Description www..com Section 12 Pin Description M Bus Mode Pinout 12.3 M BUS MODE PINOUT Table 12-7. M Bus Mode Interface Pins M Bus Mode Symbol BB# Signal Name Bus Busy Total Pins 1 Pin Type I/O OC 12 mA PQFP Pin Number 150 PBGA Pin Number C9 Function As an input, monitors this signal to determine whether the external Master has ended a Bus cycle. As an output, asserts this signal after an external arbiter has granted ownership of the Local Bus and BB# is inactive from another Master. For PCI 9054_AA revision, Signal requires an external pull-up resistor value of 510 ohms be applied to guarantee a fast transition to the inactive state when the PCI 9054_AA revision relinquishes ownership of the Local Bus. For the PCI 9054_AB revision, the pull-up resistor value must be 4.7K ohms or higher. As an input, driven by the Bus Master during a Burst transaction. The Master de-asserts before the last Data phase on the bus. As an output, driven by the PCI 9054 during the Data phase of a Burst transaction. The PCI 9054 de-asserts before the last Burst Data phase on the bus. Asserted by the Local Bus arbiter in response to BR#. Indicates the requesting Master is next. Whenever BR# is asserted, indicates that the Target device does not support Burst transactions. Multiplexed input/output pin. Can be asserted during the Local Bus Address phase of a PCI Initiator transfer or Configuration register access to specify use of Big Endian Byte ordering. Big Endian Byte order for PCI Initiator transfers or Configuration register accesses is also programmable through the Configuration registers. If wait is selected, then PCI 9054 issues WAIT# when it is a Master on the Local Bus and has internal wait states setup. As a Slave, the PCI 9054 accepts WAIT# as an input from the Bus Master. Asserted by the Master to request use of the Local Bus. The Local Bus arbiter asserts BG# when the Master is next in line for bus ownership. As an input, driven by the Master along with address and data indicating a Burst transfer is in progress. As an output, driven by the PCI 9054 along with address and data indicating a Burst transfer is in progress. Parity is even for each of up to four byte lanes on the Local Bus. Parity is checked for writes or reads to the PCI 9054. Parity is asserted for reads from or writes by the PCI 9054. DP0 is the most significant bit of the Bus address. BDIP# Burst Data in Progress 1 I/O TS 12 mA 151 B9 BG# BI# Bus Grant Burst Inhibit 1 1 1 I I 144 134 163 B11 D12 C6 BIGEND#/ Big Endian Select I WAIT# WAIT Input/Output Select (WAIT# is available at this location only in M mode) I/O TS 12 mA BR# Bus Request 1 O TP 12 mA I/O TS 12 mA 143 A12 BURST# Burst 1 148 B10 DP[0:3] Data Parity 4 I/O TS 12 mA 136-139 B13, E11, C12, A13 PCI 9054 Data Book v2.1 12-6 (c) PLX Technology, Inc. All rights reserved. www..com M Bus Mode Pinout Section 12 Pin Description Table 12-7. M Bus Mode Interface Pins (Continued) M Bus Mode Symbol LA[0:31] Signal Name Address Bus Total Pins 32 Pin Type I/O TS 12 mA PQFP Pin Number 54-60, 63-68, 71-87, 93-94 PBGA Pin Number R4, N5, L6, M6, N6, P6, M7, R7, L7, N8, R8, M8, P9, N9, L9, R10, N10, K9, R11, M10, R12, L10, M11, R13, N12, P13, K10, R14, N13, P14, L11, M13 N15, M14, J10, M15, L14, L15, K12, K13, K15, J12, J14, J15, H14, H15, H11, G14, G15, G11, F14, F13, G10, E14, E13, D15, D14, E12, C15, D13, C14, F10, B15, C13 E9 Function Carries the 32 bits of the physical Address Bus. LA0 is most significant bit of bus address. LD[0:31] Data Bus 32 I/O TS 12 mA 95-98, 100-107, 110-114, 117-131 Carries 8-, 16-, or 32-bit data quantities, depending upon the bus-width configuration. All Master accesses to the PCI 9054 are 32 bits only. LD0 is most significant bit of bus address. 1 MDREQ#/ IDMA Data Transfer Request (MDREQ# is available at this location in M mode only) PCI Initiator Programmable Almost Full End of Transfer for Current DMA Channel O TS 12 mA 153 Multiplexed input or output pin. MDREQ#: IDMA M mode Data transfer request start. Always asserted, indicating Data transfer should start. De-asserted only when the PCI Initiator FIFO becomes full. Programmable through a Configuration register. DMPAF: PCI Initiator Write FIFO Almost Full status output. Programmable through a Configuration register. EOT#: Terminates the current DMA transfer. Note: EOT# serves as a general purpose EOT. Before asserting EOT#, user should be aware of DMA channel activity. DMPAF/ O TS 12 mA I EOT# RD/WR# Read/Write 1 I/O TS 12 mA O TP 12 mA 90 M12 Asserted high for reads and low for writes. RETRY# Retry 1 149 A10 Driven by the PCI 9054 when it is a Slave to indicate a Local Master must back off and restart the cycle. In Deferred Read mode, indicates a Local Master should return for the requested data. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 12-7 Section 12--Pin Description www..com Section 12 Pin Description M Bus Mode Pinout Table 12-7. M Bus Mode Interface Pins (Continued) M Bus Mode Symbol TA# Signal Name Transfer Acknowledge Total Pins 1 Pin Type I/O DTS 12 mA PQFP Pin Number 135 PBGA Pin Number A14 Function As an input, when a Local Bus access is made to the PCI 9054, indicates a Write Data transfer can complete or that Read data on the bus is valid. As an output, when the PCI 9054 is a Bus Master, indicates a Write Data transfer is complete or that Read data on the bus is valid. Driven by the Target device, indicating an error condition occurred during a Bus cycle. Indicates the valid address and start of a new Bus access. Asserted for the first clock of a Bus access. Driven by the current Master along with the address, indicating the data-transfer size. TSIZ0 is most significant bit of bus address. Refer to Section 3.4.3.5 for further information. TEA# Transfer Error Acknowledge Address Strobe 1 I/O OC 12 mA I/O TS 12 mA I/O TS 12 mA 146 D10 TS# 1 145 A11 TSIZ[0:1] Transfer Size 2 92-91 N14, P15 PCI 9054 Data Book v2.1 12-8 (c) PLX Technology, Inc. All rights reserved. www..com C Bus Mode Pinout Section 12 Pin Description 12.4 C BUS MODE PINOUT Table 12-8. C Bus Mode Interface Pins C Bus Mode Symbol ADS# Signal Name Address Strobe Total Pins 1 Pin Type I/O TS 12 mA I PQFP Pin Number 145 PBGA Pin Number A11 Function BIGEND# Big Endian Select 1 163 C6 Can be asserted during the Local Bus Address phase of a PCI Initiator transfer or Configuration register access to specify use of Big Endian Byte ordering. Big Endian Byte order for PCI Initiator transfers or Configuration register accesses is also programmable through Configuration registers. Driven by the current Local Bus Master to indicate the last transfer in a Bus access. Asserted to indicate the Local Bus Master requires the bus. If enabled through the PCI 9054 Configuration registers, the PCI 9054 releases the bus during a DMA transfer if this signal is asserted. Asserted to indicate the PCI 9054 requires the bus to perform a PCI Target PCI-to-Local Bus access while a PCI Initiator access is pending on the Local Bus. Can be used with external logic to assert backoff to a Local Bus Master. Operational parameters are set up by way of the PCI 9054 Configuration registers. As input to the PCI 9054: For processors that burst up to four Lwords. If the Bterm Mode bit is disabled through the PCI 9054 Configuration registers, the PCI 9054 also bursts up to four Lwords. If enabled, the PCI 9054 continues to burst until BTERM# input is asserted. BTERM# is a Ready input that breaks up a Burst cycle and causes another Address cycle to occur. Used in conjunction with the PCI 9054 programmable wait state generator. As output from the PCI 9054: Asserted, along with READY#, to request break up of a burst and start of a new Address cycle (PCI Aborts only). Multiplexed input or output pin. DMPAF: PCI Initiator Write FIFO Almost Full status output. Programmable through a Configuration register. EOT#: Terminates the current DMA transfer. Note: EOT# serves as a general purpose EOT. Before asserting EOT, user should be aware of DMA channel activity. BLAST# Burst Last 1 I/O TS 12 mA I 148 B10 BREQi Bus Request 1 150 C9 BREQo Bus Request Out 1 O TP 12 mA 149 A10 BTERM# Burst Terminate 1 I/O DTS 12 mA 134 D12 1 DMPAF/ PCI Initiator Programmable Almost Full End of Transfer for Current DMA Channel O TS 12 mA I 153 E9 EOT# DP[3:0] Data Parity 4 I/O TS 12 mA 136-139 B13, E11, C12, A13 Parity is even for each of up to four byte lanes on the Local Bus. Parity is checked for writes or reads to the PCI 9054. Parity is asserted for reads from or writes by the PCI 9054. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 12-9 Section 12--Pin Description Indicates the valid address and start of a new Bus access. Asserted for the first clock of a Bus access. www..com Section 12 Pin Description C Bus Mode Pinout Table 12-8. C Bus Mode Interface Pins (Continued) C Bus Mode Symbol LA[31:2] Signal Name Address Bus Total Pins 30 Pin Type I/O TS 12 mA PQFP Pin Number 54-60, 63-68, 71-87 PBGA Pin Number R4, N5, L6, M6, N6, P6, M7, R7, L7, N8, R8, M8, P9, N9, L9, R10, N10, K9, R11, M10, R12, L10, M11, R13, N12, P13, K10, R14, N13, P14 N14, P15, L11, M13 Function Carries the upper 30 bits of the physical Address Bus. During bursts, LA[31:2] increment to indicate successive Data cycles. LBE[3:0]# Byte Enables 4 I/O TS 12 mA 92, 91, 93, 94 Encoded, based on the bus-width configuration, as follows: 32-Bit Bus The four byte enables indicate which of the four bytes are active during a Data cycle: BE3# Byte Enable 3--LD[31:24] BE2# Byte Enable 2--LD[23:16] BE1# Byte Enable 1--LD[15:8] BE0# Byte Enable 0--LD[7:0] 16-Bit Bus BE3#, BE1# and BE0# are encoded to provide BHE#, LA1, and BLE#, respectively: BE3# Byte High Enable (BHE#)--LD[15:8] BE2# not used BE1# Address bit 1 (LA1) BE0# Byte Low Enable (BLE#)--LD[7:0] 8-Bit Bus BE1# and BE0# are encoded to provide LA1 and LA0, respectively: BE3# not used BE2# not used BE1# Address bit 1 (LA1) BE0# Address bit 0 (LA0) Carries 8-, 16-, or 32-bit data quantities, depending upon a Target bus-width configuration. All Master accesses to the PCI 9054 are 32 bits only. LD[31:0] Data Bus 32 I/O TS 12 mA 95-98, 100-107, 110-114, 117-131 N15, M14, J10, M15, L14, L15, K12, K13, K15, J12, J14, J15, H14, H15, H11, G14, G15, G11, F14, F13, G10, E14, E13, D15, D14, E12, C15, D13, C14, F10, B15, C13 A12 LHOLD Hold Request 1 O TP 12 mA 143 Asserted to request use of the Local Bus. The Local Bus arbiter asserts LHOLDA when control is granted. PCI 9054 Data Book v2.1 12-10 (c) PLX Technology, Inc. All rights reserved. www..com C Bus Mode Pinout Section 12 Pin Description Table 12-8. C Bus Mode Interface Pins (Continued) C Bus Mode Symbol LHOLDA Signal Name Hold Acknowledge Total Pins 1 Pin Type I PQFP Pin Number 144 PBGA Pin Number B11 Function Asserted by the Local Bus arbiter when control is granted in response to LHOLD. Bus should not be granted to the PCI 9054 unless requested by LHOLD. LSERR# LW/R# Write/Read 1 I/O TS 12 mA I/O DTS 12 mA 90 M12 Asserted low for reads and high for writes. READY# Ready Input/Output 1 135 A14 When the PCI 9054 is a Bus Master, indicates Read data on the bus is valid or a Write Data transfer is complete. Used in conjunction with the PCI 9054 programmable wait state generator. When a Local Bus access is made to the PCI 9054, indicates the Bus Read data is valid or a Write Data transfer is complete. As an input, asserted to cause the PCI 9054 to insert wait states for Local PCI Initiator accesses to the PCI Bus. Can be thought of as a Ready input from an external Master for PCI Initiator accesses. As an output, asserted by the PCI 9054 when the internal wait state generator causes wait states. Can be thought of as an output providing PCI 9054 Ready status. WAIT# Wait Input/Output 1 I/O TS 12 mA 151 B9 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 12-11 Section 12--Pin Description System Error Interrupt Output 1 O OC 12 mA 146 D10 Synchronous level output asserted PCI Bus Target Abort bit is set (PCISR[11]=1) or Received Master Abort bit is set (PCISR[13]=1). If edge level interrupt is required, disabling and then enabling LSERR# interrupts through the interrupt/control status creates an edge if an interrupt condition still exists or a new interrupt condition occurs. www..com Section 12 Pin Description J Bus Mode Pinout 12.5 J BUS MODE PINOUT Table 12-9. J Bus Mode Interface Pins J Bus Mode Symbol ADS# Signal Name Address Strobe Total Pins 1 Pin Type I/O TS 12 mA I/O TS 12 mA I PQFP Pin Number 145 PBGA Pin Number A11 Function Indicates the valid address and start of a new Bus access. Asserted for the first clock of a Bus access. Asserted during the Address phase and de-asserted before the Data phase and before the next LCLK rising edge. Can be asserted during the Local Bus Address phase of a PCI Initiator transfer or Configuration register access to specify use of Big Endian Byte ordering. Big Endian Byte order for PCI Initiator transfers or Configuration register accesses is also programmable through the Configuration registers. Driven by the current Local Bus Master to indicate the last transfer in a Bus access. Asserted to indicate the Local Bus Master requires the bus. If enabled through the PCI 9054 Configuration registers, the PCI 9054 releases the bus during a DMA transfer if this signal is asserted. Asserted to indicate the PCI 9054 requires the bus to perform a PCI Target PCI-to-Local Bus access while a PCI Initiator access is pending on the Local Bus. Can be used with external logic to assert backoff to a Local Bus Master. Operational parameters are set up through the PCI 9054 Configuration registers. As input for processors that burst up to four Lwords. If the Bterm Mode bit is disabled through the PCI 9054 Configuration registers, the PCI 9054 also bursts up to four Lwords. If enabled, the PCI 9054 continues to burst until a BTERM# input is asserted. BTERM# is a Ready input that breaks up a Burst cycle and causes another Address cycle to occur. Used in conjunction with the PCI 9054 programmable wait state generator. As output, asserted along with READY# to request breakup of a burst and start of a new Address cycle (PCI Aborts only). Used in conjunction with DT/R# to provide control for data transceivers attached to the Local Bus. Multiplexed input or output pin. DMPAF: PCI Initiator Write FIFO Almost Full status output. Programmable through a Configuration register. EOT#: Terminates the current DMA transfer. Note: EOT# serves as a general purpose EOT. Before asserting EOT#, user should be aware of DMA channel activity. ALE Address Latch Enable 1 56 L6 BIGEND# Big Endian Select 1 163 C6 BLAST# Burst Last 1 I/O TS 12 mA I 148 B10 BREQi Bus Request 1 150 C9 BREQo Bus Request Out 1 O TP 12 mA 149 A10 BTERM# Burst Terminate 1 I/O DTS 12 mA 134 D12 DEN# Data Enable 1 O TS 12 mA 55 N5 1 DMPAF/ PCI Initiator Programmable Almost Full End of Transfer for Current DMA Channel O TS 12 mA I 153 E9 EOT# PCI 9054 Data Book v2.1 12-12 (c) PLX Technology, Inc. All rights reserved. www..com J Bus Mode Pinout Section 12 Pin Description Table 12-9. J Bus Mode Interface Pins (Continued) J Bus Mode Symbol DP[3:0] Signal Name Data Parity Total Pins 4 Pin Type I/O TS 12 mA O TS 12 mA I/O TS 12 mA PQFP Pin Number 136-139 PBGA Pin Number B13, E11, C12, A13 Function Parity is even for each of up to four byte lanes on the Local Bus. Parity is checked for writes or reads to the PCI 9054. Parity is asserted for reads from or writes by the PCI 9054. Used in conjunction with DEN# to provide control for data transceivers attached to the Local Bus. When asserted, indicates the PCI 9054 receives data. Carries the upper 27 bits of the physical Address Bus. During bursts, it is incremented to indicate successive Data cycles. The lowest two bits, LA[3:2], carry the word address of the 32-bit Memory Address. The bits are incremented during a Burst access. DT/R# Data Transmit/Receive 1 54 R4 LA[28:2] Local Address Bus 27 57-60, 63-68, 71-87 M6, N6, P6, M7, R7, L7, N8, R8, M8, P9, N9, L9, R10, N10, K9, R11, M10, R12, L10, M11, R13, N12, P13, K10, R14, N13, P14 N15, M14, J10, M15, L14, L15, K12, K13, K15, J12, J14, J15, H14, H15, H11, G14, G15, G11, F14, F13, G10, E14, E13, D15, D14, E12, C15, D13, C14, F10, B15, C13 LAD[31:0] Address/Data Bus 32 I/O TS 12 mA 95-98, 100-107, 110-114, 117-131 During an Address phase, the bus carries the upper 30 bits of the physical Address Bus. During a Data phase, the bus carries 32 bits of data. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 12-13 Section 12--Pin Description www..com Section 12 Pin Description J Bus Mode Pinout Table 12-9. J Bus Mode Interface Pins (Continued) J Bus Mode Symbol LBE[3:0]# Signal Name Byte Enables Total Pins 4 Pin Type I/O TS 12 mA PQFP Pin Number 92, 91, 93, 94 PBGA Pin Number N14, P15, L11, M13 Function Encoded, based on the bus-width configuration, as follows: 32-Bit Bus The four byte enables indicate which of the four bytes are active during a Data cycle: BE3# Byte Enable 3--LAD[31:24] BE2# Byte Enable 2--LAD[23:16] BE1# Byte Enable 1--LAD[15:8] BE0# Byte Enable 0--LAD[7:0] 16-Bit Bus BE3#, BE1# and BE0# are encoded to provide BHE#, LAD1, and BLE#, respectively: BE3# Byte High Enable (BHE#)--LAD[15:8] BE2# not used BE1# Address bit 1 (LAD1) BE0# Byte Low Enable (BLE#)--LAD[7:0] 8-Bit Bus BE1# and BE0# are encoded to provide LAD1 and LAD0, respectively: BE3# not used BE2# not used BE1# Address bit 1 (LAD1) BE0# Address bit 0 (LAD0) Asserted to request use of the Local Bus. The Local Bus arbiter asserts LHOLDA when control is granted. Asserted by the Local Bus arbiter when control is granted in response to LHOLD. The bus should not be granted to the PCI 9054 unless requested by LHOLD. Asserted low for reads and high for writes. LHOLD Hold Request 1 O TP 12 mA I 143 A12 LHOLDA Hold Acknowledge 1 144 B11 LW/R# Write/Read 1 I/O TS 12 mA O OC 12 mA 90 M12 LSERR# System Error Interrupt Output 1 146 D10 Synchronous level output asserted the PCI Bus Target Abort bit is set (PCISR[11]=1) or the Received Master Abort bit is set (PCISR[13]=1). If the edge level interrupt is required, disabling and then enabling LSERR# interrupts through the interrupt/control status creates an edge if an interrupt condition still exists or a new interrupt condition occurs. When the PCI 9054 is Bus Master, indicates the Read data on the bus is valid or a Write Data transfer is complete. Used in conjunction with the PCI 9054 programmable wait state generator. When a Local Bus access is made to the PCI 9054, indicates the bus Read data is valid or a Write Data transfer is complete. As an input, asserted to cause the PCI 9054 to insert wait states for Local PCI Initiator accesses to the PCI Bus. Can be thought of as a Ready input from an external Master for PCI Initiator accesses. As an output, asserted by the PCI 9054 when the internal wait state generator causes wait states. Can be thought of as an output providing PCI 9054 Ready status. READY# Ready Input/Output 1 I/O DTS 12 mA 135 A14 WAIT# Wait Input/Output 1 I/O TS 12 mA 151 B9 PCI 9054 Data Book v2.1 12-14 (c) PLX Technology, Inc. All rights reserved. www..com NANDTREE Test Access Method Section 12 Pin Description 12.6 NANDTREE TEST ACCESS METHOD NANDTREE, the method used by PLX, is a serial interconnection of NAND gates that are used only for testing shorts, opens, and bridging faults of installed devices on a board. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 12-15 Section 12--Pin Description Manufacturing Test (the proper soldering of components to a board) is the first step toward a successful product release. Some silicon vendors provide Joint Test Action Group (JTAG), while other silicon vendors provide an alternative method, NANDTREE, to achieve the same goal. NANDTREE, as well JTAG, provide users with a methodology to verify connectivity between the board and the components. JTAG, by comparison, is a boundary-scan test, or Design for Test (DFT) technique, that simplifies printed circuit board testing, using a standard chipboard test interface. This standard is known as the IEEE Standard Test Access Port and Boundary Scan Architecture. JTAG is a group that initiated the standardization of this test interface. The PCI 9054 supports the NANDTREE method for this verification methodology. The PCI 9054 NANDTREE is an internal, serial interconnection of all functional pins to provide a convenient method for board manufacturers to check connectivity of package pins to the board. To perform a NANDTREE check, all NANDTREEconnected pins must be forced high "1", as well as a TEST pin, to enable NANDTREE functionality. www..com Section 12 Pin Description NANDTREE Test Access Method Table 12-10. Sequential Interconnection of the PCI 9054 NANDTREE (Pin Definition) Component Name IN2 _INV1 NA2 _NAND1 NA2 _NAND2 NA2 _NAND3 NA2 _NAND4 NA2 _NAND5 NA2 _NAND6 NA2 _NAND7 NA2 _NAND8 NA2 _NAND9 NA2 _NAND10 NA2 _NAND11 NA2 _NAND12 NA2 _NAND13 NA2 _NAND14 NA2 _NAND15 NA2 _NAND16 NA2 _NAND17 NA2 _NAND18 NA2 _NAND19 NA2 _NAND20 NA2 _NAND21 NA2 _NAND22 NA2 _NAND23 NA2 _NAND24 NA2 _NAND25 NA2 _NAND26 NA2 _NAND27 NA2 _NAND28 NA2 _NAND29 NA2 _NAND30 NA2 _NAND31 NA2 _ NAND32 NA2 _NAND33 NA2 _NAND34 NA2 _NAND35 NA2 _NAND36 NA2 _NAND37 NA2 _NAND38 NA2 _NAND39 NA2 _NAND40 NA2 _NAND41 NA2 _NAND42 (.A(LA[31]), (.A1(LA[30]), (.A1(LA[29]), (.A1(LA[28]), (.A1(LA[27]), (.A1(LA[26]), (.A1(LA[25]), (.A1(LA[24]), (.A1(LA[23]), (.A1(LA[22]), (.A1(LA[21]), (.A1(LA[20]), (.A1(LA[19]), (.A1(LA[18]), (.A1(LA[17]), (.A1(LA[16]), (.A1(LA[15]), (.A1(LA[14]), (.A1(LA[13]), (.A1(LA[12]), (.A1(LA[11]), (.A1(LA[10]), (.A1(LA[9]), (.A1(LA[8]), (.A1(LA[7]), (.A1(LA[6]), (.A1(LA[5]), (.A1(LA[4]), (.A1(LA[3]), (.A1(LA[2]), (.A1(LBE[1]#/LA[1]), (.A1(LBE[0]#/LA[0]), (.A1(LAD[31]/LD[31]), (.A1(LAD[30]/LD[30]), (.A1(LAD[29]/LD[29]), (.A1(LAD[28]/LD[28]), (.A1(LAD[27]/LD[27]), (.A1(LAD[26]/LD[26]), (.A1(LAD[25]/LD[25]), (.A1(LAD[24]/LD[24]), (.A1(LAD[23]/LD[23]), (.A1(LAD[22]/LD[22]), (.A1(LAD[21]/LD[21]), Input #1 -- .A2(NAN0), .A2(NAN1), .A2(NAN2), .A2(NAN3), .A2(NAN4), .A2(NAN5), .A2(NAN6), .A2(NAN7), .A2(NAN8), .A2(NAN9), Input #2 .X(NAN0)); .X(NAN1)); .X(NAN2)); .X(NAN3)); .X(NAN4)); .X(NAN5)); .X(NAN6)); .X(NAN7)); .X(NAN8)); .X(NAN9)); .X(NAN10)); .X(NAN11)); .X(NAN12)); .X(NAN13)); .X(NAN14)); .X(NAN15)); .X(NAN16)); .X(NAN17)); .X(NAN18)); .X(NAN19)); .X(NAN20)); .X(NAN21)); .X(NAN22)); .X(NAN23)); .X(NAN24)); .X(NAN25)); .X(NAN26)); .X(NAN27)); .X(NAN28)); .X(NAN29)); .X(NAN30)); .X(NAN31)); .X(NAN32)); .X(NAN33)); .X(NAN34)); .X(NAN35)); .X(NAN36)); .X(NAN37)); .X(NAN38)); .X(NAN39)); .X(NAN40)); .X(NAN41)); .X(NAN42)); Output .A2(NAN10), .A2(NAN11), .A2(NAN12), .A2(NAN13), .A2(NAN14), .A2(NAN15), .A2(NAN16), .A2(NAN17), .A2(NAN18), .A2(NAN19), .A2(NAN20), .A2(NAN21), .A2(NAN22), .A2(NAN23), .A2(NAN24), .A2(NAN25), .A2(NAN26), .A2(NAN27), .A2(NAN28), .A2(NAN29), .A2(NAN30), .A2(NAN31), .A2(NAN32), .A2(NAN33), .A2(NAN34), .A2(NAN35), .A2(NAN36), .A2(NAN37), .A2(NAN38), .A2(NAN39), .A2(NAN40), .A2(NAN41), PCI 9054 Data Book v2.1 12-16 (c) PLX Technology, Inc. All rights reserved. www..com NANDTREE Test Access Method Section 12 Pin Description Table 12-10. Sequential Interconnection of the PCI 9054 NANDTREE (Pin Definition) (Continued) Component Name NA2 _NAND43 NA2 _NAND44 NA2 _NAND45 NA2 _NAND46 NA2 _NAND47 NA2 _NAND48 NA2 _NAND49 NA2 _NAND50 NA2 _NAND51 NA2 _NAND52 NA2 _NAND53 NA2 _NAND54 NA2 _NAND55 NA2 _NAND56 NA2 _NAND57 NA2 _NAND58 NA2 _NAND59 NA2 _NAND60 NA2 _NAND61 NA2 _NAND62 NA2 _NAND63 NA2 _NAND64 NA2 _NAND65 NA2 _NAND66 NA2 _NAND67 NA2 _NAND68 NA2 _NAND69 NA2 _NAND70 NA2 _NAND71 NA2 _NAND72 NA2 _NAND73 NA2 _NAND74 NA2 _NAND75 NA2 _NAND76 NA2 _NAND77 NA2 _NAND78 NA2 _NAND79 NA2 _NAND80 NA2 _NAND81 NA2 _NAND82 NA2 _NAND83 NA2 _NAND84 NA2 _NAND85 NA2 _NAND86 Input #1 (.A1(LAD[20]/LD[20]), (.A1(LAD[19]/LD[19]), (.A1(LAD[18]/LD[18]), (.A1(LAD[17]/LD[17]), (.A1(LAD[16]/LD[16]), (.A1(LAD[15]/LD[15]), (.A1(LAD[14]/LD[14]), (.A1(LAD[13]/LD[13]), (.A1(LAD[12]/LD[12]), (.A1(LAD[11]/LD[11]), (.A1(LAD[10]/LD[10]), (.A1(LAD[9]/LD[9]), (.A1(LAD[8]/LD[8]), (.A1(LAD[7]/LD[7]), (.A1(LAD[6]/LD[6]), (.A1(LAD[5]/LD[5]), (.A1(LAD[4]/LD[4]), (.A1(LAD[3]/LD[3]), (.A1(LAD[2]/LD[2]), (.A1(LAD[1]/LD[1]), (.A1(LAD[0]/LD[0]), (.A1(AD[31]), (.A1(AD[30]), (.A1(AD[29]), (.A1(AD[28]), (.A1(AD[27]), (.A1(AD[26]), (.A1(AD[25]), (.A1(AD[24]), (.A1(AD[23]), (.A1(AD[22]), (.A1(AD[21]), (.A1(AD[20]), (.A1(AD[19]), (.A1(AD[18]), (.A1(AD[17]), (.A1(AD[16]), (.A1(AD[15]), (.A1(AD[14]), (.A1(AD[13]), (.A1(AD[12]), (.A1(AD[11]), (.A1(AD[10]), (.A1(AD[9]), Input #2 .A2(NAN42), .A2(NAN43), .A2(NAN44), .A2(NAN45), .A2(NAN46), .A2(NAN47), .A2(NAN48), .A2(NAN49), .A2(NAN50), .A2(NAN51), .A2(NAN52), .A2(NAN53), .A2(NAN54), .A2(NAN55), .A2(NAN56), .A2(NAN57), .A2(NAN58), .A2(NAN59), .A2(NAN60), .A2(NAN61), .A2(NAN62), .A2(NAN63), .A2(NAN64), .A2(NAN65), .A2(NAN66), .A2(NAN67), .A2(NAN68), .A2(NAN69), .A2(NAN70), .A2(NAN71), .A2(NAN72), .A2(NAN73), .A2(NAN74), .A2(NAN75), .A2(NAN76), .A2(NAN77), .A2(NAN78), .A2(NAN79), .A2(NAN80), .A2(NAN81), .A2(NAN82), .A2(NAN83), .A2(NAN84), .A2(NAN85), .X(NAN43)); .X(NAN44)); .X(NAN45)); .X(NAN46)); .X(NAN47)); .X(NAN48)); .X(NAN49)); .X(NAN50)); .X(NAN51)); .X(NAN52)); .X(NAN53)); .X(NAN54)); .X(NAN55)); .X(NAN56)); .X(NAN57)); .X(NAN58)); .X(NAN59)); .X(NAN60)); .X(NAN61)); .X(NAN62)); .X(NAN63)); .X(NAN64)); .X(NAN65)); .X(NAN66)); .X(NAN67)); .X(NAN68)); .X(NAN69)); .X(NAN70)); .X(NAN71)); .X(NAN72)); .X(NAN73)); .X(NAN74)); .X(NAN75)); .X(NAN76)); .X(NAN77)); .X(NAN78)); .X(NAN79)); .X(NAN80)); .X(NAN81)); .X(NAN82)); .X(NAN83)); .X(NAN84)); .X(NAN85)); .X(NAN86)); Output PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 12-17 Section 12--Pin Description www..com Section 12 Pin Description NANDTREE Test Access Method Table 12-10. Sequential Interconnection of the PCI 9054 NANDTREE (Pin Definition) (Continued) Component Name NA2 _NAND87 NA2 _NAND88 NA2 _NAND89 NA2 _NAND90 NA2 _NAND91 NA2 _NAND92 NA2 _NAND93 NA2 _NAND94 NA2 _NAND95 NA2 _NAND96 NA2 _NAND97 NA2 _NAND98 NA2 _NAND99 NA2 _NAND100 NA2 _NAND101 NA2 _NAND102 NA2 _NAND103 NA2 _NAND104 NA2 _NAND105 NA2 _NAND106 NA2 _NAND107 NA2 _NAND108 NA2 _NAND109 NA2 _NAND110 NA2 _NAND111 NA2 _NAND112 NA2 _NAND113 NA2 _NAND114 NA2 _NAND115 NA2 _NAND116 NA2 _NAND117 NA2 _NAND118 NA2 _NAND119 NA2 _NAND120 NA2 _NAND121 NA2 _NAND122 NA2 _NAND123 NA2 _NAND124 NA2 _NAND125 NA2 _NAND126 NA2 _NAND127 NA2 _NAND128 NA2 _NAND129 NA2 _NAND130 (.A1(AD[8]), (.A1(AD[7]), (.A1(AD[6]), (.A1(AD[5]), (.A1(AD[4]), (.A1(AD[3]), (.A1(AD[2]), (.A1(AD[1]), (.A1(AD[0]), (.A1(RETRY#/BREQo), (.A1(BB#/BREQi), (.A1(BI#/BTERM#), (.A1(TA#/READY#), (.A1(LINT#), (.A1(BG#/LHOLDA), (.A1(RDWR#/LW/R#), (.A1(TS#/ADS#), (.A1(BURST#/BLAST#), (.A1(USERi/DACK0#/LLOCKi#), (.A1(CCS#), (.A1(MODE0), (.A1(MODE1), (.A1(TSIZ[1]/LBE[2]#), (.A1(TSIZ[0]/LBE[3]#), (.A1(WAIT#/BDIP#), (.A1(DP[0]), (.A1(DP[1]), (.A1(DP[2]), (.A1(DP[3]), (.A1(MDREQ#/DMPAF/EOT#), (.A1(BR#/LHOLD), (.A1(LRESETo#), (.A1(TEA#/LSERR#), (.A1(FRAME#), (.A1(IRDY#), (.A1(DEVSEL#), (.A1(TRDY#), (.A1(STOP#), (.A1(PAR), (.A1(SERR#), (.A1(LOCK#), (.A1(GNT#), (.A1(IDSEL), (.A1(CBE[0]#), Input #1 Input #2 .A2(NAN86), .A2(NAN87), .A2(NAN88), .A2(NAN89), .A2(NAN90), .A2(NAN91), .A2(NAN92), .A2(NAN93), .A2(NAN94), .A2(NAN95), .A2(NAN96), .A2(NAN97), .A2(NAN98), .A2(NAN99), .A2(NAN100), .A2(NAN101), .A2(NAN102), .A2(NAN103), .A2(NAN104), .A2(NAN105), .A2(NAN106), .A2(NAN107), .A2(NAN108), .A2(NAN109), .A2(NAN110), .A2(NAN111), .A2(NAN112), .A2(NAN113), .A2(NAN114), .A2(NAN115), .A2(NAN116), .A2(NAN117), .A2(NAN118), .A2(NAN119), .A2(NAN120), .A2(NAN121), .A2(NAN122), .A2(NAN123), .A2(NAN124), .A2(NAN125), .A2(NAN126), .A2(NAN127), .A2(NAN128), .A2(NAN129), .X(NAN87)); .X(NAN88)); .X(NAN89)); .X(NAN90)); .X(NAN91)); .X(NAN92)); .X(NAN93)); .X(NAN94)); .X(NAN95)); .X(NAN96)); .X(NAN97)); .X(NAN98)); .X(NAN99)); Output .X(NAN100)); .X(NAN101)); .X(NAN102)); .X(NAN103)); .X(NAN104)); .X(NAN105)); .X(NAN106)); .X(NAN107)); .X(NAN108)); .X(NAN109)); .X(NAN110)); .X(NAN111)); .X(NAN112)); .X(NAN113)); .X(NAN114)); .X(NAN115)); .X(NAN116)); .X(NAN117)); .X(NAN118)); .X(NAN119)); .X(NAN120)); .X(NAN121)); .X(NAN122)); .X(NAN123)); .X(NAN124)); .X(NAN125)); .X(NAN126)); .X(NAN127)); .X(NAN128)); .X(NAN129)); .X(NAN130)); PCI 9054 Data Book v2.1 12-18 (c) PLX Technology, Inc. All rights reserved. www..com NANDTREE Test Access Method Section 12 Pin Description Table 12-10. Sequential Interconnection of the PCI 9054 NANDTREE (Pin Definition) (Continued) Component Name NA2 _NAND131 NA2 _NAND132 NA2 _NAND133 NA2 _NAND134 NA2 _NAND135 NA2 _NAND136 NA2 _NAND137 NA2 _NAND138 NA2 _NAND139 NA2 _NAND140 NA2 _NAND141 NA2 _NAND142 NA2 _NAND143 Input #1 (.A1(CBE[1]#), (.A1(CBE[2]#), (.A1(CBE[3]#), (.A1(REQ#), (.A1(RST#), (.A1(INTA#), (.A1(PME#), (.A1(BIGEND#/WAIT#), (.A1(PERR#), (.A1(EECS), (.A1(EESK), (.A1(EEDI/EEDO), (.A1(ENUM#), Input #2 .A2(NAN130), .A2(NAN131), .A2(NAN132), .A2(NAN133), .A2(NAN134), .A2(NAN135), .A2(NAN136), .A2(NAN137), .A2(NAN138), .A2(NAN139), .A2(NAN140), .A2(NAN141), .A2(NAN142), Output .X(NAN131)); .X(NAN132)); .X(NAN133)); .X(NAN134)); .X(NAN135)); .X(NAN136)); .X(NAN137)); .X(NAN138)); .X(NAN139)); .X(NAN140)); .X(NAN141)); .X(NAN142)); .X(USERo/DREQ0#/LLOCKo#)); PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 12-19 Section 12--Pin Description www..com www..com 13 13.1 ELECTRICAL SPECIFICATIONS GENERAL ELECTRICAL SPECIFICATIONS Table 13-1. Absolute Maximum Ratings Specification Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Input Voltage (VIN) Output Voltage (VOUT) Maximum Package Power Dissipation (176-Pin PQFP) Maximum Package Power Dissipation (225-Pin PBGA) -55 to +125 C -40 to +85 C -0.5 to +4.6V VSS -0.5 to 5.5V VSS -0.5V to VDD +0.5 1.0W 1.0W Maximum Rating Table 13-2. Operating Ranges Min VSS Max VDD -40 to +85 C 3.0 to 3.6V Table 13-3. Capacitance (Sample Tested Only) Parameter Test Conditions Pin Type Typical CIN COUT VIN = 0V VOUT = 0V Input Output 4 6 Value Maximum 6 10 Units pF pF The following table lists the package thermal resistance (j-a). Table 13-4. Thermal Resistance of Packages Package Type 0m 176-Pin PQFP 225-Pin PBGA 65 (C/W) 72 (C/W) Air Flow 1m 45 46 2m 35 37 3m 30 32 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 13-1 Section 13--Electrical Specs Ambient Temperature Supply Voltage (VDD) Input Voltage (VIN) www..com Section 13 Electrical Specifications General Electrical Specifications Table 13-5. Electrical Characteristics over Operating Range Parameter Description Output High Voltage Output Low Voltage Input High Level Input Low Level PCI 3.3V Output High Voltage PCI 3.3V Output Low Voltage PCI 3.3V Input High Level PCI 3.3V Input Low Level Input Leakage Current DC Current Per Pin During Pre-Charge Tri-State Output Leakage Current VDD = Min VIN = VIH or VIL IOL = 1500 A -- 0.1 VDD V VDD = Min VIN = VIH or VIL Test Conditions Min Max Units VOH IOH = -12.0 mA 2.4 -- V VOL IOL = 12 mA -- 0.4 V VIH -- -- 2.0 5.5 V VIL -- -- -0.5 0.8 V VOH3 IOH = -500 A 0.9 VDD -- V VOL3 VIH3 -- -- 0.5 VDD VDD +0.5 V VIL3 -- -- -0.5 0.3 VDD V IIL VSS VIN VDD, VDD = Max -10 +10 A ILPC VP = 0.8 to 1.2V -- 1.0 mA IOZ VDD = Max -10 +10 A ICC Power Supply Current1 VDD=3.6V, PCLK = 33 MHz, LCLK = 50 MHz 120 outputs switching simultaneously -- 200 mA ICCL ICCH ICCZ 1. Quiescent Power Supply Current VCC = Max VIN = GND or VCC -- 50 A ILPC is the DC current flowing from VDD to Ground during precharge, as both PMOS and NMOS devices remain on during precharge. It is not the leakage current flowing into or out of the pin under precharge. Maximum value based upon 120 simultaneously switching outputs. PCI 9054 Data Book v2.1 13-2 (c) PLX Technology, Inc. All rights reserved. www..com Local Inputs Section 13 Electrical Specifications 13.2 LOCAL INPUTS Local Clock T T Inputs SETUP HO LD Valid Figure 13-1. PCI 9054 Local Input Setup and Hold Waveform Table 13-6. AC Electrical Characteristics (Local Inputs) over Operating Range (M Mode) Signals (Synchronous Inputs) CL = 50 pF, Vcc = 3.0V, Ta = 85 C BB# BDIP#/WAIT# BG# BI# BIGEND#/WAIT# BURST# CCS# DP[0:3] LA[0:31] LD[0:31] MDREQ#/DMPAF/EOT# RD/WR# TA# TS# TSIZ[0:1] USERi/DACK0#/LLOCKi# USERo/DREQ0#/LLOCKo# 5.0 1 6.0 7.0 9.0 7.0 6.0 1.5 3.0 6.0 3.5 8.5 (EOT#) 6.0 8.0 5.0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6.0 7.0 (LLOCKi#) 7.0 (DREQ0#) Input Clocks Local Clock Input Frequency PCI Clock Input Frequency Min 0 0 Max 50 MHz 33 MHz PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 13-3 Section 13--Electrical Specs TSETUP (ns) (WORST CASE) THOLD (ns) (WORST CASE) www..com Section 13 Electrical Specifications Local Inputs Table 13-7. AC Electrical Characteristics (Local Inputs) over Operating Range (C and J Modes) Signals (Synchronous Inputs) CL = 50 pF, Vcc = 3.0V, Ta = 85 C ADS# ALE BIGEND# BLAST# BREQi BTERM# CCS# DMPAF/EOT# DP[3:0] LAD[31:0] LBE[3:0]# LD[31:0] LHOLDA LW/R# READY# USERi/DACK0#/LLOCKi# USERo/DREQ0#/LLOCKo# WAIT# Bus Mode C, J J C, J C, J C, J C, J C, J C, J C, J J C, J C C, J C, J C, J C, J C, J C, J TSETUP (ns) (WORST CASE) 5.0 3.5 7.0 6.5 5.0 9.5 1.5 8.5 (EOT#) 3.0 6.5 9.0 3.5 7.0 8.5 9.5 7.0 (LLOCKi#) 7.0 (DREQ0#) 7.0 THOLD (ns) (WORST CASE) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Input Clocks Local Clock Input Frequency PCI Clock Input Frequency Bus Mode C, J C, J Min 0 0 Max 50 MHz 33 MHz PCI 9054 Data Book v2.1 13-4 (c) PLX Technology, Inc. All rights reserved. www..com Local Outputs Section 13 Electrical Specifications 13.3 LOCAL OUTPUTS Local Clock T V A L ID (MAX) T V A L ID (MIN) Outputs Valid Figure 13-2. PCI 9054 Local Output Delay Table 13-8. AC Electrical Characteristics (Local Outputs) over Operating Range (M Mode) Signals (Synchronous Outputs) CL = 50 pF, Vcc = 3.0V, Ta = 85 C BB# BDIP# BI# BIGEND#/WAIT# BR# BURST# DP[0:3] LA[0:31] LD[0:31] MDREQ#/DMPAF/EOT# RD/WR# RETRY# TA# TEA# TS# TSIZ[0:1] USERi/DACK0#/LLOCKi# USERo/DREQ0#/LLOCKo# Notes: All TVALID (Min) values are greater than 5 ns. Clock to Out Worst Case (ns) TVALID (Max) 9.5 10.5 9.0 10.5 (WAIT#) 10.0 10.5 10.0 10.0 11.0 13.0 (MDREQ#/DMPAF) 12.0 9.0 9.0 8.5 10.0 10.0 10.5 (DACK0#) 9.5 (USERo/LLOCKo#) Timing derating for loading is 35 PS/PF. PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 13-5 Section 13--Electrical Specs www..com Section 13 Electrical Specifications Local Outputs Table 13-9. AC Electrical Characteristics (Local Outputs) over Operating Range (C and J Modes) Signals (Synchronous Outputs) CL = 50 pF, Vcc = 3.0V, Ta = 85 C ADS# BLAST# BREQo BTERM# DEN# DMPAF/EOT# DP[3:0] DT/R# LA[31:2] LA[28:2] LAD[31:0] LBE[3:0]# LD[31:0] LHOLD LSERR# LW/R# READY# USERi/DACK0#/LLOCKi# USERo/DREQ0#/LLOCKo# WAIT# Notes: All TVALID (Min) values are greater than 5 ns. Bus Mode C, J C, J C, J C, J J C, J C, J J C J J C, J C C, J C, J C, J C, J C, J C, J C, J Output TVALID (Max) 10.0 12.5 8.5 10.0 10.0 13.0 (DMPAF) 10.0 12.5 10.0 9.5 11.0 10.0 11.0 10.0 8.5 12.0 9.5 10.5 (DACK0#) 9.5 (USERo/LLOCKo#) 10.5 Timing derating for loading is 35 PS/PF. Local 1.5V Clock 1.5V Max. 24.2 ns Max. 11.6 ns Max. 9.1 ns Address Bus Figure 13-3. PCI 9054 ALE Output Delay to the Local Clock PCI 9054 Data Book v2.1 13-6 (c) PLX Technology, Inc. All rights reserved. www..com 14 14.1 PACKAGE, SIGNAL, AND PINOUT SPECS 176-PIN PQFP HD For 176 PQFP, JC = 5 C/watt 132 D 89 133 88 Index 176 45 1 e Topside View b 44 q2 AMAX A2 R1 R C q L2 L1 L A1 q3 Cross-Section View Figure 14-1. 176-Pin PQFP Package Mechanical Dimensions--Topside and Cross-Section Views Table 14-1. 176-Pin PQFP Package Mechanical Dimensions Section 14--Physical Specs 14-1 Lead Type STD (QfP18-176 Pin STD) Dimensions (in Millimeters) Symbol Min. Nom. E D A A1 A2 e b C q L L1 L2 He Hd 2 3 R R1 23.9 23.9 -- -- 2.6 -- 0.15 0.1 0 0.3 -- -- 25.6 25.6 -- -- -- -- 24 24 -- 0.1 2.7 0.5 0.2 0.15 -- 0.5 1 0.5 26 26 15 15 0.2 0.2 HE E Max. 24.1 24.1 3 -- 2.8 -- 0.3 0.2 10 0.7 -- -- 26.4 26.4 -- -- -- -- PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. www..com Section 14 Package, Signal, and Pinout Specs 176-Pin PQFP 0.30 mm (0.012 in) Metal Pad 1.00 mm (0.040 in) Solder Mask Keepout Area Fiducial 2.54 mm (0.100 in) 1.50 mm (0.060 in) B = 27.18 mm (1.070 in) Fiducial P = 0.50 mm A = 27.18 mm (1.070 in) Note: Leave 0.002 inch solder mask clearance around pads. Figure 14-2. 176-Pin PQFP PCB Layout Suggested Land Pattern PCI 9054 Data Book v2.1 14-2 (c) PLX Technology, Inc. All rights reserved. www..com 176-Pin PQFP Section 14 Package, Signal, and Pinout Specs VDD VDD BTERM# BI# READY# TA# DP3 DP0 DP2 DP1 DP1 DP2 DP0 DP3 VSS VSS VDD VDD LCLK LCLK LHOLD BR# LHOLDA BG# ADS# TS# LSERR# TEA# VDD VDD BLAST# BURST# BREQo RETRY# BREQi BB# WAIT# BDIP# LRESETo# LRESETo# # MDREQ#/DMPAF/EOT DMPAF/EOT# LINT# TEST MODE0 MODE1 LINT# TEST MODE0 MODE1 USERo/DREQ0#/LLOCKo# USERo/DREQ0#/LLOCKo# USERo/DREQ0#/LLOCKo# USERi/DACK0#/LLOCKi# USERi/DACK0#/LLOCKi# USERi/DACK0#/LLOCK i# CCS# VSS VDD BIGEND#/WAIT# EECS EESK EEDI/EEDO PME# INTA# RST# PCLK GNT# REQ# AD31 AD30 AD29 VSS CCS# VSS VDD BIGEND# EECS EESK EEDI/EEDO PME# INTA# RST# PCLK GNT# REQ# AD31 AD30 AD29 VSS M C J VDD AD28 AD27 AD26 AD25 C/BE3# IDSEL AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 C/BE2# FRAME# IRDY# VSS VDD TRDY# DEVSEL# STOP# LOCK# PERR# SERR# VSS VDD PAR C/BE1# AD16 AD15 AD14 AD13 VDD AD12 AD11 AD10 AD09 AD08 C/BE0# AD07 AD06 VSS VDD AD28 AD27 AD26 AD25 C/BE3# IDSEL AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 C/BE2# FRAME# IRDY# VSS VDD TRDY# DEVSEL# STOP# LOCK# PERR# SERR# VSS VDD PAR C/BE1# AD16 AD15 AD14 AD13 VDD AD12 AD11 AD10 AD09 AD08 C/BE0# AD07 AD06 VSS VDD AD28 AD27 AD26 AD25 C/BE3# IDSEL AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 C/BE2# FRAME# IRDY# VSS VDD TRDY# DEVSEL# STOP# LOCK# PERR# SERR# VSS VDD PAR C/BE1# AD16 AD15 AD14 AD13 VDD AD12 AD11 AD10 AD09 AD08 C/BE0# AD07 AD06 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VDD BTERM# READY# DP3 DP2 DP1 DP0 VSS VDD LCLK LHOLD LHOLDA ADS# LSERR# VDD BLAST# BREQo BREQi WAIT# LRESETo# DMPAF/EOT# LINT# TEST MODE0 MODE1 Figure 14-3. 176-Pin PQFP PCI 9054 Pinout PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 14-3 Section 14--Physical Specs CCS# VSS VDD BIGEND# EECS EESK EEDI/EEDO PME# INTA# RST# PCLK GNT# REQ# AD31 AD30 AD29 VSS 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 PCI 9054 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 VSS LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 VDD VSS LAD15 LAD16 LAD17 LAD18 LAD19 VDD VSS LAD20 LAD21 LAD22 LAD23 LAD24 LAD25 LAD26 LAD27 VDD LAD28 LAD29 LAD30 LAD31 LBE0# LBE1# LBE3# LBE2# LW/R# VDD VSS LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 VDD VSS LD15 LD16 LD17 LD18 LD19 VDD VSS LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 VDD LD28 LD29 LD30 LD31 LBE0# LBE1# LBE3# LBE2# LW/R# VDD VSS LD31 LD30 LD29 LD28 LD27 LD26 LD25 LD24 LD23 LD22 LD21 LD20 LD19 LD18 LD17 VDD VSS LD16 LD15 LD14 LD13 LD12 VDD VSS LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 VDD LD3 LD2 LD1 LD0 LA31 LA30 TSIZ0 TSIZ1 RD/WR# VDD 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 VSS LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 VDD VSS LA19 LA20 LA21 LA22 LA23 LA24 VDD VSS LA25 LA26 LA27 LA28 ALE DEN# DT/R# LEDon/LEDin ENUM# AD0 AD1 AD2 AD3 AD4 AD5 VDD VSS LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 VDD VSS LA19 LA20 LA21 LA22 LA23 LA24 VDD VSS LA25 LA26 LA27 LA28 LA29 LA30 LA31 LEDon/LEDin ENUM# AD0 AD1 AD2 AD3 AD4 AD5 VDD VSS LA29 LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LA15 LA14 LA13 VDD VSS LA12 LA11 LA10 LA9 LA8 LA7 VDD VSS LA6 LA5 LA4 LA3 LA2 LA1 LA0 LEDon/LEDin ENUM# AD0 AD1 AD2 AD3 AD4 AD5 VDD www..com Section 14 Package, Signal, and Pinout Specs 225-Pin PBGA 14.2 225-PIN PBGA D D1 Underside View Index 4-C2 45 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RPNMLKJHGFEDCBA E1 Topside View q2 A2 4-C1 E A e AEb Figure 14-4. 225-Pin PBGA Package Mechanical Dimensions--Topside, Underside, and Cross-Section Views Table 14-2. 225-Pin PBGA Package Mechanical Dimensions Dimensions (in Millimeters) Symbol ob A A1 A2 Min. 0.6 2.13 0.5 1.48 -- -- -- -- 23.5 23.5 -- -- Nom. 0.76 -- 0.6 1.53 30 1.0 4.0 1.5 24 24 27 27 A1 Cross-Section View Max. 0.90 -- 0.7 1.85 -- -- -- -- 24.7 24.7 -- -- 2 C1 C2 e D1 E1 D E PCI 9054 Data Book v2.1 14-4 (c) PLX Technology, Inc. All rights reserved. www..com 225-Pin PBGA Section 14 Package, Signal, and Pinout Specs Topside View Pin A1 Designator (Silkscreen) Pin A1 Copper Crop Lines (Allows for visual inspection of whether the PBGA is centered on the pads) 1.500 mm 28.00 0.010" 0.100" 28.00 0.011" FHS 0.016" Solder Mask Keepout around FHS 0.025" Via Pad Diameter 0.009" Solder Mask Detail of Each Pad and Breakout Solder Mask Keepout 0.002" - 0.003" 0.028" Diameter Land Figure 14-5. 225-Pin PBGA PCB Layout Suggested Land Pattern PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 14-5 Section 14--Physical Specs www..com Section 14 Package, Signal, and Pinout Specs 225-Pin PBGA G=GND 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 M15 M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 K15 K14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1 J15 J14 J13 J12 J11 J10 J9 J8 J7 J6 J5 J4 J3 J2 J1 H15 H14 H13 H12 H11 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G15 G14 G13 G12 G11 G10 G9 G8 F7 G6 G5 G4 G3 G2 G1 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 R P N M L K J H G F E D C B A 13 Connected Grounds (40 Total Grounds) 28 No Connects (NC) Figure 14-6. 225-Pin PBGA Package Layout (Underside View) PCI 9054 Data Book v2.1 14-6 (c) PLX Technology, Inc. All rights reserved. www..com 225-Pin PBGA Section 14 Package, Signal, and Pinout Specs Table 14-3. 225-Pin PBGA PCI 9054 Pinout Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 Symbol VDD (Core) AD30 PCLK PME# NC VDD (Core) USERo/DREQ0#/ LLOCKo# TEST LRESETo# Bus Mode All All All All All All All All All Pin # C1 C2 C3 C4 C5 C6 C7 C8 C9 Symbol IDSEL AD26 AD29 GNT# EEDI/EEDO BIGEND#/WAIT# BIGEND# USERi/DACK0#/ LLOCKi# NC BB# BREQi Bus Mode All All All All All M C, J All All M C, J Pin # E1 E2 E3 E4 E5 E6 E7 E8 E9 Symbol NC VDD (Core) AD21 NC AD25 NC CCS# MODE0 MDREQ#/DMPAF/ EOT# DMPAF/EOT# NC Bus Mode All All All All All All All All M C, J Pin # G1 G2 G3 G4 G5 G6 G7 G8 G9 Symbol IRDY# VDD (Core) FRAME# C/BE2# VDD (Core) AD23 VSS VSS VSS LD20 LD11 LAD11 LD17 LD14 LAD14 VDD (Core) Bus Mode All All All All All All All All All M C J M C J All A10 RETRY# BREQo TS# ADS# BR# LHOLD DP3 DP0 TA# READY# M C, J M C, J M C, J M C, J M C, J C10 VDD (Core) All E10 All G10 A11 C11 VDD (Core) All E11 DP1 DP2 LD25 LD6 LAD6 LD22 LD9 LAD9 LD21 LD10 LAD10 VDD (Core) NC AD17 AD18 AD19 AD20 AD31 EECS VSS NC LD29 LD2 LAD2 NC M C, J M C J M C J M C J All All All All All All All All All All M C J All G11 A12 C12 DP2 DP1 LD31 LD0 LAD0 LD28 LD3 LAD3 LD26 LD5 LAD5 AD22 AD24 C/BE3# AD28 RST# VDD (Core) NC VDD (Core) VDD (Core) TEA# LSERR# M C, J M C J M C J M C J All All All All All All All All All M C, J E12 G12 A13 C13 E13 G13 LFRAME# LD15 LD16 LAD16 LD16 LD15 LAD15 DEVSEL# NC TRDY# STOP# VDD (Core) VSS VSS VSS VSS All M C J M C J All All A14 C14 E14 G14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 VDD (Core) AD27 NC REQ# INTA# EESK VDD (Core) MODE1 LINT# BDIP# WAIT# BURST# BLAST# BG# LHOLDA VDD (Core) DP0 DP3 All All All All All All All All All M C M C, J M C, J All M C, J C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 E15 F1 F2 F3 F4 F5 F6 F7 F8 F9 G15 H1 H2 H3 H4 H5 H6 H7 H8 H9 All All All All All All B10 D10 F10 H10 VSS LD14 LD17 LAD17 VDD (Core) All M C J All B11 D11 LCLK BI# BTERM# LD27 LD4 LAD4 LD24 LD7 LAD7 LD23 LD8 LAD8 AD15 VDD (Core) NC All M C, J M C J M C J M C J All All All F11 H11 B12 D12 F12 NC LD19 LD12 LAD12 LD18 LD13 LAD13 NC AD10 AD8 AD6 All M C J M C J All All All All H12 B13 D13 F13 H13 NC LD12 LD19 LAD19 LD13 LD18 LAD18 VDD (Core) AD4 AD0 All M C J M C J All All All B14 NC LD30 LD1 LAD1 PERR# LOCK# SERR# All M C J All All All D14 F14 H14 B15 J1 J2 J3 D15 L1 L2 L3 F15 N1 N2 N3 H15 R1 R2 R3 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. 14-7 Section 14--Physical Specs All www..com Section 14 Package, Signal, and Pinout Specs 225-Pin PBGA Table 14-3. 225-Pin PBGA PCI 9054 Pinout (Continued) Pin # J4 Symbol VDD (Core) Bus Mode All Pin # L4 Symbol AD11 Bus Mode All Pin # N4 Symbol AD1 LA1 LA30 DEN# LA4 LA27 NC LA9 LA22 LA13 LA18 LA16 LA15 VDD (Core) LA24 LA7 LA28 LA3 TSIZ0 LBE3# LD0 LD31 LAD31 AD7 NC AD3 ENUM# VDD (Core) LA5 LA26 VDD (Core) NC LA12 LA19 VDD (Core) NC Bus Mode All M C J M C, J All M C, J M C, J M C, J All M C, J M C, J M C, J M C J All All All All All M C, J All All M C, J All All Pin # R4 Symbol LA0 LA31 DT/R# NC Bus Mode M C J All J5 VDD (Core) All L5 AD2 LA2 LA29 ALE LA8 LA23 VDD (Core) LA14 LA17 LA21 LA10 LA30 LBE1# NC All M C J M C, J All M C, J M C, J M C, J All N5 R5 J6 AD16 All L6 N6 R6 VDD (Core) LA7 LA24 LA10 LA21 VDD (Core) LA15 LA16 LA18 LA13 LA20 LA11 LA23 LA8 LA27 LA4 All M C, J M C, J All M C, J M C, J M C, J M C, J M C, J J7 J8 J9 VSS VSS VSS LD2 LD29 LAD29 All All All M C J All M C J All M C J M C J All All All All All All All All M C, J M C, J All M C J M C J All M C J L7 L8 L9 N7 N8 N9 R7 R8 R9 J10 L10 N10 R10 J11 VDD (Core) LD9 LD22 LAD22 VDD (Core) LD10 LD21 LAD21 LD11 LD20 LAD20 PAR NC C/BE1# AD14 VDD (Core) C/BE0# LEDon/LEDin VSS LA17 LA14 LA26 LA5 VDD (Core) LD6 LD25 LAD25 LD7 LD24 LAD24 NC LD8 LD23 LAD23 L11 N11 R11 J12 L12 N12 R12 J13 L13 VDD (Core) LD4 LD27 LAD27 LD5 LD26 LAD26 AD13 AD12 AD9 AD5 NC LA3 LA28 LA6 LA25 LA11 LA20 NC LA19 LA12 LA22 LA9 RD/WR# LW/R# LA31 LBE0# LD1 LD30 LAD30 LD3 LD28 LAD28 All M C J M C J All All All All All M C, J M C, J M C, J All M C, J M C, J M C, J M C, J M C J M C J N13 R13 J14 L14 N14 R14 J15 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 R15 VDD (Core) All K12 M12 P12 NC All K13 M13 P13 LA25 LA6 LA29 LA2 TSIZ1 LBE2# M C, J M C, J M C, J K14 M14 P14 K15 M15 P15 PCI 9054 Data Book v2.1 14-8 (c) PLX Technology, Inc. All rights reserved. www..com A A.1 GENERAL INFORMATION ORDERING INSTRUCTIONS A.2 UNITED STATES AND INTERNATIONAL REPRESENTATIVES, AND DISTRIBUTORS The PCI 9054 is a 32-bit, 33-MHz PCI Bus Master I/O Accelerator featuring advanced Data Pipe Architecture technology, which includes two DMA engines, programmable Target and Initiator Data Transfer modes, and PCI messaging functions. The PCI 9054 offers 3.3V, 5V tolerant PCI and Local signaling, and supports Universal PCI Adapter designs, 3.3V core, low-power CMOS offered in two package options, a 176-pin PQFP and 225-pin (ball) PBGA. The device is designed to operate at Industrial Temperature range. Table A-1. Available Packages Package 176-pin PQFP 225-pin PBGA A list of PLX Technology, Inc., representatives and distributors can be found at http://www.plxtech.com. A.3 TECHNICAL SUPPORT PLX Technology, Inc., technical support information is listed at http://www.plxtech.com; or call 408 774-9060 or 800 759-3735. Ordering Part Number PCI 9054-AB50PI PCI 9054-AB50BI PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. A-1 Appendix A--General Info www..com www..com A abort DMA 3-20, 5-20 PCI Target 3-7, 5-6-5-7 absolute maximum rating 13-1 accesses address decode enable 11-13 pointer 11-1 burst memory-mapped 1-7 bus 1-10, 11-7 byte 2-1, 4-1, 11-7 current Target 1-9 disabled 8-2, 11-16 duration 1-9 during software reset 3-1, 5-1 Hot Swap 9-1, 9-3 I/O 2-1, 4-1 configuration 3-5, 5-5 space 11-7 internal registers 2-11, 2-12, 4-12 Local Bus 1-13 Big/Little Endian 2-7, 4-7 read 2-4, 4-4 write 2-4, 4-4 locked atomic operations 3-10, 5-9 Lword 2-1, 4-1, 11-7 Lword, partial 4-4 Max_Lat 11-14 memory base address 11-10 memory space 11-7 NANDTREE 12-15-12-19 other than VPD Expansion ROM 1-5 partial Lword 2-4, 4-4 PCI 2-7, 4-7, 11-19 Master 3-1, 5-1 PCI Bus Master 1-6 PCI Initiator 3-3, 3-5, 5-3, 5-5, 11-1 PCI Initiator memory 3-4, 5-4 PCI Target 2-1, 2-4, 2-7, 2-11, 3-1, 3-3, 3-13, 4-1, 4-4, 4-7, 4-11, 5-1, 5-4, 5-11, 11-19, 11-28 PCIBAR0 11-10 PCIBAR1 11-11 PCIBAR2 11-11 PCIBAR3 11-12 PCIBAR4 11-12 PCIBAR5 11-12 PCI-to-Local 11-3 remote 1-4 RST# timing 1-7 single 1-7 slave 1-1, 1-6 VPD 10-1, 11-1, 11-18, 11-22 Word 2-1, 4-1, 11-7 AD[31:0] 1-9, 12-3 adapter block diagram 1-1 address bits for decoding 3-12, 5-10 boundary 2-3, 4-4 burst start 2-4, 4-4 cycle 2-3, 2-4, 4-4, 11-1 data 1-1, 1-6 decode enable 11-13, 11-23 EROMBA 11-23 invariance 2-5, 4-5, 4-6 LAS0BA 11-19 LAS0RR 11-19 LAS1BA 11-28 LAS1RR 11-27 LBRD0 11-24 local bits 2-4, 4-4 local bus initialization 3-12, 5-10 local space 0 2-7, 4-7 1 2-7, 4-7 local spaces 1-1, 1-8 mapping 3-12, 5-10 multiple independent spaces 1-4 Multiplexed Bus mode 12-1 Non-multiplexed Bus mode 12-1 PCI command 11-7 status 11-8 PCI Target byte enables 5-12 initialization 3-12, 5-10 PCIBAR0 11-10 PCIBAR1 11-11 PCIBAR2 11-11 PCIBAR3 11-12 PCIBAR4 11-12 PCIBAR5 11-12 PCI-to-Local spaces 1-6 pointer 11-1 PROT_AREA 11-22 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. Index-1 Index Index www..com ADS# to C and J modes PVPDAD 11-18 random read and write 10-2 Read Ahead mode 1-6 register 1-8 register mapping 11-2-11-6 signal listing 1-9, 1-10 VPD 10-1 ADS# 1-10, 12-9, 12-12 ALE 1-10, 12-12 output delay to the local clock 13-6 arbitration DMA 3-25, 5-23 local bus 2-2, 4-2 MARBR 11-20 PCI 2-2, 4-2 arbitration, PCI or Local Bus 4-2 atomic operations, locked 3-10, 5-9 BR# 1-10, 12-6 BREQi 1-10, 12-9, 12-12 BREQo 1-10, 12-9, 12-12 BTERM# 1-10, 2-3, 4-3, 5-7, 12-9, 12-12 burst operation, zero wait state 1-1, 1-5 BURST# 1-11, 12-6 Bus See Local Bus or PCI Bus bus operation 2-1-2-15, 4-1-4-16 bus protocol devices 1-1, 1-6 byte enables 5-5, 5-12, 5-22 See Also LBE[3:0]# C C and J modes AC electrical characteristics 13-4, 13-6 accesses byte 4-1 I/O 4-1 internal registers 4-12 Local Bus Big/Little Endian 4-7 read 4-4 write 4-4 Lword 4-1 Lword, partial 4-4 PCI 4-7 PCI Initiator memory 5-4 PCI Master 5-1 PCI Target 4-1, 4-4, 4-7, 5-1 software reset, during 5-1 address boundary 4-4 cycle 4-4 local bits 4-4 PCI Target byte enables 5-12 arbitration, PCI or Local Bus 4-2 backoff during deadlock 5-13 preempt deadlock solution 5-14 software solution for deadlock 5-14 solution for deadlock 5-14 base address 5-12 Big Endian, 8-bit Local Bus lower byte lane transfer 4-6 upper byte lane transfer 4-6 B backoff during deadlock 3-16, 5-13 preempt deadlock solution 3-16, 5-14 software solution for deadlock 3-16, 5-14 solution for deadlock 3-16, 5-14 BB# 1-10, 12-6 BDIP# 1-10, 12-6 BG# 1-10, 12-6 BI# 1-10, 12-6 Big Endian See Big/Little Endian or Endian Big/Little Endian Descriptor register (BIGEND) 11-21 BIGEND 11-21 BIGEND# 1-10, 12-6, 12-9, 12-12 BIST 6-3 BLAST# 1-10, 12-9, 12-12 block diagram internal 1-2 typical adapter 1-1 Block Dual Address cycle 3-19, 5-16 PCI 9054 Data Book v2.1 Index-2 (c) PLX Technology, Inc. All rights reserved. www..com C and J modes to C and J modes Block DMA mode 5-15-5-16 Block DMA, Dual Address cycle 5-16 Bus interface pin description 12-1 operation 4-1-4-16 byte enables 5-12 command codes 4-1 configuration cycles 5-5 cycles, example 5-6 local initialization 4-7 local registers 4-7 PCI, registers 4-11, 4-12 registers 5-1 serial EEPROM 5-1 cycles 5-5 dual address 5-6 Local Bus 4-2 deadlock conditions 5-13 Delayed Read mode 5-9 Direct Local-to-PCI Master Command 4-1 DMA abort 5-20 arbitration 5-23 channel interrupts 5-20 Clear Count mode 5-18 configuration 5-1 data transfers 5-20-5-22 Local-to-PCI 5-21 PCI-to-Local 5-21 Demand mode 5-22 Dual Address cycle 5-15 Master Command codes 4-1 memory write and invalidate 5-20 operation 5-14-5-23 priority 5-20 timing diagrams, C mode only 5-63-5-72 timing diagrams, J mode only 5-81-5-82 transfer 4-4 unaligned transfers 5-22 dual address 4-1, 5-7 end of transfer (EOT#) input 5-22 Endian, Big 16-bit Local Bus 4-6 lower word lane transfer 4-6 upper word lane transfer 4-6 32-bit Local Bus 4-6 upper Lword lane transfer 4-6 8-bit Local Bus 4-6 byte number and lane cross-reference 4-5 cycle reference table 4-5 Local Bus 4-5 Local Bus accesses 4-7 Program mode 4-5 Endian, Little byte number and lane cross-reference 4-5 cycle reference table 4-5 Local Bus 4-5 Local Bus accesses 4-7 PCI Bus 4-5 Program mode 4-5 FIFOs 5-9 Continuous Burst mode 4-4 PCI Target 5-1, 5-9 functional description 5-1-5-82 I/O decode 5-4 PCI Initiator 5-5 initialization local 4-7 PCI Target 5-10 Local Address Big/Little Endian mode 4-7 mapping 5-10 Local Address increment 4-4, 5-14 Local Bus 5-1 Big/Little Endian mode 4-5-4-7 characteristics 5-10 cycles 4-2, 4-4, 4-5 FIFO, response to 5-2 Latency Timer 5-23 PCI Target access 5-11 Command codes 4-1 operation 5-1 Local NMI 6-4 Local SERR# 6-4 Local-to-PCI doorbell interrupt 6-3 map PCI software 5-10 serial EEPROM memory 4-11 map/remap 5-10, 5-12 Master Command codes 4-1 memory 5-9 commands aliased 4-1 basic 4-1 read 4-1 serial EEPROM map 4-11 write 4-1 write and invalidate, PCI Initiator 5-8 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. 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Index-3 Index www..com C and J modes to C and J modes new capabilities structure 4-11 operation 1-7 Pause Timer 5-23 PCI arbitration 4-2 Dual Address cycle 4-1 Master Command codes 4-1 PCI Bus 5-1, 5-3 cycles 4-1 FIFO, response to 5-2 internal registers, access to 4-12 Little Endian mode 4-5 PCI Target operation 5-1 software reset 5-1 wait states 4-3 PCI Initiator access 5-3 Dual Address cycle 5-6 I/O 5-5 I/O configuration access 5-5 I/O decode 5-4 memory 5-4 memory access 5-4 memory write and invalidate 5-8 operation 5-1 PCI Target abort 5-6, 5-6-5-7 PCI Initiator FIFOs 5-4 PCI Initiator timing diagrams C mode only 5-25-5-43 J mode only 5-73-5-76 PCI Target accesses to 8- or 16-bit Local Bus 4-4 Big Endian/Little Endian cycle reference table 4-5 Command code, memory write and invalidate 4-1 Command codes 4-1 Direct Data Transfer mode 5-1-5-14 during serial EEPROM initialization 4-11 example 5-12-5-13 FIFO full or empty, response to 5-2 initialization 5-10 Local Bus Big Endian/Little Endian mode accesses 4-7 lock 5-9 operation 5-8-5-13 priority 5-13 serial EEPROM, during initialization 4-7 timing diagrams C mode only 5-44-5-62 J mode only 5-77-5-80 transfer 5-9 wait states Local Bus 4-3 pinout 12-9-12-14 range for decoding 5-10, 5-12 read 5-2 accesses 4-1, 4-12 Command codes, PCI Target 4-1 FIFOs 4-4 I/O command 4-1 Local Bus accesses 4-4 memory command 4-1 memory line 4-1 memory multiple 4-1 Read Ahead mode 4-4 serial EEPROM 4-11 Read Ahead mode 5-9 in burst read cycles 4-4 READY#, serial EEPROM initialization 4-7, 4-11 response to FIFO 5-1 Scatter/Gather DMA mode 5-16-5-19 serial EEPROM 4-7-4-16 device ID registers 4-7 extra long load 4-10 extra long load registers 4-10 initialization 4-11 internal register access 4-11 long load 4-8-4-9 long load registers 4-9 memory map 4-11 new capabilities function support 4-11 operation 4-7 PCI Bus, access to internal registers 4-12 recommended 4-11 software reset 5-1 timing diagrams 4-13-4-16 vendor ID registers 4-7 signal listing 1-9-1-14 single address block DMA initialization 5-7 timing diagrams 4-13-4-16, 5-24-5-82 Vital Product Data (VPD) internal register access 4-11 new capabilities function feature 4-11 read or write serial EEPROM 4-8 wait state control 4-3 generation 4-4 Local Bus 4-3 PCI Bus 4-3 write 5-2 accesses 4-1, 4-12 Command codes, PCI Target 4-1 PCI 9054 Data Book v2.1 Index-4 (c) PLX Technology, Inc. All rights reserved. www..com C/BE[3:0]# to configuration I/O command 4-1 Local Bus accesses 4-4 memory command 4-1 memory write and invalidate 4-1 serial EEPROM operation 4-7 C/BE[3:0]# 1-9, 12-3 CAP_PTR 11-14 capacitance 13-1 CCS# 12-5 chip select 1-11 channels, dual DMA 1-3, 1-4, 1-5, 1-6, 1-8, 1-13 chip select EECS 1-11 IDSEL 1-9 initialization device 1-9 serial EEPROM 1-11 circular FIFOs summary 7-6 Clear Count mode 3-20, 5-18 clocks 1-9, 1-10, 1-12, 8-1 buffered PCI 1-8 EESK 1-11, 2-7, 4-7 input 13-3 local 13-6 local input 1-12 PCI 2-7, 4-7, 11-15 PCIMGR 11-14 PCLK 1-9 RST# 1-7 serial EEPROM 2-7, 4-7 serial EEPROM clock pin 1-11 CNTRL 3-1, 5-1, 11-33 Command codes 2-1, 4-1 Local-to-PCI 2-1 CompactPCI 1-3, 1-12 Hot Swap 9-1-9-4 adapters 1-4 applications 9-1 blue LED 9-3 board healthy 9-2 board slot control 9-2 capabilities register bit definition 9-4 capable 9-1 compliant 1-1, 1-5, 1-8 control bits 9-4 Control/Status register (HS_CSR) 9-3 controlling connection processes 9-1 ejector switch 9-3 ENUM# 9-3 friendly 9-1 hardware connection control 9-1 ID 9-4 levels of compatibility 9-1 Next_Cap pointer 9-4 platform reset 9-2 ready 9-1 register 11-1 software connection control 9-3 compatibility with PCI 9050 1-7 with PCI 9080 1-7 compatible message unit 7-1 configuration accesses 1-7 Big/Little Endian 3-11, 5-10 BTERM# 1-10 bus-width 1-12 command type 2-1, 4-1 control/status register 9-3 cycles 3-5, 5-5 example 3-6, 5-6 Hot Swap 9-1, 9-3 IDSEL 1-9 initialization 5-1 LBE[3:0]# 1-12 load information 1-6 local cycles 8-2 initialization 2-7, 4-7 registers 2-7, 2-11, 3-1, 4-7, 4-11 new capabilities 10-1 new capability linked list 11-1 PCI cycles 8-2 registers 2-11, 4-11, 4-12 PCI 9054 initialization 3-1 Power Management 8-2 read and write transactions 1-9 register space 1-7 registers 1-10, 3-1, 5-1, 11-7-11-28 address mapping 11-2-11-6 serial EEPROM 3-1, 5-1 software reset 3-1 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. 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Index-5 Index www..com Configuration Address register (DMCFGA) to DMA space 9-3, 10-1, 11-1 subsystem ID 1-7 subsystem vendor ID 1-7 system reconfiguration 9-1, 9-3 type 0 cycle 2-11, 4-12 VPD 1-1, 10-1 Configuration Address register (DMCFGA) 11-27 conversion Big/Little Endian 1-1, 1-4, 1-8, 3-11, 5-10 on-the-fly 3-11, 5-10 counter prefetch 1-1, 1-6 programmable 1-8 cycles configuration 3-5, 5-5 configuration example 3-6, 5-6 dual address 3-6, 5-6 Local Bus 2-2-2-5, 4-2-4-5 memory write and invalidate 3-7, 5-8 D DAC 3-6, 5-6 DACK0# 1-14, 12-5 data assignment convention 1-7 data bus contents for read cycles 3-14 contents for write cycles 3-14 Data Pipe Architecture I/O Accelerator 1-3 See Also dual DMA channels technology 1-3 data transfers, DMA Local-to-PCI 3-23, 5-21 PCI-to-Local 3-23, 5-21 deadlock conditions 3-15, 5-13 during access 3-15, 5-13 full 3-15, 5-13 partial 3-15, 5-13 Deferred Read mode 1-8 Local-to-PCI 1-1 Delayed Read mode 1-1, 3-10, 5-9 Demand mode, DMA support 1-8 DEN# 1-11 Descriptor register (LBRD1) 11-28 device ID 11-7 DEVSEL# 1-9, 12-3 direct interface Local Bus 1-6 Local-to-PCI Command codes 2-1 Local-to-PCI Master Command codes 4-1 Direct Slave See PCI Target DMA abort 3-20, 5-20 acknowledge 1-14 arbitration 3-25, 5-23 Arbitration register (DMAARB) 11-1, 11-39 Block Dual Address cycle 3-19, 5-16 Channel 0 Command/Status register (DMACSR0) 11-38 Descriptor Pointer register (DMADPR0) 11-35 Local Address register (DMALADR0) 11-35 Mode register (DMAMODE0) 11-34 PCI Address register (DMAPADR0) 11-35 Transfer Size register (DMASIZ0) 11-35 Channel 1 Command/Status register (DMACSR1) 11-38 Descriptor Pointer register (DMADPR1) 11-37 Local Address register (DMALADR1) 11-37 Mode register (DMAMODE1) 11-36 PCI Address register (DMAPADR1) 11-37 Transfer Size register (DMASIZ1) 11-37 channel interrupts 3-22, 5-20 channels 1-1, 1-3 channels, number of 1-8 Clear Count mode 3-20, 5-18 configuration 3-1, 5-1 controller 2-4, 4-4 cycle 11-1 data transfers Local-to-PCI 3-23, 5-21 PCI-to-Local 3-23, 5-21 Demand mode 1-8, 1-14, 3-24, 5-22 direct hardware control 1-3 dual address 3-6, 3-19 Dual Address cycle 3-17, 5-6, 5-15, 5-16 engines 1-1, 1-3 interrupts 6-1, 6-3-6-4 list management 1-3 local bus error 3-24 Master Command codes 2-1, 4-1 priority 3-20, 5-20 PCI 9054 Data Book v2.1 Index-6 (c) PLX Technology, Inc. All rights reserved. www..com DMA 0 PCI Dual Address Cycle register (DMADAC0) to EESK read 1-5 registers 11-10, 11-34-11-39 registers, address mapping 11-5 request 1-14 ring management 1-3 scatter/gather 3-20, 3-21 scatter/gather list management 1-3 Shuttle mode 1-3 Threshold register (DMAATH) 11-39 transfer 1-10, 1-13, 1-14, 2-4, 4-4 unaligned transfer support 1-7 transfers 3-24, 5-22 wait states 2-3 write 1-5 DMA 0 PCI Dual Address Cycle register (DMADAC0) 11-39 DMA 1 PCI Dual Address Cycle register (DMADAC1) 11-39 DMAARB 11-39 DMACSR0 11-38 DMACSR1 11-38 DMADAC0 3-6, 5-6, 11-39 DMADAC1 3-6, 5-6, 11-39 DMADPR0 11-35 DMADPR1 11-37 DMALADR0 11-35 DMALADR1 11-37 DMAMODE 3-6, 5-6 DMAMODE0 11-34 DMAMODE1 11-36 DMAPADR0 11-35 DMAPADR1 11-37 DMASIZ0 11-35 DMASIZ1 11-37 DMATHR 11-39 DMCBFGA 11-27 DMCFGA 3-1, 5-1 DMDAC 11-28 DMDAD 3-1, 5-1 DMLBAI 3-1, 5-1, 11-25 DMLBAM 3-1, 5-1, 11-25 DMPAF 1-11, 1-13, 12-7, 12-9, 12-12 DMPBAM 3-1, 5-1, 11-26 DMRR 3-1, 5-1, 11-25 Doorbell registers 1-8, 6-2 L2PDBELL 11-30 P2LDBELL 11-30 DP[0:3] 1-11, 12-6, 12-9 DP[3:0] 1-11, 12-13 DREQ0# 1-11, 1-14, 12-5 DT/R# 1-11, 12-13 Dual Address block DMA initialization 5-7 cycle 2-1, 3-17, 4-1, 5-15 Cycle register (DMDAC) 11-28 timing diagram 3-8, 3-18, 5-7 dual DMA channels 1-3, 1-4, 1-5, 1-6, 1-8, 1-13 E EECS 1-11, 12-3 EEDI 1-11, 12-3 EEDO 1-11, 12-3 EESK 1-11, 12-3 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. 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Index-7 Index www..com electrical characteristics over operating range to GNT# electrical characteristics over operating range 13-2 electrical specifications 13-1-13-6 AC characteristics 13-3, 13-4, 13-5, 13-6 ALE output delay 13-6 capacitance 13-1 local inputs 13-3 local outputs 13-5 delay 13-5 embedded design 12-1 host design 1-5 systems 1-1, 1-3 enable sequence 7-5 end of transfer (EOT#) input 3-24, 5-22 Endian Big 2-5-2-7 16-bit Local Bus 2-6, 4-6 lower word lane transfer 2-6, 4-6 upper word lane transfer 2-6, 4-6 32-bit Local Bus 2-5, 4-6 upper Lword lane transfer 2-5, 4-6 8-bit Local Bus 2-6, 4-6 lower byte lane transfer 2-6, 4-6 upper byte lane transfer 2-6, 4-6 byte number and lane cross-reference 2-5, 4-5 conversion 1-1, 1-4, 1-8 cycle reference table 2-5, 4-5 Local Bus 2-5, 4-5 Local Bus accesses 2-7, 4-7 on-the-fly conversion 3-11, 5-10 Program mode 2-5, 4-5 Little 2-5-2-7 byte number and lane cross-reference 2-5, 4-5 conversion 1-1, 1-4, 1-8 cycle reference table 2-5, 4-5 Local Bus 2-5, 4-5 Local Bus accesses 2-7, 4-7 on-the-fly conversion 3-11, 5-10 PCI Bus 2-5, 4-5 Program mode 2-5, 4-5 Endian, Big/Little 2-5-2-7, 4-5-4-7 See Also Endian ENUM# 9-3, 11-17, 12-3 EOT# 1-13, 12-7, 12-9, 12-12 EROMBA 3-12, 5-10, 11-23 EROMRR 11-23 Expansion ROM Range register (EROMRR) 11-23 register (EROMBA) 11-23 F F. Bit, as a flag 10-1 FIFOs circular operation 7-4 circular summary 7-6 Continuous Burst mode 2-4, 4-4 depth 1-5 enable high-performance bursting 1-7 inbound free list 7-2 inbound post queue 7-3 number of 1-8 outbound free list 7-5 outbound post queue 7-3 PCI Initiator 3-3-3-4, 5-4 PCI Target operation 3-1, 5-1 Read Ahead mode 3-10, 5-9 transfer 3-11, 5-9 programmable 1-1, 1-5 Read Ahead mode 1-6 response to 3-1, 5-1 flush 3-10, 5-9 FRAME# 1-9, 12-3, 12-5 free list FIFO, inbound 7-2 free list FIFO, outbound 7-5 free queue, inbound 7-5 functional description C and J modes 5-1-5-82 M mode 3-1-3-65 G general electrical specifications 13-1-13-2 absolute maximum ratings 13-1 operating ranges 13-1 over operating range 13-2 thermal resistance of packages 13-1 GNT# 12-3 PCI 9054 Data Book v2.1 Index-8 (c) PLX Technology, Inc. All rights reserved. www..com hold waveform to intelligent I/O H hold waveform 13-3 Hot Plug 1-1, 1-5, 1-8 Hot Swap capable 1-4 Control register (HS_CNTL) ID Hot Swap 11-17 Control/Status register (HS_CSR) 11-17 friendly 1-4 ID 11-17 Next Capability Pointer register (HS_NEXT) 11-17 resources 9-3 See Also CompactPCI Hot Swap HS_CNTL 11-17 HS_CSR 9-3, 11-17 HS_NEXT 11-17 I I/O accelerator 1-3 configuration 5-5 configuration access 3-5, 5-5 decode 3-3, 5-4 PCI Initiator 3-5, 5-5 See Also user input and output I2O messaging unit 1-8 See Also Intelligent I/O 7-1 I2O SIG 1-3 IBM, PPC401 1-1, 1-6 ID Configuration ID register (PCIIDR) 11-7 device 11-7 Hardcoded Configuration ID register (PCIHIDR) 11-33 Hardcoded Revision ID register (PCIHREV) 11-33 Power Management Capability ID register (PMCAPID) 11-14 Revision ID register (PCIREV) 11-8 serial EEPROM, revision 11-8 serial EEPROM, subsystem 11-13 serial EEPROM, vendor 11-7 Subsystem register 11-13 Subsystem Vendor register 11-12 vendor 11-7 VPD 11-18 IDMA channel 1-4 operation 3-9 PowerQUICC operation 1-4 IDSEL 1-9, 12-3 IFHPR 11-41 IFTPR 11-41 Inbound Free Head Pointer register (IFHPR) 11-41 free list FIFO 7-2 Free Tail Pointer register (IFTPR) 11-41 IPHPR 7-2 IPTPR 7-2 Post Head Pointer register (IPHPR) 11-42 post queue FIFOs 7-3 Post Tail Pointer register (IPTPR) 11-42 Queue Port register (IQP) 11-40 industrial PCI implementations 1-3 temp range operation 1-1 initialization 3-1, 5-1, 11-1 C and J modes 5-1 IDSEL 1-9 local 2-7, 4-7 M mode 3-1 PCI Target 3-12 example 3-14, 5-12 local bus 3-12, 5-10 PCI 5-10 PMC 11-15 reset 3-12, 5-10 Initialization Control register (CNTRL) 11-33 Initiator See PCI Initiator input PCI Bus 3-1, 5-1 user 6-5 INTA# 1-9, 6-1, 12-4 INTCSR 11-31-11-32 Intel i960 1-1, 1-6 intelligent I/O 7-1-7-6 circular FIFOs PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. 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Index-9 Index www..com internal block diagram to LBRD1 operation 7-4 summary 7-6 compatible message unit 7-1 enable sequence 7-5 inbound free list FIFOs 7-2 free queue 7-5 messages 7-1 post queue FIFOs 7-3 outbound free list FIFO 7-5 messages 7-1 post queue 7-5 post queue FIFOs 7-3 pointer management 7-2 internal block diagram 1-2 Interrupt Control/Status register (INTCSR) 11-31-1132 interrupts built-in self test (BIST) 6-3 control/status 11-1 disabled 8-1, 8-2, 11-16 DMA 3-22, 5-20 DMA Channel 0/1 6-3-6-4 doorbell register 6-2 ENUM# driven 9-3 interrupt 9-3, 9-4 interrupt clear 11-17 error sources 6-1 generator 1-1, 1-7 INTA# 6-1 interrupt A 1-9 line 11-2, 11-14 local input (LINT#) 6-1 output (LINT#) 6-2, 8-2 Local-to-PCI 1-6 Local-to-PCI doorbell 6-3 mailbox register 6-2 Master/Target abort 6-2 PCI local 6-1-6-5 PCI request 1-9 PCI-to-Local 1-6 pin 11-2, 11-14 power management event (PME#) 1-5, 1-9 TEA# mask 11-1 User I/O 6-1-6-5 wake-up event 1-9 IPHPR 11-42 IPTPR 11-42 IQP 11-40 IRDY# 1-9, 12-4 J J mode See C and J modes K Keep Bus mode C and J modes 1-7 M mode 1-7 L L2PDBELL 11-30 LA[0:31] 1-11, 12-7 LA[1:0] 4-4 LA[28:2] 1-11, 12-13 LA[31:2] 1-11, 3-14, 12-10 LAD[31:0] 1-11, 12-13 LAS0BA 3-12, 5-10, 11-19 LAS0RR 3-12, 5-10, 11-19 LAS1BA 3-12, 5-10, 11-28 LAS1RR 3-12, 5-10, 11-27 Latency Timer Local Bus 1-7, 2-2, 2-3, 3-11, 3-12, 3-17, 3-24, 3-25, 4-2, 5-9, 5-15, 5-23, 5-70, 11-20 timing diagram 3-62 PCI Bus 3-17, 11-9 See Also PCI Latency Timer, PCI Bus Latency Timer or Local Bus Latency Timer latency, reduced data 1-6 LBE[3:0]# 1-12, 12-10, 12-14 LBRD0 11-24 LBRD1 PCI 9054 Data Book v2.1 Index-10 (c) PLX Technology, Inc. All rights reserved. www..com LCLK to Local Bus 11-28 LCLK 1-12, 12-5 LD[0:31] 1-12, 12-7 LD[0:7] 3-14 LD[16:23] 3-14 LD[24:31] 3-14 LD[31:0] 1-12, 12-10 LD[8:15] 3-14 LEDon/LEDin 1-12, 12-5 LFRAME# 1-12 LHOLD 1-12, 12-14 LHOLDA 1-13, 12-11, 12-14 LINT# 1-13, 6-1, 6-2, 8-2, 12-5 list management 1-3 Little Endian See Big/Little Endian or Endian LLOCKi# 1-13, 1-14, 12-5 LLOCKo# 1-13, 1-14, 12-5 LMISC 11-22 Local Address Big/Little Endian mode 2-7, 4-7 EROMBA 11-23 increment 2-3, 3-17, 4-4, 5-14 LAS0BA 11-19 LAS0RR 11-19 LAS1RR 11-27 mapping 3-12, 5-10 PCIBAR2 11-11 PCIBAR3 11-12 PCIBAR4 11-12 PCIBAR5 11-12 PCI-to-Local spaces 1-6 Space 0 Local Base Address register (LAS0BA) 11-19 Space 0 Range register (LAS0RR) 11-19 Space 0/Expansion ROM register (LBRD0) 11-24 Space 1 Bus Region Descriptor register (LBRD1) 11-28 Space 1 Local Base Address register (LAS1BA) 11-28 Space 1 Range register (LAS1RR) 11-27 spaces 1-1, 1-8, 3-9, 5-8, 11-2, 11-3 Local Base Address register for PCI Memory (DMPBAM) 11-26 Local Base Address register for PCI Configuration (DMLBAI) 11-25 Local Bus 3-1, 3-12, 5-9 access internal registers 2-12, 4-12 accesses 5-1 arbitration 2-2, 4-2 atomic operation 1-14 Base Address register (DMLBAM) 11-25 Big/Little Endian mode 2-5-2-7, 4-5-4-7 characteristics defined for target regions 5-10 configuration registers 11-3 current 1-10 cycles 2-2-2-4, 4-2-4-4 direct interface 1-6 error condition 3-24 FIFO, response to 5-2 hold request 1-12 independent interface pins 12-5 interface 2-11 LAS0RR 11-19 Latency Timer 1-7, 2-2, 2-3, 3-11, 3-12, 3-17, 3-24, 3-25, 4-2, 5-9, 5-15, 5-23, 5-70, 11-20 timing diagram 3-62 PCI Target access 3-13, 5-11 Command codes 2-1, 4-1 initialization 3-12, 5-10 operation 3-1, 5-1 PCISR 11-8 PCI-to-Local 1-3 pin information 12-1 PMCSR 11-16 power management 8-1 priority control 1-4 programmable 1-6 Read Ahead mode 1-6 Read Ahead mode, in relationship to 3-10 registers 4-11 response to 3-1 response to FIFO 3-2 serial EEPROM 2-7, 4-7 signaling 1-5, 1-8 timing diagrams 3-26, 5-24 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. 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Index-11 Index www..com local input setup to M mode types 176-Pin PQFP 2-2, 4-2 225-Pin PBGA 2-2, 4-2 VPD 10-1 wait states 2-3 width 5-12 width control 1-4 local input setup 13-3 Local Miscellaneous Control register (LMISC) 11-22 Local NMI 6-4 Local Range register (DMRR) 11-25 Local SERR# 6-4 local signal output delay 13-5 Local-to-PCI Deferred Read mode 1-1 doorbell interrupt 6-3 lock atomic operations 3-10, 5-9 cycles 1-8 local output 1-14 LOCK# 1-9, 3-10, 5-9, 12-4 PCI Target 3-10, 5-9 LOCK# 1-9, 3-10, 5-9, 12-4 LRESETo# 1-13, 12-5 LSERR# 1-13, 12-11, 12-14 LW/R# 1-13, 12-14 M M mode 1-6, 2-1 AC electrical characteristics 13-3, 13-5 accesses byte 2-1 during software reset 3-1 I/O 2-1 internal registers 2-11, 2-12 Local Bus Big/Little Endian 2-7 Local Bus read 2-4 Local Bus write 2-4 Lword 2-1 PCI 2-7 PCI Master 3-1 PCI Initiator memory 3-4 PCI Target 2-1, 2-4, 2-7, 3-1 address boundary 2-3 burst start 2-4 cycle 2-3, 2-4 local bits 2-4 arbitration local bus 2-2 PCI 2-2 backoff during deadlock 3-16 preempt deadlock solution 3-16 software solution for deadlock 3-16 solution for deadlock 3-16 base address 3-14 Block DMA Dual Address cycle 3-19 Block DMA mode 3-17-3-19 Bus mode interface pin description 12-1 Bus operation 2-1-2-15 Command codes 2-1 Command codes Local-to-PCI 2-1 configuration cycles 3-5 cycles, example 3-6 local initialization 2-7 local registers 2-7, 3-1 PCI registers 2-11 registers 3-1 serial EEPROM 3-1 cycles 3-5 dual address 3-6 Local Bus 2-2 deadlock conditions 3-15 Delayed Read mode 3-10 direct Local-to-PCI Command codes 2-1 DMA abort 3-20 arbitration 3-25 channel interrupts 3-22 Clear Count mode 3-20 configuration 3-1 data transfers 3-22-3-24 Local-to-PCI 3-23 PCI-to-Local 3-23 Demand mode 3-24 Dual Address cycle 3-17 local bus error 3-24 PCI 9054 Data Book v2.1 Index-12 (c) PLX Technology, Inc. All rights reserved. www..com M mode to M mode Master Command codes 2-1 memory write and invalidate 3-20 operation 3-16-3-25 priority 3-20 timing diagrams 3-51-3-65 transfer 2-4 unaligned transfers 3-24 Dual Address cycle 2-1 dual address timing diagram 3-18 end of transfer (EOT#) input 3-24 Endian, Big 2-5-2-7 16-bit Local Bus 2-6 lower word lane transfer 2-6 upper word lane transfer 2-6 32-bit Local Bus 2-5 upper Lword lane transfer 2-5 8-bit Local Bus 2-6 lower byte lane transfer 2-6 upper byte lane transfer 2-6 byte number and lane cross-reference 2-5 cycle reference table 2-5 Local Bus 2-5 Local Bus accesses 2-7 Program mode 2-5 Endian, Little 2-5-2-7 byte number and lane cross-reference 2-5 cycle reference table 2-5 Local Bus 2-5 Local Bus accesses 2-7 Program mode 2-5 FIFOs 3-11 Continuous Burst mode 2-4 PCI Target 3-10 PCI Target operation 3-1 functional description 3-1-3-65 I/O decode 3-3 I/O PCI Initiator 3-5 IDMA operation 3-9 initialization 3-1 local 2-7 PCI Target 3-12 Keep Bus mode 1-7 Local Address Big/Little Endian mode 2-7 Mapping 3-12 Local Address increment 2-3, 3-17 Local Bus 3-14 access internal registers 2-12 Big/Little Endian mode 2-5-2-7 characteristics 3-12 cycles 2-2, 2-4, 2-5 Latency Timer 3-25 PCI Target access 3-13 Command codes 2-1 PCI Target operation 3-1 response to 3-1 response to FIFO 3-2 Local NMI 6-4 Local TEA# 6-4 Local-to-PCI doorbell interrupt 6-3 map PCI software 3-12 serial EEPROM memory 2-11 map/remap 3-12, 3-14 Master Command codes 2-1 memory 3-11 commands aliased 2-1 basic 2-1 read 2-1 serial EEPROM map 2-11 write 2-1 write and invalidate, PCI Initiator 3-7 new capabilities structure 2-10 Pause Timer 3-25 PCI arbitration 2-2 Dual Address cycle 2-1 Master Command codes 2-1 PCI Bus 3-3 access to internal registers 2-11 cycles 2-1 input 3-1 Little Endian mode 2-5 PCI Target operation 3-1 response to FIFO 3-2 software reset 3-1 wait states 2-3 PCI Initiator access 3-3 Dual Address cycle 3-6 I/O 3-5 configuration access 3-5 decode 3-3 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. 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Index-13 Index www..com Mailbox to mailbox registers memory 3-3 access 3-4 write and invalidate 3-7 operation 3-1 PCI Target abort 3-7, 3-7 PCI Initiator FIFOs 3-3-3-4 PCI Initiator timing diagrams 3-27-3-35 PCI SERR# 6-4 PCI Target accesses to 8- or 16-bit Local Bus 2-4 Big Endian/Little Endian cycle reference table 2-5 Command codes 2-1 during serial EEPROM initialization 2-7, 2-11 example 3-14-3-15 FIFO full or empty, response to 3-2 initialization 3-12 Local Bus Big Endian/Little Endian mode accesses 2-7 lock 3-10 operation 3-9-3-15 partial Lword accesses 2-4 priority 3-15 timing diagrams 3-36-3-50 transfer 3-11-3-12 transfer size 3-14-3-15 wait states 2-3 pinout 12-6-12-8 range for decoding 3-12, 3-14 read accesses 2-1, 2-12 FIFOs 2-4 I/O command 2-1 Local Bus accesses 2-4 memory command 2-1 memory line 2-1 memory multiple 2-1 PCI Target 3-2 PCI Target Command codes 2-1 Read Ahead mode 2-4 serial EEPROM 2-10 serial EEPROM operation 2-7 Read Ahead mode 3-10 in burst read cycles 2-4 read cycles 3-14 response to FIFO 3-1 Scatter/Gather DMA mode 3-19-3-20 Scatter/Gather DMA PCI Dual Address cycle 3-20, 3-21 SDMA operation 3-9 serial EEPROM 2-7-2-15 device ID registers 2-7 extra long load 2-10 initialization 2-11 internal register access 2-11 long load 2-8-2-9 memory map 2-11 new capabilities function 2-10 operation 2-7 PCI Bus access to internal registers 2-11 recommended 2-10 software reset 3-1 timing diagrams 2-13-2-16 vendor ID registers 2-7 signal listing 1-9-1-14 TA# serial EEPROM initialization 2-7, 2-11 timing diagrams 3-26-3-65 serial EEPROM 2-13-2-16 transfer size bits (TSIZ[0:1]) 2-4 Vital Product Data (VPD) internal register access 2-11 new capabilities function 2-10 read or write serial EEPROM 2-8 wait state control 2-2 generation 2-4 Local Bus 2-3 PCI Bus 2-3 write accesses 2-1, 2-12 cycles 3-14 I/O command 2-1 Local Bus accesses 2-4 memory command 2-1 memory write and invalidate 2-1 PCI Target 3-2 PCI Target Command codes 2-1 serial EEPROM operation 2-7 Mailbox register 0 (MBOX0) 11-29 register 1 (MBOX1) 11-29 register 2 (MBOX2) 11-29 register 3 (MBOX3) 11-29 register 4 (MBOX4) 11-29 register 5 (MBOX5) 11-29 register 6 (MBOX6) 11-29 register 7 (MBOX7) 11-30 mailbox registers 1-8, 6-2, 11-29-11-30 PCI 9054 Data Book v2.1 Index-14 (c) PLX Technology, Inc. All rights reserved. www..com management, pointer to new capabilities management, pointer 7-2 map PCI software 3-12, 5-10 PCI Target 1-7 remap PCI-to-Local addresses 3-12, 5-10 See Also mapping and remap serial EEPROM memory 2-11, 4-11 mapping EROMBA 11-23 LAS0BA 11-19 LAS1BA 11-28 PCI-to-Local 3-12, 5-10 register address 11-2-11-6 MARBR 11-20 Master Command codes 2-1, 4-1 Master/Target abort interrupt 6-2 maximum rating 13-1 MBOX 0 11-29 1 11-29 2 11-29 3 11-29 4 11-29 5 11-29 6 11-29 7 11-30 MDREQ# 1-13, 12-7 memory accesses 11-10, 11-11, 11-12 address spaces 11-11, 11-12, 11-19, 11-27 base address 11-10, 11-11, 11-12 commands aliased 2-1, 4-1 basic 2-1, 4-1 disabled 8-1 local spaces 1-6 location of registers 11-12 mapped configuration registers 11-2 mapping 11-19, 11-27 PCI 8-2, 11-16 PCI Target transfer 3-11, 5-9 PCIBAR0 11-10 PCIBAR2 11-11 PCIBAR3 11-12 PCIBAR4 11-12 PCIBAR5 11-12 posted writes (PMW) 1-7 prefetchable 11-11, 11-12 read 2-1, 4-1 registers, location 11-10, 11-11 remap 11-19 serial EEPROM map 2-11, 4-11 space indicator 11-10, 11-11, 11-12, 11-19, 11-27 spaces 11-7, 11-19, 11-27 write 2-1, 4-1 write and invalidate 1-8, 11-7, 11-9 write and invalidate, PCI Initiator 3-7, 5-8 write transfers 11-9 messages inbound 7-1 outbound 7-1 messaging 1-4 Messaging Queue Configuration register (MQCR) 11-41 Messaging Queue registers 11-40-11-43 address mapping 11-6 Mode/DMA Arbitration register (MARBR) 11-20 MODE[1:0] 1-13, 12-5 Motorola adapters for telecom and networking applications 1-4 high performance design 1-4 MPC850 1-1, 1-6, 2-4, 3-9, 3-18 direct connect interface 1-6 PowerQUICC adapter design 1-3, 1-4 RISC processors 1-6 MPC860 1-1, 1-6, 2-3, 2-4, 3-9, 3-18, 3-34, 3-35 direct connect interface 1-6 PowerQUICC adapter design 1-3, 1-4 RISC processors 1-6 MQCR 11-41 Multiplexed mode featured in PCI 9054 1-1 input and output, user 6-5 interface pin 12-1 LED 9-3 N NANDTREE compared to JTAG 12-15 test access method 12-15-12-19 new capabilities functions support 11-8 linked list 8-1 Next_Cap pointer 9-4 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. 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Index-15 Index www..com New Capabilities Pointer register (CAP_PTR) to PCI pointer 11-1 register 8-1 structure 1-7, 2-10, 4-11, 9-4, 10-1 support bit 8-1 VPD 10-1 New Capabilities Pointer register (CAP_PTR) new capabilities register 11-14 Non-multiplexed mode featured in PCI 9054 1-1 interface pin 12-1 output, user 6-5 P P2LDBELL 11-30 package specs 14-1-14-8 PAR 1-9, 12-4 partial Lword accesses 4-4 Pause Timer 3-25, 5-23 PBGA Local Bus types 2-2, 4-2 ordering instructions A-1 package layout 14-6 package mechanical dimensions 14-4 PCB layout suggested land pattern 14-5 pinout 14-7-14-8 PCI applications 1-4 arbitration 2-2, 4-2 Built-In Self Test register (PCIBISTR) 11-10 Cache Line Size register (PCICLSR) 11-9 Cardbus CIS Pointer register (PCICIS) 11-12 Class Code register (PCICCR) 11-9 Command Codes register (CNTRL) 11-33 Command register (PCICR) 11-7 Configuration ID register (PCIIDR) 11-7 device 1-9 Dual Address cycle 2-1, 4-1 Expansion ROM Base register (PCIERBAR) 11-13 Hardcoded Configuration ID register (PCIHIDR) 11-33 Hardcoded Revision ID register (PCIHREV) 11-33 Header Type register (PCIHTR) 11-9 Interrupt Line register (PCIILR) 11-14 Interrupt Pin register (PCIIPR) 11-14 Master Command codes 2-1, 4-1 Max_Lat register (PCIMLR) 11-14 Min_Gnt register (PCIMGR) 11-14 Revision ID register (PCIREV) 11-8 Status register (PCISR) 11-8 Subsystem ID register (PCISID) 11-13 Subsystem Vendor ID register (PCISVID) 11-12 Vital Product Data Address register (PVPDAD) 11-18 Vital Product Data Control register (PVPDCNTL) 11-18 Vital Product Data Next Capability Pointer register (PVPD_NEXT) 11-18 O OFHPR 11-42 OFTPR 11-42 176-pin PQFP See PQFP on-the-fly Big/Little Endian conversion 3-11, 5-10 operating ranges 13-1 OPHPR 11-42 OPQIM 11-40 OPQIS 11-40 OPTPR 11-43 OQP 11-40 ordering instructions A-1 Outbound Free Head Pointer register (OFHPR) 11-42 free list FIFO 7-5 free queue 7-5 Free Tail Pointer register (OFTPR) 11-42 OFHPR 7-2 OFTPR 7-2 OPHPR 11-42 Post Head Pointer register (OPHPR) 11-42 post queue 7-5 post queue FIFOs 7-3 Post Queue Interrupt Mask register (OPQIM) 11-40 Post Queue Interrupt Status register (OPQIS) 11-40 Post Tail Pointer register (OPTPR) 11-43 Queue Port register (OQP) 11-40 PCI 9054 Data Book v2.1 Index-16 (c) PLX Technology, Inc. All rights reserved. www..com PCI 9054 to PCI Target PCI 9054 compared with PCI 9050 and 9080 1-8 major features 1-5-1-7 PCI 9054_AA revision 12-6 PCI 9054_AB revision 2-7, 4-7, 12-1, 12-6 PCI Base Address register PCIBAR0 11-10 PCIBAR1 11-11 PCIBAR2 11-11 PCIBAR3 11-12 PCIBAR4 11-12 PCIBAR5 11-12 PCI Bus accesses 1-6, 2-4 accessibility of spaces 5-10 accessible spaces 3-12 board healthy 9-2 cycles 2-1, 4-1 drivers 8-1 embedded host design 1-5 features 1-1 FIFO, response to 5-2 input RST# 3-1, 5-1 internal registers, access to 2-11, 4-12 Latency Time register (PCILTR) 11-9 Latency Timer 3-17, 11-2, 11-9 Little Endian mode 2-5, 2-7, 4-5 Master 1-3 Masters 13-3, 13-4, 13-5, 13-6 PCI Target accesses 4-4 PCI Target example 3-14, 5-12 PCI Target lock 3-10, 5-9 PCI Target operation 3-1, 5-1 PCI Target transfer 3-11, 5-9 PCIMLR 11-14 PMCSR 11-16 power management interface specification 8-1 response to FIFO 3-2 software reset 3-1, 5-1 system bus interface pins 12-3-12-4 Vcc 1-8 VPD 10-1 wait states 2-3, 4-3 PCI Initiator 3-11, 5-9 access 3-3, 5-3 access to PCI Bus 12-11, 12-14 configuration 3-5, 5-5 Dual Address cycle 3-6, 5-6 FIFO 12-7, 12-9, 12-12 FIFOs 3-3-3-4, 5-4 I/O 3-5, 5-5 configuration access 3-5, 5-5 decode 3-3, 5-4 interrupts 6-4 Local Bus Address phase 12-6, 12-9, 12-12 Local Bus cycles 2-2, 4-2 Local Bus data parity 2-5, 4-5 Local Bus Endian mode 2-5, 2-7, 4-5, 4-7 Local Bus Read accesses 2-4, 4-4 Master Command codes 2-1, 4-1 memory 3-3, 5-4 access 3-4, 5-4 write and invalidate 3-7, 5-8 operation 3-1, 5-1 PCI Arbitration 2-2, 4-2 PCI Target abort 3-7, 5-6-5-7 reads 3-4-3-5, 5-5 wait states, Local Bus 2-3, 4-3 writes 3-4, 5-4 PCI Initiator register (DMDAC) 11-28 PCI Latency Timer PCI Target 1-4 PCI NMI, all modes 6-4 PCI SERR#, all modes 6-4 PCI Target 1-1, 1-6 abort 3-7, 5-6-5-7 accesses to 8- or 16-bit Local Bus 2-4, 4-4 atomic operation 1-14 Big Endian/Little Endian cycle reference table 2-5, 4-5 BTERM# input 2-3, 4-3 bursting 1-7 Command code 2-1, 4-1 Data Pipe Architecture 1-1 description 1-4 Direct Data Transfer mode 3-1-3-16, 5-1-5-14 during serial EEPROM initialization 2-7, 2-11, 4-7, 4-11 example 5-12-5-13 FIFO depth 1-8 FIFO full or empty, response to 3-2, 5-2 FIFOs depth 1-5 initialization, local bus 3-12, 5-10 Keep Bus mode 1-7 Local Bus Big Endian/Little Endian mode accesses 2-7, 4-7 Local Bus cycles 2-2, 4-2 lock 3-10, 5-9 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. 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Index-17 Index www..com PCI Target Command code to pins operation 3-9-3-15, 5-8-5-13 partial Lword accesses 2-4, 4-4 PCI Latency Timer 1-4 power management 8-1 Power mode example 8-2 priority 3-15, 5-13 Read Ahead mode 1-6 response to FIFO full or empty 3-2 space 0 enable in LAS0BA 11-19 space 1 enable in LAS1BA 11-28 transactions 1-6 transfer 3-11 transfer size 3-14 wait states 2-3, 4-3 PCI Target Command code memory write and invalidate 4-1 PCIBAR0 11-10 PCIBAR1 11-11 PCIBAR2 3-12, 5-10, 11-11 PCIBAR3 3-12, 5-10, 11-12 PCIBAR4 11-12 PCIBAR5 11-12 PCIBISTR 11-10 PCICCR 11-9 PCICIS 11-12 PCICLSR 11-9 PCICR 3-1, 5-1, 11-7 PCIERBAR 3-12, 5-10, 11-13 PCIHIDR 2-7, 4-7, 11-33 PCIHREV 11-33 PCIHTR 11-9 PCIIDR 2-7, 4-7, 11-7 PCIILR 11-14 PCIIPR 11-14 PCILTR 11-9 PCIMGR 11-14 PCIMLR 11-14 PCIREV 11-8 PCISID 11-13 PCISR 11-8 PCISVID 2-7, 4-7, 11-12 PCI-to-Local doorbell interrupt 6-3 PCLK 1-9, 12-4 PERR# 1-9, 12-4 PICMG 1-3 pinout PBGA 14-6, 14-7-14-8 PQFP 14-3 specs 14-1-14-8 pins AD[31:0] 1-9, 12-3 ADS# 1-10, 12-9, 12-12 ALE 1-10, 12-12 BB# 1-10, 12-6 BDIP# 1-10, 12-6 BG# 1-10, 12-6 BI# 1-10, 12-6 BIGEND# 1-10, 12-6, 12-9, 12-12 BLAST# 1-10, 12-9, 12-12 BR# 1-10, 12-6 BREQi 1-10, 12-9, 12-12 BREQo 1-10, 12-9, 12-12 BTERM# 1-10, 12-9, 12-12 BURST# 1-11, 12-6 C and J Bus modes 12-9-12-14 C/BE[3:0]# 1-9, 12-3 CCS# 1-11, 12-5 common to all bus modes 12-2-12-5 DACK0# 1-14, 12-5 DEN# 1-11 DEVSEL# 1-9, 12-3 DMPAF 1-11, 1-13, 12-7, 12-9, 12-12 DP[0:3] 1-11, 12-6, 12-9 PCI 9054 Data Book v2.1 Index-18 (c) PLX Technology, Inc. All rights reserved. www..com PLX Technology, Inc. to Power Management DP[3:0] 1-11, 12-13 DREQ0# 1-11, 1-14, 12-5 DT/R# 1-11, 12-13 EECS 1-11, 12-3 EEDI 1-11, 12-3 EEDO 1-11, 12-3 EESK 1-11, 12-3 ENUM# 12-3 EOT# 1-13, 12-7, 12-9, 12-12 FRAME# 1-9, 12-3, 12-5 GNT# 12-3 IDSEL 1-9, 12-3 INTA# 1-9, 12-4 IRDY# 1-9, 12-4 LA[0:31] 1-11, 12-7 LA[28:2] 1-11, 12-13 LA[31:2] 1-11, 3-14, 12-10 LAD[31:0] 1-11, 12-13 LBE[3:0]# 1-12, 12-10, 12-14 LCLK 1-12, 12-5 LD[0:31] 1-12, 12-7 LD[0:7] 3-14 LD[16:23] 3-14 LD[24:31] 3-14 LD[31:0] 1-12, 12-10 LD[8:15] 3-14 LEDon/LEDin 1-12, 12-5 LFRAME# 1-12 LHOLD 1-12, 12-14 LHOLDA 1-13, 12-11, 12-14 LINT# 1-13, 12-5 LLOCKi# 1-13, 1-14, 12-5 LLOCKo# 1-13, 1-14, 12-5 Local Bus independent interface 12-5 LOCK# 1-9, 12-4 LRESETo# 1-13, 12-5 LSERR# 1-13, 12-11, 12-14 LW/R# 1-13, 12-14 M Bus mode 12-6-12-8 MDREQ# 1-13, 12-7 MODE[1:0] 1-13, 12-5 NANDTREE sequential interconnection 12-16-12-19 PAR 1-9, 12-4 PCI system bus interface 12-3-12-4 PCLK 1-9, 12-4 PERR# 1-9, 12-4 PME# 1-9, 12-4 power and ground 12-2 processor-independent interface 12-5 RD/WR# 1-13, 12-7 READY# 1-13, 4-3, 4-4, 4-7, 4-11, 5-2, 5-4, 5-5, 5-7, 5-8, 5-14, 5-22, 12-11, 12-14, 13-4, 13-6 REQ# 12-4 RETRY# 1-13, 12-7 RST# 1-9, 12-4 serial EEPROM 12-3 SERR# 1-9, 12-4 STOP# 1-9, 12-4 TA# 1-13, 3-4, 3-5, 3-6, 3-7, 3-9, 3-10, 3-12, 12-8 2-3, 3-2 TEA# 1-14, 12-8 TEST 1-14, 12-2 TRDY# 1-9, 12-4 TS# 1-14, 12-8 TSIZ[0:1] 1-14, 3-14, 12-8 USERi 1-14, 12-5 USERo 1-14, 12-5 VDD 1-14, 12-2 VSS 1-14, 12-2 WAIT# 1-10, 1-14, 12-6, 12-11, 12-14 PLX Technology, Inc. company background 1-3 product ordering instructions A-1 representatives and distributors A-1 technical support A-1 PMC 11-15 PMCAPID 11-14 PMCSR 11-16 PMCSR_BSE 11-16 PMDATA 11-17 PME# 1-9, 12-4 PME#_Status 8-2 PMNEXT 11-15 pointer management 7-2 post queue 7-3, 7-5 Power Management 8-1-8-2 Capabilities register (PMC) 11-15 Capability ID register (PMCAPID) 11-14 Control/Status register (PMCSR) 11-16 Data register (PMDATA) 11-17 functional description 8-1-8-2 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. 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Index-19 Index www..com PowerQUICC to read Next Capability Pointer register (PMNEXT) 11-15 PMCSR Bridge Support Extension register (PMCSR_BSE) 11-16 Power mode example 8-2 system changes 8-2 wake-up request example 8-2 PowerQUICC 1-1, 1-4, 1-6 adapter design 1-3 IDMA 1-4 PQFP Local Bus types 2-2, 4-2 ordering instructions A-1 package mechanical dimensions 14-1 PCB layout suggested land pattern 14-2 pinout 14-3 preempt deadlock solution 3-16, 5-14 prefetch counter 1-1, 1-6 LAS0RR 11-19 LAS1RR 11-27 PCI Target read 1-4 PCI Target Read Ahead mode 3-10, 5-9 PCIBAR0 11-10 PCIBAR2 11-11 PCIBAR3 11-12 programmable counter 1-6, 1-8 Read Ahead mode 1-6 priority control Local Bus 1-4 DMA 3-20, 5-20 Processor-independent interface pins 12-5 programmable Local Bus 1-6 prefetch counter Master burst length 1-6 Read Ahead mode 1-6 PROT_AREA 11-22 PVPD_NEXT 11-18 PVPDAD 11-18 PVPDATA PCI VPD Data register 11-18 PVPDCNTL 11-18 Q QBAR 11-41 QSR 11-43 Queue Base Address register (QBAR) 11-41 Status/Control register (QSR) 11-43 R Range registers Local Address Space 0 for PCI-to-Local Bus (LAS0RR) 11-19 Local Address Space 1 for PCI-to-Local Bus (LAS1RR) 11-27 Local Range Register for PCI Initiator-to-PCI (DMRR) 1125 Range, Expansion ROM register (EROMRR) 11-23 ranges operating 13-1, 13-2 RD/WR# 1-13, 12-7 read accesses 2-1, 2-12, 4-1, 4-12 bursts 1-9 configuration 1-9 configuration command 2-1, 4-1 deferred 1-8 deferred PCI Initiator 11-1 DMA 1-5 FIFOs 1-7, 1-8, 2-4, 3-4, 3-9, 4-4, 5-4, 5-8 I/O command 2-1, 4-1 in registers 11-7-11-43 Local Bus accesses 2-4, 4-4 LW/R# 1-13 memory command 2-1, 4-1 line 2-1, 4-1 multiple 2-1, 4-1 PAR 1-9 PCI initialization 3-12, 5-10 Power mode example 8-2 PCI Initiator 1-5 PCI Target 1-5, 1-8, 3-2, 3-10, 5-2, 5-9 PCI Target Command codes 2-1, 4-1 PCI Target prefetching 1-4 PCI Target transfer 3-11, 5-9 PCI-to-Local Delayed mode 1-1 random read and write 10-2 Read Ahead mode 2-4, 3-10, 4-4, 5-9 PCI 9054 Data Book v2.1 Index-20 (c) PLX Technology, Inc. All rights reserved. www..com Read Ahead mode to registers READY# 1-13 sequential read only 10-1 serial EEPROM 1-11, 2-10 accidental write 10-2 control 1-8, 2-9, 4-9 operation 2-7, 4-7 transactions 1-9 VPD 10-1 data 10-1 random read and write 10-2 registers 10-1 sequential read only 10-1 serial EEPROM partitioning 10-1 Read Ahead mode in burst read cycles 2-4, 4-4 PCI Target 3-10, 5-9 supported 1-6 Read Delayed mode 3-10, 5-9 READY# 1-13, 4-3, 5-2, 5-4, 5-5, 5-7, 5-8, 5-14, 5-22 12-11, 12-14 Bus mode 13-4, 13-6 input 4-4 output 13-6 serial EEPROM initialization 4-7, 4-11 reconfiguration, system 9-1 See Also configuration recovery states, J mode only 4-4 registers addresses 1-8 BIGEND 11-21 CAP_PTR 11-14 CNTRL 11-33 DMAARB 11-39 DMACSR0 11-38 DMACSR1 11-38 DMADAC0 11-39 DMADAC1 11-39 DMADPR0 11-35 DMADPR1 11-37 DMALADR0 11-35 DMALADR1 11-37 DMAMODE0 11-34 DMAMODE1 11-36 DMAPADR0 11-35 DMAPADR1 11-37 DMASIZ0 11-35 DMASIZ1 11-37 DMATHR 11-39 DMCBFGA 11-27 DMDAC 11-28 DMLBAI 11-25 DMLBAM 11-25 DMPBAM 11-26 DMRR 11-25 doorbell 6-2, 11-30 EROMBA 11-23 EROMRR 11-23 HS_CNTL 11-17 HS_CSR 11-17 HS_NEXT 11-17 IFHPR 11-41 IFTPR 11-41 INTCSR 11-31 IPHPR 11-42 IPTPR 11-42 IQP 11-40 L2PDBELL 11-30 LAS0BA 11-19 LAS0RR 11-19 LAS1BA 11-28 LAS1RR 11-27 LBRD0 11-24 LBRD1 11-28 LMISC 11-22 mailbox 6-2, 11-29-11-30 MARBR 11-20 MBOX0 11-29 MBOX1 11-29 MBOX2 11-29 MBOX3 11-29 MBOX4 11-29 MBOX5 11-29 MBOX6 11-29 MBOX7 11-30 MQCR 11-41 OFHPR 11-42 OFTPR 11-42 OPHPR 11-42 OPQIM 11-40 OPQIS 11-40 OPTPR 11-43 OQP 11-40 P2LDBELL 11-30 PCIBAR0 11-10 PCIBAR1 11-11 PCIBAR2 11-11 PCIBAR3 11-12 PCIBAR4 11-12 PCIBAR5 11-12 PCIBISTR 11-10 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. 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Index-21 Index www..com remap to serial EEPROM PCICCR 11-9 PCICIS 11-12 PCICLSR 11-9 PCICR 11-7 PCIERBAR 11-13 PCIHIDR 2-7, 4-7, 11-33 PCIHREV 11-33 PCIHTR 11-9 PCIIDR 2-7, 4-7, 11-7 PCIILR 11-14 PCIIPR 11-14 PCILTR 11-9 PCIMGR 11-14 PCIMLR 11-14 PCIREV 11-8 PCISID 11-13 PCISR 11-8 PCISVID 2-7, 4-7, 11-12 PMC 11-15 PMCAPID 11-14 PMCSR 11-16 PMCSR_BSE 11-16 PMDATA 11-17 PMNEXT 11-15 PROT_AREA 11-22 PVPD_NEXT 11-18 PVPDAD 11-18 PVPDATA 11-18 PVPDCNTL 11-18 QBAR 11-41 QSR 11-43 remap PCI-to-Local addresses 3-12, 5-10 See Also map and mapping REQ# 12-4 reset, software 3-1, 5-1 RETRY# 1-13, 3-5, 12-7 capability 3-5 ring management 1-3 RST# 1-9, 3-1, 5-1, 12-4 runtime registers 11-29-11-33 address mapping 11-4 S scatter/gather 3-20, 3-21, 5-16 list management 1-3 ring management 1-3 SDMA operation 3-9 Serial EEPROM Control register (CNTRL) 11-33 Write-Protected Address Boundary register (PROT_AREA) 11-22 serial EEPROM 2-7-2-15, 3-1, 4-7-4-16, 5-1 accidental write to 10-2 address decode enable 11-23 address pointer 11-1 base class code 11-9 chip select 1-11 clock pin 1-11 device ID 11-7 device ID registers 2-7, 4-7 extra long load 2-10, 4-10 extra long load registers 2-10, 4-10 Hot Swap ID 11-17 initialization 2-7, 2-11, 4-7, 4-11 interface 1-1, 1-6 interface pins 12-1, 12-3 internal register access 2-11, 4-11 interrupt pin register 11-14 long load 2-8-2-9, 4-8-4-9 long load registers 2-9, 4-9 memory map 2-11, 4-11 new capabilities function 2-10, 4-11 Next_Cap pointer 11-17 operation 2-7, 4-7 PCI Bus access to internal registers 2-11 PCI Bus, access to internal registers 4-12 random read and write 10-2 read control 1-8 read data 1-11 read-only portion 10-1 recommended 2-10, 4-11 register level programming interface 11-9 revision ID 11-8 simple VPD read to 10-2 simple VPD write to 10-2 software reset 3-1, 5-1 subclass code 11-9 subsystem ID 11-13 support 1-8 timing diagrams 2-13-2-16, 4-13-4-16 vendor ID 11-7 PCI 9054 Data Book v2.1 Index-22 (c) PLX Technology, Inc. All rights reserved. www..com SERR# to Vital Product Data (VPD) vendor ID registers 2-7, 4-7 VPD address 11-18 VPD stored in 10-1 write data 1-11 Write-Protected Address Boundary register (PROT_AREA) 11-1 writes to 10-2 SERR# 1-9, 6-4, 12-4 Shuttle mode, DMA 1-3 signal listing 1-9 signal name C and J Bus modes 12-9-12-14 Local Bus mode independent interface pins 12-5 M Bus mode 12-6-12-8 PCI system bus interface pins 12-3-12-4 power and ground pins 12-2 Processor-independent interface pins 12-5 serial EEPROM interface pins 12-3 signal specs 14-1-14-8 signaling 1-5 Local Bus 1-8 support 1-1 signals synchronous inputs 13-3, 13-4 synchronous outputs 13-5, 13-6 single address block DMA initialization 5-7 software reset 3-1, 5-1 specifications See electrical specifications or general electrical specifications states, recovery J mode only 4-4 STOP# 1-9, 12-4 synchronous inputs 13-3, 13-4 outputs 13-5, 13-6 system reconfiguration 9-1 See Also configuration TEA# 1-14, 3-12, 12-8 technical support A-1 TEST 1-14, 12-2 thermal resistance, package 13-1 Timer, pause 3-25, 5-23 timing diagrams C and J modes 5-24-5-82 DMA 3-51-3-65, 5-63-5-72, 5-81-5-82 dual address 3-18 Local Bus 3-26, 5-24 M mode 3-26-3-65 PCI Initiator 3-27-3-35, 5-25-5-43, 5-73-5-76 PCI Target 3-36-3-50, 5-44-5-62, 5-77-5-80 serial EEPROM 2-13-2-16, 4-13-4-16 transfer size 3-14 TRDY# 1-9, 12-4 TS# 1-14, 12-8 TSIZ[0:1] 1-14, 2-4, 3-14, 12-8 data bus 3-14 225-pin PBGA See PBGA Type 0, configuration cycle 3-5, 5-5 Type 1, configuration cycle 3-5, 5-5 U unaligned DMA transfer support 1-7 User I/O 6-1-6-5 user input and output See Also I/O USERi 1-14, 12-5 USERo 1-14, 12-5 T TA# 1-13, 2-3, 3-2, 3-4, 3-5, 3-6, 3-7, 3-9, 3-10, 3-16, 3-24, 12-8 Bus mode 13-3, 13-5 input 2-4 output 13-5 serial EEPROM initialization 2-7, 2-11 Target See PCI Target V VDD 1-14, 12-2 vendor ID 11-7 Vital Product Data (VPD) 1-1, 10-1-10-2 address 11-2, 11-18 address pointer 11-1 capabilities register 10-1 data 11-2 PCI 9054 Data Book v2.1 (c) PLX Technology, Inc. All rights reserved. Index-23 Index www..com VSS to zero wait state burst operation data register 11-18 ID register 11-18 internal register access 2-11, 4-8, 4-11 last item in capabilities linked list 11-18 new capabilities function 2-10 Next_Cap pointer 11-18 PCI register 11-1 random read and write 10-2 read or write serial EEPROM 2-8 sequential read only 10-1 serial EEPROM accesses 11-22 values programmed with 2-9, 4-9 VPD partitioning 10-1 support in 9054 1-5, 1-8 Write-Protected Address Boundary register (PROT_AREA) 11-1 VSS 1-14, 12-2 PCI Target 1-5, 1-8, 3-2, 5-2 PCI Target Command codes 2-1, 4-1 PCI Target transfer 3-11, 5-9 posted memory (PMW) 1-7 random read and write 10-2 READY# 1-13 serial EEPROM 1-11, 2-10, 4-11, 10-2 accidental 10-2 control 2-9, 4-9 operation 2-7, 4-7 transactions 1-9 VPD 10-1 data 10-1 random read and write 10-2 serial EEPROM partitioning 10-1 simple 10-2 wake-up request example 8-2 Z zero wait state burst operation 1-1, 1-5 W wait state control 2-2, 4-3 cycle control 11-7 generation 1-8, 1-10, 1-13, 2-4, 3-11, 4-4 Local Bus 1-1, 2-3, 4-3 PCI Bus 2-3, 4-3 zero 1-1, 1-5 WAIT# 1-10, 1-14, 12-6, 12-11, 12-14 width control 1-4 write accesses 2-1, 2-12, 4-1, 4-12 and invalidate, memory 1-8 bursts 1-9 configuration 1-9 configuration command 2-1, 4-1 cycles 10-1 DMA 1-5 FIFOs 1-7, 1-8, 2-4, 3-4, 3-9, 4-4, 5-4, 5-8 flush pending 3-10, 5-9 I/O command 2-1, 4-1 in registers 11-7-11-43 Local Bus accesses 2-4, 4-4 LW/R# 1-13 memory command 2-1, 4-1 write and invalidate 2-1, 4-1 PCI Initiator 1-5 PCI power management 8-1 PCI Power mode example 8-2 PCI 9054 Data Book v2.1 Index-24 (c) PLX Technology, Inc. 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