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FAN6206 --Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
April 2010
FAN6206 Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Features
Highly Integrated Dual-Channel SR Controller Receives Synchronized Driving Signal from the Primary Side Internal Linear-Predict Timing Control for DCM Operation Ultra-Low VDD Operating Voltage for Different Output Voltage of PC Power VDD Over-Voltage Protection 14V Gate Driver Clamp
Description
The highly integrated FAN6206 is a dual-channel synchronous rectification (SR) controller. FAN6206 allows design of a cost-effective power supply with fewer external components, especially suited for dualforward topology used to obtain higher efficiency for ATX power supplies. The primary-side control method provides synchronous rectification control for dual-forward converters that operate in continuous conduction mode (CCM). FAN6206 includes a proprietary linear-predict timing control mechanism for dual-forward converters that operate in discontinuous conduction mode (DCM) at fixed or variable frequency. PWM frequency tracking with secondary-side winding detection is provided by adding dividing resistors. The primary-side signals are generated from Fairchild's FAN6210 (Primary-Side Synchronous Rectifier Signal Trigger for Dual-Forward Converter). The primary-side signals are transferred through a pulse transformer to the secondary-side. The benefits of this technique include simple control method and improved power system reliability. FAN6206 is available in 8-pin SOP package.
Applications
PC Power Server Power Open-Frame SMPS
Ordering Information
Part Number
FAN6206MY
Operating Temperature Range
-40C to +105C
Package
8-Pin Small Outline Package (SOP)
Packing Method
Tape & Reel
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
www.fairchildsemi.com
FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
Figure 2. Functional Block Diagram
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2 www.fairchildsemi.com 2
FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Marking Information
F: Fairchild Logo Z: Plant Code X: Year Code Y: Week Code TT: Package Type T: M=SOP P: Y: Green Package M: Manufacture Flow Code
Figure 3. Top Mark
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin #
1,2 3 4 5 6 7 8
Name
LPC1, LPC2 SN SP VDD GATE2 GND GATE1
Description
Winding detection. This pin is used to detect the voltage on the winding during the on-time period of the primary GATE. An internal current source, ICHG, is determined according to the voltage on the DET pin. Synchronized signal to turn on SR. This pin is used to receive the "XN" signal from the primary side to turn off the SR gate. Synchronized signal to turn on SR. This pin is used to receive the "XP" signal from the primaryside to turn-on the SR gate. Power supply pin. The threshold voltages for startup and turn-off are 8.5V and 7.5V, respectively. Driver output for freewheeling synchronous rectifier MOSFET. Ground Driver output for rectifying synchronous rectifier MOSFET.
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
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FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD VHV VL PD JA jt TJ TSTG TL ESD DC Supply Voltage SP, SN LPC
Parameter
Min.
Max.
30 30
Unit
V V V mW C/W C/W C C C kV
-0.3
7.0 400 130 46
Power Dissipation at TA < 50C Junction to Ambient Thermal Resistance Junction to Top Thermal Characteristics Operating Junction Temperature Storage Temperature Range Lead Temperature, (Soldering 10 Seconds) Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 -40 -55
+125 +150 +260 4.00 1.25
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
Min.
-40
Max.
+105
Unit
C
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
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FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Electrical Characteristics
VDD=20V, TA=25 , unless otherwise specified.
Symbol VDD Section
VOP VTH-ON1 VTH-ON2 VTH-OFF1 VTH-OFF2 IDD-OP IDD-ST VDD-OVP1 VDD-OVP2 VDD-OVP-HYS1 VDD-OVP-HYS2 tOVP1 tOVP2 VZ1 VZ2 VOL1 VOL2 VOH1 VOH2 tR1 tR2 tF1 tF2 VZ1 tPD-HIGH-SP1 tPD-HIGH-SP2 tPD-LOW-SN1 tPD-LOW-SN2 tPD-LOW-LPC1 tPD-LOW-LPC2 tON-MAX1 tON-MAX2
Parameter
Continuously Operating Voltage Turn-On Threshold Voltage Turn-On Threshold Voltage Turn-Off Threshold Voltage Turn-Off Threshold Voltage Operating Current Startup Current VDD Over-Voltage Protection 1 VDD Over-Voltage Protection 2 Hysteresis Voltage for VDD OVP 1 Hysteresis Voltage for VDD OVP 2 VDD OVP Debounce Time 1 VDD OVP Debounce Time 2 Output Voltage Maximum (Clamp) 1 Output Voltage Maximum (Clamp) 2 Output Voltage LOW 1 Output Voltage LOW 2 Output Voltage HIGH 1 Output Voltage HIGH 2 Rising Time 1 Rising Time 2 Falling Time1 Falling Time 2 Output Voltage Maximum (Clamp) Propagation Delay to OUT HIGH
Conditions
Min.
Typ.
Max.
25
Units
V V V V V mA A V V V V s s V V V V V V
8.0 8.0 7.0 7.0 VDD=15V, DET=50KHz VDD = 7.5V 20 20 1.2 1.2 40 40 VDD = 20V VDD = 20V VDD=12V, IO=50mA VDD=12V, IO=50mA VDD=12V, IO=50mA VDD=12V, IO=50mA VDD=12V, CL=7nF, OUT=2V~9V VDD=12V, CL=7nF, OUT=2V~9V VDD=12V, CL=7nF, OUT=9V~2V VDD=12V, CL=7nF, OUT=9V~2V VDD = 20V tR+tPD, (Trigger by SP), |SP-SN|=5V tR+tPD, (Trigger by SN), |SP-SN|=5V tR+tPD, (Trigger by LPC) 280 280 180 180 100 100 12 12 9 9 30 30 20 20
8.5 8.5 7.5 7.5 3 340 21 21 1.7 1.7 60 60 12 12
9.0 9.0 8.0 8.0 5 500 22 22 2.2 2.2 100 100 14 14 0.5 0.5
Output Drive for SR MOSFET Section
70 70 50 50 12 350 350 250 250 150 150 13 13
120 120 100 100 14 450 450 350 350 200 200 14 14
ns ns ns ns V ns
Propagation Delay to OUT LOW
ns
Propagation Delay to OUT LOW Maximum On Time
ns s s
Continued on the following page...
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
www.fairchildsemi.com 5
FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Electrical Characteristics
VDD=20V, TA=25C, unless otherwise specified.
Symbol SP/SN Section
VN-P(turn off) 1 VN-P(turn off) 2 VP-N(turn on) 1 VP-N(turn on) 2 Ratio_SP-SN
Parameter
Threshold Voltage of VN-VP to Turn-Off SR MOS 1 Threshold Voltage of VN-VP to Turn-Off SR MOS 2 Threshold Voltage of VP-VN to Turn-On SR MOS 1 Threshold Voltage of VP-VN to Turn-On SR MOS 2 Voltage Difference between SP and SN
Conditions
Sweep VN-P- from LOW to HIGH
Min.
Typ.
Max.
Units
3 3
4 4 4 4
5 5 5 5 5
V V V V %
Sweep VP-N- from LOW to HIGH Sweep VP-N- from LOW to HIGH | VSP-VSN | / MIN(VSP,VSN) Connect a Diode 1N4148 and Divider (Ratio 12) to LPC, VDET = 3V, VLPC = 3V
3 3
LPC Section
Ratio_LPC-RES Charge Divide Discharge Current Transfer Ratio vs. Input Voltage LPC Enable Threshold Voltage 1 LPC Enable Threshold Voltage 2 Lower Clamp Voltage 1 Lower Clamp Voltage 2 Maximum Source Current 1 Maximum Source Current 2 Threshold Voltage for Disable LPC Function Threshold Voltage for Disable LPC Function Debounce Time for Disable LPC Function Debounce Time for Disable LPC Function VLPC < VLPC-LOW VLPC < VLPC-LOW ILPC = -5A ILPC = -5A VLPC = -0.3V VLPC = -0.3V 1.3 1.3 70 70 2.79 3.00 3.21
VLPC-EN1 VLPC-EN2 VLPC-CLAMP1 VLPC-CLAMP2 ILPC-SOURCE1 ILPC-SOURCE2 VLPC-LOW1 VLPC-LOW2 tLPC-LOW1 tLPC-LOW2
1.8 1.8 0.10 0.10
2.0 2.0 0.25 0.25 250 250 1.5 1.5 100 100
2.2 2.2 0.40 0.40 300 300 1.7 1.7 130 130
V V V V A A V V s s
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
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FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Typical Performance Characteristics
These characteristic graphs are normalized at TA = 25C.
8.5 8.4
8.5 8.4
VTH-ON1 (V)
8.3 8.2 8.1 8.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
VTH-ON2 (V)
8.3 8.2 8.1 8.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 5. Turn-On Threshold Voltage 1
Figure 6. Turn-On Threshold Voltage 2
7.7
7.7
7.6
7.6
VTH-OFF1 (V)
7.5
VTH-OFF2 (V)
-40 -25 -10 5 20 35 50 65 80 95 110 125
7.5
7.4
7.4
7.3
7.3 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 7. Turn-Off Threshold Voltage 1
Figure 8. Turn-Off Threshold Voltage 2
2.9
500
2.8
IDD_OP (mA)
2.7
IDD_ST (uA)
-40 -25 -10 5 20 35 50 65 80 95 110 125
400
300
2.6
2.5
200 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 9. Operating Current
Figure 10.Startup Current
420 400
420 400
tPD-HIGH-SP1 (ns)
380 360 340 320 300 280 -40 -25 -10 5 20 35 50 65 80 95 110 125
tPD-HIGH-SP2 (ns)
380 360 340 320 300 280 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 11. Propagation Delay to OUT HIGH 1 (Trigger by SP)
Figure 12.Propagation Delay to OUT HIGH 2 (Trigger by SP)
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
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FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Typical Performance Characteristics
These characteristic graphs are normalized at TA = 25C.
350
350
tPD-LOW-SN1 (ns)
tPD-LOW-SN2 (ns)
-40 -25 -10 5 20 35 50 65 80 95 110 125
300
300
250
250
200
200
150
150 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 13. Propagation Delay to OUT LOW 1 (Trigger by SN)
Figure 14.Propagation Delay to OUT LOW 2 (Trigger by SN)
180
180
tPD-LOW-LPC1 (ns)
160
tPD-LOW-LPC2 (ns)
-40 -25 -10 5 20 35 50 65 80 95 110 125
160
140
140
120
120 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 15. Propagation Delay to OUT LOW 1 (Trigger by LPC)
Figure 16.Propagation Delay to OUT LOW 2 (Trigger by LPC)
14.0
14.0
13.5
13.5
tON_MAX1 (us)
13.0
tON-MAX2 (us)
-40 -25 -10 5 20 35 50 65 80 95 110 125
13.0
12.5
12.5
12.0
12.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 17. Maximum On Time 1
Figure 18.Maximum On Time 2
5.0
5.0
VN-P(turn off) 1 (V)
4.0
VN-P(turn off) 2 (V)
-40 -25 -10 5 20 35 50 65 80 95 110 125
4.5
4.5
4.0
3.5
3.5
3.0
3.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 19. Threshold Voltage of VN-VP to Turn Off SR MOS 1
Figure 20.Threshold Voltage of VN-VP to Turn Off SR MOS 2
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
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FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Typical Performance Characteristics
These characteristic graphs are normalized at TA = 25C.
5.0
5.0
VP-N(turn on) 2 (ns)
-40 -25 -10 5 20 35 50 65 80 95 110 125
VP-N(turn on) 1 (V)
4.5
4.5
4.0
4.0
3.5
3.5
3.0
3.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 21. Threshold Voltage of VP-VN to Turn On SR MOS 1
Figure 22.Threshold Voltage of VP-VN to Turn On SR MOS 2
2.2
2.2
2.1
2.1
VLPC-EN1 (V)
2.0
VLPC-EN2 (V)
-40 -25 -10 5 20 35 50 65 80 95 110 125
2.0
1.9
1.9
1.8
1.8 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 23. LPC Enable Threshold Voltage 1
Figure 24.LPC Enable Threshold Voltage 2
0.4
0.4
VLPC-CLAMP1 (V)
0.3
VLPC-CLAMP2 (V)
-40 -25 -10 5 20 35 50 65 80 95 110 125
0.3
0.2
0.2
0.1
0.1 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 25. Lower Clamp Voltage 1
Figure 26.Lower Clamp Voltage 2
300
300
ILPC-SOURCE1 (uA)
250
ILPC-SOURCE2 (V)
-40 -25 -10 5 20 35 50 65 80 95 110 125
275
275
250
225
225
200
200 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 27. Maximum Source Current 1
Figure 28.Maximum Source Current 2
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
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FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Function Description
Figure 29 and Figure 30 show the simplified circuit diagram of a dual-forward converter and its key waveforms. Switches Q1 and Q2 are turned on and off together. Once Q1 and Q2 are turned on, input voltage is applied across the transformer primary side and power is delivered to the secondary side through the transformer, powering D1. During this time, the magnetizing current linearly increases. When Q1 and Q2 are turned off, the magnetizing current of the transformer forces the reset diodes (DR1 and DR2) and negative input voltage is applied across the transformer primary side. During this time, magnetizing current linearly decreases to zero and the secondary-side inductor current freewheels through diode D2. When synchronous rectifier SR1 and SR2 are used instead of diodes D1 and D2, it is important to have proper timing between drive signals for SR1 and SR2. Figure 31 shows a typical application circuit. When a dual-forward converter operates in continuous conduction mode, the SR gate signals (GATE1 and GATE2) are mainly controlled by SP and SN signals. SP and SN signals are transferred through a pulse transformer from XP and XN signals, which are generated by FAN6210 (Primary-Side Synchronous Rectifier Signal Trigger for Dual Forward Converter).
Figure 31. Typical Application Circuit Figure 32 shows the timing diagram for continuous conduction mode (CCM). Figure 33 shows the timing diagram for discontinuous conduction mode (DCM). Figure 29. Simplified Circuit Diagram of Dual-Forward Converter The switching operation of SR MOSFETs Q3 and Q4 is determined by the SN and SP signals. FAN6206 turns on SR MOSFETs at the rising edge of the SP signal, while it turns off the SR MOSFETs at the rising edge of the SN signal. Within one switching cycle, SP and SN are obtained two times. With a voltage divider R1 and R2 connected from LPC1 to secondary winding, R3 and R4 connected from LPC2 to secondary winding, the PWM timing sequences and frequency can be tracked precisely. The SR MOSFET is turned on by SP signal only when the voltage level on LPC1 or LPC2 pin is pulled LOW to GND. During PWM-on period, the rectifying SR Q3 is turned on by the rising edge of the SP signal after a propagation delay (tPD-HIGH-SP1) and Q3 is turned off by the rising edge of the SN signal after a propagation delay (tPD-LOW-SN1). During PWM-off period, the freewheeling SR Q4 is turned on by the rising edge of the SP signal after a propagation delay (tPD-HIGH-SP2) and Q4 is turned off by the rising edge of the SN signal after a propagation delay (tPD-LOW-SN2) in CCM operation. Figure 30. Key Waveforms of Dual-Forward Converter In DCM operation, the proprietary Linear-Predict Timing Control (LPC) technique can provide synchronous rectification control mechanism for freewheeling SR MOSFET. Since SN signal is sent following with PWM signal, the freewheeling SR MOSFET cannot be turned off in time by SN signal before ILo linearly decreases to zero. Therefore, the LPC mechanism is applied to turn off Q3 in DCM mode.
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
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FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Figure 32. SR Gate is Driven by SP & SN Signal in CCM Mode
Figure 33. Freewheeling SR Turned Off by LPC Mechanism in DCM Mode
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
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FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Linear-Predict Timing Control
When a dual-forward converter operates in CCM or DCM; in PWM tON period, the VIN voltage is applied to the primary winding and the secondary inductor starts to rise linearly and store energy. The across voltage on secondary winding is coupled from primary winding and proportional to VIN. The SR controller can detect this winding voltage through a voltage divider and acquire the VIN level. According to this detected VIN level during PWM turn-on period, SR controller produces a charge current ICHG to charge internal capacitor, CT, of the SR controller. On the other hand, at PWM turn-off period, the energy stored in the secondary inductor is discharged. The SR controller also detects the output voltage level to modulate discharge current IDISCHG of internal capacitor, CT. Once the internal capacitor voltage reaches zero, SR controller turns off SR MOS immediately. R4 is connected between the LPC2 pin and the drain terminal of Q4. During PWM turn-on period, voltage on the LPC2 pin is pulled HIGH due to the secondary winding coupled from primary winding. At this moment, SR MOS is turned off and the internal body diode of SR MOS is reverse-biased. During PWM turn-off period, the potential on the primary winding reverses and the internal body diode starts to conduct output current. The voltage on the LPC2 pin is also pulled LOW to GND. R2 is recommended as 10k and the divided voltage level on the LPC1 pin is suggested between 3V~5V. If the voltage level of VO is 12V, the resistor values are recommended as 105k for R3 and 10k for R4. The R4 turn-off timing of Q4 is determined by the ratio R3 + R 4 as Figure 34 shows. If off earlier. R4 decreases, Q4 is turned R3 + R 4
Under-Voltage Lockout (UVLO)
The power-on and off thresholds are fixed at 8.5V and 7.5V. The VDD pin is connected to a 12V output voltage terminal.
VDD Pin Over-Voltage Protection
The over-voltage conditions are usually caused by open feedback loops. VDD over-voltage protection is built in to prevent damage if over voltage occurs. When the voltage on the VDD pin exceeds 21V, the SR controller turns off all of SR MOS operations.
Figure 34. Turn-Off Timing of Freewheeling SR
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
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FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Typical Application Circuit (Dual-Forward Converter with SR)
Application Fairchild Devices
FAN4801 PC Power FAN6210 FAN6206 90~264VAC 12V/25A
Input Voltage Range
Output
Figure 35. Application Circuit
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
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FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Physical Dimensions
5.00 4.80 3.81
8 5
A
0.65
B
6.20 5.80
4.00 3.80
1 4
1.75
5.60
PIN ONE INDICATOR
(0.33)
1.27
0.25
M
CBA
1.27
LAND PATTERN RECOMMENDATION
0.25 0.10 1.75 MAX
C 0.10 0.51 0.33 0.50 x 45 0.25 C
SEE DETAIL A
0.25 0.19
OPTION A - BEVEL EDGE
R0.10 R0.10
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13
8 0 0.90 0.406
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 36. 8-Pin Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
www.fairchildsemi.com 14
www.fairchildsemi.com
FAN6206 -- Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
(c) 2010 Fairchild Semiconductor Corporation FAN6206 * Rev. 1.0.2
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