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General Features
* Single-package High Performance, Low Power AVR 8-bit Microcontroller with LIN * * * * * *
Transceiver, 5V Regulator and Watchdog Very Low Current Consumption in Sleep Mode 8Kbytes/16Kbytes Flash Memory for Application Program (Atmel ATA6616/ATA6617) Supply Voltage Up to 40V Operating Voltage: 5V to 27V Temperature Range: Tcase -40C to +125C QFN38, 5mm x 7mm Package
1. Description
Atmel(R) ATA6616/ATA6617 is a System-in-Package (SiP) product, which is particularly suited for complete LIN-bus node applications. It supports highly integrated solutions for in-vehicle LIN networks. The first chip is the LIN-system-basis-chip (LIN-SBC) ATA6624, which has an integrated LIN transceiver, a 5V regulator and a window watchdog. The second chip is an automotive microcontroller from Atmel(R)'s series of AVR(R) 8-bit microcontroller with advanced RISC architecture, the Atmel ATtiny87 with 8-Kbytes and the Atmel ATtiny167 with 16-Kbytes flash memory. All pins of the LIN System Basis Chip as well as all pins of the AVR microcontroller are bonded out to provide customers the same flexibility for their applications as they have when using discrete parts. In section 2 you will find the pin configuration for the complete SiP. In section 3 the LIN SBC is described, and in section 6 the AVR is described in detail. Figure 1-1. Application Diagram
LIN Bus
Microcontroller with LIN Transceiver, 5V Regulator and Watchdog Atmel ATA6616 Atmel ATA6617
Atmel ATA6616/17 MCU Atmel ATtiny 87/167 LIN-SBC Atmel ATA6624
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2. Atmel ATA6616/ATA6617 LIN System in Package Solution (SIP)
2.1 Pinning Atmel ATA6616/ATA6617
Pinning QFN38
AGND AVCC LIN GND PB6 PB7 PA7 PA6 PA5 PA4 PA3 WAKE
Figure 2-1.
PB5 PB4 VCC GND GND GND PB3
31 30 29 28 27 26 25 24 23 22 21 20 32 19 33 34 35 36 37 38 1 PB2 2 PB1 3 PB0 4 PA0 5 PA1 6 PA2 7 RXD 8 INH 18 17
NTRIG EN VS VCC PVCC KL15 MODE
Atmel ATA6616/17
16 15 14
13 9 10 11 12 TXD NRES WD_OSC TM
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Note:
Pin Description
Symbol PB2 PB1 PB0 PA0 PA1 PA2 RXD(1) INH(1) TXD
(1) (1)
Function Port B 2 I/O line (PCINT10/OC1AV/USCK/SCL) Port B 1 I/O line (PCINT9/OC1BU/DO) Port B 0 I/O line (PCINT8/OC1AU/DI/SDA) Port A 0 I/O line (PCINT0/ADC0/RXD/RXLIN) Port A 1 I/O line (PCINT1/ADC1/TXD/TXLIN) Port A 2 I/O line (PCINT2/ADC2/OC0A/DO/MISO) Receive data output Battery-related output for controlling an external voltage regulator Transmit data input; active low output (strong pull down) after a local wake-up request Output undervoltage and watchdog reset (open drain) External resistor for adjustable watchdog timing For factory testing only (tie to ground) For debug mode: Low watchdog is on; high watchdog is off Ignition detection (edge sensitive) 5V regulator sense input pin 5V regulator output/driver pin Battery supply Enables the device into Normal Mode Low level watchdog trigger input from microcontroller High voltage input for local wake-up request; if not needed connect to VS System Ground LIN-SBC LIN bus line input/output
NRES TM
WD_OSC(1)
(1) (1)
MODE KL_15 VCC VS EN
(1)
PVCC(1)
(1) (1) (1)
NTRIG(1) WAKE GND LIN
(1) (1)
(1)
1. This identifies the pins of the LIN SBC Atmel(R) ATA6624
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Table 2-1.
Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Note:
Pin Description (Continued)
Symbol PA3 AVCC AGND PA4 PA5 PA6 PA7 PB7 PB6 PB5 PB4 VCC GND GND GND PB3 Backside Function Port A 3 I/O line (PCINT3/ADC3/ISRC/INT0) Analog supply voltage Analog ground Port A 4 I/O line (PCINT4/ADC4/ICP1/DI/SDA/MOSI) Port A 5 I/O line (PCINT5/ADC5/T1/USCK/SCL) Port A 6 I/O line (PCINT6/ADC6/AIN0/SS) Port A 7 I/O line (PCINT7/ADC7/AIN1) Port B 7 I/O line (PCINT15/ADC10/OC1BX / RESET) Port B 6 I/O line (PCINT14/ADC9/OC1AX/INT0) Port B 5 I/O line (PCINT13/ADC8/OC1BW/XTAL2/CLKO) Port B 4 I/O line (PCINT12/OC1AW/XTAL1/CLKI) AVR supply voltage System ground Ground (optional) Ground (optional) Port B 3 I/O line (PCINT11/OC1BV) Heat slug is connected to GND
1. This identifies the pins of the LIN SBC Atmel(R) ATA6624
2.2
Absolute Maximum Ratings
Maximum Ratings of the SiP
Table 2-2.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) CDM ESD STM 5.3.1 Machine Model ESD AEC-Q100-RevE Storage temperature Operating temperature
(1)
Symbol
Min.
Typ.
Max.
Unit
3
KV
1 150 Ts Tcase Rthjc Rthja 150 150 -55 -40 6 30 165 165 10 170 170 +150 +125
KV V C C K/W K/W C C C
Thermal resistance junction to heat slug Thermal resistance junction to ambient Thermal shutdown of VCC regulator Thermal shutdown of LIN output Thermal shutdown hysteresis Note:
1. Tcase means the temperature of the heat slug (backside). It is mandatory that this backside temperature is 125C in the application.
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3. LIN System-basis-chip Block
3.1 Features
* * * * * *
Master and Slave Operation Possible Supply Voltage up to 40V Operating voltage VS = 5V to 27V Typically 10A Supply Current During Sleep Mode Typically 57A Supply Current in Silent Mode Linear Low-drop Voltage Regulator: - Normal, Fail-safe, and Silent Mode - VCC = 5.0V 2% - In Sleep Mode VCC is Switched Off VCC Undervoltage Detection (4ms Reset Time) and Watchdog Reset Logical Combined at Open Drain Output NRES Negative Trigger Input for Watchdog Boosting the Voltage Regulator Possible with an External NPN Transistor LIN Physical Layer According to LIN 2.0, 2.1 Specification and SAEJ2602-2 Wake-up Capability via LIN-bus, Wake Pin, or Kl_15 Pin INH Output to Control an External Voltage Regulator or to Switch off the Master Pull-up Resistor TXD Time-out Timer Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery Adjustable Watchdog Time via External Resistor Advanced EMC and ESD Performance Fulfills the OEM "Hardware Requirements for LIN in Automotive Applications Rev.1.1" Interference and Damage Protection According ISO7637
* * * * * * * * * * * *
3.2
Description
The LIN-SBC is a fully integrated LIN transceiver, which complies with the LIN 2.0, 2.1 and SAEJ2602-2 specifications. It has a low-drop voltage regulator with a 5V/50mA output and a window watchdog. The LIN-SBC is designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN-driver ensures secure data communication up to 20kBaud. Sleep Mode and Silent Mode guarantee very low current consumption.
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Figure 3-1. Block Diagram
VS Normal and Fail-safe Mode PVCC Receiver
INH
RXD
Normal Mode
+
RF Filter WAKE KL_15 PVCC Edge Detection Wake-up Bus Timer LIN
TXD
TXD Time-out Timer
Slew Rate Control
Short Circuit and Overtemperature Protection
Control Unit
EN
Debounce Time
Mode Select
Normal/Silent/ Fail-safe Mode 3.3/5V /50 mA/2% Undervoltage Reset
VCC PVCC NRES
Internal Testing Unit GND PVCC
OUT
Watchdog
Adjustable Watchdog Oscillator
WD_OSC
MODE
TM
NTRIG
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3.3
3.3.1
Functional Description
Physical Layer Compatibility Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions. Supply Pin (VS) The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if VS falls below VSth < 4V in order to avoid false bus messages. After switching on VS, the IC starts in Fail-safe Mode, and the voltage regulator is switched on (i.e., output capability). The supply current is typically 10A in Sleep Mode and 57A in Silent Mode.
3.3.2
3.3.3
Ground Pin (GND) The IC does not affect the LIN Bus in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS. The mandatory system ground is pin 5. Voltage Regulator Output Pin (VCC) The internal 5V voltage regulator is capable of driving loads up to 50mA. It is able to supply the microcontroller and other ICs on the PCB and is protected against overload by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun. To boost the maximum load current, an external NPN transistor with its base connected to the VCC pin and its emitter connected to PVCC can be used. Voltage Regulator Sense Pin (PVCC) The PVCC is the sense input pin of the voltage regulator. For normal applications (i.e., when only using the internal output transistor), this pin is connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be connected to the output of this transistor, i.e., its emitter terminal. Bus Pin (LIN) A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN 2.x specification are implemented. The allowed voltage range is between -27V and +40V. Reverse currents from the LIN bus to VS are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to recessive bus state are slope controlled.
3.3.4
3.3.5
3.3.6
3.3.7
Input/Output Pin (TXD) In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled to ground in order to have a low LIN bus. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output. It is current-limited to < 8mA. and is latched to low if the last wake-up event was from pin WAKE or KL_15.
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3.3.8 TXD Dominant Time-out Function The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced to low for longer than tDOM > 6ms, the LIN-bus driver is switched to recessive state. To reactivate the LIN-bus driver, switch TXD to high (> 10s). 3.3.9 Output Pin (RXD) The Output pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically 5k to VCC. The AC characteristics can be defined with an external load capacitor of 20pF. The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., VS = 0V). 3.3.10 Enable Input Pin (EN) The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in Normal Mode with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 5V/50 mA output capability. If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data transmission is then possible, and the current consumption is reduced to IVS typ. 57A. The VCC regulator has its full functionality. If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmission is possible, and the voltage regulator is switched off. 3.3.11 Wake Input Pin (WAKE) The Wake Input pin is a high-voltage input used to wake up the device from Sleep Mode or Silent Mode. It is usually connected to an external switch in the application to generate a local wake-up. A pull-up current source, typically 10A, is implemented. If a local wake-up is not needed for the application, connect the Wake pin directly to the VS pin. 3.3.12 Mode Input Pin (MODE) Connect the MODE pin directly or via an external resistor to GND for normal watchdog operation. To debug the software of the connected microcontroller, connect the MODE pin to VCC and the watchdog is switched off. TM Input Pin The TM pin is used for final production measurements at Atmel. In normal application, it must always be connected to GND.
3.3.13
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3.3.14
KL_15 Pin The KL_15 pin is a high-voltage input used to wake up the device from Sleep or Silent Mode. It is an edge-sensitive pin (low-to-high transition). It is usually connected to ignition to generate a local wake-up in the application when the ignition is switched on. Although KL_15 pin is at high voltage (VBatt), it is possible to switch the IC into Sleep or Silent Mode. Connect the KL_15 pin directly to GND if you do not need it. A debounce timer with a typical TdbKl_15 of 160s is implemented. The input voltage threshold can be adjusted by varying the external resistor due to the input current IKL_15. To protect this pin against voltage transients, a serial resistor of 47 k and a ceramic capacitor of 100nF are recommended. With this RC combination you can increase the wake-up time TwKL_15 and, therefore, the sensitivity against transients on the ignition Kl.15. You can also increase the wake-up time using external capacitors with higher values.
3.3.15
INH Output Pin The INH Output pin is used to switch an external voltage regulator on during Normal or Fail-safe Mode. The INH pin is switched off in Sleep or Silent Mode. It is possible to switch off the external 1k master resistor via the INH pin for master node applications. The INH pin is switched off during VCC undervoltage reset.
3.3.16
Reset Output Pin (NRES) The Reset Output pin, an open-drain output, switches to low during VCC undervoltage or a watchdog failure. WD_OSC Output Pin The WD_OSC Output pin provides a typical voltage of 1.2V, which supplies an external resistor with values between 34k and 120k to adjust the watchdog oscillator time. NTRIG Input Pin The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge triggers the watchdog. The trigger signal (low) must exceed a minimum time ttrigmin to generate a watchdog trigger.
3.3.17
3.3.18
3.3.19
Wake-up Events from Sleep or Silent Mode * LIN-bus * WAKE pin * EN pin * KL_15
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3.4 Modes of Operation
Modes of Operation
Unpowered Mode VBatt = 0V b a b b c+d+e a: VS > 5V b: VS < 4V c: Bus wake-up event d: Wake up from WAKE or KL_15 pin e: NRES switches to low
Figure 3-2.
Fail-safe Mode b e EN = 1
Go to silent command
VCC: 5V/50mA With undervoltage monitoring Communication: OFF Watchdog: ON EN = 1 c+d
EN = 0 TXD = 1 Normal Mode VCC: 5V/50mA With undervoltage monitoring
Go to sleep command Local wake-up event
Silent Mode VCC: 5V/50mA With undervoltage monitoring Communication: OFF Watchdog: OFF
EN = 1
Communication: ON Watchdog: ON
EN = 0 TXD = 0
Sleep Mode VCC: switched off Communication: OFF Watchdog: OFF
Table 3-1.
Mode of Operation Fail-safe
Modes of Operation
Transceiver Off VCC 5V Watchdog On WD_OSC 1.23V INH On RXD High, except after wake up LIN depending High 0V LIN Recessive TXD depending Recessive Recessive
Normal Silent Sleep
On Off Off
5V 5V 0V
On Off Off
1.23V 0V 0V
On Off Off
3.4.1
Normal Mode This is the normal transmitting and receiving mode of the LIN interface in acoordance with the LIN specification LIN 2.x. The voltage regulator is active and can source up to 50mA. The undervoltage detection is activated. The watchdog needs a trigger signal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes its state to Fail-safe Mode.
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3.4.2
Silent Mode A falling edge at EN when TXD is high switches the IC into Silent Mode. The TXD Signal has to be logic high during the Mode Select window (see Figure 3-3 on page 10). The transmission path is disabled in Silent Mode. The overall supply current from VBatt is a combination of the IVSsi = 57A plus the VCC regulator output current IVCC. A 5V regulator with 2% tolerance can source up to 50mA. The internal slave termination between the LIN pin and the VS pin is disabled in Silent Mode. Only a weak pull-up current (typically 10A) between the LIN pin and the VS pin is present. Silent Mode can be activated independently from the actual level on the LIN, WAKE, or KL_15 pins. If an undervoltage condition occurs, NRES is switched to low, and the IC changes its state to Fail-safe Mode. A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on the internal slave termination between the LIN pin and the VS pin. Figure 3-3. Switch to Silent Mode
Normal Mode Silent Mode
EN
TXD
Mode select window td = 3.2s
NRES
VCC
Delay time silent mode td_silent = maximum 20s LIN LIN switches directly to recessive mode
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (tbus) and followed by rising edge at the LIN pin (see Figure 3-4 on page 11) results in a remote wake-up request. The device switches from Silent Mode to Fail-safe Mode. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 3-4 on page 11). EN high can be used to switch directly to Normal Mode.
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Figure 3-4. LIN Wake-up from Silent Mode
Bus wake-up filtering time tbus Fail-safe mode Normal mode
LIN bus
Node in silent mode
RXD
High
Low
High
TXD
Watchdog
Watchdog off
Start watchdog lead time td
VCC voltage regulator
Silent mode 3.3V/5V/50mA
Fail safe mode 3.3V/5V/50mA
Normal mode
EN High EN
NRES
Undervoltage detection active
3.4.3
Sleep Mode A falling edge at EN when TXD is low switches the IC into Sleep Mode. The TXD Signal has to be logic low during the Mode Select window (Figure 3-5 on page 12). In order to avoid any influence to the LIN-pin during switching into sleep mode it is possible to switch the EN up to 3.2s earlier to LOW than the TXD. Therefore, the best and easiest way are two falling edges at TXD and EN at the same time.The transmission path is disabled in Sleep Mode. The supply current IVSsleep from VBatt is typically 10A. The VCC regulator is switched off. NRES and RXD are low. The internal slave termination between the LIN pin and VS pin is disabled, only a weak pull-up current (typically 10A) between the LIN pin and the VS pin is present. Sleep Mode can be activated independently from the current level on the LIN, WAKE, or KL_15 pin. A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on the internal slave termination between the LIN pin and the VS pin.
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A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (tbus) and a following rising edge at pin LIN results in a remote wake-up request. The device switches from Sleep Mode to Fail-safe Mode. The VCC regulator is activated, and the remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 3-6 on page 13). Figure 3-5. Switch to Sleep Mode
Normal Mode Sleep Mode
EN
Mode select window TXD td = 3.2s NRES
VCC
Delay time sleep mode td_sleep = maximum 20s LIN LIN switches directly to recessive mode
3.4.4
Fail-safe Mode The device automatically switches to Fail-safe Mode at system power up and the voltage regulator is switched on (see Figure 3-7 on page 16).The NRES output switches to low for tres = 4ms and gives a reset to the microcontroller. LIN communication is switched off. The IC stays in this mode until EN is switched to high. The IC then changes to Normal Mode. A power down of VBatt (VS < 4V) during Silent or Sleep Mode switches the IC into Fail-safe Mode. A low at NRES switches into Fail-safe Mode directly. During Fail-safe Mode the TXD pin is an output and signals the last wake-up source.
3.4.5
Unpowered Mode If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor (see Figure 3-7 on page 16). After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from Unpowered Mode to Fail-safe Mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends on the VCC capacitor and the load. The NRES is low for the reset time delay treset. During this time, treset, no mode change is possible.
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Figure 3-6. LIN Wake-up from Sleep Mode
Bus wake-up filtering time tbus Fail-safe Mode Normal Mode
LIN bus
RXD
Low or floating
Low
TXD
VCC voltage regulator
On state Off state Regulator wake-up time EN High
EN Reset time NRES Floating Microcontroller start-up time delay
Watchdog
Watchdog off
Start watchdog lead time td
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3.5
3.5.1
Wake-up Scenarios from Silent or Sleep Mode
Remote Wake-up via Dominant Bus State A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver. A falling edge at the LIN pin followed by a dominant bus level VBUSdom maintained for a certain time period (tBUS) and a rising edge at pin LIN result in a remote wake-up request. The device switches from Silent or Sleep Mode to Fail-safe Mode. The VCC voltage regulator is/remains activated, the INH pin is switched to high, and the remote wake-up request is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller. A low level at the LIN pin in the Normal Mode starts the bus wake-up filtering time, and if the IC is switched to Silent or Sleep Mode, it will receive a wake-up after a positive edge at the LIN pin.
3.5.2
Local Wake-up via Pin WAKE A falling edge at the WAKE pin followed by a low level maintained for a certain time period (tWAKE) results in a local wake-up request. The device switches to Fail-safe Mode. The local wake-up request is indicated by a low level at the RXD pin to generate an interrupt in the microcontroller and a strong pull down at TXD. When the WAKE pin is low, it is possible to switch to Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to high > 10s before the negative edge at WAKE starts a new local wake-up request. Local Wake-up via Pin KL_15 A positive edge at pin KL_15 followed by a high voltage level for a certain time period (> tKL_15) results in a local wake-up request. The device switches into the Fail-safe Mode. The extra long wake-up time ensures that no transients at KL_15 create a wake-up. The local wake-up request is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller and a strong pull down at TXD. During high-level voltage at pin KL_15, it is possible to switch to Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to low > 250s before the positive edge at KL_15 starts a new local wake-up request. With external RC combination, the time is even longer. Wake-up Source Recognition The device can distinguish between a local wake-up request (Wake or KL_15 pins) and a remote wake-up request (via LIN bus). The wake-up source can be read on the TXD pin in Fail-safe Mode. A high level indicates a remote wake-up request (weak pull up at the TXD pin); a low level indicates a local wake-up request (strong pull down at the TXD pin). The wake-up request flag (signalled on the RXD pin) as well as the wake-up source flag (signalled on the TXD pin) is immediately reset if the microcontroller sets the EN pin to high (see Figure 3-3 on page 10 and Figure 3-4 on page 11) and the IC is in Normal Mode. The last wake-up source flag is stored and signalled in Fail-safe Mode at the TXD pin.
3.5.3
3.5.4
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3.5.5 Fail-safe Features * During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to the power dissipation, the chip temperature exceeds TLINoff, and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off, the VCC regulator works independently. * During a short-circuit from LIN to GND the IC can be switched into Sleep or Silent Mode. If the short-circuit disappears, the IC starts with a remote wake-up. * The reverse current is very low < 2A at the LIN pin during loss of VBatt. This is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. * During a short circuit at VCC, the output limits the output current to IVCC_lin. Due to undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into Fail-safe Mode. If the chip temperature exceeds the value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on again. Because of the Fail-safe Mode, the VCC voltage will switch on again even though EN is switched off from the microcontroller. The microcontroller can start with its normal operation. * EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected. * RXD pin is set floating if VBatt is disconnected. * TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected. * If TXD is short-circuited to GND, it is possible to switch to Sleep Mode via ENABLE after tdom > 20ms. * If the WD_OSC pin has a short-circuit to GND or the resistor is disconnected, the watchdog runs with an internal oscillator and guarantees a reset after the second NTRIG signal at the latest. 3.5.6 Voltage Regulator The voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the microcontroller. It is recommended to use an electrolythic capacitor with C > 1.8F and a ceramic capacitor with C = 100nF. The values of these capacitors can be varied by the customer, depending on the application. The main power dissipation of the IC is created from the VCC output current IVCC, which is needed for the application. In Figure 3-8 on page 16 the safe operating area of the Atmel(R) ATA6616/ATA6617 is shown.
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Figure 3-7.
VCC Voltage Regulator: Ramp-up and Undervoltage Detection
VS 12V
5.5V/3.8V
t
VCC 5V/3.3V Vthun
TVCC NRES 5V/3.3V
TReset
Tres_f
t
t
Figure 3-8.
Power Dissipation: Safe Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambient Temperatures Due to Rthja = 25K/W
60 Tamb = 105C Tamb = 125C
50
IVCC (mA)
40
30 20
10
0 3 5 7 9 11 13 15 17 19
VS (V)
For programming purposes of the microcontroller it is potentially necessary to supply the VCC output via an external power supply while the VS Pin of the system basis chip is disconnected. This behavior is no problem for the system basis chip.
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3.6 Watchdog
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window of Twd. The trigger signal must exceed a minimum time ttrigmin > 200ns. If a triggering signal is not received, a reset signal will be generated at output NRES. After a watchdog reset, the IC starts with the lead time. The timing basis of the watchdog is provided by the internal oscillator. Its time period, Tosc, is adjustable via the external resistor Rwd_osc (34k to 120k). During Silent or Sleep Mode the watchdog is switched off to reduce current consumption. The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES disappears. It is defined as lead time td. After wake up from Sleep or Silent Mode, the lead time td starts with the negative edge of the RXD output. 3.6.1 Typical Timing Sequence with RWD_OSC = 51k The trigger signal Twd is adjustable between 20ms and 64ms using the external resistor RWD_OSC. For example, with an external resistor of RWD_OSC = 51k 1%, the typical parameters of the watchdog are as follows: tosc = 0.405 x RWD_OSC - 0.0004 x (RWD_OSC)2 (RWD_OSC in k; tosc in s) tOSC = 19.6s due to 51k td = 7895 x 19.6s = 155ms t1 = 1053 x 19.6s = 20.6ms t2 = 1105 x 19.6s = 21.6ms tnres = constant = 4 ms After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES stays low for the time treset (typically 4ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. The lead time, t d , follows the reset and is td = 155ms. In this time, the first watchdog pulse from the microcontroller is required. If the trigger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a watchdog reset with tNRES = 4ms will reset the microcontroller after td = 155ms. The times t1 and t2 have a fixed relationship between each other. A triggering signal from the microcontroller is anticipated within the time frame of t2 = 21.6ms. To avoid false triggering from glitches, the trigger pulse must be longer than tTRIG,min > 200ns. This slope serves to restart the watchdog sequence. If the triggering signal fails in this open window t2, the NRES output will be drawn to ground. A triggering signal during the closed window t1 immediately switches NRES to low.
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Figure 3-9.
Timing Sequence with RWD_OSC = 51k
VCC
Undervoltage Reset NRES treset = 4ms
Watchdog Reset tnres = 4ms
td = 155ms t1 = 20.6ms twd t2 = 21ms
t1
t2
NTRIG
ttrig > 200ns
3.6.2
Worst Case Calculation with RWD_OSC = 51 k The internal oscillator has a tolerance of 20%. This means that t1 and t2 can vary by 20%. The worst case calculation for the watchdog period twd is calculated below. The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum t2. t1,min = 0.8 x t1 = 16.5ms, t1,max = 1.2 x t1 = 24.8ms t2,min = 0.8 x t2 = 17.3ms, t2,max = 1.2 x t2 = 26ms twdmax = t1min + t2min = 16.5ms + 17.3ms = 33.8ms twdmin = t1max = 24.8ms twd = 29.3ms 4.5ms (15%) A microcontroller with an oscillator tolerance of 15% is sufficient to correctly supply the trigger inputs.
Table 3-2.
RWD_OSC k 34 51 91 120
Typical Watchdog Timings
Oscillator Period tosc/s 13.3 19.61 33.54 42.84 Lead Time td/ms 105 154.8 264.80 338.22 Closed Window t1/ms 14.0 20.64 35.32 45.11 Open Window t2/ms 14.7 21.67 37.06 47.34 Trigger Period from Microcontroller twd/ms 19.9 29.32 50.14 64.05 Reset Time tnres/ms 4 4 4 4
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3.7 Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage VS Pulse time 500ms; Ta = 25C Output current IVCC 50mA Pulse time 2min; Ta = 25C Output current IVCC 50mA WAKE (with 33k serial resistor) KL_15 (with 50k/100nF) DC voltage Transient voltage due to ISO7637 (coupling 1nF) INH - DC voltage LIN - DC voltage Logic pins (RxD, TxD, EN, NRES, NTRIG, WD_OSC, MODE, TM) Output current NRES PVCC DC voltage VCC DC voltage ESD according to IBEE LIN EMC Test Spec. 1.0 following IEC 61000-4-2 - Pin VS, LIN to GND - Pin WAKE (33k serial resistor) to GND ESD HBM following STM5.1 with 1.5k 100pF - Pin VS, LIN, WAKE to GND Junction temperature Storage temperature Tj Ts INRES -0.3 -0.3 Symbol VS VS VS -1 -150 Min. -0.3 Typ. Max. +40 +40 27 Unit V V V
+40 +100
V V
-0.3 -27 -0.3
VS + 0.3 +40 +5.5 +2 +5.5 +6.5
V V V mA V V
6 5 8 -40 -55 +150 +150
KV KV KV C C
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9132D-AUTO-12/10
3.8
No. 1 1.1
Electrical Characteristics
Parameters VS Pin Nominal DC voltage range Sleep Mode VLIN > VS - 0.5V VS < 14V (Tj = 25C) Sleep Mode VLIN > VS - 0.5V VS < 14V (Tj = 125C) Bus recessive VS < 14V (Tj = 25C) Without load at VCC Bus recessive VS < 14V (Tj = 125C) Without load at VCC VS VS IVSsleep 5 27 V A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins
VS
3
10
14
A
A
1.2
Supply current in Sleep Mode
VS
IVSsleep
5
11
16
A
A
VS
IVSsi
47
57
67
A
A
1.3
Supply current in Silent Mode
VS
IVSsi
56
66
76
A
A
1.4
Bus recessive Supply current in Normal VS < 14V Mode Without load at VCC Bus dominant Supply current in Normal VS < 14V Mode VCC load current 50 mA Supply current in Fail-safe Mode VS undervoltage threshold VS undervoltage threshold hysteresis RXD Output Pin Low-level output sink current Normal Mode VLIN = 0V VRXD = 0.4V Bus recessive VS < 14V Without load at VCC
VS
IVSrec
0.3
0.8
mA
A
1.5
VS
IVSdom
50
53
mA
A
1.6
VS
IVSfail VSth VSth_hys
250
550
A
A
1.7 1.8 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.4
VS VS
4.0
4.5 0.2
5
V V
A A
RXD RXD RXD TXD TXD
IRXD VRXDL RRXD VTXDL VTXDH RTXD ITXD
1.3
2.5
8 0.4
mA V k V V k A
A A A A A A A
Low-level output voltage IRXD = 1mA Internal resistor to VCC TXD Input/Output Pin Low-level voltage input High-level voltage input Pull-up resistor High-level leakage current VTXD = 0V VTXD = VCC
3 -0.3 2 125 -3
5
7 +0.8 VCC + 0.3V
TXD TXD
250
400 +3
3.5
Fail-safe Mode Low-level output sink VLIN = VS current at local wake-up VWAKE = 0V request VTXD = 0.4V
TXD
ITXDwake
2
2.5
8
mA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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3.8
No. 4 4.1 4.2 4.3 4.4 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 7 7.1 7.2 7.3
Electrical Characteristics (Continued)
Parameters EN Input Pin Low-level voltage input High-level voltage input Pull-down resistor Low-level input current Low-level voltage input High-level voltage input Pull-up resistor High-level leakage current Mode Input Pin Low-level voltage input High-level voltage input Leakage current INH Output Pin High-level voltage Switch-on resistance between VS and INH Leakage current Sleep Mode VINH = 0V/27V, VS = 27V IINH = -15mA INIT INIT INIT VINHH RINH IINHL -3 VS - 0.75 30 VS 50 +3 V A A A A VMODE = VCC or VMODE = 0V MODE MODE MODE VMODEL VMODEH IMODE -0.3 2 -3 +0.8 VCC + 0.3V +3 V V A A A A VNTRIG = 0V VNTRIG = VCC VEN = VCC VEN = 0V EN EN EN EN NTRIG NTRIG NTRIG NTRIG VENL VENH REN IEN VNTRIGL VNTRIGH RNTRIG INTRIG -0.3 2 50 -3 -0.3 2 125 -3 250 125 +0.8 VCC + 0.3V 200 +3 +0.8 VCC + 0.3V 400 +3 V V k A V V k A A A A A A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins
NTRIG Watchdog Input Pin
8
LIN Bus Driver: Bus Load Conditions: Load 1 (Small): 1nF, 1k; Load 2 (Large): 10nF, 500; RRXD = 5k; CRXD = 20pF; Load 3 (Medium): 6.8 nF, 660 Characterized on Samples; 10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 Kbit/s, 10.8 and 10.9 at 10.4 Kbit/s. Driver recessive output voltage Driver dominant voltage Driver dominant voltage Driver dominant voltage Driver dominant voltage Pull-up resistor to VS Load1/Load2 VVS = 7V Rload = 500 VVS = 18V Rload = 500 VVS = 7.0V Rload = 1000 VVS = 18V Rload = 1000 The serial diode is mandatory LIN LIN LIN LIN LIN LIN LIN VBUSrec V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k RLIN VSerDiode 0.6 0.8 20 0.4 30 60 1.0 0.9 x VS VS 1.2 2 V V V V V k V A A A A A A D
8.1 8.2 8.3 8.4 8.5 8.6 8.7
Voltage drop at the serial In pull-up path with Rslave ISerDiode = 10mA diodes
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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3.8
No. 8.8
Electrical Characteristics (Continued)
Parameters LIN current limitation VBUS = VBatt_max Input leakage current at the receiver including pull-up resistor as specified Leakage current LIN recessive Input leakage current Driver off VBUS = 0V VBatt = 12V Driver off 8V < VBatt < 18V 8V < VBUS < 18V VBUS VBatt Test Conditions Pin LIN Symbol IBUS_LIM Min. 40 Typ. 120 Max. 200 Unit mA Type* A
5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins
8.9
LIN
IBUS_PAS_dom
-1
-0.35
mA
A
8.10
LIN
IBUS_PAS_rec
10
20
A
A
8.11
Leakage current when control unit disconnected from ground. GNDDevice = VS VBatt = 12V Loss of local ground 0V < VBUS < 18V must not affect communication in the residual network. Leakage current at a disconnected battery. Node has to sustain the VBatt disconnected current that can flow VSUP_Device = GND under this condition. Bus 0V < VBUS < 18V must remain operational under this condition. LIN Bus Receiver Center of receiver threshold VBUS_CNT = (Vth_dom + Vth_rec)/2
LIN
IBUS_NO_gnd
-10
+0.5
+10
A
A
8.12
LIN
IBUS_NO_bat
0.1
2
A
A
9 9.1 9.2 9.3 9.4 9.5 9.6 10 10.1
LIN LIN LIN LIN LIN LIN
VBUS_CNT VBUSdom VBUSrec VBUShys VLINH VLINL
0.475 x VS 0.6 x VS 0.028 x VS VS - 2V -27
0.5 x VS
0.525 x VS 0.4 x VS 0.175 x VS VS + 0.3V VS - 3.3V
V V V
A A A A A A
Receiver dominant state VEN = 5V Receiver recessive state VEN = 5V Receiver input hysteresis Pre_Wake detection LIN High-level input voltage Pre_Wake detection LIN Activates the LIN receiver Low-level input voltage Internal Timers Dominant time for wake-up via LIN bus Time delay for mode change from Fail-safe into Normal Mode via EN pin VLIN = 0V Vhys = Vth_rec - Vth_dom
0.1 x VS
V V V
LIN
tbus
30
90
150
s
A
10.2
VEN = 5V
EN
tnorm
5
15
20
s
A
10.3
Time delay for mode change from Normal V = 0V Mode to Sleep Mode via EN EN pin
EN
tsleep
2
7
12
s
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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3.8
No. 10.4
Electrical Characteristics (Continued)
Parameters TXD dominant time-out time Test Conditions VTXD = 0V Pin TXD Symbol tdom Min. 6 Typ. 13 Max. 20 Unit ms Type* A
5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins
10.5
Time delay for mode change from Silent V = 5V Mode into Normal Mode EN via EN THRec(max) = 0.744 x VS THDom(max) = 0.581 x VS VS = 7.0V to 18V tBit = 50s D1 = tbus_rec(min)/(2 x tBit) THRec(min) = 0.422 x VS THDom(min) = 0.284 x VS VS = 7.6V to 18V tBit = 50s D2 = tbus_rec(max)/(2 x tBit) THRec(max) = 0.778 x VS THDom(max) = 0.616 x VS VS = 7.0V to 18V tBit = 96s D3 = tbus_rec(min)/(2 x tBit) THRec(min) = 0.389 x VS THDom(min) = 0.251 x VS VS = 7.6V to 18V tBit = 96s D4 = tbus_rec(max)/(2 x tBit) VS = 7.0V to 18V
EN
ts_n
5
15
40
s
A
10.6
Duty cycle 1
LIN
D1
0.396
A
10.7
Duty cycle 2
LIN
D2
0.581
A
10.8
Duty cycle 3
LIN
D3
0.417
A
10.9
Duty cycle 4
LIN
D4
0.590
A
10.10 11
Slope time falling and rising edge at LIN
LIN
tSLOPE_fall tSLOPE_rise
3.5
22.5
s
A
Receiver Electrical AC Parameters of the LIN Physical Layer LIN Receiver, RXD Load Conditions CRXD = 20pF Propagation delay of V = 7.0V to 18V receiver (Figure 3-10 on S trx_pd = max(trx_pdr , trx_pdf) page 26) Symmetry of receiver VS = 7.0V to 18V propagation delay rising =t -t t edge minus falling edge rx_sym rx_pdr rx_pdf NRES Open Drain Output Pin VS 5.5V Low-level output voltage INRES = 1mA INRES = 250A Low-level output low Undervoltage reset time 10k to VCC VCC = 0V VS 5.5V CNRES = 20pF NRES VNRESL VNRESLL treset tres_f 2 1.5 4 0.2 0.14 0.2 6 10 V V V ms s A RXD trx_pd 6 s A
11.1
11.2 12 12.1
RXD
trx_sym
-2
+2
s
A
12.2 12.3 12.4
NRES NRES NRES
A A A
Reset debounce time for VS 5.5V falling edge CNRES = 20pF
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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3.8
No. 13 13.1 13.2 13.3 13.4 13.5 13.6 14 14.1 14.2 14.3 14.4 15 15.1 15.2 15.3 15.4 15.5 16 16.1 16.2 16.3 16.4 16.5
Electrical Characteristics (Continued)
Parameters Watchdog Oscillator Voltage at WD_OSC in Normal Mode Possible values of resistor Oscillator period Oscillator period Oscillator period Oscillator period Watchdog lead time after reset Watchdog closed window Watchdog open window Watchdog reset time NRES KL_15 Pin High-level input voltage RV = 47 k Low-level input voltage RV = 47 k KL_15 pull-down current Internal debounce time KL_15 wake-up time WAKE Pin High-level input voltage Low-level input voltage WAKE pull-up current High-level leakage current Time of low pulse for wake-up via WAKE pin Initializes a wake-up signal VS < 27V VWAKE = 0V VS = 27V VWAKE = 27V VWAKE = 0V WAKE WAKE WAKE WAKE WAKE VWAKEH VWAKEL IWAKE IWAKEL IWAKEL VS - 1V -1 -30 -5 30 70 -10 +5 150 VS + 0.3V VS - 3.3V V V A A s A A A A A VS < 27V VKL_15 = 27V Without external capacitor RV = 47k, C = 100nF Positive edge initializes a wake-up KL_15 KL_15 KL_15 KL_15 KL_15 VKL_15H VKL_15L IKL_15 TdbKL_15 TwKL_15 80 0.4 4 -1 50 160 2 VS + 0.3V +2 65 250 4.5 V V A s ms A A A A C NRES ROSC = 34k ROSC = 51k ROSC = 91k ROSC = 120k IWD_OSC = -200A VVS 4V WD_ OSC WD_ OSC VWD_OSC ROSC tOSC tOSC tOSC tOSC 1.13 34 10.65 15.68 26.83 34.2 13.3 19.6 33.5 42.8 1.23 1.33 120 15.97 23.52 40.24 51.4 V k s s s s A A A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins
Watchdog Timing Relative to tOSC td t1 t2 tnres 3.2 7895 1053 1105 4 4.8 cycles cycles cycles ms A A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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3.8
No. 18 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9
Electrical Characteristics (Continued)
Parameters Test Conditions 5.5V < VS < 18V (0mA to 50mA) 4V < VS < 5.5V VS > 4V IVCC = -20mA VS > 4V IVCC = -50mA VS > 3.3V IVCC = -15mA 5.5V < VS < 18V 5mA < IVCC < 50mA 10Hz to 100kHz CVCC = 10F VS = 14V, IVCC = -15mA 0.2 < ESR < 5 at 100kHz Referred to VCC VS > 5.5V Referred to VCC VS > 5.5V Pin Symbol Min. Typ. Max. Unit Type*
5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins VCC Voltage Regulator, PVCC = VCC Output voltage VCC Output voltage VCC at low VS Regulator drop voltage Regulator drop voltage Regulator drop voltage Line regulation Load regulation Power supply ripple rejection VCC VCC VS, VCC VS, VCC VS, VCC VCC VCC VCC VCC VCC VCC VCC VCC IVCClim VthunN VthunN Vhysthun tVCC VCCnor VCClow VD1 VD2 VD3 VCCline VCCload 50 -240 1.8 4.2 250 130 300 -130 10 4.8 0.5 400 4.9 VS - VD 5.1 5.1 250 600 200 1 2 V V mV mV mV % % dB mA F V mV s A A A A A A A A A D A A A
Output current limitation VS > 5.5V
18.10 Load capacity VCC undervoltage 18.11 threshold 18.12 18.13 Hysteresis of undervoltage threshold
Ramp-up time VS > 5.5V CVCC = 2.2F to VCC = 5V Iload = -5mA at VCC
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Figure 3-10. Definition of Bus Timing Characteristics
tBit TXD (Input to transmitting node) tBit tBit
tBus_dom(max)
tBus_rec(min)
THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal THRec(min) THDom(min)
Thresholds of receiving node1
Thresholds of receiving node2
tBus_dom(min)
tBus_rec(max)
RXD (Output of receiving node1) trx_pdf(1) trx_pdr(1)
RXD (Output of receiving node2) trx_pdr(2) trx_pdf(2)
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4. Atmel ATtiny87/ATtiny167 Microcontroller Block for Atmel ATA6616/ATA6617
4.1 Features
* High Performance, Low Power AVR 8-bit Microcontroller * Advanced RISC Architecture
- 123 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation * Non-volatile Program and Data Memories - 8 Kbytes/16 Kbytes of In-System Programmable (ISP) Program Memory Flash * Endurance: 10,000 Write/Erase Cycles - 512 Bytes In-System Programmable EEPROM * Endurance: 100,000 Write/Erase Cycles - 512 Bytes Internal SRAM - Programming Lock for Self-Programming Flash Program and EEPROM Data Security - Low Size LIN/UART Software In-System Programmable * Peripheral Features - LIN 2.1 and 1.3 Controller or 8-Bit UART - 8-bit Asynchronous Timer/Counter0: * 10-bit Clock Prescaler * 1 Output Compare or 8-bit PWM Channel - 16-bit Synchronous Timer/Counter1: * 10-bit Clock Prescaler * External Event Counter * 2 Output Compares Units or 16-bit PWM Channels each Driving up to 4 Ouput Pins - Master/Slave SPI Serial Interface, - Universal Serial Interface (USI) with Start Condition Detector (Master/Slave SPI, TWI, ...) - 10-bit ADC: * 11 Single Ended Channels * 8 Differential ADC Channel Pairs with Programmable Gain (8x or 20x) - On-chip Analog Comparator with Selectable Voltage Reference - 100A 10% Current Source (LIN Node Identification) - On-chip Temperature Sensor - Programmable Watchdog Timer with Separate On-chip Oscillator * Special Microcontroller Features - Dynamic Clock Switching (External/Internal RC/Watchdog Clock) for Power Control, EMC Reduction - DebugWIRE On-chip Debug (OCD) System - Hardware In-System Programmable (ISP) via SPI Port - External and Internal Interrupt Sources - Interrupt and Wake-up on Pin Change - Low Power Idle, ADC Noise Reduction, and Power-down Modes - Enhanced Power-on Reset Circuit - Programmable Brown-out Detection Circuit - Internal Calibrated RC Oscillator 8MHz - 4MHz to 16MHz and 32KHz Crystal/Ceramic Resonator Oscillators
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* * I/O and Packages
- 16 Programmable I/O Lines - 20-pin SOIC, 32-pad QFN and 20-pin TSSOP * * Operating Voltage: - 2.7V to 5.5V for Atmel ATtiny87/ATtiny167 * * Speed Grade: - 0MHz to 8MHz at 2.7V to 5.5V (Automotive Temperature Range: -40C to +125C) - 0MHz to 16MHz at 4.5V to 5.5V (Automotive Temperature Range: -40C to +125C)
4.2
4.2.1
Description
Comparison between Atmel ATtiny87 and Atmel ATtiny167 Atmel ATtiny87 and Atmel ATtiny167 are hardware and software compatible. They differ only in memory sizes as shown in Table 4-1. Table 4-1.
Device ATtiny167 ATtiny87
Memory Size Summary
Flash 16KBytes 8KBytes EEPROM 512Bytes 512Bytes SRAM 512Bytes 512Bytes Interrupt Vector size 2-instruction-words / vector 2-instruction-words / vector
4.2.2
Part Description The Atmel(R) ATtiny87/167 is a low-power CMOS 8-bit microcontroller based on the AVR(R) enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATtiny87/167 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Atmel ATtiny87/167 provides the following features: 8K/16K byte of In-System Programmable Flash, 512bytes EEPROM, 512bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, a LIN controller, Internal and External Interrupts, a 11-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The Boot program can use any interface to download the application program in the Flash memory.
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By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel(R) ATtiny87/167 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The Atmel ATtiny87/167 AVR(R) is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 4.2.3 Automotive Quality Grade The Atmel ATtiny87/167 have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (temperature and voltage). The quality and reliability of the Atmel(R) ATtiny87/167 have been verified during regular product qualification as per AEC-Q100 grade 1. As indicated in the ordering information paragraph, this document refers only to grade 1 products, for grade 0 products refer to appendix A.
Table 4-2.
Temperature Grade Identification for Automotive Products
Temperature Identifier Z D Comments Grade 1 Grade 0
Temperature -40C / +125C -40C / +150C
4.2.4
Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min. and Max values will be available after the device is characterized.
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9132D-AUTO-12/10
4.2.5
Block Diagram Figure 4-1. Block Diagram
GND VCC
Watchdog Timer Watchdog Oscillator
Power Supervision POR / BOD & RESET
debugWIRE
PROGRAM LOGIC
Oscillator Circuits / Clock Generation
Flash
SRAM
CPU EEPROM
AVCC AGND
Timer/Counter-1
DATABUS
Timer/Counter-0
A/D Conv.
SPI & USI
Analog Comp.
2
Internal Voltage References
11
PORT B (8)
PORT A (8)
LIN / UART
RESET XTAL[1;2] PB[0..7] PA[0..7]
4.2.6
Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
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4.2.7 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
4.3
4.3.1
AVR CPU Core
Overview This section discusses the AVR(R) core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 4-2. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash Program Memory
Program Counter
Status and Control Interrupt Unit 32 x 8 General Purpose Registrers Watchdog Timer
Instruction Register
Indirect Addressing
Instruction Decoder
A.D.C.
Direct Addressing
ALU
Control Lines
Analog Comparator
I/O Module1
Data SRAM
I/O Module 2
I/O Module n EEPROM
I/O Lines
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In order to maximize performance and parallelism, the AVR(R) uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.
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4.3.2 ALU - Arithmetic Logic Unit The high-performance AVR(R) ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "Instruction Set" section for a detailed description. Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 4.3.3.1 SREG - AVR Status Register The AVR Status Register - SREG - is defined as:
Bit Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG
4.3.3
* Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. * Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the "Instruction Set Description" for detailed information. * Bit 4 - S: Sign Bit, S = N
V
The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the "Instruction Set Description" for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetics. See the "Instruction Set Description" for detailed information.
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* Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. 4.3.4 General Purpose Register File The Register File is optimized for the AVR (R) Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * One 8-bit output operand and one 8-bit result input * Two 8-bit output operands and one 8-bit result input * Two 8-bit output operands and one 16-bit result input * One 16-bit output operand and one 16-bit result input Figure 4-3 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-3. AVR CPU General Purpose Working Registers
7 R0 R1 R2 ... R13 General Purpose Working Registers R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-3, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
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4.3.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-4 on page 35. Figure 4-4. The X-, Y-, and Z-registers
15 X-register 7 R27 (0x1B) 15 Y-register 7 R29 (0x1D) 15 Z-register 7 R31 (0x1F) ZH 0 7 R30 (0x1E) YH 0 7 R28 (0x1C) ZL 0 0 XH 0 7 R26 (0x1A) YL 0 0 XL 0 0
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.3.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR(R) Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present
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4.3.5.1
SPH and SPL - Stack Pointer Register
Bit 15 SP15 SP7 7 Read/Write R/W R/W Initial Value 14 SP14 SP6 6 R/W R/W 13 SP13 SP5 5 R/W R/W 12 SP12 SP4 4 R/W R/W 11 SP11 SP3 3 R/W R/W 10 SP10 SP2 2 R/W R/W 9 SP9 SP1 1 R/W R/W 8 SP8 SP0 0 R/W R/W SPH SPL
ISRAM end (See Table 4-3 on page 39)
4.3.6
Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR(R) CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 4-5. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-6. Single Cycle ALU Operation
T1 T2 T3 T4
clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back
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4.3.7 Reset and Interrupt Handling The AVR(R) provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in Section 4.8 "Interrupts" on page 82. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. 4.3.7.1 Interrupt behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
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Assembly Code Example
in cli sbi sbi out r16, SREG EECR, EEMPE EECR, EEPE SREG, r16 ; restore SREG value (I-bit) ; store SREG value ; start EEPROM write ; disable interrupts during timed sequence
C Code Example
char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example
sei sleep ; set Global Interrupt Enable ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending ; interrupt(s)
C Code Example
_SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */
4.3.7.2
Interrupt Response Time The interrupt execution response for all the enabled AVR(R) interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.
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4.4 AVR Memories
This section describes the different memories in the Atmel(R) ATtiny87/167. The AVR(R) architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the Atmel ATtiny87/167 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.
Table 4-3.
Memory Mapping.
Memory Size Start Address End Address Size Mnemonic Flash size Flash end ISRAM size ISRAM start ISRAM end E2 size E2 end 0x1FFF 0x0FFF(4.4.1) 0x0000 0x001F 64 bytes 0x0020 0x005F 160 bytes 0x0060 0x00FF 512 bytes 0x0100 0x02FF 512 bytes 0x0000 0x01FF
(1)
ATtiny87 8Kbytes 0x0000
ATtiny167 16Kbytes 0x3FFF(1) 0x1FFF(4.4.1)
Flash
32 bytes
32 Registers
Start Address End Address Size
I/O Registers
Start Address End Address Size
Ext I/O Registers
Start Address End Address Size
Internal SRAM
Start Address End Address Size
EEPROM
Start Address End Address
Notes:
1. Byte address.
4.4.1
Word (16-bit) address.In-System Re-programmable Flash Program Memory
The Atmel ATtiny87/167 contains On-chip In-System Reprogrammable Flash memory for program storage (see "Flash size" in Table 4-3 on page 39). Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16 bits wide. Atmel ATtiny87/167 does not have separate Boot Loader and Application Program sections, and the SPM instruction can be executed from the entire Flash. See SELFPRGEN description in Section 4.21.2.1 "Store Program Memory Control and Status Register - SPMCSR" on page 244 for more details. The Flash memory has an endurance of at least 10,000 write/erase cycles in automotive range. The Atmel ATtiny87/167 Program Counter (PC) address the program memory locations. Section 4.22 "Memory Programming" on page 250 contains a detailed description on Flash data serial downloading using the SPI pins. Constant tables can be allocated within the entire Program memory address space (see the LPM - Load Program memory instruction description). Timing diagrams for instruction fetch and execution are presented in Section 4.3.6 "Instruction Execution Timing" on page 36.
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Figure 4-7.
Program Memory Map
Program Memory 0x0000
Flash end
4.4.2
SRAM Data Memory Figure 4-8 shows how the Atmel(R) ATtiny87/167 SRAM Memory is organized. The Atmel ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next locations address the internal data SRAM (see "ISRAM size" in Table 4-3 on page 39). The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers and the internal data SRAM in the Atmel ATtiny87/167 are all accessible through all these addressing modes. The Register File is described in Section 4.3.4 "General Purpose Register File" on page 34.
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Figure 4-8. Data Memory Map
Data Memory
32 Registers 64 I/O Registers 160 Ext I/O Reg. 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00FF ISRAM start
Internal SRAM (ISRAM size) ISRAM end
4.4.2.1
Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 4-9. Figure 4-9. On-chip Data SRAM Access Cycles
T1 T2 T3
clkCPU Address Data WR Data RD
Compute Address Address valid
Memory Access Instruction
Next Instruction
4.4.3
EEPROM Data Memory The Atmel(R) ATtiny87/167 contains EEPROM memory (see "E2 size" in Table 4-3 on page 39). It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles in automotive range. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control Register. Section 4.22 "Memory Programming" on page 250 contains a detailed description on EEPROM programming in SPI or Parallel Programming mode.
Read
Write
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4.4.3.1
EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 4-4. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, Vcc is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See "Preventing EEPROM Corruption" on page 44 for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to "Atomic Byte Programming" on page 42 and "Split Byte Programming" on page 42 for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
4.4.3.2
Atomic Byte Programming Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEARL Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 1. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations. Split Byte Programming It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short access time for some limited period of time (typically if the power supply voltage falls). In order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. But since the erase and write operations are split, it is possible to do the erase operations when the system allows doing time-critical operations (typically after Power-up). Erase To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 1). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations.
4.4.3.3
4.4.3.4
4.4.3.5
Write To write a location, the user must write the address into EEAR and the data into EEDR. If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (programming time is given in Table 1). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations.
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The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in Section 4.5.5.1 "OSCCAL - Oscillator Calibration Register" on page 61. The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
Assembly Code Example
EEPROM_write: ; Wait for completion of previous write sbic rjmp ldi out out out out sbi sbi ret EECR,EEPE EEPROM_write r16, (0<; Set Programming mode
; Set up address (r18:r17) in address register
; Write data (r16) to data register ; Write logical one to EEMPE ; Start eeprom write by setting EEPE
C Code Example
void EEPROM_write(unsigned char ucAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<43
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
Assembly Code Example
EEPROM_read: ; Wait for completion of previous write sbic rjmp out out sbi in ret EECR,EEPE EEPROM_read EEARH, r18 EEARL, r17 EECR,EERE r16,EEDR
; Set up address (r18:r17) in address register
; Start eeprom read by writing EERE ; Read data from data register
C Code Example
unsigned char EEPROM_read(unsigned char ucAddress) { /* Wait for completion of previous write */ while(EECR & (1<4.4.3.6
Preventing EEPROM Corruption During periods of low Vcc, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR(R) RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low Vcc reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
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4.4.4 I/O Memory The I/O space definition of the Atmel(R) ATtiny87/167 is shown in Section 4.26 "Register Summary" on page 290. All Atmel ATtiny87/167 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and Peripherals Control Registers are explained in later sections. 4.4.4.1 General Purpose I/O Registers The Atmel(R) ATtiny87/167 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Status Flags. The General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 4.4.5 4.4.5.1 Register Description EEARH and EEARL - EEPROM Address Register
Bit 7 EEAR7 Bit Read/Write Read/Write Initial Value Initial Value 7 R R/W 0 X 6 EEAR6 6 R R/W 0 X 5 EEAR5 5 R R/W 0 X 4 EEAR4 4 R R/W 0 X 3 EEAR3 3 R R/W 0 X 2 EEAR2 2 R R/W 0 X 1 EEAR1 1 R R/W 0 X 0 EEAR8 EEAR0 0 R/W R/W X X EEARH EEARL
* Bit 7:1 - Reserved Bits These bits are reserved for future use and will always read as 0 in Atmel(R) ATtiny87/167.
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* Bits 8:0 - EEAR8:0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL - specifies the high EEPROM address in the EEPROM space (see "E2 size" in Table 4-3 on page 39). The EEPROM data bytes are addressed linearly between 0 and "E2 size". The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.
Note: For information only - ATtiny47: EEAR8 exists as register bit but it is not used for addressing.
4.4.5.2
EEDR - EEPROM Data Register
Bit Read/Write Initial Value 7 EEDR7 R/W 0 6 EEDR6 R/W 0 5 EEDR5 R/W 0 4 EEDR4 R/W 0 3 EEDR3 R/W 0 2 EEDR2 R/W 0 1 EEDR1 R/W 0 0 EEDR0 R/W 0 EEDR
* Bits 7:0 - EEDR7:0: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 4.4.5.3 EECR - EEPROM Control Register
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 EEPM1 R/W X 4 EEPM0 R/W X 3 EERIE R/W 0 2 EEMPE R/W 0 1 EEPE R/W X 0 EERE R/W 0 EECR
* Bit 7,6 - Res: Reserved Bits These bits are reserved for future use and will always read as 0 in Atmel ATtiny87/167. After reading, mask out these bits. For compatibility with future AVR(R) devices, always write these bits to zero. * Bits 5, 4 - EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 4-4. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
Table 4-4.
EEPROM Mode Bits
Typical Programming Time 3.4ms 1.8ms 1.8ms -
EEPM1 0 0 1 1
EEPM0 0 1 0 1
Operation Erase and Write in one operation (Atomic Operation) Erase Only Write Only Reserved for future use
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* Bit 3 - EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming. * Bit 2 - EEMPE: EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not. When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. * Bit 1 - EEPE: EEPROM Program Enable The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. * Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable Signal - EERE - is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. 4.4.5.4 General Purpose I/O Register 2 - GPIOR2
Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 GPIOR2 R/W 0 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20
4.4.5.5
General Purpose I/O Register 1 - GPIOR1
Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 GPIOR1 R/W 0 GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10
4.4.5.6
General Purpose I/O Register 0 - GPIOR0
Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 GPIOR0 R/W 0 GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00
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4.5
System Clock and Clock Options
The Atmel(R) ATtiny87/167 provides a large number of clock sources. They can be divided into two categories: internal and external. Some external clock sources can be shared with the asynchronous timer. After reset, the clock source is determined by the CKSEL Fuses. Once the device is running, software clock switching is possible to any other clock sources. Hardware controls are provided for clock switching management but some specific procedures must be observed. Clock switching should be performed with caution as some settings could result in the device having an incorrect configuration.
4.5.1
Clock Systems and their Distribution Figure 4-10 presents the principal clock systems in the AVR(R) and their distribution. All of the clocks may not need to be active at any given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes or by using features of the dynamic clock switch circuit (See Section 4.6 "Power Management and Sleep Modes" on page 65 and "Dynamic Clock Switch" on page 55). The clock systems are detailed below. Figure 4-10. Clock Distribution
Asynchronous Timer/Counter0 General I/O Modules ADC CPU Core RAM Flash and EEPROM
clkADC
clkI/O clkASY
AVR Clock Control Unit
clkCPU clkFLASH
Reset Logic Source Clock Prescaler
Watchdog Timer Watchdog Clock
Clock Switch
Multiplexer CKOUT Fuse Watchdog Oscillator Calibrated RC Oscillator
External Clock
Low-frequency Crystal Oscillator
Crystal Oscillator
PB4 / XTAL1 / CLKI
PB5 / XTAL2 / CLKO
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4.5.1.1 CPU Clock - clkCPU The CPU clock is routed to parts of the system concerned with the AVR(R) core operation. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. I/O Clock - clkI/O The I/O clock is used by the majority of the I/O modules, like synchronous Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Flash Clock - clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. Asynchronous Timer Clock - clkASY The asynchronous timer clock allows the asynchronous Timer/Counter to be clocked directly from an external clock or an external low frequency crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. ADC Clock - clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. Clock Sources The device has the following clock source options, selectable by Flash Fuse bits (default) or by the CLKSELR register (dynamic clock switch circuit) as shown below. The clock from the selected source is input to the AVR(R) clock generator, and routed to the appropriate modules. Device Clocking Options Select(1) versus PB4 and PB5 Functionality
CKSEL3..0(2) CSEL3..0(3) 0000 b 0010 b 0011 b 01xx b 100x b 101x b 110x b 111x b PB4 CLKI I/O I/O XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 PB5 CLKO - I/O CLKO - I/O CLKO - I/O XTAL2 XTAL2 XTAL2 XTAL2 XTAL2
4.5.1.2
4.5.1.3
4.5.1.4
4.5.1.5
4.5.2
Table 4-5.
Device Clocking Option External Clock Calibrated Internal RC Oscillator 8.0MHz Watchdog Oscillator 128kHz External Low-frequency Oscillator External Crystal/Ceramic Resonator (0.4 - 0.9MHz) External Crystal/Ceramic Resonator (0.9 - 3.0MHz) External Crystal/Ceramic Resonator (3.0 - 8.0MHz) External Crystal/Ceramic Resonator (8.0 - 16.0MHz) Notes: 2. Flash Fuse bits 3. CLKSELR register bits
1. For all fuses "1" means unprogrammed while "0" means programmed
The various choices for each clocking option are given in the following sections.
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When the CPU wakes up from Power-down or Power-save, or when a new clock source is enabled by the dynamic clock switch circuit, the selected clock source is used to time the start-up, ensuring stable oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up sequence. The number of WDT Oscillator cycles used for each time-out is shown in Table 4-6.
Table 4-6.
Number of Watchdog Oscillator Cycles
Typ. Time-out (Vcc = 5.0V) 4.3ms 69ms Number of Cycles 512 8K (8,192) 4.1ms 65ms
Typ. Time-out (Vcc = 5.0V)
4.5.2.1
Default Clock Source At reset, the CKSEL and SUT fuse settings are copied into the CLKSELR register. The device will then use the clock source and the start-up timings defined by the CLKSELR bits (CSEL3..0 and CSUT1:0). The device is shipped with CKSEL Fuses = 0010 b, SUT Fuses = 10 b, and CKDIV8 Fuse programmed. The default clock source setting is therefore the Internal RC Oscillator running at 8 MHz with the longest start-up time and an initial system clock divided by 8. This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer. This set-up must be taken into account when using ISP tools.
4.5.2.2
Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be accurately calibrated by the user. See Table 4-81 on page 269 and Section 4.25.7 "Internal Oscillator Speed" on page 288 for more details. If selected, it can operate without external components. At reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically configuring the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 4-81 on page 269. By adjusting the OSCCAL register in software, see Section 4.5.5.1 "OSCCAL - Oscillator Calibration Register" on page 61, it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in Table 4-81 on page 269. The Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out even when this Oscillator is used as the device clock. For more information on the pre-programmed calibration value, see the section Section 4.22.4 "Calibration Byte" on page 252.
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Table 4-7. Internal Calibrated RC Oscillator Operating Modes(1)
Frequency Range 7.6 - 8.4 Notes:
(2)
(MHz)
CKSEL3..0(3)(4) CSEL3..0(5) 0010
1. If 8MHz frequency exceeds the specification of the device (depends on Vcc), the CKDIV8 fuse can be programmed in order to divide the internal frequency by 8 2. The frequency ranges are guideline values 3. The device is shipped with this CKSEL = "0010" 4. Flash Fuse bits. 5. CLKSELR register bits
When this Oscillator is selected, start-up times are determined by the SUT Fuses or by CSUT field as shown in Table 4-8.
Table 4-8.
SUT1..0 CSUT1..0(2) 00(3) 01 10 Notes:
(4) (1)
Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
Start-up Time from Power-down/save 6 CK 6 CK 6 CK Additional Delay from Reset (Vcc = 5.0V) 14CK 14CK + 4.1ms 14CK + 65ms Reserved Recommended Usage BOD enabled Fast rising power Slowly rising power
11 1. Flash Fuse bits 2. CLKSELR register bits
3. This setting is only available if RSTDISBL fuse is not set 4. The device is shipped with this option selected
4.5.2.3
128 KHz Internal Oscillator The 128KHz internal Oscillator is a low power Oscillator providing a clock of 128KHz. The frequency is nominal at 5V and 25C. This clock may be selected as the system clock by programming CKSEL Fuses or CSEL field as shown in Table 4-5 on page 49. When this clock source is selected, start-up times are determined by the SUT Fuses or by CSUT field as shown in Table 4-9.
Table 4-9.
SUT1..0 CSUT1..0(2) 00
(3) (1)
Start-up Times for the 128kHz Internal Oscillator
Start-up Time from Power-down/save 6 CK 6 CK 6 CK Additional Delay from Reset (Vcc = 5.0V) 14CK 14CK + 4.1ms 14CK + 65ms Reserved Recommended Usage BOD enabled Fast rising power Slowly rising power
01 10 11 Notes:
1. Flash Fuse bits 2. CLKSELR register bits 3. This setting is only available if RSTDISBL fuse is not set
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4.5.2.4
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 4-11. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 4-10. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 4-11. Crystal Oscillator Connections
C2 C1 XTAL2 XTAL1 GND
The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by CKSEL3..1 fuses or by CSEL3..1 field as shown in Table 4-10.
Table 4-10.
CKSEL3..1 CSEL3..1(2) 100(3) 101 110 111 Notes:
Crystal Oscillator Operating Modes
(1)
Frequency Range (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 16.0
Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) - 12 - 22 12 - 22 12 - 22
1. Flash Fuse bits 2. CLKSELR register bits 3. This option should not be used with crystals, only with ceramic resonators
The CKSEL0 Fuse together with the SUT1..0 Fuses or CSEL0 together with CSUT1..0 field select the start-up times as shown in Table 4-11.
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Table 4-11.
CKSEL0(1) CSEL0(2) 0 0 0 0 1 1 1 1 Notes:
Start-up Times for the Crystal Oscillator Clock Selection
SUT1..0(1) CSUT1..0(2) 00 01 10(5) 11 00 01(5) 10 11 Start-up Time from Power-down/save 258 CK(3) 258 CK(3) 1K (1024) CK(4) 1K (1024)CK(4) 1K (1024)CK(4) 16K (16384) CK 16K (16384) CK 16K (16384) CK Additional Delay from Reset (Vcc = 5.0V) Recommended Usage 14CK + 4.1ms 14CK + 65ms 14CK 14CK + 4.1ms 14CK + 65 ms 14CK 14CK + 4.1ms 14CK + 65ms Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power
1. Flash Fuse bits. 2. CLKSELR register bits. 3. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 4. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. 5. This setting is only available if RSTDISBL fuse is not set.
4.5.2.5
Low-frequency Crystal Oscillator To use a 32.768kHz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting CKSEL fuses or CSEL field as shown in Table 4-5 on page 49. The crystal should be connected as shown in Figure 4-12. Refer to the 32.768kHz Crystal Oscillator Application Note for details on oscillator operation and how to choose appropriate values for C1 and C2. The 32.768kHz watch crystal oscillator can be used by the asynchronous timer if the (high-frequency) Crystal Oscillator is not running or if the External Clock is not enabled (See "Enable/Disable Clock Source" on page 57.). The asynchronous timer is then able to start itself this low-frequency crystal oscillator.
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Figure 4-12. Low-frequency Crystal Oscillator Connections
C1 = 12 - 22pF XTAL2 32.768KHz XTAL1 C2 = 12 - 22pF GND
12 - 22pF capacitors may be necessary if parasitic impedance (pads, wires & PCB) is very low.
When this oscillator is selected, start-up times are determined by the SUT fuses or by CSUT field as shown in Table 4-12.
Table 4-12.
SUT1..0 CSUT1..0(2) 00 01 10 11 Notes:
(1)
Start-up Times for the Low Frequency Crystal Oscillator Clock Selection
Start-up Time from Power-down/save 1K (1024) CK 1K (1024) CK
(3) (3)
Additional Delay from Reset (Vcc = 5.0V) 4.1ms 65ms 65ms Reserved
Recommended Usage Fast rising power or BOD enabled Slowly rising power Stable frequency at start-up
32K (32768) CK
1. Flash Fuse bits 2. CLKSELR register bits 3. These options should only be used if frequency stability at start-up is not important for the application
4.5.2.6
External Clock To drive the device from this external clock source, CLKI should be driven as shown in Figure 4-13. To run the device on an external clock, the CKSEL Fuses or CSEL field must be programmed as shown in Table 4-5 on page 49. Figure 4-13. External Clock Drive Configuration
External Clock Signal
~
(XTAL2) (CLKO)
CLKI
(XTAL1)
GND
When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT field as shown in Table 4-13 This external clock can be used by the asynchronous timer if the high or low frequency Crystal Oscillator is not running (See "Enable/Disable Clock Source" on page 57.). The asynchronous timer is then able to enable this input.
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Table 4-13.
SUT1..0(1) CSUT1..0(2) 00 01 10 11 Notes: 1. Flash Fuse bits 2. CLKSELR register bits 3. Additional delay (+ 4ms) available if RSTDISBL fuse is set
Start-up Times for the External Clock Selection
Start-up Time from Power-down/save 6CK 6CK 6CK Additional Delay from Reset (Vcc = 5.0V) 14CK (+ 4.1ms(3)) 14CK + 4.1ms 14CK + 65ms Reserved Recommended Usage BOD enabled Fast rising power Slowly rising power
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to "System Clock Prescaler" on page 61 for details. 4.5.2.7 Clock Output Buffer If not using a crystal oscillator, the device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse or COUT bit of CLKSELR register has to be programmed. This option is useful when the device clock is needed to drive other circuits on the system. Note that the clock will not be output during reset and the normal operation of I/O pin will be overridden when the fuses are programmed. If the System Clock Prescaler is used, it is the divided system clock that is output. Dynamic Clock Switch Features The Atmel(R) ATtiny87/167 provides a powerful dynamic clock switch circuit that allows users to turn on and off clocks of the device on the fly. The built-in de-glitching circuitry allows clocks to be enabled or disabled asynchronously. This enables efficient power management schemes to be implemented easily and quickly. In a safety application, the dynamic clock switch circuit allows continuous monitoring of the external clock permitting a fallback scheme in case of clock failure. The control of the dynamic clock switch circuit must be supervised by software. This operation is facilitated by the following features: * Safe commands, to avoid unintentional commands, a special write procedure must be followed to change the CLKCSR register bits (See "CLKPR - Clock Prescaler Register" on page 62.): * Exclusive action, the actions are controlled by a decoding table (commands) written to the CLKCSR register. This ensures that only one command operation can be launched at any time. The main actions of the decoding table are: - `Disable Clock Source', - `Enable Clock Source', - `Request Clock Availability', - `Clock Source Switching', - `Recover System Clock Source', - `Enable Watchdog in Automatic Reload Mode'.
4.5.3 4.5.3.1
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* Command status return. The `Request Clock Availability' command returns status via the CLKRDY bit in the CLKCSR register. The `Recover System Clock Source' command returns a code of the current clock source in the CLKSELR register. This information is used in the supervisory software routines as shown in Section 4.5.3.7 on page 57. 4.5.3.2 CLKSELR Register Fuses Substitution At reset, bits of the Low Fuse Byte are copied into the CLKSELR register. The content of this register can subsequently be user modified to overwrite the default values from the Low Fuse Byte. CKSEL3..0, SUT1..0 and CKOUT fuses correspond respectively to CSEL3..0, CSUT1:0 and ~(COUT) bits of the CLKSELR register as shown in Figure 4-14 on page 56. Source Selection The available codes of clock source are given in Table 4-5 on page 49. Figure 4-14. Fuses Substitution and Clock Source Selection
Fuse: Register:
Fuse Low Byte
Internal Data Bus
CLKSELR
R/W Reg.
SEL-0
SEL Decoder
SEL-1 SEL-2
CKSEL[3..0]
CLKSEL[3..0] SUT[1..0] CKOUT
CSEL[3..0] CSUT[1..0] COUT
SEL-n
Default
Reset
Selected Configuration
SCLKRq *
()
SUT[1..0]
CKOUT
EN-0
SEL Encoder
EN-1 EN-2
Clock Switch Current Configuration
SCLKRq * : Command of Clock Control & Status Register
()
EN-n
The CLKSELR register contains the CSEL, CSUT and COUT values which will be used by the `Enable/Disable Clock Source', `Request for Clock Availability' or `Clock Source Switching' commands. Source Recovering The `Recover System Clock Source' command updates the CKSEL field of CLKSELR register (See "System Clock Source Recovering" on page 57.).
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4.5.3.3 Enable/Disable Clock Source The `Enable Clock Source' command selects and enables a clock source configured by the settings in the CLKSELR register. CSEL3..0 will select the clock source and CSUT1:0 will select the start-up time (just as CKSEL and SUT fuse bits do). To be sure that a clock source is operating, the `Request for Clock Availability' command must be executed after the `Enable Clock Source' command. This will indicate via the CLKRDY bit in the CLKCSR register that a valid clock source is available and operational. The `Disable Clock Source' command disables the clock source indicated by the settings of CLKSELR register (only CSEL3..0). If the clock source indicated is currently the one that is used to drive the system clock, the command is not executed. Because the selected configuration is latched at clock source level, it is possible to enable many clock sources at a given time (ex: the internal RC oscillator for system clock + an oscillator with external crystal). The user (code) is responsible of this management. 4.5.3.4 COUT Command The `CKOUT' command allows to drive the CLKO pin. Refer to Section 4.5.2.7 "Clock Output Buffer" on page 55 for using. Clock Availability `Request for Clock Availability' command enables a hardware oscillation cycle counter driven by the selected source clock, CSEL3..0. The count limit value is determined by the settings of CSUT1..0. The clock is declared ready (CLKRDY = 1) when the count limit value is reached. The CLKRDY flag is reset when the count starts. Once set, this flag remains unchanged until a new count is commanded. To perform this checking, the CKSEL and CSUT fields should not be changed while the operation is running. Note that once the new clock source is selected (`Enable Clock Source' command), the count procedure is automatically started. The user (code) should wait for the setting of the CLKRDY flag in CLKSCR register before using a newly selected clock. At any time, the user (code) can ask for the availability of a clock source. The user (code) can request it by writing the `Request for Clock Availability' command in the CLKSCR register. A full polling of the status of clock sources can thus be done. 4.5.3.6 System Clock Source Recovering The `Recover System Clock Source' command returns the current clock source used to drive the system clock as per Table 4-5 on page 49. The CKSEL field of CLKSELR register is then updated with this returned value. There is no information on the SUT used or status on CKOUT. Clock Switching To drive the system clock, the user can switch from the current clock source to any other of the following ones (one of them being the current clock source): 1. Calibrated internal RC oscillator 8.0MHz, 2. Internal watchdog oscillator 128kHz, 3. External clock, 4. External low-frequency oscillator, 5. External Crystal/Ceramic Resonator.
4.5.3.5
4.5.3.7
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The clock switching is performed by a sequence of commands. First, the user (code) must make sure that the new clock source is operating. Then the `Clock Source Switching' command can be issued. Once this command has been successfully completed using the `Recover System Clock Source' command, the user (code) may stop the previous clock source. It is strongly recommended to run this sequence only once the interrupts have been disabled. The user (code) is responsible for the correct implementation of the clock switching sequence. Here is a "light" C-code that describes such a sequence of commands. C Code Example
void ClockSwiching (unsigned char clk_number, unsigned char sut) { #define #define #define #define CLOCK_RECOVER CLOCK_ENABLE CLOCK_SWITCH CLOCK_DISABLE 0x05 0x02 0x04 0x01
unsigned char previous_clk, temp; // Disable interrupts temp = SREG; asm ("cli"); // Save the current system clock source CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK_RECOVER; previous_clk = CLKSELR & 0x0F; // Enable the new clock source CLKSELR = ((sut << 4 ) & 0x30) | (clk_number & 0x0F); CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK_ENABLE; // Wait for clock validity while ((CLKCSR & (1 << CLKRDY)) == 0); // Switch clock source CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK_SWITCH; // Wait for effective switching while (1){ CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK_RECOVER; if ((CLKSELR & 0x0F) == (clk_number & 0x0F)) break; } // Shut down unneeded clock source if (previous_clk != (clk_number & 0x0F)) { CLKSELR = previous_clk; CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK_DISABLE; } // Re-enable interrupts SREG = temp; }
Warning: In the Atmel(R) ATtiny87/167, only one among the three external clock sources can be enabled at a given time. Moreover, the enables of the external clock and of the external low-frequency oscillator are shared with the asynchronous timer.
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4.5.3.8 Clock Monitoring A safe system needs to monitor its clock sources. Two domains need to be monitored: * Clock sources for peripherals, * Clocks sources for system clock generation. In the first domain, the user (code) can easily check the validity of the clock(s) (See "COUT Command" on page 57.). In the second domain, the lack of a clock results in the code not running. Thus, the presence of the system clock needs to be monitored by hardware. Using the on-chip watchdog allows this monitoring. Normally, the watchdog reloading is performed only if the code reaches some specific software labels, reaching these labels proves that the system clock is running. Otherwise the watchdog reset is enabled. This behavior can be considered as a clock monitoring. If the standard watchdog functionality is not desired, the Atmel(R) ATtiny87/167 watchdog permits the system clock to be monitored without having to resort to the complexity of a full software watchdog handler. The solution proposed in the Atmel ATtiny87/167 is to automate the watchdog reloading with only one command, at the beginning of the session. So, to monitor the system clock, the user will have two options: 1. Using the standard watchdog features (software reload), 2. Or using the automatic reloading (hardware reload). The two options are exclusive. Warning: These two options make sense ONLY if the clock source at RESET is an INTERNAL SOURCE. The fuse settings determine this operation. Figure 4-15. Watchdog Timer with Automatic Reloading
WD Interrupt WD Reset
WatchDog
Reload
WatchDog Clock
0 WDP[3..0]
1 Enable
Automatic Reloading Mode
Register:
WDIE
WDIF
WDE
WDTCSR
Checker
System CLK
Internal Bus
The `Enable Watchdog in Automatic Reload Mode' command has priority over the standard watchdog enabling. In this mode, only the reset function of the watchdog is enabled (no more watchdog interrupt). The WDP3..0 bits of the WDTCSR register always determine the watchdog timer prescaling. As the watchdog will not be active before executing the `Enable Watchdog in Automatic Reload Mode' command, it is recommended to activate this command before switching to an external clock source (See following notes).
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Notes:
1. ONLY the reset (watchdog reset included) disables this function. The Watchdog System Reset Flag (WDRF bit of MCUSR register) can be used to monitor the reset cause. 2. ONLY clock frequencies (4 * WatchDog Clock frequency) can be monitored.
Here is a "light" C-code of a clock switching function using automatic clock monitoring. C Code Example
void ClockSwiching (unsigned char clk_number, unsigned char sut) { #define #define #define #define #define CLOCK_RECOVER CLOCK_ENABLE CLOCK_SWITCH CLOCK_DISABLE WD_ARL_ENABLE 0x05 0x02 0x04 0x01 0x06 0x07
#define WD_2048CYCLES
unsigned char previous_clk, temp; // Disable interrupts temp = SREG; asm ("cli"); // Save the current system clock source CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK_RECOVER; previous_clk = CLKSELR & 0x0F; // Enable the new clock source CLKSELR = ((sut << 4 ) & 0x30) | (clk_number & 0x0F); CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK_ENABLE; // Wait for clock validity while ((CLKCSR & (1 << CLKRDY)) == 0); // Enable the watchdog in automatic reload mode WDTCSR = (1 << WDCE) | (1 << WDE); WDTCSR = (1 << WDE ) | WD_2048CYCLES; CLKCSR = 1 << CLKCCE; CLKCSR = WD_ARL_ENABLE; // Switch clock source CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK_SWITCH; // Wait for effective switching while (1){ CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK_RECOVER; if ((CLKSELR & 0x0F) == (clk_number & 0x0F)) break; } // Shut down unneeded clock source if (previous_clk != (clk_number & 0x0F)) { CLKSELR = previous_clk; CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK_DISABLE; } // Re-enable interrupts SREG = temp; }
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4.5.4 4.5.4.1 System Clock Prescaler Features The Atmel(R) ATtiny87/167 system clock can be divided by setting the Clock Prescaler Register - CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 4-14 on page 63. 4.5.4.2 Switching Time When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. 4.5.5 4.5.5.1 Register Description OSCCAL - Oscillator Calibration Register
Bit Read/Write Initial Value 7 CAL7 R/W 6 CAL6 R/W 5 CAL5 R/W 4 CAL4 R/W 3 CAL3 R/W 2 CAL2 R/W 1 CAL1 R/W 0 CAL0 R/W
OSCCAL
Device Specific Calibration Value
* Bits 7:0 - CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. The factory-calibrated value is automatically written to this register during chip reset, giving an oscillator frequency of 8.0 MHz at 25C. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to any frequency in the range 7.3 - 8.1MHz within 2% accuracy. Calibration outside that range is not guaranteed. Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM or Flash write may fail. The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.
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The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the frequency range 7.3 - 8.1MHz. 4.5.5.2 CLKPR - Clock Prescaler Register
Bit Read/Write Initial Value 7 CLKPCE R/W 0 6 - R 0 5 - R 0 4 - R 0 3 2 1 0 CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR R/W R/W R/W R/W See Bit Description
* Bit 7 - CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. * Bits 6:4 - Res: Reserved Bits These bits are reserved bits in the Atmel(R) ATtiny87/167 and will always read as zero. * Bits 3:0 - CLKPS3:0: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 4-14. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting in order not to disturb the procedure. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to "0000". If CKDIV8 is programmed, CLKPS bits are reset to "0011", giving a division factor of eight at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
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Table 4-14.
CLKPS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Clock Prescaler Select
CLKPS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CLKPS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CLKPS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock Division Factor 1 2 4 8 16 32 64 128 256 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
4.5.5.3
CLKCSR - Clock Control & Status Register
Bit Read/Write Initial Value 7 CLKCCE R/W 0 6 - R 0 5 - R 0 4 CLKRDY R 0 3 CLKC3 R/W 0 2 CLKC2 R/W 0 1 CLKC1 R/W 0 0 CLKC0 R/W 0
CLKCSR
* Bit 7 - CLKCCE: Clock Control Change Enable The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The CLKCCE bit is only updated when the other bits in CLKCSR are simultaneously written to zero. CLKCCE is cleared by hardware four cycles after it is written or when the CLKCSR bits are written. Rewriting the CLKCCE bit within this time-out period does neither extend the time-out period, nor clear the CLKCCE bit. * Bits 6:5 - Res: Reserved Bits These bits are reserved bits in the Atmel(R) ATtiny87/167 and will always read as zero. * Bits 4 - CLKRDY: Clock Ready Flag This flag is the output of the `Clock Availability' logic. This flag is cleared by the `Request for Clock Availability' command or `Enable Clock Source' command being entered. It is set when `Clock Availability' logic confirms that the (selected) clock is running and is stable. The delay from the request and the flag setting is not fixed, it depends on the clock start-up time, the clock frequency and, of course, if the clock is alive. The user's code has to differentiate between `no_clock_signal' and `clock_signal_not_yet_available' condition.
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* Bits 3:0 - CLKC3:0: Clock Control Bits 3 - 0 These bits define the command to provide to the `Clock Switch' module. The special write procedure must be followed to change the CLKC3..0 bits (See "Bit 7 - CLKCCE: Clock Control Change Enable" on page 63.). 1. Write the Clock Control Change Enable (CLKCCE) bit to one and all other bits in CLKCSR to zero. 2. Within 4 cycles, write the desired value to CLKCSR register while clearing CLKCCE bit. Interrupts should be disabled when setting CLKCSR register in order not to disturb the procedure.
Table 4-15.
No command
Clock Command List
CLKC3..0 0000 b 0001 b 0010 b 0011 b 0100 b 0101 b 0110 b 0111 b 1xxx b
Clock Command Disable clock source Enable clock source Request for clock availability Clock source switch Recover system clock source code Enable watchdog in automatic reload mode CKOUT command No command
4.5.5.4
CLKSELR - Clock Selection Register
Bit Read/Write Initial Value 7 R 0 6 COUT R/W ~ (CKOUT) fuse 5 4 CSUT1 CSUT0 R/W R/W SUT1..0 fuses 3 CSEL3 R/W 2 1 CSEL2 CSEL1 R/W R/W CKSEL3..0 fuses 0 CSEL0 R/W
CLKSELR
* Bit 7- Res: Reserved Bit This bit is reserved bit in the Atmel(R) ATtiny87/167 and will always read as zero. * Bit 6 - COUT: Clock Out The COUT bit is initialized with ~(CKOUT) Fuse bit. The COUT bit is only used in case of `CKOUT' command. Refer to Section 4.5.2.7 "Clock Output Buffer" on page 55 for using. In case of `Recover System Clock Source' command, COUT it is not affected (no recovering of this setting). * Bits 5:4 - CSUT1:0: Clock Start-up Time CSUT bits are initialized with the values of SUT Fuse bits. In case of `Enable/Disable Clock Source' command, CSUT field provides the code of the clock start-up time. Refer to subdivisions of Section 4.5.2 "Clock Sources" on page 49 for code of clock start-up times. In case of `Recover System Clock Source' command, CSUT field is not affected (no recovering of SUT code).
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* Bits 3:0 - CSEL3:0: Clock Source Select CSEL bits are initialized with the values of CKSEL Fuse bits. In case of `Enable/Disable Clock Source', `Request for Clock Availability' or `Clock Source Switch' command, CSEL field provides the code of the clock source. Refer to Table 4-5 on page 49 and subdivisions of Section 4.5.2 "Clock Sources" on page 49 for clock source codes. In case of `Recover System Clock Source' command, CSEL field contains the code of the clock source used to drive the Clock Control Unit as described in Figure 4-10 on page 48.
4.6
Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR(R) provides various sleep modes allowing the user to tailor the power consumption to the application's requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes. See "BOD Disable" on page 66 for more details.
4.6.1
Sleep Modes Figure 4-10 on page 48 presents the different clock systems in the Atmel(R) ATtiny87/167, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 4-16 shows the different sleep modes, their wake up sources and BOD disable ability.
Table 4-16.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains Oscillators Main Clock Source Enabled INT1, INT0 and Pin Change Wake-up Sources USI Start Condition SPM/EEPROM Ready
Sleep Mode Idle ADC Noise Reduction Power-down Power-Save Notes:
X
X X
X X
X X
X X
X X(1) X(1)
X X
X X
X X X X
X X X X
X X
X
X
X
X
(1)
X
1. For INT1 and INT0, only level interrupt
To enter any of the four sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, or Power-save) will be activated by the SLEEP instruction. See Table 4-17 on page 70 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
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Software BOD Disable X X
Timer0 Osc. Enable
Other I/O
clkFLASH
Timer0
clkCPU
clkADC
clkASY
WDT
ADC
clkIO
65
4.6.2
BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 4-69 on page 251, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 4-16. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe operation in case the Vcc level has dropped during the sleep period. When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60 s to ensure that the BOD is working correctly before the MCU continues executing code. BOD disable is controlled by BODS bit (BOD Sleep) in the control register MCUCR, see "MCUCR - MCU Control Register" on page 70. Setting it to one turns off the BOD in relevant sleep modes, while a zero in this bit keeps BOD active. Default setting keeps BOD active, i.e. BODS is cleared to zero. Writing to the BODS bit is controlled by a timed sequence and an enable bit, see "MCUCR - MCU Control Register" on page 70.
4.6.3
Idle Mode When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, Analog Comparator, ADC, USI start condition, Asynchronous Timer/Counter, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the SPI interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register - ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
4.6.4
ADC Noise Reduction Mode When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the USI start condition, the asynchronous Timer/Counter and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, a USI start condition interrupt, an asynchronous Timer/Counter interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.
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4.6.5 Power-down Mode When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the USI start condition, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, the USI start condition interrupt, an external level interrupt on INT0 or INT1, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to Section 4.9 "External Interrupts" on page 85 for details. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in Section 4.5.2 "Clock Sources" on page 49. 4.6.6 Power-save Mode When the SM1..0 bits are written to 11, the SLEEP instruction makes the MCU enter Power-save mode. This mode is identical to Power-down, with one exception: If Timer/Counter0 is clocked asynchronously, i.e., the AS0 bit in ASSR is set, Timer/Counter0 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in TIMSK0, and the global interrupt enable bit in SREG is set. If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in Power-save mode if AS0 is 0. This sleep mode basically halts all clocks except clkASY, allowing operation only of asynchronous modules, including Timer/Counter0 if clocked asynchronously. 4.6.7 Power Reduction Register The Power Reduction Register (PRR), see "PRR - Power Reduction Register" on page 70, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped.
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4.6.8
Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR(R) controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device's functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to Section 4.18 "ADC - Analog to Digital Converter" on page 214 for details on ADC operation. Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to Section 4.19 "AnaComp - Analog Comparator" on page 236 for details on how to configure the Analog Comparator. Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Section 4.7.1.5 "Brown-out Detection" on page 74 for details on how to configure the Brown-out Detector. Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to Section 4.7.2 "Internal Voltage Reference" on page 76 for details on the start-up time. Output the internal voltage reference is not needed in the deeper sleep modes. This module should be turned off to reduce significantly to the total current consumption. Refer to Section 4.17.3.1 "AMISCR - Analog Miscellaneous Control Register" on page 213 for details on how to disable the internal voltage reference output.
4.6.8.1
4.6.8.2
4.6.8.3
4.6.8.4
4.6.8.5
Internal Current Source The Internal Current Source is not needed in the deeper sleep modes. This module should be turned off to reduce significantly to the total current consumption. Refer to Section 4.17.3.1 "AMISCR - Analog Miscellaneous Control Register" on page 213 for details on how to disable the Internal Current Source.
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4.6.8.6 Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Section 4.7.3 "Watchdog Timer" on page 76 for details on how to configure the Watchdog Timer. Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section Section 4.10.2.6 "Digital Input Enable and Sleep Modes" on page 96 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to Vcc/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to Vcc/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to Section 4.18.12.6 "DIDR1 - Digital Input Disable Register 1" on page 234 and Section 4.18.12.5 "DIDR0 - Digital Input Disable Register 0" on page 234 for details. 4.6.8.8 On-chip Debug System If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the main clock source is enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Register Description SMCR - Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management.
4.6.8.7
4.6.9 4.6.9.1
Bit Read/Write Initial Value
7 - R 0
6 - R 0
5 - R 0
4 - R 0
3 - R 0
2 SM1 R/W 0
1 SM0 R/W 0
0 SE R/W 0 SMCR
* Bits 7..3 Res: Reserved Bits These bits are unused bits in the Atmel(R) ATtiny87/167, and will always read as zero. * Bits 2..1 - SM1..0: Sleep Mode Select Bits 1, and 0 These bits select between the four available sleep modes as shown in Table 4-17.
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Table 4-17.
SM1 0 0 1 1
Sleep Mode Select
SM0 0 1 0 1 Sleep Mode Idle ADC Noise Reduction Power-down Power-save
* Bit 0 - SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer's purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 4.6.9.2 MCUCR - MCU Control Register
Bit Read/Write Initial Value 7 - R 0 6 BODS R/W 0 5 BODSE R/W 0 4 PUD R/W 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0
MCUCR
* Bit 6 - BODS: BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 4-16 on page 65. Writing to the BODS bit is controlled by a timed sequence and an enable bit, BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to zero within four clock cycles. The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. * Bit 5 - BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence. 4.6.9.3 PRR - Power Reduction Register
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 PRLIN R/W 0 4 PRSPI R/W 0 3 PRTIM1 R/W 0 2 PRTIM0 R/W 0 1 PRUSI R/W 0 0 PRADC R/W 0 PRR
* Bit 7 - Res: Reserved bit This bit is reserved in Atmel(R) ATtiny87/167 and will always read as zero. * Bit 6 - Res: Reserved bit This bit is reserved in Atmel ATtiny87/167 and will always read as zero.
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* Bit5 - PRLIN: Power Reduction LIN / UART controller Writing a logic one to this bit shuts down the LIN by stopping the clock to the module. When waking up the LIN again, the LIN should be re initialized to ensure proper operation. * Bit 4 - PRSPI: Power Reduction Serial Peripheral Interface If using debugWIRE On-chip Debug System, this bit should not be written to one. Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation. * Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. * Bit 2 - PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module in synchronous mode (AS0 is 0). When the Timer/Counter0 is enabled, operation will continue like before the shutdown. * Bit 1 - PRUSI: Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re-initialized to ensure proper operation. * Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.
4.7
4.7.1 4.7.1.1
System Control and Reset
Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be an RJMP - Relative Jump - instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 4-16 shows the reset circuit. Tables in Section 4.23.5 "RESET Characteristics" on page 270 defines the electrical parameters of the reset circuitry. The I/O ports of the AVR(R) are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in Section 4.5.2 "Clock Sources" on page 49.
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4.7.1.2
Reset Sources The Atmel(R) ATtiny87/167 has four sources of reset: * Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). * External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. * Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog System Reset mode is enabled. * Brown-out Reset. The MCU is reset when the supply voltage Vcc is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.
Figure 4-16. Reset Circuit
DATA BUS
MCU Status Register (MCUSR)
PORF BORF EXTRF WDRF
Power-on Reset Circuit
BODLEVEL [2..0] Pull-up Resistor RSTDISBL
Brown-out Reset Circuit
Spike Filter
Watchdog Oscillator
Clock Generator
CK
Delay Counters
TIMEOUT
CKSEL[3:0] SUT[1:0]
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4.7.1.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 4-84 on page 270. The POR is activated whenever Vcc is below the detection level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after Vcc rise. The RESET signal is activated again, without any delay, when Vcc decreases below the detection level. Figure 4-17. MCU Start-up, RESET Tied to Vcc
VCCRR VCC VPORMAX VPOT VPORMIN TIME-OUT INTERNAL RESET tTOUT
Figure 4-18. MCU Start-up, RESET Extended Externally
VCCRR VCC VPOR
RESET
VRST
TIME-OUT INTERNAL RESET
tTOUT
4.7.1.4
External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 4-83 on page 270) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage - VRST - on its positive edge, the delay counter starts the MCU after the Time-out period - tTOUT - has expired. The External Reset can be disabled by the RSTDISBL fuse, see Table 4-70 on page 251.
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Figure 4-19. External Reset During Operation
CC
4.7.1.5
Brown-out Detection Atmel(R) ATtiny87/167 has an On-chip Brown-out Detection (BOD) circuit for monitoring the Vcc level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses (Table 4-85 on page 271). The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST / 2 and VBOT- = VBOT - VHYST / 2. When the BOD is enabled, and Vcc decreases to a value below the trigger level (VBOT- in Figure 4-20), the Brown-out Reset is immediately activated. When Vcc increases above the trigger level (VBOT+ in Figure 4-20), the delay counter starts the MCU after the Time-out period tTOUT has expired. The BOD circuit will only detect a drop in Vcc if the voltage stays below the trigger level for longer than tBOD given in Table 4-86 on page 271. Figure 4-20. Brown-out Reset During Operation
VCC VBOTVBOT+
RESET
TIME-OUT
tTOUT
INTERNAL RESET
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4.7.1.6 Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 76 for details on operation of the Watchdog Timer. Figure 4-21. Watchdog System Reset During Operation
CC
CK
4.7.1.7
MCU Status Register - MCUSR The MCU Status Register provides information on which reset source caused an MCU reset.
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 WDRF R/W 2 1 BORF EXTRF R/W R/W See Bit Description 0 PORF R/W MCUSR
* Bit 7..4 - Res: Reserved Bits These bits are unused bits in the Atmel(R) ATtiny87/167, and will always read as zero. * Bit 3 - WDRF: Watchdog System Reset Flag This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 2 - BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 1 - EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 0 - PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.
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4.7.2
Internal Voltage Reference Atmel(R) ATtiny87/167 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 4-87 on page 271. To save power, the reference is not always turned on. The reference is on during the following situations: 1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses). 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACIRS bit in ACSR). 3. When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACIRS bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode or in Power-save, the user can avoid the three conditions above to ensure that the reference is turned off before entering in these power reduction modes.
4.7.2.1
4.7.3
Watchdog Timer Atmel(R) ATtiny87/167 has an Enhanced Watchdog Timer (WDT). The main features are: * Clocked from separate On-chip Oscillator * 4 Operating modes
- Interrupt - System Reset - Interrupt and System Reset - Clock Monitoring * Selectable Time-out period from 16ms to 8s * Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
4.7.3.1
Watchdog Timer Behavior The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 KHz oscillator.
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Figure 4-22. Watchdog Timer
~128 KHz OSCILLATOR WATCHDOG PRESCALER
OSC / 2K OSC / 4K OSC / 8K OSC / 16K OSC / 32K OSC / 64K OSC / 128K OSC / 256K OSC / 512K OSC / 1024K
WATCHDOG RESET WDP0 WDP1 WDP2 WDP3 CLOCK MONITORING WDE WDIF
MCU RESET
INTERRUPT WDIE
The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued. In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset. The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows: 1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation.
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The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. Assembly Code Example(1)
WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in andi out r16, MCUSR r16, (0xff & (0<; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional time-out lds r16, WDTCR ori r16, (1<C Code Example(1)
void WDT_off(void) { __disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<78
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The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example(1)
WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCR ori r16, (1<C Code Example(1)
void WDT_Prescaler_Change(void) { __disable_interrupt(); __watchdog_reset(); /* Start timed sequence */ WDTCR |= (1<4.7.3.2
Clock monitoring The Watchdog Timer can be used to detect a loss of system clock. This configuration is driven by the dynamic clock switch circuit. Please refer to Section 4.5.3.8 "Clock Monitoring" on page 59 for more information.
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4.7.3.3
Watchdog Timer Control Register - WDTCR
Bit Read/Write Initial Value 7 WDIF R/W 0 6 WDIE R/W 0 5 WDP3 R/W 0 4 WDCE R/W 0 3 WDE R/W X 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCR
* Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. * Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied. If the Watchdog Timer is used as clock monitor (c.f. Section * "Bits 3:0 - CLKC3:0: Clock Control Bits 3 - 0" on page 64), the System Reset Mode is enabled and the Interrupt Mode is automatically disabled.
Table 4-18.
Clock Monitor x On
Watchdog Timer Configuration
WDTON 0 y
(1)
WDE 0 y
(1)
WDIE Mode 0 y
(1)
Action on Time-out None Reset Interrupt Reset Interrupt, then go to System Reset Mode Reset
Stopped System Reset Mode Interrupt Mode System Reset Mode Interrupt and System Reset Mode System Reset Mode
0 0 Off 0 1 Note:
0 1 1 x
1 0 1 x
1. At least one of these three enables (WDTON, WDE & WDIE) equal to 1
* Bit 4 - WDCE: Watchdog Change Enable This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to one, hardware will clear WDCE after four clock cycles.
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* Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. * Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 4-19 on page 81.
Table 4-19.
WDP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Watchdog Timer Prescale Select
WDP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reserved Number of WDT Oscillator Cycles 2K (2048) cycles 4K (4096) cycles 8K (8192) cycles 16K (16384) cycles 32K (32768) cycles 64K (65536) cycles 128K (131072) cycles 256K (262144) cycles 512K (524288) cycles 1024K (1048576) cycles Typical Time-out at Vcc = 5.0V 16ms 32ms 64ms 0.125s 0.25s 0.5s 1.0s 2.0s 4.0s 8.0s
WDP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
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4.8
Interrupts
This section describes the specifics of the interrupt handling as performed in Atmel (R) ATtiny87/167. For a general explanation of the AVR(R) interrupt handling, refer to Section 4.3.7 "Reset and Interrupt Handling" on page 37.
4.8.1
Innterrupt Vectors in Atmel ATtiny87/167
Table 4-20.
Vector Nb. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Reset and Interrupt Vectors in Atmel(R) ATtiny87/167
Program Address ATtiny87 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 ATtiny167 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 Source RESET INT0 INT1 PCINT0 PCINT1 WDT TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 COMPA TIMER0 OVF LIN TC LIN ERR SPI, STC ADC EE READY ANALOG COMP USI START USI OVF Interrupt Definition External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset External Interrupt Request 0 External Interrupt Request 1 Pin Change Interrupt Request 0 Pin Change Interrupt Request 1 Watchdog Time-out Interrupt Timer/Counter1 Capture Event Timer/Counter1 Compare Match A Timer/Coutner1 Compare Match B Timer/Counter1 Overflow Timer/Counter0 Compare Match A Timer/Counter0 Overflow LIN/UART Transfer Complete LIN/UART Error SPI Serial Transfer Complete ADC Conversion Complete EEPROM Ready Analog Comparator USI Start Condition Detection USI Counter Overflow
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4.8.2 Program Setup in ATtiny87 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny87 is (2-byte step - using "rjmp" instruction):
Address(1) Label Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 RESET: 0x0015 0x0016 0x0017 0x0018 0x0019 ... Note: ... 16-bit address rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp ldi out ldi out sei ... xxx ... RESET INT0addr INT1addr PCINT0addr PCINT1addr WDTaddr ICP1addr OC1Aaddr OC1Baddr OVF1addr OC0Aaddr OVF0addr LINTCaddr LINERRaddr SPIaddr ADCCaddr ERDYaddr ACIaddr USISTARTaddr USIOVFaddr Comments ; Reset Handler ; IRQ0 Handler ; IRQ1 Handler ; PCINT0 Handler ; PCINT1 Handler ; Watchdog Timer Handler ; Timer1 Capture Handler ; Timer1 Compare A Handler ; Timer1 Compare B Handler ; Timer1 Overflow Handler ; Timer0 Compare A Handler ; Timer0 Overflow Handler ; LIN Transfer Complete Handler ; LIN Error Handler ; SPI Transfer Complete Handler ; ADC Conversion Complete Handler ; EEPROM Ready Handler ; Analog Comparator Handler ; USI Start Condition Handler ; USI Overflow Handler
r16, high(RAMEND); Main program start SPH,r16 r16, low(RAMEND) SPL,r16 ; Enable interrupts ; Set Stack Pointer to top of RAM
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4.8.3
Program Setup in ATtiny167 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny167 is (4-byte step - using "jmp" instruction):
Address(1) Label Code 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 RESET: 0x0029 0x002A 0x002B 0x002C 0x002D ... Note: ... 1. 16-bit address jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp ldi out ldi out sei ... xxx ... RESET INT0addr INT1addr PCINT0addr PCINT1addr WDTaddr ICP1addr OC1Aaddr OC1Baddr OVF1addr OC0Aaddr OVF0addr LINTCaddr LINERRaddr SPIaddr ADCCaddr ERDYaddr ACIaddr USISTARTaddr USIOVFaddr Comments ; Reset Handler ; IRQ0 Handler ; IRQ1 Handler ; PCINT0 Handler ; PCINT1 Handler ; Watchdog Timer Handler ; Timer1 Capture Handler ; Timer1 Compare A Handler ; Timer1 Compare B Handler ; Timer1 Overflow Handler ; Timer0 Compare A Handler ; Timer0 Overflow Handler ; LIN Transfer Complete Handler ; LIN Error Handler ; SPI Transfer Complete Handler ; ADC Conversion Complete Handler ; EEPROM Ready Handler ; Analog Comparator Handler ; USI Start Condition Handler ; USI Overflow Handler
r16, high(RAMEND); Main program start SPH,r16 r16, low(RAMEND) SPL,r16 ; Enable interrupts ; Set Stack Pointer to top of RAM
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4.9
4.9.1
External Interrupts
Overview The External Interrupts are triggered by the INT1..0 pins or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT1..0 or PCINT15..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCINT1 will trigger if any enabled PCINT15..8 pin toggles. The pin change interrupt PCINT0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT15..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The INT1..0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Register A - EICRA. When the INT1..0 interrupts are enabled and are configured as level triggered, the interrupts will trigger as long as the pin is held low. The recognition of falling or rising edge interrupts on INT1..0 requires the presence of an I/O clock, described in Section 4.5.1 "Clock Systems and their Distribution" on page 48. Low level interrupts and the edge interrupt on INT1..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down or Power-save, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in Section 4.5.1 "Clock Systems and their Distribution" on page 48.
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4.9.2
Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 4-23.
Figure 4-23. Timing of Pin Change Interrupts
0 PCINT[i] pin
pin_lat pin_sync pcint_in[i] pcint_sync pcint_set/flag
D LE
Q
D
Q PCINT[i] bit (of PCMSKn) 7 clk
D
Q
D
Q
D
Q
PCIFn (interrupt flag)
clk
clk PCINT[i] pin pin_lat pin_sync pcint_in[i] pcint_syn pcint_set/flag PCIFn
4.9.3 4.9.3.1
External Interrupts Register Description External Interrupt Control Register A - EICRA The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 EICRA
* Bit 7..4 - Res: Reserved Bits These bits are unused bits in the Atmel(R) ATtiny87/167, and will always read as zero. * Bit 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 4-21. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
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* Bit 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 4-21. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
Table 4-21.
ISCn1 0 0 1 1
Interrupt Sense Control
ISCn0 0 1 0 1 Description The low level of INTn generates an interrupt request. Any logical change on INTn generates an interrupt request. The falling edge of INTn generates an interrupt request. The rising edge of INTn generates an interrupt request.
4.9.3.2
External Interrupt Mask Register - EIMSK
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 INT1 R/W 0 0 INT0 R/W 0 EIMSK
* Bit 7, 2 - Res: Reserved Bits These bits are unused bits in the Atmel(R) ATtiny87/167, and will always read as zero. * Bit 1 - INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector. * Bit 0 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
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4.9.3.3
External Interrupt Flag Register - EIFR
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 INTF1 R/W 0 0 INTF0 R/W 0 EIFR
* Bit 7, 2 - Res: Reserved Bits These bits are unused bits in the Atmel(R) ATtiny87/167, and will always read as zero. * Bit 1 - INTF1: External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt. * Bit 0 - INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. 4.9.3.4 Pin Change Interrupt Control Register - PCICR
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 PCIE1 R/W 0 0 PCIE0 R/W 0 PCICR
* Bit 7, 2 - Res: Reserved Bits These bits are unused bits in the Atmel ATtiny87/167, and will always read as zero. * Bit 1 - PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register. * Bit 0 - PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
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4.9.3.5 Pin Change Interrupt Flag Register - PCIFR
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 PCIF1 R/W 0 0 PCIF0 R/W 0 PCIFR
* Bit 7, 2 - Res: Reserved Bits These bits are unused bits in the Atmel(R) ATtiny87/167, and will always read as zero. * Bit 1 - PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. * Bit 0 - PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 4.9.3.6 Pin Change Mask Register 1 - PCMSK1
Bit Read/Write Initial Value 7 6 5 4 3 2 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 PCINT9 R/W 0 0 PCINT8 R/W 0 PCMSK1
* Bit 7..0 - PCINT15..8: Pin Change Enable Mask 15..8 Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 4.9.3.7 Pin Change Mask Register 0 - PCMSK0
Bit Read/Write Initial Value 7 PCINT7 R/W 0 6 PCINT6 R/W 0 5 PCINT5 R/W 0 4 PCINT4 R/W 0 3 PCINT3 R/W 0 2 PCINT2 R/W 0 1 PCINT1 R/W 0 0 PCINT0 R/W 0 PCMSK0
* Bit 7..0 - PCINT7..0: Pin Change Enable Mask 7..0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.
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4.10
4.10.1
I/O-Ports
Introduction All AVR(R) ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both Vcc and Ground as indicated in Figure 4-24. Refer to Section 4.23 "Electrical Characteristics" on page 267 for a complete list of parameters. Figure 4-24. I/O Pin Equivalent Schematic
Rpu
Pxn
Logic Cpin
See Figure "General Digital I/O" for Details
All registers and bit references in this section are written in general form. A lower case "x" represents the numbering letter for the port, and a lower case "n" represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in "Register Description for I/O Ports" on page 109. Three I/O memory address locations are allocated for each port, one each for the Data Register - PORTx, Data Direction Register - DDRx, and the Port Input Pins - PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable - PUD bit in MCUCR or PUDx in PORTCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in "Ports as General Digital I/O" on page 91. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in "Alternate Port Functions" on page 96. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.
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4.10.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 4-25 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 4-25. General Digital I/O(1)
PUD
Q
D
DDxn Q CLR
RESET
WDx RDx
1 Pxn
Q D PORTxn Q CLR
0
WPx RESET WRx SLEEP RRx
SYNCHRONIZER
D Q D Q
RPx
PINxn L Q Q
clk I/O
PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clkI/O : I/O CLOCK
WDx: RDx: WRx: RRx: RPx: WPx:
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports.
4.10.2.1
Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in "Register Description for I/O Ports" on page 109, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
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If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 4.10.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI assembler instruction can be used to toggle one single bit in a port. Break-Before-Make Switching In the Break-Before-Make mode when switching the DDRxn bit from input to output an immediate tri-state period lasting one system clock cycle is introduced as indicated in Figure 4-26. For example, if the system clock is 4MHz and the DDRxn is written to make an output, the immediate tri-state period of 250ns is introduced, before the value of PORTxn is seen on the port pin. To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system clock cycles. The Break-Before-Make is a port-wise mode and it is activated by the port-wise BBMx enable bits. For further information about the BBMx bits, see "Port Control Register - PORTCR" on page 99. When switching the DDRxn bit from output to input there is no immediate tri-state period introduced.
4.10.2.3
Figure 4-26. Break Before Make, Switching between Input and Output
SYSTEM CLOCK R 16 R 17 INSTRUCTIONS PORTx DDRx Px0
immediate tri-state cycle
0x02 0x01 out DDRx, r16 nop 0x55 0x01 0x02
tri-state
out DDRx, r17
0x01
Px1
tri-state
tri-state
immediate tri-state cycle
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4.10.2.4 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0, 0) and output high ({DDxn, PORTxn} = 1, 1), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0, 1) or output low ({DDxn, PORTxn} = 1, 0) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register or the PUDx bit in PORTCR Register can be set to disable all pull-ups in the port. Switching between input with pull-up and output low generates the same problem. The user m u s t u s e e it h e r t h e tr i - s t a t e ( { D D x n , P O R T x n } = 0 , 0 ) o r th e o u t p u t h i g h s t a t e ({DDxn, PORTxn} = 1, 1) as an intermediate step. Table 4-22 summarizes the control signals for the pin value.
Table 4-22.
DDxn 0 0 0 1 1 Note:
Port Pin Configurations
PUD (in MCUCR)(1) X 0 1 X X I/O Input Input Input Output Output Pull-up Comment No Yes No No No Tri-state (Hi-Z) Pxn will source current if ext. pulled low. Tri-state (Hi-Z) Output Low (Sink) Output High (Source)
PORTxn 0 1 1 0 1
1. Or port-wise PUDx bit in PORTCR register.
4.10.2.5
Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 4-25, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 4-27 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 4-27. Synchronization when Reading an Externally Applied Pin Value
SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd, max t pd, min 0xFF XXX XXX in r17, PINx
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the "SYNC LATCH" signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between 1/2 and 11/2 system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 4-28. The out instruction sets the "SYNC LATCH" signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 4-28. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd 0xFF out PORTx, r16 0xFF
nop
in r17, PINx
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.
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Assembly Code Example(1)
... ; Define pull-ups and set outputs high ; Define directions for port pins ldi ldi out out nop ; Read port pins in ... r16,PINB r16,(1<; Insert nop for synchronization
C Code Example
unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<95
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4.10.2.6
Digital Input Enable and Sleep Modes As shown in Figure 4-25, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down or Power-save mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to Vcc/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in "Alternate Port Functions" on page 96. If a logic high level ("one") is present on an asynchronous external interrupt pin configured as "Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin" while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change.
4.10.2.7
Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to Vcc or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.
4.10.3
Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 4-29 shows how the port pin control signals from the simplified Figure 4-25 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR(R) microcontroller family.
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Figure 4-29. Alternate Port Functions(1)
PUOExn PUOVxn
1 0
PUD
DDOExn DDOVxn
1 0
QD DDxn Q CLR
PVOExn PVOVxn
WDx RESET RDx
1 Pxn 0
Q D
1 0
PORTxn
DIEOExn DIEOVxn
1 0
Q CLR
PTOExn WPx
RESET RRx
WRx
SLEEP SYNCHRONIZER
D
SET
RPx
Q
D
Q
PINxn L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
PUD: PULLUP DISABLE WDx: RDx: RRx: WRx: RPx: WPx: clkI/O: DIxn: AIOxn: WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
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Table 4-23 summarizes the function of the overriding signals. The pin and port indexes from Figure 4-29 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. . Table 4-23.
Signal Name PUOE
Generic Description of Overriding Signals for Alternate Functions
Full Name Pull-up Override Enable Pull-up Override Value Data Direction Override Enable Data Direction Override Value Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, (PUD or PDUx)} = 0, 1, 0. If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, PUD and PUDx Register bits. If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.
PUOV
DDOE
DDOV
PVOE
If this signal is set and the Output Driver is enabled, the port Port Value Override value is controlled by the PVOV signal. If PVOE is cleared, and Enable the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit. Port Value Override If PVOE is set, the port value is set to PVOV, regardless of the Value setting of the PORTxn Register bit. Port Toggle Override If PTOE is set, the PORTxn Register bit is inverted. Enable Digital Input Enable Override Enable Digital Input Enable Override Value If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode). If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode). This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the Schmitt Trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.
PVOV PTOE
DIEOE
DIEOV
DI
Digital Input
AIO
This is the Analog Input/output to/from alternate functions. The Analog Input/Output signal is connected directly to the pad, and can be used bi-directionally.
The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.
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4.10.3.1 MCU Control Register - MCUCR
Bit Read/Write Initial Value 7 - R 0 6 BODS R/W 0 5 BODSE R/W 0 4 PUD R/W 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 MCUCR
* Bit 4 - PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0, 1). See "Configuring the Pin" on page 91 for more details about this feature. 4.10.3.2 Port Control Register - PORTCR
Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 BBMB R/W 0 4 BBMA R/W 0 3 R/W 0 2 R/W 0 1 PUDB R/W 0 0 PUDA R/W 0 PORTCR
* Bits 5, 4 - BBMx: Break-Before-Make Mode Enable When these bits are written to one, the port-wise Break-Before-Make mode is activated. The intermediate tri-state cycle is then inserted when writing DDRxn to make an output. For further information, see "Break-Before-Make Switching" on page 92. * Bits 1, 0 - PUDx: Port-Wise Pull-up Disable When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0, 1). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up Disable bit (PUD) from the MCUCR register. See "Configuring the Pin" on page 91 for more details about this feature.
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4.10.3.3
Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 4-24.
Table 4-24.
Port Pin
Port A Pins Alternate Functions
Alternate Function PCINT7 (Pin Change Interrupt 7) ADC7 (ADC Input Channel 7) AIN1 (Analog Comparator Positive Input) XREF (Internal Voltage Reference Output) AREF (External Voltage Reference Input) PCINT6 (Pin Change Interrupt 6) ADC6 (ADC Input Channel 6) AIN0 (Analog Comparator Negative Input) SS (SPI Slave Select Input) PCINT5 (Pin Change Interrupt 5) ADC5 (ADC Input Channel 5) T1 (Timer/Counter1 Clock Input) USCK (Three-wire Mode USI Alternate Clock Input) SCL (Two-wire Mode USI Alternate Clock Input) SCK (SPI Master Clock) PCINT4 (Pin Change Interrupt 4) ADC4 (ADC Input Channel 4) ICP1 (Timer/Counter1 Input Capture Trigger) DI (Three-wire Mode USI Alternate Data Input) SDA (Two-wire Mode USI Alternate Data Input / Output) MOSI (SPI Master Output / Slave Input) PCINT3 (Pin Change Interrupt 3) ADC3 (ADC Input Channel 3) ISRC (Current Source Pin) INT1 (External Interrupt1 Input) PCINT2 (Pin Change Interrupt 2) ADC2 (ADC Input Channel 2) OC0A (Output Compare and PWM Output A for Timer/Counter0) DO (Three-wire Mode USI Alternate Data Output) MISO (SPI Master Input / Slave Output) PCINT1 (Pin Change Interrupt 1) ADC1 (ADC Input Channel 1) TXD (UART Transmit Pin) TXLIN (LIN Transmit Pin) PCINT0 (Pin Change Interrupt 0) ADC0 (ADC Input Channel 0) RXD (UART Receive Pin) RXLIN (LIN Receive Pin)
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
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The alternate pin configuration is as follows: * PCINT7/ADC7/AIN1/XREF/AREF - Port A, Bit7 PCINT7: Pin Change Interrupt, source 7. ADC7: Analog to Digital Converter, channel 7. AIN1: Analog Comparator Positive Input. This pin is directly connected to the positive input of the Analog Comparator. XREF: Internal Voltage Reference Output. The internal voltage reference 2.56V or 1.1V is output when XREFEN is set and if either 2.56V or 1.1V is used as reference for ADC conversion. When XREF output is enabled, the pin port pull-up and digital output driver are turned off. AREF: External Voltage Reference Input for ADC. The pin port pull-up and digital output driver are disabled when the pin is used as an external voltage reference input for ADC or as when the pin is only used to connect a bypass capacitor for the voltage reference of the ADC. * PCINT6/ADC6/AIN0/SS - Port A, Bit6 PCINT6: Pin Change Interrupt, source 6. ADC6: Analog to Digital Converter, channel 6. AIN0: Analog Comparator Negative Input. This pin is directly connected to the negative input of the Analog Comparator. SS: SPI Slave Select Input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDA6. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDA6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTA6 bit. * PCINT5/ADC5/T1/USCK/SCL/SCK - Port A, Bit5 PCINT5: Pin Change Interrupt, source 5. ADC5: Analog to Digital Converter, channel 5. T1: Timer/Counter1 Clock Input. USCK: Three-wire Mode USI Clock Input. SCL: Two-wire Mode USI Clock Input. SCK: SPI Master Clock output, Slave Clock input pin. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDA5. When the SPI is enabled as a master, the data direction of this pin is controlled by DDA5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTA5 bit. * PCINT4/ADC4/ICP1/DI/SDA/MOSI - Port A, Bit 4 PCINT4: Pin Change Interrupt, source 4. ADC4: Analog to Digital Converter, channel 4. ICP1: Timer/Counter1 Input Capture Trigger. The PA3 pin can act as an Input Capture pin for Timer/Counter1.
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DI:
Three-wire Mode USI Data Input. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function.
SDA: Two-wire Mode Serial Interface (USI) Data Input / Output. MOSI: SPI Master Output / Slave Input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDA3. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDA3. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTA3 bit. * PCINT3/ADC3/ISRC/INT1 - Port A, Bit 3 PCINT3: Pin Change Interrupt, source 3. ADC3: Analog to Digital Converter, channel 3. ISCR: Current Source Output pin. While current is sourced by the Current Source module, the user can use the Analog to Digital Converter channel 4 (ADC4) to measure the pin voltage. INT1: External Interrupt, source 1. The PA4 pin can serve as an external interrupt source. * PCINT2/ADC2/OC0A/DO/MISO - Port A, Bit 2 PCINT2: Pin Change Interrupt, source 2. ADC2: Analog to Digital Converter, channel 2. OC0A: Output Compare Match A or output PWM A for Timer/Counter0. The pin has to be configured as an output (DDA2 set (one)) to serve these functions. DO: Three-wire Mode USI Data Output. Three-wire mode data output overrides PORTA2 and it is driven to the port when the data direction bit DDA2 is set. PORTA2 still enables the pull-up, if the direction is input and PORTA2 is set (one). MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDA2. When the SPI is enabled as a Salve, the data direction of this pin is controlled by DDA2. When the pin is forced to be an input, the pull-up can still be controlled by PORTA2. * PCINT1/ADC1/TXD/TXLIN - Port A, Bit 1 PCINT1: Pin Change Interrupt, source 1. ADC1: Analog to Digital Converter, channel 1. TXD: UART Transmit pin. When the UART transmitter is enabled, this pin is configured as an output regardless the value of DDA1. PORTA1 still enables the pull-up, if the direction is input and PORTA2 is set (one). TXLIN: LIN Transmit pin. When the LIN is enabled, this pin is configured as an output regard less the value of DDA1. PORTA1 still enables the pull-up, if the direction is input and PORTA2 is set (one). * PCINT0/ADC0/RXD/RXLIN - Port A, Bit 0 PCINT0: Pin Change Interrupt, source 0. ADC0: Analog to Digital Converter, channel 0.
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RXD: UART Receive pin. When the UART receiver is enabled, this pin is configured as an input regardless of the value of DDA0. When the pin is forced to be an input, a logical one in PORTA0 will turn on the internal pull-up. RXLIN: LIN Receive pin. When the LIN is enabled, this pin is configured as an input regardless of the value of DDA0. When the pin is forced to be an input, a logical one in PORTA0 will turn on the internal pull-up. Table 4-25 and Table 4-26 relate the alternate functions of Port A to the overriding signals shown in Figure 4-29 on page 97.
Table 4-25.
Signal Name PUOE PUOV DDOE
Overriding Signals for Alternate Functions in PA7..PA4
PA6/PCINT6/ ADC6/AIN0/SS SPE & MSTR PORTA6 & PUD SPE & MSTR PA5/PCINT5/ADC5/ T1/USCK/SCL/SCK SPE & MSTR PORTA5 & PUD (SPE & MSTR) | (USI_2_WIRE & USIPOS) PA4/PCINT4/ADC4/ ICP1/DI/SDA/MOSI SPE & MSTR PORTA4 & PUD (SPE & MSTR) | (USI_2_WIRE & USIPOS) { (SPE & MSTR) ? (0) : (USI_SHIFTOUT | PORTA4) & DDRA4) }
PA7/PCINT7/ ADC7/AIN1 /XREF/AREF 0 0 0
DDOV
0
0
(USI_SCL_HOLD | PORTA5) & DDRA6
PVOE
0
0
(SPE & MSTR) | (SPE & MSTR) | (USI_2_WIRE & USIPOS (USI_2_WIRE & USIPOS & DDRA5) & DDRA4) { (SPE & MSTR) ? (SCK_OUTPUT) : ~ (USI_2_WIRE & USIPOS & DDRA5) } USI_PTOE & USIPOS ADC5D | (USISIE & USIPOS) | (PCIE0 & PCMSK05) (USISIE & USIPOS) | (PCIE0 & PCMSK05) PCINT5 -/- T1 -/- USCK -/- SCL -/- SCK ADC5 { (SPE & MSTR) ? (MOSI_OUTPUT) : ~ (USI_2_WIRE & USIPOS & DDRA4) } 0 ADC4D | (USISIE & USIPOS) | (PCIE0 & PCMSK04) (USISIE & USIPOS) | (PCIE0 & PCMSK04) PCINT4 -/- ICP1 -/- DI -/- SDA -/- MOSI ADC4
PVOV
0
0
PTOE DIEOE
0 ADC7D | (PCIE0 & PCMSK07) PCIE0 & PCMSK07 PCINT7 ADC7 -/- AIN1 -/XREF -/- AREF
0 ADC6D | (PCIE0 & PCMSK06) PCIE0 & PCMSK06 PCINT6 -/- SS ADC6 -/- AIN0
DIEOV DI AIO
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Table 4-26.
Overriding Signals for Alternate Functions in PA3..PA0
PA2/PCINT2/ADC2/ OC0A/DO/MISO SPE & MSTR PORTA2 & PUD SPE & MSTR 0 (SPE & MSTR) | (USI_2_WIRE & USI_3_WIRE & USIPOS) | OC0A PA1/PCINT1/ADC1/ TXD/TXLIN LIN_TX_ENABLE { (LIN_TX_ENABLE) ? (0) : (PORTA1 & PUD) } LIN_TX_ENABLE LIN_TX_ENABLE PA0/PCINT0/ADC0/ RXD/RXLIN LIN_RX_ENABLE PORTA0 & PUD LIN_RX_ENABLE 0
PA3/PCINT3/ADC3 Signal / Name ISRC/INT1 PUOE PUOV DDOE DDOV 0 PORTA3 & PUD 0 0
PVOE
0
LIN_TX_ENABLE
0
PVOV
0
{ (SPE & MSTR) ? (MISO_OUTPUT) : { (LIN_TX_ENABLE) ? ( ( USI_2_WIRE & (LIN_TX) : (0) } USI_3_WIRE & USIPOS ) ? (USI_SHIFTOUT) : (OC0A) ) } 0 ADC2D | (PCIE0 & PCMSK02) 0 ADC1D | (PCIE0 & PCMSK01)
0
PTOE
0 ADC3D | INT1_ENABLE | (PCIE0 & PCMSK03) INT1_ENABLE | (PCIE0 & PCMSK03) PCINT3 -/- INT1 ADC3 -/- ISRC
0 ADC0D | (PCIE0 & PCMSK00)
DIEOE
DIEOV DI AIO
PCIE0 & PCMSK02 PCINT2 -/- MISO ADC2
PCIE0 & PCMSK01 PCINT1 ADC1
PCIE0 & PCMSK00 PCINT0 ADC0
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4.10.3.4 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 4-27.
Table 4-27.
Port Pin
Port B Pins Alternate Functions
Alternate Functions PCINT15 (Pin Change Interrupt 15) ADC10 (ADC Input Channel 10) OC1BX (Output Compare and PWM Output B-X for Timer/Counter1) RESET (Reset input pin) dW (debugWIRE I/O) PCINT14 (Pin Change Interrupt 14) ADC9 (ADC Input Channel 9) OC1AX (Output Compare and PWM Output A-X for Timer/Counter1) INT0 (External Interrupt0 Input) PCINT13 (Pin Change Interrupt 13) ADC8 (ADC Input Channel 8) OC1BW (Output Compare and PWM Output B-W for Timer/Counter1) XTAL2 (Chip clock Oscillator pin 2) CLKO (System clock output) PCINT12 (Pin Change Interrupt 12) OC1AW (Output Compare and PWM Output A-W for Timer/Counter1) XTAL1 (Chip clock Oscillator pin 1) CLKI (External clock input) PCINT11 (Pin Change Interrupt 11) OC1BV (Output Compare and PWM Output B-V for Timer/Counter1) PCINT10 (Pin Change Interrupt 10) OC1AV (Output Compare and PWM Output A-V for Timer/Counter1) USCK (Three-wire Mode USI Default Clock Input) SCL (Two-wire Mode USI Default Clock Input) PCINT9 (Pin Change Interrupt 9) OC1BU (Output Compare and PWM Output B-U for Timer/Counter1) DO (Three-wire Mode USI Default Data Output) PCINT8 (Pin Change Interrupt 8) OC1AU (Output Compare and PWM Output A-U for Timer/Counter1) DI (Three-wire Mode USI Default Data Input) SDA (Two-wire Mode USI Default Data Input / Output)
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
The alternate pin configuration is as follows: * PCINT15/ADC10/OC1BX/RESET/dW - Port B, Bit 7 PCINT15: Pin Change Interrupt, source 15. ADC10: Analog to Digital Converter, channel 10. OC1BX: Output Compare and PWM Output B-X for Timer/Counter1. The PB7 pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC1BX pin is also the output pin for the PWM mode timer function (c.f. OC1BX bit of TCCR1D register).
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RESET: Reset input pin. When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources. When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an I/O pin. If PB7 is used as a reset pin, DDB7, PORTB7 and PINB7 will all read 0. dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. * PCINT14/ADC9/OC1AX/INT0 - Port B, Bit 6 PCINT14: Pin Change Interrupt, source 14. ADC9: Analog to Digital Converter, channel 9. OC1AX: Output Compare and PWM Output A-X for Timer/Counter1. The PB6 pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1AX pin is also the output pin for the PWM mode timer function (c.f. OC1AX bit of TCCR1D register). INT0: External Interrupt0 Input. The PB6 pin can serve as an external interrupt source. * PCINT13/ADC8/OC1BW/XTAL2/CLKO - Port B, Bit 5 PCINT13: Pin Change Interrupt, source 13. ADC8: Analog to Digital Converter, channel 8. OC1BW: Output Compare and PWM Output B-W for Timer/Counter1. The PB5 pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1BW pin is also the output pin for the PWM mode timer function (c.f. OC1BW bit of TCCR1D register). XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. CLKO: Divided system clock output. The divided system clock can be output on the PB5 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB5 and DDB5 settings. It will also be output during reset. * PCINT12/OC1AW/XTAL1/CLKI - Port B, Bit 4 PCINT12: Pin Change Interrupt, source 12. OC1AW: Output Compare and PWM Output A-W for Timer/Counter1. The PB4 pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC1AW pin is also the output pin for the PWM mode timer function (c.f. OC1AW bit of TCCR1D register). XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. CLKI: External clock input. When used as a clock pin, the pin can not be used as an I/O pin.
Note: If PB4 is used as a clock pin (XTAL1 or CLKI), DDB4, PORTB4 and PINB4 will all read 0.
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* PCINT11/OC1BV - Port B, Bit 3 PCINT11: Pin Change Interrupt, source 11. OC1BV: Output Compare and PWM Output B-V for Timer/Counter1. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1BV pin is also the output pin for the PWM mode timer function (c.f. OC1BV bit of TCCR1D register). * PCINT10/OC1AV/USCK/SCL - Port B, Bit 2 PCINT10: Pin Change Interrupt, source 10. OC1AV: Output Compare and PWM Output A-V for Timer/Counter1. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The OC1AV pin is also the output pin for the PWM mode timer function (c.f. OC1AV bit of TCCR1D register). USCK: Three-wire Mode USI Clock Input. SCL: Two-wire Mode USI Clock Input. * PCINT9/OC1BU/DO - Port B, Bit 1 PCINT9: Pin Change Interrupt, source 9. OC1BU: Output Compare and PWM Output B-U for Timer/Counter1. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC1BU pin is also the output pin for the PWM mode timer function (c.f. OC1BU bit of TCCR1D register). DO: Three-wire Mode USI Data Output. Three-wire mode data output overrides PORTB1 and it is driven to the port when the data direction bit DDB1 is set. PORTB1 still enables the pull-up, if the direction is input and PORTB1 is set (one). * PCINT8/OC1AU/DI/SDA - Port B, Bit 0 IPCINT8: Pin Change Interrupt, source 8. OC1AU: Output Compare and PWM Output A-U for Timer/Counter1. The PB0 pin has to be configured as an output (DDB0 set (one)) to serve this function. The OC1AU pin is also the output pin for the PWM mode timer function (c.f. OC1AU bit of TCCR1D register). DI: Three-wire Mode USI Data Input. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function.
SDA: Two-wire Mode Serial Interface (USI) Data Input / Output.
Table 4-28 and Table 4-29 relate the alternate functions of Port B to the overriding signals shown in Figure 4-29 on page 97.
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Table 4-28.
Overriding Signals for Alternate Functions in PB7..PB4
Signal PB7/PCINT15/ADC10/ PB6/PCINT14/ADC9/ PB5/PCINT13/ADC8/ PB4/PCINT12/ Name OC1BX/RESET/dW OC1AX/INT0 OC1BW/XTAL2/CLKO OC1AW/XTAL1/CLKI PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE 0 0 0 0 OC1B_ENABLE & OC1BX OC1B 0 ADC10D | (PCIE1 & PCMSK15) PCIE1 & PCMSK15 PCINT15 RESET -/- ADC10 -/0 0 0 0 OC1A_ENABLE & OC1AX OC1A 0 ADC9D | INT0_ENABLE | (PCIE1 & PCMSK14) INT0_ENABLE | (PCIE1 & PCMSK14) PCINT14 -/- INT1 ADC9 -/- ISRC 0 0 0 0 OC1B_ENABLE & OC1BW OC1B 0 ADC8D | (PCIE1 & PCMSK13) PCIE1 & PCMSK13 PCINT13 ADC8 -/- XTAL2 0 0 0 0 OC1A_ENABLE & OC1AW OC1A 0 (PCIE1 & PCMSK13)
DIEOV DI AIO
1 PCINT12 XTAL1 -/- CLKI
Table 4-29.
Signal Name PUOE PUOV DDOE
Overriding Signals for Alternate Functions in PB3..PB0
PB2/PCINT10/ OC1AV/USCK/SCL 0 0 (USI_2_WIRE & USIPOS) (USI_SCL_HOLD | PORTB2) & DDRB2 (USI_2_WIRE & USIPOS & DDRB2) | (OC1A_ENABLE & OC1AV) { (USI_2_WIRE & USIPOS & DDRB2) ? (0) : (OC1A) } USI_PTOE & USIPOS (USISIE & USIPOS) | (PCIE1 & PCMSK10) (USISIE & USIPOS) | (PCIE1 & PCMSK10) PCINT10 -/- USCK -/SCL 0 PB1/PCINT9/ OC1BU/DO 0 0 0 PB0/IPCINT8/ OC1AU/DI/SDA 0 0 (USI_2_WIRE & USIPOS) (USI_SHIFTOUT | PORTB0) & DDRB0) (USI_2_WIRE & USIPOS & DDRB0) | (OC1A_ENABLE & OC1AU) { (USI_2_WIRE & USIPOS & DDRB0) ? (0) : (OC1A) } 0 (USISIE & USIPOS) | (PCIE1 & PCMSK8) (USISIE & USIPOS) | (PCIE1 & PCMSK8) PCINT8 -/- DI -/- SDA 0
PB3/PCINT11/ OC1BV 0 0 0
DDOV
0
0 (USI_2_WIRE & USI_3_WIRE & USIPOS) | (OC1B_ENABLE & OC1BU) { (USI_2_WIRE & USI_3_WIRE & USIPOS) ? (USI_SHIFTOUT) : (OC1B) } 0 PCIE1 & PCMSK9 1 PCINT9 0
PVOE
OC1B_ENABLE & OC1BV
PVOV
OC1B
PTOE DIEOE DIEOV DI AIO
0 PCIE1 & PCMSK11 1 PCINT11 0
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4.10.4 Register Description for I/O Ports
4.10.4.1
Port A Data Register - PORTA
Bit Read/Write Initial Value 7 PORTA7 R/W 0 6 PORTA6 R/W 0 5 PORTA5 R/W 0 4 PORTA4 R/W 0 3 PORTA3 R/W 0 2 PORTA2 R/W 0 1 PORTA1 R/W 0 0 PORTA0 R/W 0 PORTA
4.10.4.2
Port A Data Direction Register - DDRA
Bit Read/Write Initial Value 7 DDA7 R/W 0 6 DDA6 R/W 0 5 DDA5 R/W 0 4 DDA4 R/W 0 3 DDA3 R/W 0 2 DDA2 R/W 0 1 DDA1 R/W 0 0 DDA0 R/W 0 DDRA
4.10.4.3
Port A Input Pins Register - PINA
Bit Read/Write Initial Value 7 PINA7 R/(W) N/A 6 PINA6 R/(W) N/A 5 PINA5 R/(W) N/A 4 PINA4 R/(W) N/A 3 PINA3 R/(W) N/A 2 PINA2 R/(W) N/A 1 PINA1 R/(W) N/A 0 PINA0 R/(W) N/A PINA
4.10.4.4
Port B Data Register - PORTB
Bit Read/Write Initial Value 7 6 5 4 3 2 1 0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 PORTB
4.10.4.5
Port B Data Direction Register - DDRB
Bit Read/Write Initial Value 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB
4.10.4.6
Port B Input Pins Register - PINB
Bit Read/Write Initial Value 7 PINB7 R/(W) N/A 6 PINB6 R/(W) N/A 5 PINB5 R/(W) N/A 4 PINB4 R/(W) N/A 3 PINB3 R/(W) N/A 2 PINB2 R/(W) N/A 1 PINB1 R/(W) N/A 0 PINB0 R/(W) N/A PINB
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4.11
8-bit Timer/Counter0 and Asynchronous Operation
Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are:
4.11.1
Features * * * * * * *
Single Channel Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) Allows Clocking from External Crystal (i.e. 32kHz Watch Crystal) Independent of the I/O Clock
4.11.2
Overview Many register and bit references in this section are written in general form. * A lower case "n" replaces the Timer/Counter number, in this case 0. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. * A lower case "x" replaces the Output Compare unit channel, in this case A. However, when using the register or bit defines in a program, the precise form must be used, i.e., OCR0A for accessing Timer/Counter0 output compare channel A value and so on. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 4-30. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "8-bit Timer/Counter Register Description" on page 124.
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Figure 4-30. 8-bit Timer/Counter0 Block Diagram
TCCRnx
count clear direction Control Logic
TOVn (Int.Req.) clkTn XTAL2
BOTTOM
TOP Prescaler
Oscillator XTAL1
Timer/Counter TCNTn
=0
= 0xFF
OCnx (Int.Req.) clk I/O
DATA BUS
=
Waveform Generation
OCnx
OCRnx
Synchronized Status flags
clk I/O Synchronization Unit clk ASY
Status flags
ASSRn asynchronous mode select (ASn)
The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the XTAL1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0A). See "Output Compare Unit" on page 113. for details. The compare match event will also set the compare flag (OCF0A) which can be used to generate an Output Compare interrupt request.
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4.11.2.1
Definitions The following definitions are used extensively throughout the section:
BOTTOM MAX TOP
The counter reaches the BOTTOM when it becomes zero (0x00). The counter reaches its MAXimum when it becomes 0xFF (decimal 255). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation.
4.11.3
Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter control register (TCCR0).The clock source clkT0 is by default equal to the MCU clock, clkI/O. When the AS0 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to XTAL1 and XTAL2 or directly from XTAL1. For details on asynchronous operation, see "Asynchronous Status Register - ASSR" on page 127. For details on clock sources and prescaler, see "Timer/Counter0 Prescaler" on page 123. Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 4-31 shows a block diagram of the counter and its surrounding environment. Figure 4-31. Counter Unit Block Diagram
DATA BUS
TOVn (Int.Req.)
4.11.4
XTAL2 count TCNTn clear direction Control Logic clk Tn Prescaler clkTnS Oscillator XTAL1
bottom
top clk I/O
Signal description (internal signals): count direction clear clkT0 top bottom Increment or decrement TCNT0 by 1. Selects between increment and decrement. Clear TCNT0 (set all bits to zero). Timer/Counter0 clock. Signalizes that TCNT0 has reached maximum value. Signalizes that TCNT0 has reached minimum value (zero).
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Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0A. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 116. The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt. 4.11.5 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF0A flag is automatically cleared when the interrupt is executed. Alternatively, the OCF0A flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation ("Modes of Operation" on page 116). Figure 4-32 shows a block diagram of the Output Compare unit. Figure 4-32. Output Compare Unit, Block Diagram
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top bottom FOCn
Waveform Generator
OCnx
WGMn1:0
COMnX1:0
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The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0A Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0A Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is disabled the CPU will access the OCR0A directly. 4.11.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the OCF0A flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or toggled). Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. The setup of the OC0A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0A value is to use the Force Output Compare (FOC0A) strobe bit in Normal mode. The OC0A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM0A1:0 bits are not double buffered together with the compare value. Changing the COM0A1:0 bits will take effect immediately. 4.11.6 Compare Match Output Unit The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 4-33 shows a simplified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin.
4.11.5.2
4.11.5.3
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Figure 4-33. Compare Match Output Logic
COMnx1 COMnx0 FOCnx
Waveform Generator
D
Q
1 OCnx Pin
OCnx D
DATA BUS
0
Q
PORT D Q
DDR
clk I/O
4.11.6.1
Compare Output Function The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0A state before the output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of operation. See "8-bit Timer/Counter Register Description" on page 124.
4.11.6.2
Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0A1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on the OC0A Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 4-30 on page 124. For fast PWM mode, refer to Table 4-31 on page 124, and for phase correct PWM refer to Table 4-32 on page 125. A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0A strobe bits.
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4.11.7
Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0A1:0 bits control whether the output should be set, cleared, or toggled at a compare match (See "Compare Match Output Unit" on page 114.). For detailed timing information refer to "Timer/Counter Timing Diagrams" on page 120.
4.11.7.1
Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
4.11.7.2
Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 4-34. The counter value (TCNT0) increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 4-34. CTC Mode, Timing Diagram
OCnx Interrupt Flag Set
TCNTn
OCnx (Toggle) Period
1 2 3 4
(COMnx1:0 = 1)
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An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC0A = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation:
f clk_I/O f OCnx = ------------------------------------------------------2 x N x ( 1 + OCRnx )
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 4.11.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 4-35. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0.
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Figure 4-35. Fast PWM Mode, Timing Diagram
OCRnx Interrupt Flag Set
OCRnx Update and TOVn Interrupt Flag Set
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 4-31 on page 124). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0A Register at the compare match between OCR0A and TCNT0, and clearing (or setting) the OC0A Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation:
f clk_I/O f OCnxPWM = -------------------N x 256
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The waveform generated will have a maximum frequency of foc0A = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
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4.11.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 4-36. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. Figure 4-36. Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnxi OCnxi
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 4-32 on page 125). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output.
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The PWM waveform is generated by clearing (or setting) the OC0A Register at the compare match between OCR0A and TCNT0 when the counter increments, and setting (or clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation:
f clk_I/O f OCnxPCPWM = -------------------N x 510
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 4.11.8 Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT0) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when interrupt flags are set. Figure 4-37 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 4-37. Timer/Counter Timing Diagram, no Prescaling
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 4-38 shows the same timing data, but with the prescaler enabled. Figure 4-38. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
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Figure 4-39 shows the setting of OCF0A in all modes except CTC mode. Figure 4-39. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 4-40 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 4-40. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRnx
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
4.11.9
Asynchronous Operation of Timer/Counter0 When Timer/Counter0 operates asynchronously, some considerations must be taken. * Warning: When switching between asynchronous and synchronous clocking of Timer/Counter0, the timer registers TCNT0, OCR0A, and TCCR0A might be corrupted. A safe procedure for switching clock source is: a) Disable the Timer/Counter0 interrupts by clearing OCIE0A and TOIE0. b) Select clock source by setting AS0 and EXCLK as appropriate. c) Write new values to TCNT0, OCR0A, and TCCR0A. d) To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, and TCR0UB. e) Clear the Timer/Counter0 interrupt flags. f) Enable interrupts, if needed. * If an 32.768 kHzwatch crystal is used, the CPU main clock frequency must be more than four times the Oscillator or external clock frequency.
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* When writing to one of the registers TCNT0, OCR0A, or TCCR0A, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g. writing to TCNT0 does not disturb an OCR0A write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register - ASSR has been implemented. * When entering Power-save mode after having written to TCNT0, OCR0A, or TCCR0A, the user must wait until the written register has been updated if Timer/Counter0 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare0 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR0A or TCNT0. If the write cycle is not finished, and the MCU enters sleep mode before the OCR0UB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. * If Timer/Counter0 is used to wake the device up from Power-save mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: a) Write a value to TCCR0A, TCNT0, or OCR0A. b) Wait until the corresponding Update Busy flag in ASSR returns to zero. c) Enter Power-save or ADC Noise Reduction mode. * When the asynchronous operation is selected, the oscillator for Timer/Counter0 is always running, except in Power-down mode. After a Power-up Reset or wake-up from Power-down mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter0 after power-up or wake-up from Power-down mode. The contents of all Timer/Counter0 Registers must be considered lost after a wake-up from Power-down mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a clock signal is applied to the XTAL1 pin. * Description of wake up from Power-save mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. * Reading of the TCNT0 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT0 is clocked on the asynchronous clock, reading TCNT0 must be done through a register synchronized to the internal I/O clock domain (CPU main clock). Synchronization takes place for every rising XTAL1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT0 will read as the previous value (before entering sleep) until the next rising XTAL1 edge. The phase of the XTAL1 clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT0 is thus as follows:
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a) Write any value to either of the registers OCR0A or TCCR0A. b) Wait for the corresponding Update Busy Flag to be cleared. c) Read TCNT0. * During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 4.11.10 Timer/Counter0 Prescaler Figure 4-41. Prescaler for Timer/Counter0
XTAL2 Oscillator XTAL1 clkI/O
0 1
clkTnS Clear
0 1
10-BIT T/C PRESCALER
clkTnS/32
clkTnS/128
EXCLK
ASn
PSRn
0
CSn0 CSn1 CSn2
TIMER/COUNTERn CLOCK SOURCE clkTn
The clock source for Timer/Counter0 is named clkT0S. clkT0S is by default connected to the main system I/O clock clkIO. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked from the XTAL oscillator or XTAL1 pin. This enables use of Timer/Counter0 as a Real Time Counter (RTC). A crystal can then be connected between the XTAL1 and XTAL2 pins to serve as an independent clock source for Timer/Counter0. A external clock can also be used using XTAL1 as input. Setting AS0 and EXCLK enables this configuration. For Timer/Counter0, the possible prescaled selections are: clkT0S/8, clk T0S/32, clkT0S/64, clk T0S /128, clk T0S /256, and clk T0S /1024. Additionally, clk T0S as well as 0 (stop) may be selected. Setting the PSR0 bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler.
clkTnS/1024
clkTnS/256
clkTnS/64
clkTnS/8
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4.11.11 4.11.11.1
8-bit Timer/Counter Register Description Timer/Counter0 Control Register A - TCCR0A
Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 WGM01 R/W 0 0 WGM00 R/W 0 TCCR0A COM0A1 COM0A0
* Bit 7:6 - COM0A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0A pin must be set in order to enable the output driver. When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. Table 4-30 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM).
Table 4-30.
COM0A1 0 0 1 1
Compare Output Mode, non-PWM Mode
COM0A0 0 1 0 1 Description Normal port operation, OC0A disconnected. Toggle OC0A on Compare Match. Clear OC0A on Compare Match. Set OC0A on Compare Match.
Table 4-31 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 4-31.
COM0A1 0 0 1 1 Note:
Compare Output Mode, Fast PWM Mode(1)
COM0A0 0 1 0 1 Description Normal port operation, OC0A disconnected. Clear OC0A on Compare Match. Set OC0A at BOTTOM (non-inverting mode). Set OC0A on Compare Match. Clear OC0A at BOTTOM (inverting mode).
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See Section 4.11.7.3 "Fast PWM Mode" on page 117 for more details.
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Table 4-32 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A0 0 1 0 1 Description Normal port operation, OC0A disconnected. Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting.
Table 4-32.
COM0A1 0 0 1 1 Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 119 for more details.
* Bit 5:2 - Res: Reserved Bits These bits are reserved in the Atmel(R) ATtiny87/167 and will always read as zero. * Bit 6, 3 - WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used, see Table 4-33. Modes of operation supported by the Timer/Counter unit are: Normal mode (Counter), Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (See "Modes of Operation" on page 116.).
Table 4-33.
Mode 0 1 2 3 Notes:
Waveform Generation Mode Bit Description
WGM00 (PWM0) 0 1 0 1 Timer/Counter Mode of Operation Normal PWM, Phase Correct CTC Fast PWM TOP 0xFF 0xFF OCR0A 0xFF Update of OCR0A at Immediate TOP Immediate TOP TOV0 Flag Set on(1)(2) MAX BOTTOM MAX MAX
WGM01 (CTC0) 0 0 1 1
1. MAX = 0xFF 2. BOTTOM = 0x00
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4.11.11.2
Timer/Counter0 Control Register B - TCCR0B
Bit Read/Write Initial Value 7 FOC0A W 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0B
* Bit 7 - FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare. A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. * Bit 6:3 - Res: Reserved Bits These bits are reserved in the Atmel(R) ATtiny87/167 and will always read as zero. * Bit 2:0 - CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 4-34.
Table 4-34.
CS02 0 0 0 0 1 1 1 1
Clock Select Bit Description
CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 Description No clock source (Timer/Counter stopped). clkT0S (No prescaling) clkT0S/8 (From prescaler) clkT0S/32 (From prescaler) clkT0S/64 (From prescaler) clkT0S/128 (From prescaler) clkT0S/256 (From prescaler) clkT0S/1024 (From prescaler)
4.11.11.3
Timer/Counter0 Register - TCNT0
Bit Read/Write Initial Value 7 TCNT07 R/W 0 6 TCNT06 R/W 0 5 TCNT05 R/W 0 4 TCNT04 R/W 0 3 TCNT03 R/W 0 2 TCNT02 R/W 0 1 TCNT01 R/W 0 0 TCNT00 R/W 0 TCNT0
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Register.
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4.11.11.4 Output Compare Register A - OCR0A
Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR0A R/W 0 OCR0A7 OCR0A6 OCR0A5 OCR0A4 OCR0A3 OCR0A2 OCR0A1 OCR0A0
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. 4.11.11.5 Asynchronous Status Register - ASSR
Bit Read/Write Initial Value 7 - R 0 6 EXCLK R/W 0 5 AS0 R/W 0 4 R 0 3 R 0 2 - R 0 1 R 0 0 ASSR R 0 TCN0UB OCR0AUB TCR0AUB TCR0BUB
* Bit 7 - Res: Reserved Bit This bit is reserved in the Atmel(R) ATtiny87/167 and will always read as zero. * Bit 6 - EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on XTAL1 pin instead of an external crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal oscillator will only run when this bit is zero. * Bit 5 - AS0: Asynchronous Timer/Counter0 When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clkI/O and the Timer/Counter0 acts as a synchronous peripheral. When AS0 is written to one, Timer/Counter0 is clocked from the low-frequency crystal oscillator (Section 4.5.2.5 "Low-frequency Crystal Oscillator" on page 53) or from external clock on XTAL1 pin (Section 4.5.2.6 "External Clock" on page 54) depending on EXCLK setting. When the value of AS0 is changed, the contents of TCNT0, OCR0A, and TCCR0A might be corrupted. AS0 also acts as a flag: Timer/Counter0 is clocked from the low-frequency crystal or from external clock ONLY IF the calibrated internal RC oscillator or the internal watchdog oscillator is used to drive the system clock. After setting AS0, if the switching is available, AS0 remains to 1, else it is forced to 0. * Bit 4 - TCN0UB: Timer/Counter0 Update Busy When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set. When TCNT0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value. * Bit 3 - OCR0AUB: Output Compare 0 Register A Update Busy When Timer/Counter0 operates asynchronously and OCR0A is written, this bit becomes set. When OCR0A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR0A is ready to be updated with a new value. * Bit 2 - Res: Reserved Bit This bit is reserved in the Atmel ATtiny87/167 and will always read as zero.
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* Bit 1 - TCR0AUB: Timer/Counter0 Control Register A Update Busy When Timer/Counter0 operates asynchronously and TCCR0A is written, this bit becomes set. When TCCR0A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR0A is ready to be updated with a new value. * Bit 0 - TCR0BUB: Timer/Counter0 Control Register B Update Busy When Timer/Counter0 operates asynchronously and TCCR0B is written, this bit becomes set. When TCCR0B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR0B is ready to be updated with a new value. If a write is performed to any of the four Timer/Counter0 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT0, OCR0A, TCCR0A and TCCR0B are different. When reading TCNT0, the actual timer value is read. When reading OCR0A, TCCR0A or TCCR0B the value in the temporary storage register is read. 4.11.11.6 Timer/Counter0 Interrupt Mask Register - TIMSK0
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 OCIE0A R/W 0 0 TOIE0 R/W 0 TIMSK0
* Bit 7:2 - Res: Reserved Bits These bits are reserved in the Atmel(R) ATtiny87/167 and will always read as zero. * Bit 1 - OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter0 Interrupt Flag Register - TIFR0. * Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter0 Interrupt Flag Register - TIFR0.
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4.11.11.7 Timer/Counter0 Interrupt Flag Register - TIFR0
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 OCF0A R/W 0 0 TOV0 R/W 0 TIFR0
* Bit 7:2 - Res: Reserved Bits These bits are reserved in the Atmel(R) ATtiny87/167 and will always read as zero. * Bit 1 - OCF0A: Output Compare Flag 0 A The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0A - Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Interrupt Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Interrupt is executed. * Bit 0 - TOV0: Timer/Counter0 Overflow Flag The TOV0 bit is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0A (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. 4.11.11.8 General Timer/Counter Control Register - GTCCR
Bit Read/Write Initial Value 7 TSM R/W 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 PSR0 R/W 0 0 PSR1 R/W 0 GTCCR
* Bit 1 - PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the "Bit 7 - TSM: Timer/Counter Synchronization Mode" on page 132 for a description of the Timer/Counter Synchronization mode.
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4.12
4.12.1
Timer/Counter1 Prescaler
Overview Most bit references in this section are written in general form. A lower case "n" replaces the Timer/Counter number.
4.12.1.1
Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. Prescaler Reset The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/Counter. Since the prescaler is not affected by the Timer/Counter's clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to.
4.12.1.2
4.12.1.3
External Clock Source An external clock source applied to the T1 pin can be used as Timer/Counter clock (clkT1). The T1 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 4-42 shows a functional equivalent block diagram of the T1 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clk T1 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 4-42. T1 Pin Sampling
Tn_sync (To Clock Select Logic)
Tn
D LE
Q
D
Q
D
Q
clk I/O Synchronization Edge Detector
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The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50 % duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 4-43. Prescaler for Timer/Counter1(1)
CLKI/O
Clear
10-BIT T/C PRESCALER
CK/8 CK/64 CK/256 CK/1024
PSRn
0
Tn
Synchronization
CSn0 CSn1 CSn2
clkTn
TIMER/COUNTERn CLOCK SOURCE
Note:
1. The synchronization logic on the input pin (T1) is shown in Figure 4-42.
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4.12.2 4.12.2.1
Timer/Counter1 Prescalers Register Description General Timer/Counter Control Register - GTCCR
Bit Read/Write Initial Value 7 TSM R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 PSR0 R/W 0 0 PSR1 R/W 0 GTCCR
* Bit 7 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR0 and PSR1 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR0 and PSR1 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. * Bit 0 - PSR1: Prescaler Reset Timer/Counter1 When this bit is one, Timer/Counter1 prescaler will be reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.
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4.13 16-bit Timer/Counter1
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: 4.13.1 Features * * * * * * * * * * * * 4.13.2 Overview Many register and bit references in this section are written in general form. * A lower case "n" replaces the Timer/Counter number, in this case 1. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. * A lower case "x" replaces the Output Compare unit channel, in this case A or B. However, when using the register or bit defines in a program, the precise form must be used, i.e., OCR1A for accessing Timer/Counter1 output compare channel A value and so on. * A lower case "i" replaces the index of the Output Compare output pin, in this case U, V, W or X. However, when using the register or bit defines in a program, the precise form must be used. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 4-44. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "16-bit Timer/Counter Register Description" on page 157.
True 16-bit Design (i.e., Allows 16-bit PWM) Two independent Output Compare Units Four Controlled Output Pins per Output Compare Unit Double Buffered Output Compare Registers One Input Capture Unit Input Capture Noise Canceler Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator External Event Counter Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
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Figure 4-44. 16-bit Timer/Counter1 Block Diagram(1)
Count Clear Direction Control Logic TOVn (Int.Req.) clk Tn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn
=
=0
OCFnA (Int.Req.) Waveform Generation
=
OCRnA Fixed TOP Values
OCnAU
OCnAV
OCnAW
DATABUS
OCFnB (Int.Req.) Waveform Generation
OCnAX
=
OCRnB
OCnBU
OCnBV
OCnBW
OCnBX ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector Noise Canceler ICPn
ICRn
TCCRnA
TCCRnB
TCCRnC
Note:
1. Refer to Table 4-27 on page 105, and Table 4-24 on page 100 for Timer/Counter1 pin placement and description.
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4.13.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section "Accessing 16-bit Registers" on page 136. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkTn). The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins See "Output Compare Units" on page 142.. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (Section 4.19 "AnaComp - Analog Comparator" on page 236). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output. 4.13.2.2 Definitions The following definitions are used extensively throughout the section:
BOTTOM MAX The counter reaches the BOTTOM when it becomes 0x0000. The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65,535). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation.
TOP
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4.13.3
Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR(R) CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte.
4.13.3.1
Code Examples The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using "C", the compiler handles the 16-bit access.
Assembly Code Examples(1)
... ; Set TCNT1 to 0x01FF ldi ldi sts sts lds lds ... r17,0x01 r16,0xFF TCNT1H,r17 TCNT1L,r16 r16,TCNT1L r17,TCNT1H
; Read TCNT1 into r17:r16
C Code Examples(1)
unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: The example code assumes that the part specific header file is included
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The assembly code example returns the TCNT1 value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_ReadTCNT1: ; Save global interrupt flag in cli ; Read TCNT1 into r17:r16 lds lds out ret r16,TCNT1L r17,TCNT1H SREG,r18 r18,SREG ; Disable interrupts
; Restore global interrupt flag
C Code Example(1)
unsigned int TIM16_ReadTCNT1(void) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. The example code assumes that the part specific header file is included.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
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The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_WriteTCNT1: ; Save global interrupt flag in cli ; Set TCNT1 to r17:r16 sts sts out ret TCNT1H,r17 TCNT1L,r16 SREG,r18 r18,SREG ; Disable interrupts
; Restore global interrupt flag
C Code Example(1)
void TIM16_WriteTCNT1(unsigned int i) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; } Note: 1. The example code assumes that the part specific header file is included1
The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. 4.13.3.2 Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case.
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4.13.4 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see Section 4.12 "Timer/Counter1 Prescaler" on page 130. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 4-45 shows a block diagram of the counter and its surroundings. Figure 4-45. Counter Unit Block Diagram
DATA BUS
(8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) Clear Direction Control Logic clkTn Edge Detector Tn
4.13.5
TCNTn (16-bit Counter)
( From Prescaler ) TOP BOTTOM
Signal description (internal signals): Count Direction Clear clkT1 TOP BOTTOM Increment or decrement TCNT1 by 1. Select between increment and decrement. Clear TCNT1 (set all bits to zero). Timer/Counter clock. Signalize that TCNT1 has reached maximum value. Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
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The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1A/B. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 147. The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 4.13.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 4-46. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. Figure 4-46. Input Capture Unit Block Diagram
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit) WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
ICRn (16-bit Register)
TCNTn (16-bit Counter)
ACIC
ICNCn
ICESn
ICPn Noise Canceler ACO Analog Comparator Edge Detector ICF1n (Int.Req.)
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 flag can be cleared by software by writing a logical one to its I/O bit location.
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Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter's TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to "Accessing 16-bit Registers" on page 136. 4.13.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Only Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 4-42 on page 130). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP1 pin. 4.13.6.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. 4.13.6.3 Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.
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Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal's duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt handler is used). 4.13.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1A/B). If TCNT equals OCR1A/B the comparator signals a match. A match will set the Output Compare Flag (OCF1A/B) at the next timer clock cycle. If enabled (OCIE1A/B = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1A/B flag is automatically cleared when the interrupt is executed. Alternatively the OCF1A/B flag can be cleared by software by writing a logical one to its I/O bit locations. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1A/B1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See "Modes of Operation" on page 147.) A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 4-47 shows a block diagram of the Output Compare unit. The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded.
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Figure 4-47. Output Compare Unit, Block Diagram
DATA BUS
(8-bit)
TEMP (8-bit)
OCRnxH Buf.(8-bit)
OCRnxL Buf.(8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
OCRnx Buffer (16-bit Register)
TCNTn (16-bit Counter)
OCRnxH (8-bit)
OCRnxL (8-bit)
OCRnx (16-bit Register)
= (16-bit Comparator )
OCFnx TOP BOTTOM (Int.Req.)
OCnxU
Waveform Generator
OCnxV
WGMn3:0
COMnx1:0 OCnxW
OCnxX
The OCR1A/B Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1A/B Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1A/B Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1A/B Buffer Register, and if double buffering is disabled the CPU will access the OCR1A/B directly. The content of the OCR1A/B (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1A/B is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1A/B Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCR1A/BH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte (OCR1A/BL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1A/B buffer or OCR1A/B Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to "Accessing 16-bit Registers" on page 136.
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4.13.7.1
Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1A/B) bit. Forcing compare match will not set the OCF1A/B flag or reload/clear the timer, but the OC1A/Bi pins will be updated as if a real compare match had occurred (the COM1A/B1:0 bits settings define whether the OC1A/Bi pins are set, cleared or toggled - if the respective OCnxi bit is set). Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1A/B to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1A/B value, the compare match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting. The setup of the OC1A/B should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC1A/B value is to use the Force Output Compare (FOC1A/B) strobe bits in Normal mode. The OC1A/B Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1A/B1:0 bits are not double buffered together with the compare value. Changing the COM1A/B1:0 bits will take effect immediately.
4.13.7.2
4.13.7.3
4.13.8
Compare Match Output Unit The Compare Output mode (COM1A/B1:0) bits have two functions. The Waveform Generator uses the COM1A/B1:0 bits for defining the Output Compare (OC1A/B) state at the next compare match. Secondly the COM1A/B1:0 and OCnxi bits control the OC1A/Bi pin output source. Figure 4-49 shows a simplified schematic of the logic affected by the COM1A/B1:0 and OCnxi bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM1A/B1:0 and OCnxi bits are shown. When referring to the OC1A/B state, the reference is for the internal OC1A/B Register, not the OC1A/Bi pin. If a system reset occur, the OC1A/B Register is reset to "0".
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Figure 4-48. Compare Match Output
OC1AU(*)
1
PINB0 20 PB0 / OC1AU
0
PORTB0 OC1AV(*)
DDB0 PINB2
1
18 PB2 / OC1AV PORTB2 OC1AW(*)
1 0
DDB2 PINB4 14 PB4 / OC1AW
0
OCR1A 16-bit Register
PORTB4 COM1A0 COM1A1 OCF1A Waveform Generation FOC1A
Top Bottom
DDB4 PINB6
1
OC1AX(*)
= WGM10 WGM11 WGM12 WGM13
12 PB6 / OC1AX PORTB6
0
DDB6
Count Clear Direction
TCNT1 16-bit Counter
FOC1B Waveform Generation
OC1BU(*)
1
PINB1 19 PB1 / OC1BU
0
= OCF1B COM1B0 COM1B1
PORTB1 OC1BV(*)
DDB1 PINB3
1
OCR1B 16-bit Register
17 PB3 / OC1BV PORTB3 OC1BW(*)
1 0
DDB3 PINB5 13 PB5 / OC1BW
0
PORTB5 OC1BX(*)
DDB5 PINB7
1
(*) OC1xi: TCCR1D register bit
11 PB7 / OC1BX PORTB7
0
DDB7
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Figure 4-49. Compare Match Output Logic
OCnxi
COMnx1 COMnx0 FOCnx
Waveform Generator
D
Q
1 OCnxi Pin
OCnx D
DATA BUS
0
Q
PORT D Q
clk I/O
DDR
4.13.8.1
Compare Output Function The general I/O port function is overridden by the Output Compare (OC1A/B) from the Waveform Generator if either of the COM1A/B1:0 bits are set and if OCnxi respective bit is set in TCCR1D register. However, the OC1A/Bi pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1A/Bi pin (DDR_OC1A/Bi) must be set as output before the OC1A/B value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 4-35, Table 4-36 and Table 4-37 for details. The design of the Output Compare pin logic allows initialization of the OC1A/B state before the output is enabled. Note that some COM1A/B1:0 bit settings are reserved for certain modes of operation. See "16-bit Timer/Counter Register Description" on page 157. The COM1A/B1:0 bits have no effect on the Input Capture unit.
4.13.8.2
Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1A/B1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1A/B1:0 = 0 tells the Waveform Generator that no action on the OC1A/B Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 4-35 on page 157. For fast PWM mode refer to Table 4-36 on page 158, and for phase correct and phase and frequency correct PWM refer to Table 4-37 on page 158. A change of the COM1A/B1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1A/B strobe bits.
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4.13.9 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1A/B1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1A/B1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1A/B1:0 bits control whether the output should be set, cleared or toggle at a compare match (See "Compare Match Output Unit" on page 144.). The OCnxi bits over control the setting of the COM1A/B1:0 bits as shown in Figure 4-49 on page 146. For detailed timing information refer to "Timer/Counter Timing Diagrams" on page 155. 4.13.9.1 Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 4.13.9.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 4-50. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.
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Figure 4-50. CTC Mode, Timing Diagram
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnAi (Toggle) Period
1 2 3 4
(COMnA1:0 = 1)
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered. For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1) and OC1Ai is set. The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the following equation:
f clk_I/O f OCnA = -------------------------------------------------------2 x N x ( 1 + OCRnA )
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000.
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4.13.9.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1A/B) is set on the compare match between TCNT1 and OCR1A/B, and cleared at TOP. In inverting Compare Output mode output is cleared on compare match and set at TOP. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
log ( TOP + 1 ) R FPWM = ---------------------------------log ( 2 )
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 4-51. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1A/B and TCNT1. The OC1A/B interrupt flag will be set when a compare match occurs. Figure 4-51. Fast PWM Mode, Timing Diagram
OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnxi OCnxi
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
8
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The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1A/B. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1A/B Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1A/B pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1A/B1:0 to three (see Table 4-36 on page 158). The actual OC1A/B value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is generated by setting (or clearing) the OC1A/B Register at the compare match between OCR1A/B and TCNT1, and clearing (or setting) the OC1A/B Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation:
f clk_I/O f OCnxPWM = ------------------------------------N x ( 1 + TOP )
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1A/B Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1A/B is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1A/B equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1A/B1:0 bits.)
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A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 4.13.9.4 Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1A/B) is cleared on the compare match between TCNT1 and OCR1A/B while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
R PCPWM = log ( TOP + 1 ) ---------------------------------log ( 2 )
In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 4-52. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1A/B and TCNT1. The OC1A/B interrupt flag will be set when a compare match occurs.
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Figure 4-52. Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnxi OCnxi
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set accordingly at the same timer clock cycle as the OCR1A/B Registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1A/B. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1A/B Registers are written. As the third period shown in Figure 4-52 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1A/B Register. Since the OCR1A/B update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation.
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In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1A/B pins. Setting the COM1A/B1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1A/B1:0 to three (See Table on page 158). The actual OC1A/B value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is generated by setting (or clearing) the OC1A/B Register at the compare match between OCR1A/B and TCNT1 when the counter increments, and clearing (or setting) the OC1A/B Register at compare match between OCR1A/B and TCNT1 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation:
f clk_I/O f OCnxPCPWM = --------------------------------2 x N x TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1A/B Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1A/B is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 4.13.9.5 Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1A/B) is cleared on the compare match between TCNT1 and OCR1A/B while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1A/B Register is updated by the OCR1A/B Buffer Register, (see Figure 4-52 and Figure 4-53). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation:
R PFCPWM = log ( TOP + 1 ) ---------------------------------log ( 2 )
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In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 4-53. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1A/B and TCNT1. The OC1A/B interrupt flag will be set when a compare match occurs. Figure 4-53. Phase and Frequency Correct PWM Mode, Timing Diagram
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
OCRnx/TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnxi OCnxi
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1A/B Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1A/B. As Figure 4-53 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCR1A/B Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature.
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In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1A/B pins. Setting the COM1A/B1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1A/B1:0 to three (See Table on page 158). The actual OC1A/B value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is generated by setting (or clearing) the OC1A/B Register at the compare match between OCR1A/B and TCNT1 when the counter increments, and clearing (or setting) the OC1A/B Register at compare match between OCR1A/B and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation:
f clk_I/O f OCnxPFCPWM = --------------------------------2 x N x TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1A/B Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1A/B is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 4.13.10 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCR1A/B Register is updated with the OCR1A/B buffer value (only for modes utilizing double buffering). Figure 4-54 shows a timing diagram for the setting of OCF1A/B. Figure 4-54. Timer/Counter Timing Diagram, Setting of OCF1A/B, No Prescaling
clkI/O clkTn
(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
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Figure 4-55 shows the same timing data, but with the prescaler enabled. Figure 4-55. Timer/Counter Timing Diagram, Setting of OCF1A/B, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 4-56 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1A/B Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM. Figure 4-56. Timer/Counter Timing Diagram, no Prescaling
clkI/O clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
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Figure 4-57 shows the same timing data, but with the prescaler enabled. Figure 4-57. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clk I/O clk Tn
(clk /8) I/O
TCNTn
(CTC and FPWM)
TOP - 1 TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICF n (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
4.13.11 4.13.11.1
16-bit Timer/Counter Register Description Timer/Counter1 Control Register A - TCCR1A
Bit Read/Write Initial Value 7 COM1A1 R/W 0 6 COM1A0 R/W 0 5 COM1B1 R/W 0 4 COM1B0 R/W 0 3 - R 0 2 - R 0 1 WGM11 R/W 0 0 WGM10 TCCR1A R/W 0
* Bit 7:6 - COM1A1:0: Compare Output Mode for Channel A * Bit 5:4 - COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1Ai and OC1Bi respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1Ai output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1Bi output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit and OC1xi bit (TCCR1D) corresponding to the OC1Ai or OC1Bi pin must be set in order to enable the output driver. When the OC1Ai or OC1Bi is connected to the pin, the function of the COM1A/B1:0 bits is dependent of the WGM13:0 bits setting. Table 4-35 shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 4-35.
OC1Ai OC1Bi 0
Compare Output Mode, non-PWM
COM1A0 COM1B0 x Normal port operation, OC1A/OC1B disconnected. 0 0 0 1 0 1 Toggle OC1A/OC1B on Compare Match. Clear OC1A/OC1B on Compare Match (Set output to low level). Set OC1A/OC1B on Compare Match (Set output to high level). Description
COM1A1 COM1B1 x
1 1 1
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Table 4-36 shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Compare Output Mode, Fast PWM(1)
COM1A1 COM1B1 x 0 0 1 1 COM1A0 COM1B0 x 0 1 0 1 Description Normal port operation, OC1A/OC1B disconnected. WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. Clear OC1A/OC1B on Compare Match Set OC1A/OC1B at TOP Set OC1A/OC1B on Compare Match Clear OC1A/OC1B at TOP
Table 4-36.
OC1Ai OC1Bi 0 1 1 1 1 Note:
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See "Fast PWM Mode" on page 149. for more details.
Table 4-37 shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode.
Table 4-37.
OC1Ai OC1Bi 0 1 1 1 1 Note:
Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1)
COM1A1 COM1B1 x 0 0 1 1 COM1A0 COM1B0 x 0 1 0 1 Description Normal port operation, OC1A/OC1B disconnected. WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. Clear OC1A/OC1B on Compare Match when up-counting. Set OC1A/OC1B on Compare Match when downcounting. Set OC1A/OC1B on Compare Match when up-counting. Clear OC1A/OC1B on Compare Match when downcounting.
1. A special case occurs when OC1A/OC1B equals TOP and COM1A1/COM1B1 is set. See "Phase Correct PWM Mode" on page 151. for more details.
* Bit 3:2 - Reserved Bits These bits are reserved for future use. * Bit 1:0 - WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 4-38. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See "Modes of Operation" on page 147.).
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Table 4-38.
Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note:
Waveform Generation Mode Bit Description(1)
WGM12 (CTC1) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WGM11 (PWM11) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WGM10 Timer/Counter (PWM10) Mode of Operation 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Normal PWM, Phase Correct, 8-bit PWM, Phase Correct, 9-bit PWM, Phase Correct, 10-bit CTC Fast PWM, 8-bit Fast PWM, 9-bit Fast PWM, 10-bit PWM, Phase and Frequency Correct PWM, Phase and Frequency Correct PWM, Phase Correct PWM, Phase Correct CTC (Reserved) Fast PWM Fast PWM TOP 0xFFFF 0x00FF 0x01FF 0x03FF OCR1A 0x00FF 0x01FF 0x03FF ICR1 OCR1A ICR1 OCR1A ICR1 - ICR1 OCR1A Update of OCR1A/B at Immediate TOP TOP TOP Immediate TOP TOP TOP BOTTOM BOTTOM TOP TOP Immediate - TOP TOP TOV1 Flag Set on MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP TOP BOTTOM BOTTOM BOTTOM BOTTOM MAX - TOP TOP
WGM13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.
4.13.11.2
Timer/Counter1 Control Register B - TCCR1B
Bit Read/Write Initial Value 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 - R 0 4 WGM13 R/W 0 3 WGM12 R/W 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1B
* Bit 7 - ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. * Bit 6 - ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. 159
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* Bit 5 - Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. * Bit 4:3 - WGM13:2: Waveform Generation Mode See TCCR1A Register description. * Bit 2:0 - CS12:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 4-54 and Figure 4-55.
Table 4-39.
CS12 0 0 0 0 1 1 1 1
Clock Select Bit Description
CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 Description No clock source (Timer/Counter stopped). clkI/O/1 (No prescaling) clkI/O/8 (From prescaler) clkI/O/64 (From prescaler) clkI/O/256 (From prescaler) clkI/O/1024 (From prescaler) External clock source on T1 pin. Clock on falling edge. External clock source on T1 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 4.13.11.3 Timer/Counter1 Control Register C - TCCR1C
Bit Read/Write Initial Value 7 FOC1A R/W 0 6 FOC1B R/W 0 5 - R/W 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 TCCR1C
* Bit 7 - FOC1A: Force Output Compare for Channel A * Bit 6 - FOC1B: Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1nx output is changed according to its COM1A/B1:0 and OC1nx bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1A/B1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero.
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4.13.11.4 Timer/Counter1 Control Register D - TCCR1D
Bit Read/Write Initial Value 7 OC1BX
R/W
6 OC1BW
R/W
5 OC1BV
R/W
4 OC1BU
R/W
3 OC1AX
R/W
2 OC1AW
R/W
1 OC1AV
R/W
0 OC1AU TCCR1D
R/W
0
0
0
0
0
0
0
0
* Bit 7:4 - OC1Bi: Output Compare Pin Enable for Channel B The OC1Bi bits enable the Output Compare pins of Channel B as shown in Figure 4-49 on page 146. * Bit 3:0 - OC1Ai: Output Compare Pin Enable for Channel A The OC1Ai bits enable the Output Compare pins of Channel A as shown in Figure 4-49 on page 146. 4.13.11.5 Timer/Counter1 - TCNT1H and TCNT1L
Bit 7 6 5 4 3 TCNT1[15:8] TCNT1[7:0] R/W R/W 0 0 2 1 0 TCNT1H TCNT1L R/W 0 R/W 0 R/W 0
Read/Write Initial Value
R/W 0
R/W 0
R/W 0
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 136. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1A/B Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. 4.13.11.6 Output Compare Register A - OCR1AH and OCR1AL
Bit 7 6 5 4 3 OCR1A[15:8] OCR1A[7:0] R/W R/W 0 0 2 1 0 OCR1AH OCR1AL R/W 0 R/W 0 R/W 0
Read/Write Initial Value
R/W 0
R/W 0
R/W 0
4.13.11.7
Output Compare Register B - OCR1BH and OCR1BL
Bit 7 6 5 4 3 OCR1B[15:8] OCR1B[7:0] R/W R/W 0 0 2 1 0 OCR1BH OCR1BL R/W 0 R/W 0 R/W 0
Read/Write Initial Value
R/W 0
R/W 0
R/W 0
The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1A/B pin.
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The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 136. 4.13.11.8 Input Capture Register - ICR1H and ICR1L
Bit 7 6 5 4 3 ICR1[15:8] ICR1[7:0] R/W R/W 0 0 2 1 0 ICR1H ICR1L R/W 0 R/W 0 R/W 0
Read/Write Initial Value
R/W 0
R/W 0
R/W 0
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 136. 4.13.11.9 Timer/Counter1 Interrupt Mask Register - TIMSK1
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 ICIE1 R/W 0 4 - R 0 3 - R 0 2 OCIE1B R/W 0 1 OCIE1A R/W 0 0 TOIE1 R/W 0 TIMSK1
* Bit 7..6 - Reserved Bits These bits are reserved for future use. * Bit 5 - ICIE1: Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See "Innterrupt Vectors in Atmel ATtiny87/167" on page 82.) is executed when the ICF1 flag, located in TIFR1, is set. * Bit 4..3 - Reserved Bits These bits are reserved for future use. * Bit 2 - OCIE1B: Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See "Innterrupt Vectors in Atmel ATtiny87/167" on page 82.) is executed when the OCF1B flag, located in TIFR1, is set. * Bit 1 - OCIE1A: Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See "Innterrupt Vectors in Atmel ATtiny87/167" on page 82.) is executed when the OCF1A flag, located in TIFR1, is set.
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* Bit 0 - TOIE1: Timer/Counter Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See "Innterrupt Vectors in Atmel ATtiny87/167" on page 82.) is executed when the TOV1 flag, located in TIFR1, is set. 4.13.11.10 Timer/Counter1 Interrupt Flag Register - TIFR1
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 ICF1 R/W 0 4 - R 0 3 - R 0 2 OCF1B R/W 0 1 OCF1A R/W 0 0 TOV1 R/W 0 TIFR1
* Bit 7..6 - Reserved Bits These bits are reserved for future use. * Bit 5 - ICF1: Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. * Bit 4..3 - Reserved Bits These bits are reserved for future use. * Bit 2 - OCF1B: Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. * Bit 1 - OCF1A: Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. * Bit 0 - TOV1: Timer/Counter Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes, the TOV1 flag is set when the timer overflows. Refer to Table 4-38 on page 159 for the TOV1 flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
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4.14
SPI - Serial Peripheral Interface
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel(R) ATtiny87/167 and peripheral devices or between several AVR(R) devices. The Atmel ATtiny87/167 SPI includes the following features:
4.14.1
Features * * * * * * * *
Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode
Figure 4-58. SPI Block Diagram(1)
clk IO
DIVIDER /2/4/8/16/32/64/128
SPI2X
Note:
1. Refer to Table 4-24 on page 100 for SPI pin placement.
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The interconnection between Master and Slave CPUs with SPI is shown in Figure 4-59. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out - Slave In, MOSI, line, and from Slave to Master on the Master In - Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of transmission flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 4-59. SPI Master-slave Interconnection
SHIFT ENABLE
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed fclkio/4.
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 4-40. For more details on automatic port overrides, refer to Section 4.10.3 "Alternate Port Functions" on page 96. SPI Pin Overrides(1)
Direction, Master SPI User Defined Input User Defined User Defined Direction, Slave SPI Input User Defined Input Input
Table 4-40.
Pin MOSI MISO SCK SS Note:
1. See Section 4.10.3.4 "Alternate Functions of Port B" on page 105 for a detailed description of how to define the direction of the user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI with DDRB.
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Assembly Code Example(1)
SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi out ldi out ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait for transmission complete in sbrs rjmp ret r17,SPSR r17,SPIF Wait_Transmit r17,(1<; Enable SPI, Master, set clock rate fck/16
C Code Example(1)
void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<167
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
Assembly Code Example(1)
SPI_SlaveInit: ; Set MISO output, all others input ldi out ldi out ret SPI_SlaveReceive: ; Wait for reception complete sbis rjmp in ret SPSR,SPIF SPI_SlaveReceive r16,SPDR r17,(1<; Enable SPI
; Read received data and return
C Code Example(1)
void SPI_SlaveInit(void) { /* Set MISO output, all others input */ DDR_SPI = (1<168
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4.14.2 4.14.2.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 4.14.2.2 Master Mode When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the pin will be driving the SS pin of the SPI Slave. If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a Slave, the MOSI and SCK pins become inputs. 2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed. Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. 4.14.2.3 SPI Control Register - SPCR
Bit Read/Write Initial Value 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR
* Bit 7 - SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global Interrupt Enable bit in SREG is set. * Bit 6 - SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. * Bit 5 - DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first.
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* Bit 4 - MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. * Bit 3 - CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 4-60 and Figure 4-61 for an example. The CPOL functionality is summarized below:
Table 4-41.
CPOL Functionality
CPOL 0 1 Leading Edge Rising Falling Trailing Edge Falling Rising
* Bit 2 - CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 4-60 and Figure 4-61 for an example. The CPOL functionality is summarized below:
Table 4-42.
CPHA Functionality
CPHA 0 1 Leading Edge Sample Setup Trailing Edge Setup Sample
* Bits 1, 0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the clkIO frequency fclkio is shown in the following table:
Table 4-43.
SPI2X 0 0 0 0 1 1 1 1
Relationship Between SCK and the Oscillator Frequency
SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 SCK Frequency
fclkio/4 fclkio/16 fclkio/64 fclkio/128 fclkio/2 fclkio/8 fclkio/32 fclkio/64
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4.14.2.4 SPI Status Register - SPSR
Bit Read/Write Initial Value 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 SPI2X R/W 0 SPSR
* Bit 7 - SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR). * Bit 6 - WCOL: Write COLlision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. * Bit 5..1 - Res: Reserved Bits These bits are reserved bits in the Atmel(R) ATtiny87/167 and will always read as zero. * Bit 0 - SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 4-43). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fclkio/4 or lower. The SPI interface on the Atmel(R) ATtiny87/167 is also used for program memory and EEPROM downloading or uploading. See Section 4.22.8 "Serial Downloading" on page 262 for serial programming and verification. 4.14.2.5 SPI Data Register - SPDR
Bit Read/Write Initial Value 7 SPD7 R/W X 6 SPD6 R/W X 5 SPD5 R/W X 4 SPD4 R/W X 3 SPD3 R/W X 2 SPD2 R/W X 1 SPD1 R/W X 0 SPD0 R/W X SPDR Undefined
* Bits 7:0 - SPD7:0: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. 4.14.3 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 4-60 and Figure 4-61. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 4-41 and Table 4-42, as done below:
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Table 4-44.
CPOL Functionality
Leading Edge Trailing Edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) SPI Mode 0 1 2 3 Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling)
CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1
Figure 4-60. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
Figure 4-61. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) LSB first (DORD = 1)
MSB LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
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4.15
4.15.1
USI - Universal Serial Interface
Features * * * * * *
Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability
4.15.2
Overview The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. A simplified block diagram of the USI is shown on Figure 4-62. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "Register Descriptions" on page 181. Figure 4-62. Universal Serial Interface, Block Diagram
DQ LE
Bit7 Bit0 DO (Output only)
DI/SDA 3 2 1 0 TIM0 COMP
(Input/Open Drain)
USIDR
USIDB
3 2 1 0 [1] 0 1
CLOCK HOLD
DATA BUS
USIOIF
USISIF
USIDC
USIPF
4-bit Counter
USCK/SCL
(Input/Open Drain)
USISR
2
Two-wire Clock Control Unit
USIWM1
USIWM0
USICS1
USICS0
USICLK
USIOIE
USISIE
USICR
The 8-bit USI Data Register is directly accessible via the data bus and contains the incoming and outgoing data. The register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. The USI Data Register is a serial shift register and the most significant bit that is the output of the serial shift register is connected to one of two output pins depending of the wire mode configuration. A transparent latch is inserted between the USI Data Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration.
USITC
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The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows. 4.15.3 4.15.3.1 Functional Descriptions Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names used by this mode are: DI, DO, and USCK. Figure 4-63. Three-wire Mode Operation, Simplified Diagram
DO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DI
USCK SLAVE
DO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DI
USCK PORTxn MASTER
Figure 4-63 shows two USI units operating in Three-wire mode, one as Master and one as Slave. The two USI Data Register are interconnected in such way that after eight USCK clocks, the data in each register are interchanged. The same clock also increments the USI's 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR.
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Figure 4-64. Three-wire Mode, Timing Diagram
CYCLE USCK USCK DO DI
MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
( Reference )
1 2 3 4 5 6 7 8
A
B
C
D
E
The Three-wire mode timing is shown in Figure 4-64 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., samples data at negative and changes the output at positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1. Referring to the timing diagram (Figure 4-64), a bus transfer involves the following steps: 1. The Slave device and Master device sets up its data output and, depending on the protocol used, enables its output driver (mark A and B). The output is set up by writing the data to be transmitted to the USI Data Register. Enabling of the output is done by setting the corresponding bit in the port Data Direction Register. Note that point A and B does not have any specific order, but both must be at least one half USCK cycle before point C where the data is sampled. This must be done to ensure that the data setup requirement is satisfied. The 4-bit counter is reset to zero. 2. The Master generates a clock pulse by software toggling the USCK line twice (C and D). The bit value on the slave and master's data input (DI) pin is sampled by the USI on the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter will count both edges. 3. Step 2. is repeated eight times for a complete register (byte) transfer. 4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that the transfer is completed. The data bytes transferred must now be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor if it is set to Idle mode. Depending of the protocol used the slave device can now set its output to high impedance. 4.15.3.2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master:
SPITransfer: sts ldi sts ldi USIDR,r16 r16,(1<175
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SPITransfer_loop: sts lds sbrs rjmp lds ret USICR,r16 r16, USISR r16, USIOIF SPITransfer_loop r16,USIDR
The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRA or DDRB Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register. The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/4):
SPITransfer_Fast: sts ldi ldi sts sts sts sts sts sts sts sts sts sts sts sts sts sts sts sts lds ret USIDR,r16 r16,(1<176
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4.15.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave:
init: ldi sts ... SlaveSPITransfer: sts ldi sts lds sbrs rjmp lds ret USIDR,r16 r16,(1<SlaveSPITransfer_loop:
The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO is configured as output and USCK pin is configured as input in the DDR Register. The value stored in register r16 prior to the function is called is transferred to the master device, and when the transfer is completed the data received from the Master is stored back into the r16 Register. Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge USI Data Register clock. The loop is repeated until the USI Counter Overflow Flag is set. 4.15.3.4 Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA.
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Figure 4-65. Two-wire Mode Operation, Simplified Diagram
VCC
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SDA
SCL HOLD SCL Two-wire Clock Control Unit SLAVE
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SDA
SCL PORTxn MASTER
Figure 4-65 shows two USI units operating in Two-wire mode, one as Master and one as Slave. It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used. The main differences between the Master and Slave operation at this level, is the serial clock generation which is always done by the Master, and only the Slave uses the clock control unit. Clock generation must be implemented in software, but the shift operation is done automatically by both devices. Note that only clocking on negative edge for shifting data is of practical use in this mode. The slave can insert wait states at start or end of transfer by forcing the SCL clock low. This means that the Master must always check if the SCL line was actually released after it has generated a positive edge. Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The clock is generated by the master by toggling the USCK pin via the PORT Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow.
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Figure 4-66. Two-wire Mode, Typical Timing Diagram
SDA SCL
S 1-7 8 9 1-8 9 1-8 9 P
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
A
B
C
D
E
F
Referring to the timing diagram (Figure 4-66), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero. Note that the USI Data Register bit must be set to one for the output to be enabled. The slave device's start detector logic (Figure 4-67.) detects the start condition and sets the USISIF Flag. The flag can generate an interrupt if necessary. 2. In addition, the start detector will hold the SCL line low after the Master has forced an negative edge on this line (B). This allows the Slave to wake up from sleep or complete its other tasks before setting up the USI Data Register to receive the address. This is done by clearing the start condition flag and reset the counter. 3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave samples the data and shift it into the USI Data Register at the positive edge of the SCL clock. 4. After eight bits are transferred containing slave address and data direction (read or write), the Slave counter overflows and the SCL line is forced low (D). If the slave is not the one the Master has addressed, it releases the SCL line and waits for a new start condition. 5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle before holding the SCL line low again (i.e., the Counter Register must be set to 14 before releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables its output. If the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E). 6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the Master (F). Or a new start condition is given. If the Slave is not able to receive more data it does not acknowledge the data byte it has last received. When the Master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted. Figure 4-67. Start Condition Detector, Logic Diagram
USISIF CLOCK HOLD
DQ SDA
CLR
DQ
CLR
SCL Write( USISIF)
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4.15.3.5
Start Condition Detector The start condition detector is shown in Figure 4-67. The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode. The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time set by the CKSEL Fuses (see Section 4.5.1 "Clock Systems and their Distribution" on page 48) must also be taken into the consideration. Refer to the USISIF bit description on page 182 for further details.
4.15.4
Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design. Half-duplex Asynchronous Data Transfer By utilizing the USI Data Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only. 4-bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the counter is clocked externally, both clock edges will generate an increment.
4.15.4.1
4.15.4.2
4.15.4.3
12-bit Timer/Counter Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit counter. Edge Triggered External Interrupt By setting the counter to maximum value (F) it can function as an additional external interrupt. The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit. Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
4.15.4.4
4.15.4.5
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4.15.5 4.15.5.1 Register Descriptions USIDR - USI Data Register
Bit Read/Write Initial Value 7 USID7 R/W 0 6 USID6 R/W 0 5 USID5 R/W 0 4 USID4 R/W 0 3 USID3 R/W 0 2 USID2 R/W 0 1 USID1 R/W 0 0 USID0 R/W 0 USIDR
* Bits 7:0 - USID7..0: USI Data When accessing the USI Data Register (USIDR) the Serial Register can be accessed directly. If a serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed. A (left) shift operation is performed depending of the USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a Timer/Counter0 Compare Match, or directly by software using the USICLK strobe bit. Note that even when no wire mode is selected (USIWM1..0 = 0) both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register. The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent) during the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0). The output will be changed immediately when a new MSB written as long as the latch is open. The latch ensures that data input is sampled and data output is changed on opposite clock edges. Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the USI Data Register. 4.15.5.2 USIBR - USI Buffer Register
Bit Read/Write Initial Value 7 USIB7 R 0 6 USIB6 R 0 5 USIB5 R 0 4 USIB4 R 0 3 USIB3 R 0 2 USIB2 R 0 1 USIB1 R 0 0 USIB0 R 0 USIBR
* Bits 7:0 - USID7..0: USI Buffer The content of the Serial Register is loaded to the USI Buffer Register when the transfer is completed, and instead of accessing the USI Data Register (the Serial Register) the USI Data Buffer can be accessed when the CPU reads the received data. This gives the CPU time to handle other program tasks too as the controlling of the USI is not so timing critical. The USI flags as set same as when reading the USIDR register.
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4.15.5.3
USISR - USI Status Register The Status Register contains Interrupt Flags, line Status Flags and the counter value.
Bit Read/Write Initial Value 7 USISIF R/W 0 6 USIOIF R/W 0 5 USIPF R/W 0 4 USIDC R 0 3 USICNT3 R/W 0 2 1 0 USICNT2 USICNT1 USICNT0 USISR R/W R/W R/W 0 0 0
* Bit 7 - USISIF: Start Condition Interrupt Flag When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is detected. When output disable mode or Three-wire mode is selected and (USICSx = 11b & USICLK = 0) or (USICS = 10b & USICLK = 0), any edge on the SCK pin sets the flag. An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode. A start condition interrupt will wakeup the processor from all sleep modes. * Bit 6 - USIOIF: Counter Overflow Interrupt Flag This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in Two-wire mode. A counter overflow interrupt will wakeup the processor from Idle sleep mode. * Bit 5 - USIPF: Stop Condition Flag When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is useful when implementing Two-wire bus master arbitration. * Bit 4 - USIDC: Data Output Collision This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The flag is only valid when Two-wire mode is used. This signal is useful when implementing Two-wire bus master arbitration. * Bits 3:0 - USICNT3..0: Counter Value These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU. The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an external clock source (USICS1 = 1). Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input (USCK/SCL) are can still be used by the counter.
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4.15.5.4 USICR - USI Control Register
Bit Read/Write Initial Value 7 USISIE R/W 0 6 USIOIE R/W 0 5 USIWM1 R/W 0 4 USIWM0 R/W 0 3 USICS1 R/W 0 2 USICS0 R/W 0 1 USICLK W 0 0 USITC W 0
USICR
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe. * Bit 7 - USISIE: Start Condition Interrupt Enable Setting this bit to one enables the Start Condition detector interrupt. If there is a pending interrupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed. Refer to the USISIF bit description on page 182 for further details. * Bit 6 - USIOIE: Counter Overflow Interrupt Enable Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed. Refer to the USIOIF bit description on page 182 for further details. * Bit 5:4 - USIWM1:0: Wire Mode These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI Data Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations between USIWM1:0 and the USI operation is summarized in Table 4-45.
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Table 4-45.
0
Relations between USIWM1..0 and the USI Operation
0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit. The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port operation. When operating as master, clock pulses are software generated by toggling the PORT Register, while the data direction is set to output. The USITC bit in the USICR Register can be used for this purpose. Two-wire mode. Uses SDA (DI) and SCL (USCK) pins(1). The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and uses open-collector output drives. The output drivers are enabled by setting the corresponding bit for SDA and SCL in the DDR Register. When the output driver is enabled for the SDA pin, the output driver will force the line SDA low if the output of the USI Data Register or the corresponding bit in the PORT Register is zero. Otherwise the SDA line will not be driven (i.e., it is released). When the SCL pin output driver is enabled the SCL line will be forced low if the corresponding bit in the PORT Register is zero, or by the start detector. Otherwise the SCL line will not be driven. The SCL line is held low when a start detector detects a start condition and the output is enabled. Clearing the Start Condition Flag (USISIF) releases the line. The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on the SDA and SCL port pin are disabled in Two-wire mode. Two-wire mode. Uses SDA and SCL pins. Same operation as for the Two-wire mode described above, except that the SCL line is also held low when a counter overflow occurs, and is held low until the Counter Overflow Flag (USIOIF) is cleared.
USIWM1 USIWM0 Description
0
1
1
0
1
1
Note:
1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion between the modes of operation.
* Bit 3:2 - USICS1:0: Clock Source Select These bits set the clock source for the USI Data Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and therefore the output is changed immediately. Clearing the USICS1:0 bits enables software strobe option. When using this option, writing a one to the USICLK bit clocks both the USI Data Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clocking and software clocking by the USITC strobe bit. Table 4-46 on page 185 shows the relationship between the USICS1..0 and USICLK setting and clock source used for the USI Data Register and the 4-bit counter.
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Table 4-46.
USICS1 0 0 0 1 1 1 1
Relations between the USICS1..0 and USICLK Setting
USICS0 0 0 1 0 1 0 1 USICLK 0 1 X 0 0 1 1 USI Data Register Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, positive edge External, negative edge External, positive edge External, negative edge 4-bit Counter Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, both edges External, both edges Software clock strobe (USITC) Software clock strobe (USITC)
* Bit 1 - USICLK: Clock Strobe Writing a one to this bit location strobes the USI Data Register to shift one step and the counter to increment by one, provided that the USICS1..0 bits are set to zero and by doing so the software clock strobe option is selected. The output will change immediately when the clock strobe is executed, i.e., in the same instruction cycle. The value shifted into the USI Data Register is sampled the previous instruction cycle. The bit will be read as zero. When an external clock source is selected (USICS1 = 1), the USICLK function is changed from a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the USITC strobe bit as clock source for the 4-bit counter (see Table 4-46). * Bit 0 - USITC: Toggle Clock Port Pin Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0. The toggling is independent of the setting in the Data Direction Register, but if the PORT value is to be shown on the pin the DDB2 must be set as output (to one). This feature allows easy clock generation when implementing master devices. The bit will be read as zero. When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. 4.15.5.5 USIPP - USI Pin Position
Bit Read/Write Initial Value 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 USIPOS R/W 0 USIPP
* Bits 7:1 - Res: Reserved Bits These bits are reserved bits in the Atmel(R) ATtiny87/167 and always reads as zero. * Bit 0 - USIPOS: USI Pin Position Setting or clearing this bit changes the USI pin position.
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Table 4-47.
USIPOS 0
USI Pin Position
USI Pin Position DI, SDA PB0 - (PCINT8/OC1AU) PB1 - (PCINT9/OC1BU) PB2 - (PCINT10/OC1AV) PA4 - (PCINT4/ADC4/ICP1/MOSI) PA2 - (PCINT2/ADC2/OC0A/MISO) PA5 - (PCINT5/ADC5/T1/SCK) DO USCK, SCL DI, SDA
PortB (Default)
1
Port A DO (Alternate) USCK, SCL
4.16
LIN/UART - Local Interconnect Network Controller or UART
The LIN (Local Interconnect Network) is a serial communications protocol which efficiently supports the control of mechatronics nodes in distributed automotive applications. The main properties of the LIN bus are: * * * * * *
Single master with multiple slaves concept Low cost silicon implementation based on common UART/SCI interface Self synchronization with on-chip oscillator in slave node Deterministic signal transmission with signal propagation time computable in advance Low cost single-wire implementation Speed up to 20Kbit/s.
LIN provides a cost efficient bus communication where the bandwidth and versatility of CAN are not required. The specification of the line driver/receiver needs to match the ISO9141 NRZ-standard. If LIN is not required, the controller alternatively can be programmed as Universal Asynchronous serial Receiver and Transmitter (UART). 4.16.1 LIN Features * Hardware Implementation of LIN 2.1 (LIN 1.3 Compatibility) * Small, CPU Efficient and Independent Master/Slave Routines Based on "LIN Work Flow * * * * * * * 4.16.2 UART Features * * * * *
Full Duplex Operation (Independent Serial Receive and Transmit Processes) Asynchronous Operation High Resolution Baud Rate Generator Hardware Support of 8 Data Bits, Odd/Even/No Parity Bit, 1 Stop Bit Frames Data Over-Run and Framing Error Detection Concept" of LIN 2.1 Specification Automatic LIN Header Handling and Filtering of Irrelevant LIN Frames Automatic LIN Response Handling Extended LIN Error Detection and Signaling Hardware Frame Time-out Detection "Break-in-data" Support Capability Automatic Re-synchronization to Ensure Proper Frame Integrity Fully Flexible Extended Frames Support Capabilities
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4.16.3 4.16.3.1 LIN Protocol Master and Slave A LIN cluster consists of one master task and several slave tasks. A master node contains the master task as well as a slave task. All other nodes contain a slave task only. Figure 4-68. LIN Cluster with One Master Node and "n" Slave Nodes
master node
master task slave task
slave node 1
slave task
slave node n
slave task
LIN bus
The master task decides when and which frame shall be transferred on the bus. The slave tasks provide the data transported by each frame. Both the master task and the slave task are parts of the Frame handler 4.16.3.2 Frames A frame consists of a header (provided by the master task) and a response (provided by a slave task). The header consists of a BREAK and SYNC pattern followed by a PROTECTED IDENTIFIER. The identifier uniquely defines the purpose of the frame. The slave task appointed for providing the response associated with the identifier transmits it. The response consists of a DATA field and a CHECKSUM field. Figure 4-69. Master and Slave Tasks Behavior in LIN Frame
Master Task Slave Task 1 Slave Task 2 HEADER RESPONSE RESPONSE HEADER
The slave tasks waiting for the data associated with the identifier receives the response and uses the data transported after verifying the checksum. Figure 4-70. Structure of a LIN Frame
FRAME SLOT HEADER BREAK
Field
RESPONSE PROTECTED IDENTIFIER
Field Field
SYNC
DATA-0
Field
DATA-n
Field
CHECKSUM
Field
Break Delimiter
Response Space
Inter-Byte Space
Inter-Frame Space
Each byte field is transmitted as a serial byte, LSB first.
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Data Transport Two types of data may be transported in a frame; signals or diagnostic messages. * Signals Signals are scalar values or byte arrays that are packed into the data field of a frame. A signal is always present at the same position in the data field for all frames with the same identifier. * Diagnostic messages Diagnostic messages are transported in frames with two reserved identifiers. The interpretation of the data field depends on the data field itself as well as the state of the communicating nodes.
4.16.3.4
Schedule Table The master task (in the master node) transmits frame headers based on a schedule table. The schedule table specifies the identifiers for each header and the interval between the start of a frame and the start of the following frame. The master application may use different schedule tables and select among them. Compatibility with LIN 1.3 LIN 2.1 is a super-set of LIN 1.3. A LIN 2.1 master node can handle clusters consisting of both LIN 1.3 slaves and/or LIN 2.1 slaves. The master will then avoid requesting the new LIN 2.1 features from a LIN 1.3 slave: * Enhanced checksum, * Re-configuration and diagnostics, * Automatic baud rate detection, * "Response error" status monitoring. LIN 2.1 slave nodes can not operate with a LIN 1.3 master node (e.g. the LIN1.3 master does not support the enhanced checksum). The LIN 2.1 physical layer is backwards compatible with the LIN1.3 physical layer. But not the other way around. The LIN 2.1 physical layer sets greater requirements, i.e. a master node using the LIN 2.1 physical layer can operate in a LIN 1.3 cluster.
4.16.3.5
4.16.4
LIN/UART Controller The LIN/UART controller is divided in three main functions: * Tx LIN Header function, * Rx LIN Header function, * LIN Response function. These functions mainly use two services: * Rx service, * Tx service. Because these two services are basically UART services, the controller is also able to switch into an UART function.
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4.16.4.1 LIN Overview The LIN/UART controller is designed to match as closely as possible to the LIN software application structure. The LIN software application is developed as independent tasks, several slave tasks and one master task (c.f. Section 4.16.3.4 on page 188). The Atmel(R) ATtiny87/167 conforms to this perspective. The only link between the master task and the slave task will be at the cross-over point where the interrupt routine is called once a new identifier is available. Thus, in a master node, housing both master and slave task, the Tx LIN Header function will alert the slave task of an identifier presence. In the same way, in a slave node, the Rx LIN Header function will alert the slave task of an identifier presence. When the slave task is warned of an identifier presence, it has first to analyze it to know what to do with the response. Hardware flags identify the presence of one of the specific identifiers from 60 (0x3C) up to 63 (0x3F). For LIN communication, only four interrupts need to be managed: * LIDOK: New LIN identifier available, * LRXOK: LIN response received, * LTXOK: LIN response transmitted, * LERR: LIN Error(s). The wake-up management can be automated using the UART wake-up capability and a node sending a minimum of 5 low bits (0xF0) for LIN 2.1 and 8 low bits (0x80) for LIN 1.3. Pin change interrupt on LIN wake-up signal can be also used to exit the device of one of its sleep modes. Extended frame identifiers 62 (0x3E) and 63 (0x3F) are reserved to allow the embedding of user-defined message formats and future LIN formats. The byte transfer mode offered by the UART will ensure the upwards compatibility of LIN slaves with accommodation of the LIN protocol. 4.16.4.2 UART Overview The LIN/UART controller can also function as a conventional UART. By default, the UART operates as a full duplex controller. It has local loop back circuitry for test purposes. The UART has the ability to buffer one character for transmit and two for receive. The receive buffer is made of one 8-bit serial register followed by one 8-bit independent buffer register. Automatic flag management is implemented when the application puts or gets characters, thus reducing the software overhead. Because transmit and receive services are independent, the user can save one device pin when one of the two services is not used. The UART has an enhanced baud rate generator providing a maximum error of 2% whatever the clock frequency and the targeted baud rate.
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4.16.4.3
LIN/UART Controller Structure Figure 4-71. LIN/UART Controller Block Diagram
CLK IO Prescaler Sample /bit Finite State Machine BAUD_RATE FSM
RxD
Get Byte RX
Frame Time-out
Put Byte TX
TxD
Synchronization
Monitoring
Data FIFO
BUFFER
4.16.4.4
LIN/UART Command Overview Figure 4-72. LIN/UART Command Dependencies
Tx Response Tx Header IDOK TXOK Rx Response RXOK
Rx Header or LIN Abort
Automatic Return Recommended Way Possible Way
LIN DISABLE UART
Byte Transfer
Rx Byte
Full Duplex Tx Byte
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Table 4-48.
LENA 0 x
LIN/UART Command List
LCMD[1] x 0 0 1 LCMD[0] x 0 1 0 1 0 0 1 1 Command Disable peripheral Rx Header - LIN Abort Tx Header Rx Response Tx Response Byte transfer Rx Byte Tx Byte Full duplex no CRC, no Time out LTXDL=LRXDL=0 (LINDLR: read only register) LIN Withdrawal LCMD[2..0]=000 after Tx LCMD[2..0]=000 after Rx LCMD[2..0]=000 after Tx Comment
LCMD[2]
1 1
0 1 0 1
4.16.4.5
Enable/Disable Setting the LENA bit in LINCR register enables the LIN/UART controller. To disable the LIN/UART controller, LENA bit must be written to 0. No wait states are implemented, so, the disable command is taken into account immediately. LIN Commands Clearing the LCMD[2] bit in LINCR register enables LIN commands. As shown in Table 4-48 on page 191, four functions controlled by the LCMD[1..0] bits of LINCR register are available (c.f. Figure 4-72 on page 190). Rx Header/LIN Abort Function This function (or state) is mainly the withdrawal mode of the controller. When the controller has to execute a master task, this state is the start point before enabling a Tx Header command. When the controller has only to execute slave tasks, LIN header detection/acquisition is enabled as background function. At the end of such an acquisition (Rx Header function), automatically the appropriate flags are set, and in LIN 1.3, the LINDLR register is set with the uncoded length value. This state is also the start point before enabling the Tx or the Rx Response command. A running function (i.e. Tx Header, Tx or Rx Response) can be aborted by clearing LCMD[1..0] bits in LINCR register (See "Break-in-data" on page 201.). In this case, an abort flag LABORT - in LINERR register will be set to inform the other software tasks. No wait states are implemented, so, the abort command is taken into account immediately. Rx Header function is responsible for: * The BREAK field detection, * The hardware re-synchronization analyzing the SYNCH field, * The reception of the PROTECTED IDENTIFIER field, the parity control and the update of the LINDLR register in case of LIN 1.3, * The starting of the Frame_Time_Out, * The checking of the LIN communication integrity.
4.16.4.6
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Tx Header Function In accordance with the LIN protocol, only the master task must enable this function. The header is sent in the appropriate timed slots at the programmed baud rate (c.f. LINBRR & LINBTR registers). The controller is responsible for: * The transmission of the BREAK field - 13 dominant bits, * The transmission of the SYNCH field - character 0x55, * The transmission of the PROTECTED IDENTIFIER field. It is the full content of the LINIDR register (automatic check bits included). At the end of this transmission, the controller automatically returns to Rx Header / LIN Abort state (i.e. LCMD[1..0] = 00) after setting the appropriate flags. This function leaves the controller in the same setting as after the Rx Header function. This means that, in LIN 1.3, the LINDLR register is set with the uncoded length value at the end of the Tx Header function. During this function, the controller is also responsible for: * The starting of the Frame_Time_Out, * The checking of the LIN communication integrity. Rx and TX Response Functions These functions are initiated by the slave task of a LIN node. They must be used after sending an header (master task) or after receiving an header (considered as belonging to the slave task). When the TX Response order is sent, the transmission begins. A Rx Response order can be sent up to the reception of the last serial bit of the first byte (before the stop-bit). In LIN 1.3, the header slot configures the LINDLR register. In LIN 2.1, the user must configure the LINDLR register, either LRXDL[3..0] for Rx Response either LTXDL[3..0] for Tx Response. When the command starts, the controller checks the LIN13 bit of the LINCR register to apply the right rule for computing the checksum. Checksum calculation over the DATA bytes and the PROTECTED IDENTIFIER byte is called enhanced checksum and it is used for communication with LIN 2.1 slaves. Checksum calculation over the DATA bytes only is called classic checksum and it is used for communication with LIN 1.3 slaves. Note that identifiers 60 (0x3C) to 63 (0x3F) shall always use classic checksum. At the end of this reception or transmission, the controller automatically returns to Rx Header / LIN Abort state (i.e. LCMD[1..0] = 00) after setting the appropriate flags. If an LIN error occurs, the reception or the transmission is stopped, the appropriate flags are set and the LIN bus is left to recessive state. During these functions, the controller is responsible for: * The initialization of the checksum operator, * The transmission or the reception of `n' data with the update of the checksum calculation, * The transmission or the checking of the CHECKSUM field, * The checking of the Frame_Time_Out, * The checking of the LIN communication integrity.
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While the controller is sending or receiving a response, BREAK and SYNCH fields can be detected and the identifier of this new header will be recorded. Of course, specific errors on the previous response will be maintained with this identifier reception. Handling Data of LIN response A FIFO data buffer is used for data of the LIN response. After setting all parameters in the LINSEL register, repeated accesses to the LINDAT register perform data read or data write (c.f. "Data Management" on page 203). Note that LRXDL[3..0] and LTXDL[3..0] are not linked to the data access. 4.16.4.7 UART Commands Setting the LCMD[2] bit in LINENR register enables UART commands. Tx Byte and Rx Byte services are independent as shown in Table 4-48 on page 191. * Byte Transfer: the UART is selected but both Rx and Tx services are disabled, * Rx Byte: only the Rx service is enable but Tx service is disabled, * Tx Byte: only the Tx service is enable but Rx service is disabled, * Full Duplex: the UART is selected and both Rx and Tx services are enabled. This combination of services is controlled by the LCMD[1..0] bits of LINENR register (c.f. Figure 4-72 on page 190). Data Handling The FIFO used for LIN communication is disabled during UART accesses. LRXDL[3..0] and LTXDL[3..0] values of LINDLR register are then irrelevant. LINDAT register is then used as data register and LINSEL register is not relevant. Rx Service Once this service is enabled, the user is warned of an in-coming character by the LRXOK flag of LINSIR register. Reading LINDAT register automatically clears the flag and makes free the second stage of the buffer. If the user considers that the in-coming character is irrelevant without reading it, he directly can clear the flag (see specific flag management described in Section 4.16.6.2 on page 205). The intrinsic structure of the Rx service offers a 2-byte buffer. The fist one is used for serial to parallel conversion, the second one receives the result of the conversion. This second buffer byte is reached reading LINDAT register. If the 2-byte buffer is full, a new in-coming character will overwrite the second one already recorded. An OVRERR error in LINERR register will then accompany this character when read. A FERR error in LINERR register will be set in case of framing error. Tx Service If this service is enabled, the user sends a character by writing in LINDAT register. Automatically the LTXOK flag of LINSIR register is cleared. It will rise at the end of the serial transmission. If no new character has to be sent, LTXOK flag can be cleared separately (see specific flag management described in Section 4.16.6.2 on page 205). There is no transmit buffering. No error is detected by this service.
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4.16.5 4.16.5.1
LIN / UART Description Reset The AVR(R) core reset logic signal also resets the LIN/UART controller. Another form of reset exists, a software reset controlled by LSWRES bit in LINCR register. This self-reset bit performs a partial reset as shown in Table 4-49.
Table 4-49.
Reset of LIN/UART Registers
Name LINCR LINSIR LINENIR LINERR LINBTR LINBRRL LINBRRH LINDLR LINIDR LINSEL LINDAT Reset Value 0000 0000 b 0000 0000 b 0000 0000 b 0000 0000 b 0010 0000 b 0000 0000 b 0000 0000 b 0000 0000 b 1000 0000 b 0000 0000 b 0000 0000 b LSWRES Value 0000 0000 b 0000 0000 b xxxx 0000 b 0000 0000 b 0010 0000 b uuuu uuuu b xxxx uuuu b 0000 0000 b 1000 0000 b xxxx 0000 b 0000 0000 b u=unchanged x=unknown Comment
Register LIN Control Reg. LIN Status & Interrupt Reg. LIN Enable Interrupt Reg. LIN Error Reg. LIN Bit Timing Reg. LIN Baud Rate Reg. Low LIN Baud Rate Reg. High LIN Data Length Reg. LIN Identifier Reg. LIN Data Buffer Selection LIN Data
4.16.5.2
Clock The I/O clock signal (clki/o) also clocks the LIN/UART controller. It is its unique clock.
4.16.5.3
LIN Protocol Selection LIN13 bit in LINCR register is used to select the LIN protocol: * LIN13 = 0 (default): LIN 2.1 protocol, * LIN13 = 1: LIN 1.3 protocol. The controller checks the LIN13 bit in computing the checksum (enhanced checksum in LIN2.1 / classic checksum in LIN 1.3). This bit is irrelevant for UART commands.
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4.16.5.4 Configuration Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the controller in the following configuration (Table 4-50):
Table 4-50.
Mode
Configuration Table versus Mode
LCONF[1..0] 00 b 01 b 10 b 11 b 00 b 01 b 10 b 11 b Configuration LIN standard configuration (default) No CRC field detection or transmission Frame_Time_Out disable Listening mode 8-bit data, no parity & 1 stop-bit 8-bit data, even parity & 1 stop-bit 8-bit data, odd parity & 1 stop-bit Listening mode, 8-bit data, no parity & 1 stop-bit
LIN
UART
The LIN configuration is independent of the programmed LIN protocol. The listening mode connects the internal Tx LIN and the internal Rx LIN together. In this mode, the TXLIN output pin is disabled and the RXLIN input pin is always enabled. The same scheme is available in UART mode. Figure 4-73. Listening Mode
internal
Tx LIN LISTEN
internal
1 0
TXLIN
Rx LIN
RXLIN
4.16.5.5
Busy Signal LBUSY bit flag in LINSIR register is the image of the BUSY signal. It is set and cleared by hardware. It signals that the controller is busy with LIN or UART communication. Busy Signal in LIN Mode
Figure 4-74. Busy Signal in LIN Mode
FRAME SLOT HEADER BREAK
Field
RESPONSE PROTECTED IDENTIFIER
Field Field
LIN bus 1) LBUSY 2) LBUSY 3) LBUSY
SYNC Node providing the master task
DATA-0
Field
DATA-n
Field
CHECKSUM
Field
Node providing a slave task Node providing neither the master task, neither a slave task LCMD=Tx Header LIDOK LCMD=Tx or Rx Response LTXOK or LRXOK
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When the busy signal is set, some registers are locked, user writing is not allowed: * "LIN Control Register" - LINCR - except LCMD[2..0], LENA & LSWRES, * "LIN Baud Rate Registers" - LINBRRL & LINBRRH, * "LIN Data Length Register" - LINDLR, * "LIN Identifier Register" - LINIDR, * "LIN Data Register" - LINDAT. If the busy signal is set, the only available commands are: * LCMD[1..0] = 00 b, the abort command is taken into account at the end of the byte, * LENA = 0 and/or LCMD[2] = 0, the kill command is taken into account immediately, * LSWRES = 1, the reset command is taken into account immediately. Note that, if another command is entered during busy signal, the new command is not validated and the LOVRERR bit flag of the LINERR register is set. The on-going transfer is not interrupted. Busy Signal in UART Mode During the byte transmission, the busy signal is set. This locks some registers from being written: * "LIN Control Register" - LINCR - except LCMD[2..0], LENA & LSWRES, * "LIN Data Register" - LINDAT. The busy signal is not generated during a byte reception. 4.16.5.6 Bit Timing Baud rate Generator The baud rate is defined to be the transfer rate in bits per second (bps): * BAUD: Baud rate (in bps), * fclki/o: System I/O clock frequency, * LDIV[11..0]: Contents of LINBRRH & LINBRRL registers - (0-4095), the pre-scaler receives clki/o as input clock. * LBT[5..0]: Least significant bits of - LINBTR register- (0-63) is the number of samplings in a LIN or UART bit (default value 32). Equation for calculating baud rate: BAUD = fclki/o / LBT[5..0] x (LDIV[11..0] + 1) Equation for setting LINDIV value: LDIV[11..0] = ( fclki/o / LBT[5..0] x BAUD ) - 1 Note that in reception a majority vote on three samplings is made.
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Re-synchronization in LIN Mode When waiting for Rx Header, LBT[5..0] = 32 in LINBTR register. The re-synchronization begins when the BREAK is detected. If the BREAK size is not in the range (10.5 bits min., 28 bits max. -- 13 bits nominal), the BREAK is refused. The re-synchronization is done by adjusting LBT[5..0] value to the SYNCH field of the received header (0x55). Then the PROTECTED IDENTIFIER is sampled using the new value of LBT[5..0]. The re-synchronization implemented in the controller tolerates a clock deviation of 20% and adjusts the baud rate in a 2% range. The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be reset to 32 for the next header. The LINBTR register can be used to (software) re-calibrate the clock oscillator. The re-synchronization is not performed if the LIN node is enabled as a master. Handling LBT[5..0] LDISR bit of LINBTR register is used to: * Disable the re-synchronization (for instance in the case of LIN MASTER node), * To enable the setting of LBT[5..0] (to manually adjust the baud rate especially in the case of UART mode). A minimum of 8 is required for LBT[5..0] due to the sampling operation. Note that the LENA bit of LINCR register is important for this handling (see Figure 4-75 on page 197). Figure 4-75. Handling LBT[5..0]
Write in LINBTR register LENA ?
=1
(LINCR bit 4)
=0
LDISR
to write =0
=1
LBT[5..0] = LBT[5..0] to write
(LBT[5..0]min=8)
LBT[5..0] forced to 0x20 LDISR forced to 0 Enable re-synch. in LIN mode
LDISR forced to 1 Disable re-synch. in LIN mode
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4.16.5.7
Data Length Section 4.16.4.6 "LIN Commands" on page 191 describes how to set or how are automatically set the LRXDL[3..0] or LTXDL[3..0] fields of LINDLR register before receiving or transmitting a response. In the case of Tx Response the LRXDL[3..0] will be used by the hardware to count the number of bytes already successfully sent. In the case of Rx Response the LTXDL[3..0] will be used by the hardware to count the number of bytes already successfully received. If an error occurs, this information is useful to the programmer to recover the LIN messages. Data Length in LIN 2.1 * If LTXDL[3..0]=0 only the CHECKSUM will be sent, * If LRXDL[3..0]=0 the first byte received will be interpreted as the CHECKSUM, * If LTXDL[3..0] or LRXDL[3..0] >8, values will be forced to 8 after the command setting and before sending or receiving of the first byte. Data Length in LIN 1.3 * LRXDL and LTXDL fields are both hardware updated before setting LIDOK by decoding the data length code contained in the received PROTECTED IDENTIFIER (LRXDL = LTXDL). * Via the above mechanism, a length of 0 or >8 is not possible. Data Length in Rx Response
Figure 4-76. LIN2.1 - Rx Response - No Error
LIDOK
1st Byte 2 nd Byte 3 rd Byte 4 th Byte
LRXOK DATA-0 4 ? 0 1 2 3 4 DATA-1 DATA-2 DATA-3 CHECKSUM
LIN bus LRXDL (*) LTXDL (*) LBUSY
LCMD=Rx Response LINDLR=0x?4 (*) : LRXDL & LTXDL updated by user
LCMD2..0=000b
* The user initializes LRXDL field before setting the Rx Response command, * After setting the Rx Response command, LTXDL is reset by hardware, * LRXDL field will remain unchanged during Rx (during busy signal), * LTXDL field will count the number of received bytes (during busy signal), * If an error occurs, Rx stops, the corresponding error flag is set and LTXDL will give the number of received bytes without error, * If no error occurs, LRXOK is set after the reception of the CHECKSUM, LRXDL will be unchanged (and LTXDL = LRXDL).
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Data Length in Tx Response Figure 4-77. LIN1.3 - Tx Response - No Error
LIDOK
1st Byte 2 nd Byte 3 rd Byte 4 th Byte
LTXOK DATA-0 DATA-1 1 DATA-2 2 DATA-3 3 CHECKSUM 4
LIN bus LRXDL (*) LTXDL (*) LBUSY 4 4
0
LCMD2..0=000b LCMD=Tx Response (*) : LRXDL & LTXDL updated by Rx Response or Tx Response task
* The user initializes LTXDL field before setting the Tx Response command, * After setting the Tx Response command, LRXDL is reset by hardware, * LTXDL will remain unchanged during Tx (during busy signal), * LRXDL will count the number of transmitted bytes (during busy signal), * If an error occurs, Tx stops, the corresponding error flag is set and LRXDL will give the number of transmitted bytes without error, * If no error occurs, LTXOK is set after the transmission of the CHECKSUM, LTXDL will be unchanged (and LRXDL = LTXDL). Data Length after Error Figure 4-78. Tx Response - Error
LERR
1st Byte 2 nd Byte 3 rd Byte
LIN bus LRXDL LTXDL LBUSY 4 4
DATA-0 0
DATA-1 1
DATA-2
ERROR
2
LCMD2..0=000b LCMD=Tx Response
Note:
Information on response (ex: error on byte) is only available at the end of the serialization/de-serialization of the byte.
Data Length in UART Mode * The UART mode forces LRXDL and LTXDL to 0 and disables the writing in LINDLR register, * Note that after reset, LRXDL and LTXDL are also forced to 0.
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4.16.5.8
xxOK Flags There are three xxOK flags in LINSIR register: * LIDOK: LIN IDentifier OK It is set at the end of the header, either by the Tx Header function or by the Rx Header. In LIN 1.3, before generating LIDOK, the controller updates the LRXDL & LTXDL fields in LINDLR register. It is not driven in UART mode. * LRXOK: LIN RX response complete It is set at the end of the response by the Rx Response function in LIN mode and once a character is received in UART mode. * LTXOK: LIN TX response complete It is set at the end of the response by the Tx Response function in LIN mode and once a character has been sent in UART mode. These flags can generate interrupts if the corresponding enable interrupt bit is set in the LINENIR register (see Section 4.16.5.13 "Interrupts" on page 202).
4.16.5.9
xxERR Flags LERR bit of the LINSIR register is an logical `OR' of all the bits of LINERR register (see Section 4.16.5.13 "Interrupts" on page 202). There are eight flags: * LBERR = LIN Bit ERRor. A unit that is sending a bit on the bus also monitors the bus. A LIN bit error will be flagged when the bit value that is monitored is different from the bit value that is sent. After detection of a LIN bit error the transmission is aborted. * LCERR = LIN Checksum ERRor. A LIN checksum error will be flagged if the inverted modulo-256 sum of all received data bytes (and the protected identifier in LIN 2.1) added to the checksum does not result in 0xFF. * LPERR = LIN Parity ERRor (identifier). A LIN parity error in the IDENTIFIER field will be flagged if the value of the parity bits does not match with the identifier value. (See LP[1:0] bits in Section 4.16.6.8 "LIN Identifier Register - LINIDR" on page 209). A LIN slave application does not distinguish between corrupted parity bits and a corrupted identifier. The hardware does not undertake any correction. However, the LIN slave application has to solve this as: - known identifier (parity bits corrupted), - or corrupted identifier to be ignored, - or new identifier. * LSERR = LIN Synchronization ERRor. A LIN synchronization error will be flagged if a slave detects the edges of the SYNCH field outside the given tolerance. * LFERR = LIN Framing ERRor. A framing error will be flagged if dominant STOP bit is sampled. Same function in UART mode. * LTOERR = LIN Time Out ERRor. A time-out error will be flagged if the MESSAGE frame is not fully completed within the maximum length T Frame_Maximum by any slave task upon transmission of the SYNCH and IDENTIFIER fields (see Section 4.16.5.10 "Frame Time Out" on page 201).
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* LOVERR = LIN OVerrun ERRor. Overrun error will be flagged if a new command (other than LIN Abort) is entered while `Busy signal' is present. In UART mode, an overrun error will be flagged if a received byte overwrites the byte stored in the serial input buffer. * LABORT LIN abort transfer reflects a previous LIN Abort command (LCMD[2..0] = 000) while `Busy signal' is present. After each LIN error, the LIN controller stops its previous activity and returns to its withdrawal mode (LCMD[2..0] = 000 b) as illustrated in Figure 4-78 on page 199. Writing 1 in LERR of LINSIR register resets LERR bit and all the bits of the LINERR register. 4.16.5.10 Frame Time Out According to the LIN protocol, a frame time-out error is flagged if: T Frame > T Frame_Maximum. This feature is implemented in the LIN/UART controller.
Figure 4-79. LIN Timing and Frame Time-out
T Frame T Header
BREAK
Field
T Response
PROTECTED IDENTIFIER
Field Field Nominal
SYNC
DATA-0
Field
DATA-n
Field
CHECKSUM
Field
T Header_Nominal T Response_Nominal T Frame_Nominal
= = =
34 x
T Bit
+
10 ( Number_of_Data + 1 ) x
T Header_Nominal
T Bit T Response_Nominal
Maximun
before Time-out
T Header_Maximum T Response_Maximum T Frame_Maximum
4.16.5.11 Break-in-data
= = =
T Header_Nominal 1.4 x T Response_Nominal T Header_Maximum + T Response_Maximum
1.4 x
According to the LIN protocol, the LIN/UART controller can detect the BREAK/SYNC field sequence even if the break is partially superimposed with a byte of the response. When a BREAK/SYNC field sequence happens, the transfer in progress is aborted and the processing of the new frame starts. * On slave node(s), an error is generated (i.e. LBERR in case of Tx Response or LFERR in case of Rx Response). Information on data error is also available, refer to the Section "Data Length after Error" on page 199. * On master node, the user (code) is responsible for this aborting of frame. To do this, the master task has first to abort the on-going communication (clearing LCMD bits - LIN Abort command) and then to apply the Tx Header command. In this case, the abort error flag LABORT - is set. On the slave node, the BREAK detection is processed with the synchronization setting available when the LIN/UART controller processed the (aborted) response. But the re-synchronization restarts as usual. Due to a possible difference of timing reference between the BREAK field and the rest of the frame, the time-out values can be slightly inaccurate.
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4.16.5.12
Checksum The last field of a frame is the checksum. In LIN 2.1, the checksum contains the inverted eight bit sum with carry over all data bytes and the protected identifier. This calculation is called enhanced checksum.
n n unsigned char DATA + PROTECTED ID + unsigned char DATA + PROTECTED ID 8 CHECKSUM = 255 - n n 0 0
In LIN 1.3, the checksum contains the inverted eight bit sum with carry over all data bytes. This calculation is called classic checksum.
n n CHECKSUM = 255 - unsigned char DATA n + unsigned char DATA n 8 0 0
Frame identifiers 60 (0x3C) to 61 (0x3D) shall always use classic checksum. 4.16.5.13 Interrupts As shown in Figure 4-80 on page 202, the four communication flags of the LINSIR register are combined to drive two interrupts. Each of these flags have their respective enable interrupt bit in LINENIR register. (see Section 4.16.5.8 "xxOK Flags" on page 200 and Section 4.16.5.9 "xxERR Flags" on page 200). Figure 4-80. LIN Interrupt Mapping
LINERR.7 LABORT LINERR.6 LTOERR LINERR.5 LOVERR LINERR.4 LFERR LINERR.3 LSERR LINERR.2 LPERR LINERR.1 LCERR LINERR.0 LBERR LINSIR.2 LIDOK LINSIR.1 LTXOK LINSIR.0 LRXOK LENERR LENIDOK LENTXOK LENRXOK LINENIR.3 LINENIR.2 LINENIR.1 LINENIR.0 LINSIR.3 LERR
LIN ERR
LIN TC
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4.16.5.14 Message Filtering Message filtering based upon the whole identifier is not implemented. Only a status for frame headers having 0x3C, 0x3D, 0x3E and 0x3F as identifier is available in the LINSIR register.
Table 4-51.
Frame Status
LIDST[2..0] 0xx b 100 b 101 b 110 b 111 b Frame Status No specific identifier 60 (0x3C) identifier 61 (0x3D) identifier 62 (0x3E) identifier 63 (0x3F) identifier
The LIN protocol says that a message with an identifier from 60 (0x3C) up to 63 (0x3F) uses a classic checksum (sum over the data bytes only). Software will be responsible for switching correctly the LIN13 bit to provide/check this expected checksum (the insertion of the ID field in the computation of the CRC is set - or not - just after entering the Rx or Tx Response command). 4.16.5.15 Data Management LIN FIFO Data Buffer To preserve register allocation, the LIN data buffer is seen as a FIFO (with address pointer accessible). This FIFO is accessed via the LINDX[2..0] field of LINSEL register through the LINDAT register. LINDX[2..0], the data index, is the address pointer to the required data byte. The data byte can be read or written. The data index is automatically incremented after each LINDAT access if the LAINC (active low) bit is cleared. A roll-over is implemented, after data index = 7 it is data index=0. Otherwise, if LAINC bit is set, the data index needs to be written (updated) before each LINDAT access. The first byte of a LIN frame is stored at the data index=0, the second one at the data index=1, and so on. Nevertheless, LINSEL must be initialized by the user before use. UART Data Register The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will be for data out and in read access, LINDAT will be for data in. In UART mode the LINSEL register is unused.
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4.16.5.16
OCD Support When a debugger break occurs, the state machine of the LIN/UART controller is stopped (included frame time-out) and further communication may be corrupted.
4.16.6
LIN / UART Register Description Table 4-52.
Name LINCR LINSIR LINENIR LINERR LINBTR LINBRRL LINBRRH LINDLR LINIDR LINSEL LINDAT 0 0 0 0 0 0 0 0 1 0 0
LIN/UART Register Bits Summary
Bit 7 Bit 6 LIN13 0 0 0 0 0 0 0 0 0 0 0 R/W R -- R R R LDIV6 R/W -- R R/W LP0 R -- R R/W 0 0 LDATA6 0 0 0 LTXDL2 0 0 0 LTOERR LIDST1 0 0 Bit 5 LCONF1 R/W R -- R R LBT5 1 R/(W) LDIV5 R/W -- R R/W R/W -- R R/W 0 0 LDATA5 0 0 0 LTXDL1 0 0 0 LOVERR LIDST0 0 0 Bit 4 LCONF0 R/W R -- R R LBT4 LDIV4 R/W -- R R/W R/W -- R R/W 0 0 LDATA4 LTXDL0 0 0 0 0 LFERR 0 LBUSY Bit 3 LENA R/W LERR 0 R/Wone 0 0 R/W R LBT3 LDIV3 R/W R/W R/W LID3 R/W LAINC R/W R/W LDATA3 0 0 0 0 0 0 LDIV11 LRXDL3 0 Bit 2 LCMD2 R/W LIDOK 0 Bit 1 LCMD1 R/W LTXOK 0 Bit 0 LCMD0 R/W LRXOK
LSWRES R/W R -- R R LDISR R/W LDIV7 R/W -- R R/W LP1 R -- R R/W LDATA7 LTXDL3 LABORT LIDST2
0 R/Wone 0 R/Wone 0 R/Wone 0 0 R/W R LBT2 0 R/(W) LDIV2 R/W R/W R/W LID2 R/W R/W R/W 0 0 0 LINDX2 LDATA2 0 0 0 LDIV10 LRXDL2 0 0 R/W R LBT1 LDIV1 R/W LDIV9 R/W R/W LID1 R/W R/W R/W 0 0 0 LINDX1 LDATA1 0 0 LRXDL1 0 0 0 R/W R LBT0 LDIV0 R/W LDIV8 R/W R/W LID0 R/W R/W R/W LINDX0 LDATA0 LRXDL0
LENERR LENIDOK LENTXOK LENRXOK LSERR LPERR LCERR LBERR
0 R/(W) 0 R/(W)
0 R/(W) 0 R/(W)
LID5/LDL1 LID4/LDL0
4.16.6.1
LIN Control Register - LINCR
Bit Read/Write Initial Value 7 LSWRES R/W 0 6 LIN13 R/W 0 5 LCONF1 R/W 0 4 LCONF0 R/W 0 3 LENA R/W 0 2 LCMD2 R/W 0 1 LCMD1 R/W 0 0 LCMD0 R/W 0
LINCR
* Bit 7 - LSWRES: Software Reset - 0 = No action, - 1 = Software reset (this bit is self-reset at the end of the reset procedure). * Bit 6 - LIN13: LIN 1.3 mode - 0 = LIN 2.1 (default), - 1 = LIN 1.3.
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* Bit 5:4 - LCONF[1:0]: Configuration a. LIN mode (default = 00): - 00 = LIN Standard configuration (listen mode "off", CRC "on" & Frame_Time_Out "on", - 01 = No CRC, No Frame_Time_Out (listen mode "off"), - 10 = No Frame_Time_Out (listen mode "off" & CRC "on"), - 11 = Listening mode (CRC "on" & Frame_Time_Out "on"). b. UART mode (default = 00): - 00 = 8-bit, no parity (listen mode "off"), - 01 = 8-bit, even parity (listen mode "off"), - 10 = 8-bit, odd parity (listen mode "off"), - 11 = Listening mode, 8-bit, no parity. * Bit 3 - LENA: Enable - 0 = Disable (both LIN and UART modes), - 1 = Enable (both LIN and UART modes). * Bit 2:0 - LCMD[2..0]: Command and mode The command is only available if LENA is set. - 000 = LIN Rx Header - LIN abort, - 001 = LIN Tx Header, - 010 = LIN Rx Response, - 011 = LIN Tx Response, - 100 = UART Rx & Tx Byte disable, - 11x = UART Rx Byte enable, - 1x1 = UART Tx Byte enable. 4.16.6.2 LIN Status and Interrupt Register - LINSIR
Bit Read/Write Initial Value 7 LIDST2 R 0 6 LIDST1 R 0 5 LIDST0 R 0 4 LBUSY R 0 3 LERR R/Wone 0 2 LIDOK R/Wone 0 1 LTXOK R/Wone 0 0 LRXOK LINSIR R/Wone 0
* Bits 7:5 - LIDST[2:0]: Identifier Status - 0xx = no specific identifier, - 100 = Identifier 60 (0x3C), - 101 = Identifier 61 (0x3D), - 110 = Identifier 62 (0x3E), - 111 = Identifier 63 (0x3F). * Bit 4 - LBUSY: Busy Signal - 0 = Not busy, - 1 = Busy (receiving or transmitting).
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* Bit 3 - LERR: Error Interrupt It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective enable bit - LENERR - is set in LINENIR. - 0 = No error, - 1 = An error has occurred. The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also resets all LINERR bits. In UART mode, this bit is also cleared by reading LINDAT. * Bit 2 - LIDOK: Identifier Interrupt This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR. - 0 = No identifier, - 1 = Slave task: Identifier present, master task: Tx Header complete. The user clears this bit by writing 1, in order to reset this interrupt. * Bit 1 - LTXOK: Transmit Performed Interrupt This bit generates an interrupt if its respective enable bit - LENTXOK - is set in LINENIR. - 0 = No Tx, - 1 = Tx Response complete. The user clears this bit by writing 1, in order to reset this interrupt. In UART mode, this bit is also cleared by writing LINDAT. * Bit 0 - LRXOK: Receive Performed Interrupt This bit generates an interrupt if its respective enable bit - LENRXOK - is set in LINENIR. - 0 = No Rx - 1 = Rx Response complete. The user clears this bit by writing 1, in order to reset this interrupt. In UART mode, this bit is also cleared by reading LINDAT. 4.16.6.3 LIN Enable Interrupt Register - LINENIR
Bit Read/Write Initial Value 7 R 0 6 R 0 5 R 0 4 R 0 3 LENERR R/W 0 2 1 0 LENIDOK LENTXOK LENRXOK LINENIR R/W R/W R/W 0 0 0
* Bits 7:4 - Reserved Bits - These bits are reserved for future use. For compatibility with future devices, they must be written to zero when LINENIR is written. * Bit 3 - LENERR: Enable Error Interrupt - 0 = Error interrupt masked, - 1 = Error interrupt enabled.
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* Bit 2 - LENIDOK: Enable Identifier Interrupt - 0 = Identifier interrupt masked, - 1 = Identifier interrupt enabled. * Bit 1 - LENTXOK: Enable Transmit Performed Interrupt - 0 = Transmit performed interrupt masked, - 1 = Transmit performed interrupt enabled. * Bit 0 - LENRXOK: Enable Receive Performed Interrupt - 0 = Receive performed interrupt masked, - 1 = Receive performed interrupt enabled. 4.16.6.4 LIN Error Register - LINERR
Bit Read/Write Initial Value 7 6 5 LABORT LTOERR LOVERR R R R 0 0 0 4 LFERR R 0 3 LSERR R 0 2 LPERR R 0 1 LCERR R 0 0 LBERR R 0
LINERR
* Bit 7 - LABORT: Abort Flag - 0 = No warning, - 1 = LIN abort command occurred. This bit is cleared when LERR bit in LINSIR is cleared. * Bit 6 - LTOERR: Frame_Time_Out Error Flag - 0 = No error, - 1 = Frame_Time_Out error. This bit is cleared when LERR bit in LINSIR is cleared. * Bit 5 - LOVERR: Overrun Error Flag - 0 = No error, - 1 = Overrun error. This bit is cleared when LERR bit in LINSIR is cleared. * Bit 4 - LFERR: Framing Error Flag - 0 = No error, - 1 = Framing error. This bit is cleared when LERR bit in LINSIR is cleared. * Bit 3 - LSERR: Synchronization Error Flag - 0 = No error, - 1 = Synchronization error. This bit is cleared when LERR bit in LINSIR is cleared.
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* Bit 2 - LPERR: Parity Error Flag - 0 = No error, - 1 = Parity error. This bit is cleared when LERR bit in LINSIR is cleared. * Bit 1 - LCERR: Checksum Error Flag - 0 = No error, - 1 = Checksum error. This bit is cleared when LERR bit in LINSIR is cleared. * Bit 0 - LBERR: Bit Error Flag - 0 = no error, - 1 = Bit error. This bit is cleared when LERR bit in LINSIR is cleared. 4.16.6.5 LIN Bit Timing Register - LINBTR
Bit Read/Write Initial Value 7 LDISR R/W 0 6 R 0 5 LBT5 R/(W) 1 4 LBT4 R/(W) 0 3 LBT3 R/(W) 0 2 LBT2 R/(W) 0 1 LBT1 R/(W) 0 0 LBT0 R/(W) 0
LINBTR
* Bit 7 - LDISR: Disable Bit Timing Re synchronization - 0 = Bit timing re-synchronization enabled (default), - 1 = Bit timing re-synchronization disabled. * Bits 5:0 - LBT[5:0]: LIN Bit Timing Gives the number of samples of a bit. sample-time = (1 / fclki/o ) x (LDIV[11..0] + 1) Default value: LBT[6:0]=32 -- Min. value: LBT[6:0]=8 -- Max. value: LBT[6:0]=63 4.16.6.6 LIN Baud Rate Register - LINBRR
Bit 7 LDIV7 15 R/W 0 6 LDIV6 14 R/W 0 5 LDIV5 13 R/W 0 4 LDIV4 12 R/W 0 3 LDIV3 LDIV11 11 R/W 0 2 LDIV2 LDIV10 10 R/W 0 1 LDIV1 LDIV9 9 R/W 0 0 LDIV0 LDIV8 8 R/W 0
LINBRRL LINBRRH
Bit Read/Write Initial Value
* Bits 15:12 - Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when LINBRR is written. * Bits 11:0 - LDIV[11:0]: Scaling of clki/o Frequency The LDIV value is used to scale the entering clki/o frequency to achieve appropriate LIN or UART baud rate.
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4.16.6.7 LIN Data Length Register - LINDLR
Bit Read/Write Initial Value 7 LTXDL3 R/W 0 6 LTXDL2 R/W 0 5 LTXDL1 R/W 0 4 LTXDL0 R/W 0 3 LRXDL3 R/W 0 2 LRXDL2 R/W 0 1 LRXDL1 R/W 0 0 LRXDL0 LINDLR R/W 0
* Bits 7:4 - LTXDL[3:0]: LIN Transmit Data Length In LIN mode, this field gives the number of bytes to be transmitted (clamped to 8 Max). In UART mode this field is unused. * Bits 3:0 - LRXDL[3:0]: LIN Receive Data Length In LIN mode, this field gives the number of bytes to be received (clamped to 8 Max). In UART mode this field is unused. 4.16.6.8 LIN Identifier Register - LINIDR
Bit Read/Write Initial Value 7 LP1 R 0 6 LP0 R 0 5 4 LID5 / LDL1 LID4 / LDL0 R/W R/W 0 0 3 LID3 R/W 0 2 LID2 R/W 0 1 LID1 R/W 0 0 LID0 R/W 0
LINIDR
* Bits 7:6 - LP[1:0]: Parity In LIN mode:
LP0 = LID4 ^ LID2 ^ LID1 ^ LID0 LP1 = ! ( LID1 ^ LID3 ^ LID4 ^ LID5 )
In UART mode this field is unused. * Bits 5:4 - LDL[1:0]: LIN 1.3 Data Length In LIN 1.3 mode: - 00 = 2-byte response, - 01 = 2-byte response, - 10 = 4-byte response, - 11 = 8-byte response. In UART mode this field is unused. * Bits 3:0 - LID[3:0]: LIN 1.3 Identifier In LIN 1.3 mode: 4-bit identifier. In UART mode this field is unused. * Bits 5:0 - LID[5:0]: LIN 2.1 Identifier In LIN 2.1 mode: 6-bit identifier (no length transported). In UART mode this field is unused.
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4.16.6.9
LIN Data Buffer Selection Register - LINSEL
Bit Read/Write Initial Value 7 6 5 4 3 LAINC R/W 0 2 LINDX2 R/W 0 1 LINDX1 R/W 0 0 LINDX0 LINSEL R/W 0
* Bits 7:4 - Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when LINSEL is written. * Bit 3 - LAINC: Auto Increment of Data Buffer Index In LIN mode: - 0 = Auto incrementation of FIFO data buffer index (default), - 1 = No auto incrementation. In UART mode this field is unused. * Bits 2:0 - LINDX 2:0: FIFO LIN Data Buffer Index In LIN mode: location (index) of the LIN response data byte into the FIFO data buffer. The FIFO data buffer is accessed through LINDAT. In UART mode this field is unused. 4.16.6.10 LIN Data Register - LINDAT
Bit Read/Write Initial Value 7 LDATA7 R/W 0 6 LDATA6 R/W 0 5 LDATA5 R/W 0 4 LDATA4 R/W 0 3 LDATA3 R/W 0 2 LDATA2 R/W 0 1 LDATA1 R/W 0 0 LDATA0 LINDAT R/W 0
* Bits 7:0 - LDATA[7:0]: LIN Data In / Data out In LIN mode: FIFO data buffer port. In UART mode: data register (no data buffer - no FIFO). - In Write access, data out. - In Read access, data in.
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4.17
4.17.1
ISRC - Current Source
Features * 100A Constant current source * 10% Absolute Accuracy The Atmel(R) ATtiny87/167 features a 100A 10% Current Source. Up on request, the current is flowing through an external resistor. The voltage can be measured on the dedicated pin shared with the ADC. Using a resistor in series with a 0.5% tolerance is recommended. To protect the device against big values, the ADC must be configured with AVcc as internal reference to perform the first measurement. Afterwards, another internal reference can be chosen according to the previous measured value to refine the result. When ISRCEN bit is set, the ISRC pin sources 100A. Otherwise this pin keeps its initial function. Figure 4-81. Current Source Block Diagram
AVCC
100 uA
ISRCEN ADC Input
ADCn/ ISRC
External Resistor
4.17.2 4.17.2.1
Typical Applications LIN Current Source During the configuration of a LIN node in a cluster, it may be necessary to attribute dynamically an unique physical address to every cluster node. The way to do it is not described in the LIN protocol. The Current Source offers an excellent solution to associate a physical address to the application supported by the LIN node. A full dynamic node configuration can be used to set-up the LIN nodes in a cluster. Atmel ATtiny87/167 proposes to have an external resistor used in conjunction with the Current Source. The device measures the voltage to the boundaries of the resistance via the Analog to Digital converter. The resulting voltage defines the physical address that the communication handler will use when the node will participate in LIN communication. In automotive applications, distributed voltages are very disturbed. The internal Current Source solution of Atmel ATtiny87/167 immunizes the address detection the against any kind of voltage variations.
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Table 4-53.
Physical Address 0 1 2 3 4 5 6 7 Note:
Example of Resistor Values(5%) for a 8-address System (AVcc = 5V(1))
Resistor Value Rload (Ohm) 1 000 2 200 3 300 4 700 6 800 10 000 15 000 22 000 Typical Measured Voltage (V) 0.1 0.22 0.33 0.47 0.68 1 1.5 2.2 Minimum Reading with a 2.56V ref Typical Reading with a 2.56V ref 40 88 132 188 272 400 600 880 Maximum Reading with a 2.56V ref
1. 5V range: Max Rload 30K 3V range: Max Rload 15K
Table 4-54.
Physical Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note:
Example of Resistor Values(1%) for a 16-address System (AVcc = 5V(1))
Resistor Value Rload (Ohm) 1 000 1 200 1500 1800 2200 2700 3300 4700 6 800 8 200 10 000 12 000 15 000 18 000 22 000 27 000 Typical Measured Voltage (V) 0.1 0.12 0.15 0.18 0.22 0.27 0.33 0.47 0.68 0.82 1.0 1.2 1.5 1.8 2.2 2.7 Minimum Reading with a 2.56V ref 38 46 57 69 84 104 127 181 262 316 386 463 579 694 849 1023 Typical Reading with a 2.56V ref 40 48 60 72 88 108 132 188 272 328 400 480 600 720 880 1023 Maximum Reading with a 2.56V ref 45 54 68 81 99 122 149 212 306 369 450 540 675 810 989 1023
1. 5V range: Max Rload 30K 3V range: Max Rload 15K
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4.17.2.2 Current Source for Low Cost Transducer An external transducer based on a variable resistor can be connected to the Current Source. This can be, for instance: * A thermistor, or temperature-sensitive resistor, used as a temperature sensor, * A CdS photoconductive cell, or luminosity-sensitive resistor, used as a luminosity sensor, * ... Using the Current Source with this type of transducer eliminates the need for additional parts otherwise required in resistor network or Wheatstone bridge. 4.17.2.3 Voltage Reference for External Devices An external resistor used in conjunction with the Current Source can be used as voltage reference for external devices. Using a resistor in series with a lower tolerance than the Current Source accuracy ( 2%) is recommended. Table 4-54 gives an example of voltage references using standard values of resistors. Threshold Reference for Internal Analog Comparator An external resistor used in conjunction with the Current Source can be used as threshold reference for internal Analog Comparator (see Section 4.19 "AnaComp - Analog Comparator" on page 236). This can be connected to AIN0 (negative Analog Compare input pin) as well as AIN1 (positive Analog Compare input pin). Using a resistor in series with a lower tolerance than the Current Source accuracy ( 2%) is recommended. Table 4-54 gives an example of threshold references using standard values of resistors. Control Register AMISCR - Analog Miscellaneous Control Register
Bit Read/Write Initial Value 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 1 0 AREFEN XREFEN ISRCEN AMISCR R/W R/W R/W 0 0 0
4.17.2.4
4.17.3 4.17.3.1
* Bit 0 - ISRCEN: Current Source Enable Writing this bit to one enables the Current Source as shown in Figure 4-81. It is recommended to use DIDR register bit function when ISRCEN is set and to turn off the Current Source once the ADC measurement is done.
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4.18
4.18.1
ADC - Analog to Digital Converter
Features * * * * * * * * * * * * * * * * * *
10-bit Resolution 1.0LSB Integral Non-linearity 2LSB Absolute Accuracy 13 - 260s Conversion Time (Low - High Resolution) Up to 15kSPS at Maximum Resolution 11 Multiplexed Single Ended Input Channels 8 Differential input pairs with selectable gain Temperature sensor input channel Voltage from Internal Current Source Driving (ISRC) Optional Left Adjustment for ADC Result Readout 0 - AVcc ADC Input Voltage Range Selectable 1.1V / 2.56V ADC Voltage Reference Free Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt Sources Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler Unipolar / Bipolar Input Mode Input Polarity Reversal Mode
4.18.2
Overview The Atmel(R) ATtiny87/167 features a 10-bit successive approximation ADC. The ADC is connected to a 11-channel Analog Multiplexer which allows 16 differential voltage input combinations and 11 single-ended voltage inputs constructed from the pins PA7..PA0 or PB7..PB4. The differential input is equipped with a programmable gain stage, providing amplification steps of 8x or 20x on the differential input voltage before the A/D conversion. The single-ended voltage inputs refer to 0V (AGND). The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 4-82. Internal reference voltages of nominally 1.1V or 2.56V are provided On-chip. Alternatively, AVcc can be used as reference voltage for single ended channels. There are also options to output the internal 1.1V or 2.56V reference voltages or to input an external voltage reference and turn-off the internal voltage reference. These options are selected using the REFS[1:0] bits of the ADMUX control register and using AREFEN and XREFEN bits of the AMISCR control register.
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Figure 4-82. Analog to Digital Converter Block Schematic
8-Bit Data Bus ADC Conversion Complete IRQ
ADIE
Analog Misc. (AMISCR)
XREFEN AREFEN REFS1
ADC Multiplexer Select (ADMUX)
ADLAR MUX[4..0] REFS0
ADC Control & Status Register A & B (ADCSRA/ADCSRB)
ADEN ADPS[2..0] ADTS[2..0] ADATE ADSC BIN ADIF
ADIF
ADC Data Register (ADCH / ADCL) Trigger Select
Interrupt Flags ADC[9..0] Start
Internal 2.56 / 1.1V Reference Mux. Decoder
Prescaler
Conversion Logic Sample & Hold Comparator 10-bit DAC
AVCC
AGND AVCC/ 4
Bandgap Reference Temperature Sensor ADC10 ADC9 ADC8 AREF ADC7 XREF ADC6 ADC5 ADC4 ISRC / ADC3 Mux. ADC2 ADC1 ADC0 Pos. Input Mux.
ADC Multiplexer Output
x8 / x20 Gain Amplifier
Neg. Input Mux.
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4.18.3
Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents AGND and the maximum value represents the voltage on AVcc, the voltage reference on AREF pin or an internal 1.1V / 2.56V voltage reference. The voltage reference for the ADC may be selected by writing to the REFS[1..0] bits in ADMUX and AREFEN bit in AMISCR. The AVcc supply, the AREF pin or an internal 1.1V / 2.56V voltage reference may be selected as the ADC voltage reference. The analog input channel and differential gain are selected by writing to the MUX[4..0] bits in ADMUX register. Any of the 11 ADC input pins ADC[10..0] can be selected as single ended inputs to the ADC. The positive and negative inputs to the differential gain amplifier are described in Table 4-59. If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input pair by the selected gain factor 8x or 20x, according to the setting of the MUX[4..0] bits in ADMUX register. This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. The on-chip temperature sensor is selected by writing the code defined in Table 4-59 to the MUX[4..0] bits in ADMUX register when its dedicated ADC channel is used as an ADC input. A specific ADC channel (defined in Table 4-59) is used to measure the voltage to the boundaries of an external resistance flowing by a current driving by the Internal Current Source (ISRC). The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA register. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX register. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
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4.18.4 Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA register. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB register (see description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG register is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. Figure 4-83. ADC Auto Trigger Logic
CLK IO ADTS[2:0] Start ADIF SOURCE 1 ... ... ... ... SOURCE n ADSC Edge Detector Conversion Logic ADATE ADC Prescaler CLKADC
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA register. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA register to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started.
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4.18.5
Prescaling and Conversion Timing Figure 4-84. ADC Prescaler
ADEN Start CLK IO
CK/128 CK/2 CK/4 CK/8 CK/16 CK/64 CK/32
Reset
7-bit ADC Prescaler
ADPS0 ADPS1 ADPS2
By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get maximum resolution. If a lower resolution than 10bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate. The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA register. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA register. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA register, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA register is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 14.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place 2 ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 4-55.
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Figure 4-85. ADC Timing Diagram, First Conversion (Single Conversion Mode)
First Conversion Next Conversion
Cycle Number
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
ADC Clock ADEN ADSC ADIF ADCH ADCL Sign and MSB of Result LSB of Result MUX and REFS Update
MUX and REFS Update
Sample & Hold
Conversion Complete
Figure 4-86. ADC Timing Diagram, Single Conversion
One Conversion Next Conversion
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete
MUX and REFS Update
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Figure 4-87. ADC Timing Diagram, Auto Triggered Conversion
One Conversion Next Conversion
Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete Prescaler Reset
Prescaler Reset
Figure 4-88. ADC Timing Diagram, Free Running Conversion
One Conversion 11 12 13 Next Conversion 1 2 3 4
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
Sign and MSB of Result LSB of Result
Conversion Complete
Sample & Hold MUX and REFS Update
Table 4-55.
Condition
ADC Conversion Time
Sample and Hold (Cycles from Start of Conversion) 13.5cycles 1.5cycles 2cycles Conversion Time (Cycles) 25cycles 13cycles 13.5cycles
First conversion Normal conversions Auto Triggered conversions
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4.18.6 Changing Channel or Reference Selection The MUX[4:0] and REFS[1:0] bits in the ADMUX register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA register is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: a. When ADATE or ADEN is cleared. b. c. During conversion, minimum one ADC clock cycle after the trigger event. After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. 4.18.6.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 4.18.6.2 ADC Voltage Reference The voltage reference for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVcc, internal 1.1V/2.56V voltage reference or external AREF pin. The first ADC conversion result after switching voltage reference source may be inaccurate, and the user is advised to discard this result.
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4.18.7
ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: a. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. b. c. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. 4.18.7.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 4-89. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10 k or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. Signal components higher than the Nyquist frequency (fADC/2) should not be present to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 4-89. Analog Input Circuitry
IIH ADCn 1..100 kO CS/H= 14 pF IIL VCC/2
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4.18.7.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b. c. Use the ADC noise canceler function to reduce induced noise from the CPU. If any port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress.
4.18.7.3
ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: * Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 4-90. Offset Error
Output Code
Ideal ADC Actual ADC
Offset Error
VREF Input Voltage
* Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5LSB below maximum). Ideal value: 0 LSB
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Figure 4-91. Gain Error
Output Code Gain Error
Ideal ADC Actual ADC
VREF Input Voltage
* Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0LSB. Figure 4-92. Integral Non-linearity (INL)
Output Code
* Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1LSB). Ideal value: 0LSB.
INL
Ideal ADC Actual ADC VREF Input Voltage
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Figure 4-93. Differential Non-linearity (DNL)
Output Code 0x3FF
1 LSB
DNL
0x000 0 VREF Input Voltage
* Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always 0.5LSB. * Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: 0.5LSB.
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4.18.8
ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). The form of the conversion result depends on the type of the conversion as there are three types of conversions: single ended conversion, unipolar differential conversion and bipolar differential conversion. Single Ended Conversion For single ended conversion, the result is:
V IN x 1024 ADC = ---------------------------V REF
4.18.8.1
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 4-58 on page 229 and Table 4-59 on page 230). 0x000 represents analog ground, and 0x3FF represents the selected voltage reference minus one LSB. The result is presented in one-sided form, from 0x3FF to 0x000. 4.18.8.2 Unipolar Differential Conversion If differential channels and an unipolar input mode are used, the result is:
( V POS - V NEG ) x 1024 ADC = ----------------------------------------------------------- x GAIN V REF
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage reference (see Table 4-58 on page 229 and Table 4-59 on page 230). The voltage on the positive pin must always be larger than the voltage on the negative pin or otherwise the voltage difference is saturated to zero. The result is presented in one-sided form, from 0x000 (0d) to 0x3FF (+1023d). The GAIN is either 8x or 20x. 4.18.8.3 Bipolar Differential Conversion As default the ADC converter operates in the unipolar input mode, but the bipolar input mode can be selected by writing the BIN bit in the ADCSRB register to one. In the bipolar input mode two-sided voltage differences are allowed and thus the voltage on the negative input pin can also be larger than the voltage on the positive input pin. If differential channels and a bipolar input mode are used, the result is:
( V POS - V NEG ) x 512 ADC = ------------------------------------------------------- x GAIN V REF
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage reference. The result is presented in two's complement form, from 0x200 (-512d) through 0x000 (+0d) to 0x1FF (+511d). The GAIN is either 8x or 20x. However, if the signal is not bipolar by nature (9 bits + sign as the 10th bit), this scheme loses one bit of the converter dynamic range. Then, if the user wants to perform the conversion with the maximum dynamic range, the user can perform a quick polarity check of the result and use the unipolar differential conversion with selectable differential input pair. When the polarity check is performed, it is sufficient to read the MSB of the result (ADC9 in ADCH register). If the bit is one, the result is negative, and if this bit is zero, the result is positive.
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4.18.9 Temperature Measurement The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended ADC input. MUX[4..0] bits in ADMUX register enables the temperature sensor. The internal 1.1V voltage reference must also be selected for the ADC voltage reference source in the temperature sensor measurement. When the temperature sensor is enabled, the ADC converter can be used in single conversion mode to measure the voltage over the temperature sensor. The measured voltage has a linear relationship to the temperature as described in Table 4-56. The voltage sensitivity is approximately 1LSB/C and the accuracy of the temperature measurement is 10C using manufacturing calibration values (TS_GAIN, TS_OFFSET). The values described in Table 4-56 are typical values. However, due to the process variation the temperature sensor output varies from one chip to another. Table 4-56. Temperature vs. Sensor Output Voltage (Typical Case): Example ADC Values
-40C 0x00F6 +25C 0x0144 +85C 0c01B8
Temperature/C
4.18.10
Manufacturing Calibration Calibration values determined during test are available in the signature row. The temperature in degrees Celsius can be calculated using the formula:
( [ ( ADCH 8 ) ADCL ] - ( 273 + 25 - TS_OFFSET ) ) x 128 T = ------------------------------------------------------------------------------------------------------------------------------------------------------ + 25 TS_GAIN
Where: a. ADCH & ADCL are the ADC data registers, b. c. is the temperature sensor gain TSOFFSET is the temperature sensor offset correction term TS_GAIN is the unsigned fixed point 8-bit temperature sensor gain factor in 1/128th units stored in the signature row TS_OFFSET is the signed twos complement temperature sensor offset reading stored in the signature row. See Table 4-65 on page 246 for signature row parameter address.
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The following code example allows to read Signature Row data:
.equ TS_GAIN = 0x0005 .equ TS_OFFSET = 0x0003 LDI R30,LOW(TS_GAIN) LDI R31,HIGH (TS_GAIN) RCALL Read_signature_row MOV R17,R16 ; Save R16 result LDI R30,LOW(TS_OFFSET) LDI R31,HIGH (TS_OFFSET) RCALL Read_signature_row ; R16 holds TS_OFFSET and R17 holds TS_GAIN Read_signature_row: IN R16,SPMCSR ; Wait for SPMEN ready SBRC R16,SPMEN ; Exit loop here when SPMCSR is free RJMP Read_signature_row LDI R16,((1<4.18.11
Internal Voltage Reference Output The internal voltage reference is output on XREF pin as described in Table 4-57 if the ADC is turned on (see Section 4.7.2.1 "Voltage Reference Enable Signals and Start-up Time" on page 76). Addition of an external filter capacitor (5 - 10nF) on XREF pin may be necessary. XREF current load must be from 1A to 100A with VCC from 2.7V to 5.5V for XREF = 1.1V and with VCC from 4.5V to 5.5V for XREF = 2.56V. XREF pin can be coupled to an analog input of the ADC.
Table 4-57.
XREFEN(1) 0 1(2) 1(1) Notes:
Internal Voltage Reference Output
REFS1(2) x 0 1 REFS0(3) x 1 1 Voltage Reference Output (Iload 100A) Hi-Z, the pin can be used as AREF input or other alternate functions. XREF = 1.1V(3) XREF = 2.56V(3)(4)
1. See "Bit 1 - XREFEN: Internal Voltage Reference Output Enable" on page 235. 2. See "Bit 7:6 - REFS1:REFS0: Voltage Reference Selection Bits" on page 229. 3. In these configurations, the pin pull-up must be turned off and the pin digital output must be set in Hi-Z. 4. Vcc in range 4.5 - 5.5V.
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4.18.12 4.18.12.1 Register Description ADMUX - ADC Multiplexer Selection Register
Bit Read/Write Initial Value 7 REFS1 R/W 0 6 REFS0 R/W 0 5 ADLAR R/W 0 4 MUX4 R/W 0 3 MUX3 R/W 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX
* Bit 7:6 - REFS1:REFS0: Voltage Reference Selection Bits These bits and AREFEN bit from the Analog Miscellaneous Control Register (AMISCR) select the voltage reference for the ADC, as shown in Table 4-58. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA register is set). Whenever these bits are changed, the next conversion will take 25 ADC clock cycles. If active channels are used, using AVCC or an external AREF higher than (AVcc - 1V) is not recommended, as this will affect ADC accuracy. The internal voltage reference options may not be used if an external voltage is being applied to the AREF pin.
Table 4-58.
REFS1 X X 0 1
Voltage Reference Selections for ADC
REFS0 0 0 1 1 AREFEN Voltage Reference (VREF) Selection 0 1 0 0 AVcc used as Voltage Reference, disconnected from AREF pin. External Voltage Reference at AREF pin (AREF 2.0V) Internal 1.1V Voltage Reference. Internal 2.56V Voltage Reference.
* Bit 5 - ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see "ADCL and ADCH - The ADC Data Register" on page 232. * Bits 4:0 - MUX4:0: Analog Channel and Gain Selection Bits These bits select which combination of analog inputs are connected to the ADC. In case of differential input, gain selection is also made with these bits. Refer to Table 4-59 for details. If these bits are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA register is set).
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Table 4-59.
MUX[4..0] 0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 0 1111 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111
Input Channel Selections
Single Ended Input ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC3 / ISRC (PA3) ADC4 (PA4) ADC5 (PA5) ADC6 (PA6) ADC7 / AREF (PA7) ADC8 (PB5) ADC9 (PB6) ADC10 (PB7) Temperature Sensor Bandgap Reference (1.1 V) AVcc/4 GND (0V) (reserved) ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC4 (PA4) N/A ADC5 (PA5) ADC6 (PA6) ADC8 (PB5) ADC9 (PB6) ADC6 (PA6) ADC7 (PA7) ADC9 (PB6) ADC10 (PB7) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC5 (PA5) 8x 20x 8x 20x 8x 20x 8x 20x 8x 20x 8x 20x 8x 20x 8x 20x NA NA NA Positive Differential Input Negative Differential Input Gain
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4.18.12.2 ADCSRA - ADC Control and Status Register A
Bit Read/Write Initial Value 7 ADEN R/W 0 6 ADSC R/W 0 5 ADATE R/W 0 4 ADIF R/W 0 3 ADIE R/W 0 2 ADPS2 R/W 0 1 ADPS1 R/W 0 0 ADPS0 R/W 0 ADCSRA
* Bit 7 - ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. * Bit 6 - ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. * Bit 5 - ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. * Bit 4 - ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. * Bit 3 - ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated. * Bits 2:0 - ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC.
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Table 4-60.
ADPS2 0 0 0 0 1 1 1 1
ADC Prescaler Selections
ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 Division Factor 2 2 4 8 16 32 64 128
4.18.12.3
ADCL and ADCH - The ADC Data Register ADLAR = 0
Bit 15 - ADC7 7 R R 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL
Read/Write Initial Value
ADLAR = 1
Bit 15 ADC9 ADC1 7 R R 0 0 14 ADC8 ADC0 6 R R 0 0 13 ADC7 - 5 R R 0 0 12 ADC6 - 4 R R 0 0 11 ADC5 - 3 R R 0 0 10 ADC4 - 2 R R 0 0 9 ADC3 - 1 R R 0 0 8 ADC2 - 0 R R 0 0 ADCH ADCL
Read/Write Initial Value
When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. * ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in "ADC Conversion Result" on page 226.
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4.18.12.4 ADCSRB - ADC Control and Status Register B
Bit Read/Write Initial Value 7 BIN R/W 0 6 ACME R/W 0 5 ACIR1 R/W 0 4 ACIR0 R/W 0 3 - R 0 2 ADTS2 R/W 0 1 ADTS1 R/W 0 0 ADTS0 R/W 0 ADCSRB
* Bit 7- BIN: Bipolar Input Mode The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions are supported and the voltage on the positive input must always be larger than the voltage on the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode two-sided conversions are supported and the result is represented in the two's complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit. * Bit 3 - Res: Reserved Bit This bit is reserved for future use. For compatibility with future devices it must be written to zero when ADCSRB register is written. * Bits 2:0 - ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA register is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA register is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
Table 4-61.
ADTS2 0 0 0 0 1 1 1 1
ADC Auto Trigger Source Selections
ADTS1 0 0 1 1 0 0 1 1 ADTS0 0 1 0 1 0 1 0 1 Trigger Source Free Running mode Analog Comparator External Interrupt Request 0 Timer/Counter1 Compare Match A Timer/Counter1 Overflow Timer/Counter1 Compare Match B Timer/Counter1 Capture Event Watchdog Interrupt Request
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4.18.12.5
DIDR0 - Digital Input Disable Register 0
Bit 7 6 ADC7D / ADC6D / AIN1D AIN0D R/W R/W 0 0 5 ADC5D R/W 0 4 ADC4D R/W 0 3 ADC3D R/W 0 2 ADC2D R/W 0 1 ADC1D R/W 0 0 ADC0D DIDR0 R/W 0
Read/Write Initial Value
* Bits 7:0 - ADC7D:ADC0D: ADC7:0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 4.18.12.6 DIDR1 - Digital Input Disable Register 1
Bit 7 Read/Write Initial Value R 0 6 ADC10D R/W 0 5 ADC9D R/W 0 4 ADC8D R/W 0 3 R 0 2 R 0 1 R 0 0 R 0 DIDR1
* Bit 7 - Res: Reserved Bit This bit is reserved for future use. For compatibility with future devices it must be written to zero when DIDR1 register is written. * Bits 6..4 - ADC10D..ADC8D: ADC10..8 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC10:8 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. * Bits 3:0 - Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when DIDR1 is written.
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4.18.12.7 AMISCR - Analog Miscellaneous Control Register
Bit Read/Write Initial Value 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 1 0 AREFEN XREFEN ISRCEN R/W R/W R/W 0 0 0 AMISCR
* Bits 7:3 - Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when AMISCR is written. * Bit 2 - AREFEN: External Voltage Reference Input Enable When this bit is written logic one, the voltage reference for the ADC is input from AREF pin as described in Table 4.18.11 on page 228. If active channels are used, using AVcc or an external AREF higher than (AVcc - 1V) is not recommended, as this will affect ADC accuracy. The internal voltage reference options may not be used if an external voltage is being applied to the AREF pin. It is recommended to use DIDR register bit function (digital input disable) when AREFEN is set. * Bit 1 - XREFEN: Internal Voltage Reference Output Enable When this bit is written logic one, the internal voltage reference 1.1V or 2.56V is output on XREF pin as described in Table 4.18.11 on page 228. It is recommended to use DIDR register bit function (digital input disable) when XREFEN is set.
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4.19
AnaComp - Analog Comparator
The Analog Comparator compares the input values on the positive pin (AIN1) and negative pin (AIN0). When the voltage on the positive pin is higher than the voltage on the negative pin, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 4-94.
Figure 4-94. Analog Comparator Block Diagram(1)(2)
ADC Multiplexer Output (1) ACME ADEN ACD AIN1 (PA7) Interrupt Sensivity Control AIN0 (PA6) (from ADC) ACIRS ACIS1 ACIS0 ACIE ACI 16-bit Timer/Counter Input Capture AVcc ACO
Analog Comparator Interrupt
Internal 2.56 / 1.1V Reference REFS0 REFS1
1.1 V
2.56 V
2.56 V/2 2.56V/4 2.56V/8
ACIR0 ACIR1
Notes:
1. See Table 4-63 on page 239 and Table 4-64 on page 239 2. Refer to Table 4-24 on page 100 for Analog Comparator pin placement.
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4.19.1 4.19.1.1 Register Description ADC Control and Status Register B - ADCSRB
Bit Read/Write Initial Value 7 BIN R 0 6 ACME R/W 0 5 ACIR1 R/W 0 4 ACIR0 R/W 0 3 -- R 0 2 ADTS2 R/W 0 1 ADTS1 R/W 0 0 ADTS0 R/W 0 ADCSRB
* Bit 6 - ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the positive input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the positive input of the Analog Comparator. When the Analog to Digital Converter (ADC) is configured as single ended input channel, it is possible to select any of the ADC[10..0] pins to replace the positive input to the Analog Comparator. The ADC multiplexer (MUX[4..0]) is used to select this input, and consequently, the ADC must be switched off to utilize this feature. * Bits 5, 4 - ACIR1, ACIR0: Analog Comparator Internal Voltage Reference Select When ACIRS bit is set in ADCSRA register, these bits select a voltage reference for the negative input to the Analog Comparator, see Table 4-64 on page 239. 4.19.1.2 ACSR - Analog Comparator Control and Status Register
Bit Read/Write Initial Value 7 ACD R/W 0 6 ACIRS R/W 0 5 ACO R N/A 4 ACI R/W 0 3 ACIE R/W 0 2 ACIC R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR
* Bit 7 - ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit of ACSR register. Otherwise an interrupt can occur when the bit is changed. * Bit 6 - ACIRS: Analog Comparator Internal Reference Select When this bit is set an Internal Reference Voltage replaces the negative input to the Analog Comparator (c.f. Table 4-64 on page 239). If ACIRS is cleared, AIN0 is applied to the negative input to the Analog Comparator. * Bit 5 - ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. * Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. * Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
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* Bit 2 - ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. * Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 4-62.
Table 4-62.
ACIS1 0 0 1 1 Note:
ACIS1 / ACIS0 Settings
ACIS0 0 1 0 1 Interrupt Mode Comparator Interrupt on Output Toggle. Reserved Comparator Interrupt on Falling Output Edge. Comparator Interrupt on Rising Output Edge.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.
4.19.1.3
DIDR0 - Digital Input Disable Register 0
Bit 7 6 ADC7D / ADC6D / AIN1D AIN0D R/W R/W 0 0 5 ADC5D R/W 0 4 ADC4D R/W 0 3 ADC3D R/W 0 2 ADC2D R/W 0 1 ADC1D R/W 0 0 ADC0D DIDR0 R/W 0
Read/Write Initial Value
* Bits 7,6 - AIN1D, AIN0D: AIN1D and AIN0D Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding Analog Compare pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN0/1 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 4.19.2 4.19.2.1 Analog Comparator Inputs Analog Compare Positive Input It is possible to select any of the inputs of the ADC Positive Input Multiplexer to replace the positive input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB register) is set and the ADC is switched off (ADEN in ADCSRA register is zero), MUX[4..0] in ADMUX register select the input pin to replace the positive input to the Analog Comparator, as shown in Table 4-63. If ACME is cleared or ADEN is set, AIN1 pin is applied to the positive input to the Analog Comparator.
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Table 4-63.
ACME 0 x 1 1 1 1 1 1 1 1 1 1 1 1
Analog Comparator Positive Input
ADEN x 1 0 0 0 0 0 0 0 0 0 0 0 0 MUX[4..0] x xxxx b x xxxx b 0 0000 b 0 0001 b 0 0010 b 0 0011 b 0 0100 b 0 0101 b 0 0110 b 0 0111 b 0 1000 b 0 1001 b 0 1010 b Other Analog Comparator Positive Input - Comment AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 / ISRC ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 This doesn't make sense - Don't use. ADC Switched Off. ADC Switched On
4.19.2.2
Analog Compare Negative Input It is possible to select an internal voltage reference to replace the negative input to the Analog Comparator. The output of a 2-bit DAC using the Internal Voltage Reference of the DAC is available when ACIRS bit of ACSR register is set. The voltage reference division factor is done by ACIR[1..0] of ADCSRB register. If ACIRS is cleared, AIN0 pin is applied to the negative input to the Analog Comparator.
Table 4-64.
ACIRS 0 1 1 1 1 1
Analog Comparator Negative Input
REFS[1..0] Analog Comparator Negative Input - Comment x 0 0b 0 1b 1 0b 1 1b 1 1b 1 1b 1 1b AIN0 Reserved 2.56V - using Internal 2.56V Voltage Reference 1.28V (1/2 of 2.56 V) - using Internal 2.56V Voltage Reference 0.64V (1/4 of 2.56 V - using Internal 2.56V Voltage Reference 0.32V (1/8 of 2.56 V) - using Internal 2.56V Voltage Reference x x 0 0b 0 1b 1 0b 1 1b
ACIR[1..0]
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4.20
4.20.1
DebugWIRE On-chip Debug System
Features * * * * * * * * * *
Complete Program Flow Control Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin Real-time Operation Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs) Unlimited Number of Program Break Points (Using Software Break Points) Non-intrusive Operation Electrical Characteristics Identical to Real Device Automatic Configuration System High-Speed Operation Programming of Non-volatile Memories
4.20.2
Overview The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the program flow, execute AVR(R) instructions in the CPU and to program the different non-volatile memories.
4.20.3
Physical Interface When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. Figure 4-95. The debugWIRE Setup
+1.8 - +5.5V Vcc
dW
dW (RESET) GND
Figure 4-95 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses.
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When designing a system where debugWIRE will be used, the following observations must be made for correct operation: * Pull-up resistors on the dW/(RESET) line must not be smaller than 10k. The pull-up resistor is not required for debugWIRE functionality. * Connecting the RESET pin directly to Vcc will not work. * Capacitors connected to the RESET pin must be disconnected when using debugWire. * All external reset sources must be disconnected. 4.20.4 Software Break Points DebugWIRE supports Program memory break points by the AVR(R) BREAK instruction. Setting a break point in AVR Studio(R) will insert a BREAK instruction in the Program memory. The instruction replaced by the BREAK instruction will be stored. When program execution is continued, the stored instruction will be executed before continuing from the Program memory. A break can be inserted manually by putting the BREAK instruction in the program. The Flash must be re-programmed each time a break point is changed. This is automatically handled by AVR Studio through the debugWIRE interface. The use of break points will therefore reduce the Flash Data retention. Devices used for debugging purposes should not be shipped to end customers. 4.20.5 Limitations of DebugWIRE The debugWIRE communication pin (dW) is physically located on the same pin as External Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is enabled. The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e., when the program in the CPU is running. When the CPU is stopped, care must be taken while accessing some of the I/O Registers via the debugger (AVR Studio). A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should be disabled when debugWire is not used. 4.20.6 DebugWIRE Related Register in I/O Memory The following section describes the registers used with the debugWire. DebugWIRE Data Register - DWDR
Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 DWDR R/W 0 DWDR[7:0]
4.20.6.1
The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations.
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4.21
Flash Programming
The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface (i.e. LIN, USART, ...) and associated protocol to read code and write (program) that code into the Program memory. The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation: * Alternative 1, fill the buffer before a Page Erase - Fill temporary page buffer - Perform a Page Erase - Perform a Page Write * Alternative 2, fill the buffer after Page Erase - Perform a Page Erase - Fill temporary page buffer - Perform a Page Write If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be re-written. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page.
4.21.1 4.21.1.1
Self-Programming the Flash Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write "00000011 b" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. * The CPU is halted during the Page Erase operation.
4.21.1.2
Filling the Temporary Buffer (Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write "00000001 b" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost.
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4.21.1.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write "00000101 b" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. * The CPU is halted during the Page Write operation. 4.21.2 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers ZL and ZH in the register file. The number of bits actually used is implementation dependent.
Bit 15 Z15 Z7 Bit 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0 ZH (R31) ZL (R30)
Since the Flash is organized in pages (see Table 4-73 on page 253), the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is shown in Figure 4-96. Note that the Page Erase and Page Write operations are addressed independently. Therefore it is of major importance that the software addresses the same page in both the Page Erase and Page Write operation. The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 4-96. Addressing the Flash During SPM(1)
BIT 15 ZPCMSB ZPAGEMSB 10 0 PCMSB PROGRAM COUNTER
PCPAGE
Z - POINTER
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. The different variables used in Table 4-66 are listed in Table 4-73 on page 253.
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4.21.2.1
Store Program Memory Control and Status Register - SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
Bit Read/Write Initial Value
7 - R 0
6 RWWSB R 0
5 SIGRD R 0
4 CTPB R/W 0
3 RFLB R/W 0
2 PGWRT R/W 0
1 PGERS R/W 0
0 SPMEN R/W 0 SPMCSR
* Bit 7 - Res: Reserved Bit This bit is a reserved bit in the Atmel(R) ATtiny87/167 and will always read as zero. * Bit 6 - RWWSB: Read-While-Write Section Busy This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero in Atmel ATtiny87/167. * Bit 5 - SIGRD: Signature Row Read If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. See "Reading the Signature Row from Software" on page 246. for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. * Bit 4 - CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. * Bit 3 - RFLB: Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See "Reading the Fuse and Lock Bits from Software" on page 245. for details. * Bit 2 - PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. * Bit 1 - PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Zpointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.
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* Bit 0 - SPMEN: Self Programming Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either SIGRD, CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than "10 0001 b ", "01 0001 b ", "00 1001 b ", "00 0101 b ", "00 0011 b" or "00 0001 b" in the lower six bits will have no effect.
Note: Only one SPM instruction should be active at any time.
4.21.2.2
EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When RFLB and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
4.21.2.3
Bit Rd (Z=0x0001)
7 -
6 -
5 -
4 -
3 -
2 -
1 LB2
0 LB1
The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. See Table 4-71 on page 252 for a detailed description and mapping of the Fuse Low byte.
Bit Rd (Z=0x0000)
7 FLB7
6 FLB6
5 FLB5
4 FLB4
3 FLB3
2 FLB2
1 FLB1
0 FLB0
Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte will be loaded in the destination register as shown below. See Table 4-70 on page 251 for detailed description and mapping of the Fuse High byte.
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Bit Rd (Z=0x0003)
7 FHB7
6 FHB6
5 FHB5
4 FHB4
3 FHB3
2 FHB2
1 FHB1
0 FHB0
Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse byte will be loaded in the destination register as shown below. See Table 4-69 on page 251 for detailed description and mapping of the Extended Fuse byte.
Bit Rd (Z=0x0002)
7 -
6 -
5 -
4 -
3 -
2 -
1 -
0 EFB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. 4.21.2.4 Reading the Signature Row from Software To read the Signature Row from software, load the Z-pointer with the signature byte address given in Table 4-65 on page 246 and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the SIGRD and SPMEN bits are set in SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
Table 4-65.
Signature Row Addressing
Signature Byte Device Signature Byte 0 Device Signature Byte 1 Device Signature Byte 2 Z-Pointer Address 0x0000 0x0002 0x0004 0x0001 0x0003 0x0005
8MHz RC Oscillator Calibration Byte TSOFFSET - Temp Sensor Offset TSGAIN - Temp Sensor Gain Note: All other addresses are reserved for future use.
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4.21.2.5 Preventing Flash Corruption During periods of low Vcc, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. * First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. * Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR(R) RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low Vcc reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 2. Keep the AVR core in Power-down sleep mode during periods of low Vcc. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes. 4.21.2.6 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 4-66 shows the typical programming time for Flash accesses from the CPU.
Table 4-66.
SPM Programming Time
Symbol Min Programming Time 3.7ms Max Programming Time 4.5ms
Flash write (Page Erase, Page Write, and write Lock bits by SPM)
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4.21.2.7
Simple Assembly Code Example for a Boot Loader Note that the RWWSB bit will always be read as zero in Atmel(R) ATtiny87/167. Nevertheless, it is recommended to check this bit as shown in the code example, to ensure compatibility with devices supporting Read-While-Write.
;- The routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y-pointer ; the first data location in Flash is pointed to by the Z-pointer ;- Error handling is not included ;- Registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcsrval (r20) ; - Storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size .equ PAGESIZEB = PAGESIZE*2 .org SMALLBOOTSTART ; AGESIZEB is page size in BYTES, not words
Write_page: ; Page Erase ldi spmcsrval, (1<r0, Y+ r1, Y+ spmcsrval, (1<; Execute Page Write subi ZL, low(PAGESIZEB) ; restore pointer sbci ZH, high(PAGESIZEB) ; not required for PAGESIZEB<=256 ldi spmcsrval, (1<248
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Rdloop: lpm ld cpse rjmp sbiw brne r0, Z+ r1, Y+ r0, r1 Error loophi:looplo, 1 Rdloop
; use subi for PAGESIZEB<=256
; To ensure compatibility with devices supporting Read-While-Write ; Return to RWW section ; Verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; Clear temporary page buffer ldi spmcsrval, (1<249
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4.22
4.22.1
Memory Programming
Program and Data Memory Lock Bits The Atmel(R) ATtiny87/167 provides two Lock bits which can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional features listed in Table 4-68. The Lock bits can only be erased to "1" with the Chip Erase command. The Atmel ATtiny87/167 has no separate Boot Loader section. Lock Bit Byte(1)
Bit No 7 6 5 4 3 2 LB2 LB1 Note: 1 0 Description - - - - - - Lock bit Lock bit Default Value 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed)
Table 4-67.
Lock Bit Byte
1. "1" means unprogrammed, "0" means programmed.
Table 4-68.
LB Mode 1 2
Lock Bit Protection Modes(1)(2)
Protection Type LB1 1 0 No memory lock features enabled. Further programming of the Flash and EEPROM is disabled in Parallel and Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode(1). Further programming and verification of the Flash and EEPROM is disabled in Parallel and Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode(1). LB2 1 1
Memory Lock Bits
3 Notes:
0
0
1. Program the Fuse bits before programming the LB1 and LB2. 2. "1" means unprogrammed, "0" means programmed.
4.22.2
Fuse Bits The Atmel(R) ATtiny87/167 has three Fuse bytes. Table 4-69, Table 4-70 & Table 4-71 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. The SPM instruction is enabled for the whole Flash if the SELFPRGEN fuse is programmed ("0"), otherwise it is disabled.
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Note that the fuses are read as logical zero, "0", if they are programmed.
Table 4-69.
- - - - - - -
Extended Fuse Byte
Bit No 7 6 5 4 3 2 1 0 Description - - - - - - - Self Programming Enable Default Value 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed)
Fuse Extended Byte
SELFPRGEN
Table 4-70.
Fuse High Byte
Bit No 7 6 5 4 3 2 1 0 Description External Reset Disable DebugWIRE Enable Enable Serial Program and Data Downloading Watchdog Timer always on EEPROM memory is preserved through the Chip Erase Brown-out Detector trigger level Brown-out Detector trigger level Brown-out Detector trigger level Default Value 1 (unprogrammed) 1 (unprogrammed) 0 (programmed, SPI programming enabled) 1 (unprogrammed) 1 (unprogrammed, EEPROM not preserved) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed)
(1)
Fuse High Byte RSTDISBL DWEN SPIEN(2) WDTON(3) EESAVE BODLEVEL2(4) BODLEVEL1 BODLEVEL0 Notes:
(4) (4)
1. See Section 4.10.3.4 "Alternate Functions of Port B" on page 105 for description of RSTDISBL Fuse. 2. The SPIEN Fuse is not accessible in serial programming mode. 3. See Section 4.7.3.3 "Watchdog Timer Control Register - WDTCR" on page 80 for details. 4. See Table 4-85 on page 271 for BODLEVEL Fuse coding.
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Table 4-71.
CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes:
(4)
Fuse Low Byte
Bit No 7 6 5 4 3 2 1 0 Description Divide clock by 8 Clock output Select start-up time Select start-up time Select Clock source Select Clock source Select Clock source Select Clock source Default Value 0 (programmed) 1 (unprogrammed) 1 (unprogrammed)(1) 0 (programmed)(1) 0 (programmed)(2) 0 (programmed)(2) 1 (unprogrammed)(2) 0 (programmed)(2)
Fuse Low Byte
(3)
1. The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 4-8 on page 51 for details. 2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 4-7 on page 51 for details. 3. The CKOUT Fuse allows the system clock to be output on PORTB5. See Section 4.5.2.7 "Clock Output Buffer" on page 55 for details. 4. See Section 4.5.4 "System Clock Prescaler" on page 61 for details.
4.22.2.1
Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space.
4.22.3
Table 4-72.
Device
Signature Bytes
Address 0 1 2 Value 0x1E 0x94 0x87 Signature Byte Description Indicates manufactured by Atmel Indicates 16 KB Flash memory Indicates ATtiny167 device when address 1 contains 0x94
ATtiny167
4.22.4
Calibration Byte The Atmel(R) ATtiny87/167 has a byte calibration value for the internal RC Oscillator. This byte resides in the high byte of address 0x000 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator.
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4.22.5 Page Size Table 4-73.
Device ATtiny87 ATtiny167
Number of Words in a Page and No. of Pages in the Flash
Flash Size 4K words 8K words Page Size 64 words 64 words PCWORD PC[5:0] PC[5:0] No. of Pages 64 128 PCPAGE PC[11:6] PC[12:6] PCMSB 11 12
Table 4-74.
Device ATtiny87 ATtiny167
Number of Words in a Page and No. of Pages in the EEPROM
EEPROM Size 512bytes Page Size PCWORD 4bytes EEA[1:0] No. of Pages 128 PCPAGE EEA[8:2] EEAMSB 8
4.22.6
Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the Atmel(R) ATtiny87/167. Pulses are assumed to be at least 250 ns unless otherwise noted. Signal Names In this section, some pins of the Atmel ATtiny87/167 are referenced by signal names describing their functionality during parallel programming, see Figure 4-97 and Figure 4-98. Pins not described in the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Figure 4-76. When pulsing WR or OE, the command loaded determines the action executed. The different commands are shown in Figure 4-77. Figure 4-97. Parallel Programming
WR XA0 XA1 / BS2 PAGEL / BS1 PB0 PB1 PB2 PB3 XTAL1 / PB4 OE RDY / BSY +12 V PB5 PB6 RESET / PB7 GND
PA7 - PA0
4.22.6.1
+4.5 - +5.5V Vcc +4.5 - +5.5V AVcc
DATA
Note:
Vcc - 0.3V < AVcc < Vcc + 0.3V, however, AVcc should always be within 4.5 to 5.5V
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Figure 4-98. Pin Name Mapping
Signal Name in Programming Mode WR XA0 XA1 / BS2 Pin Name PB0 PB1 PB2 I/O Function I I I Write Pulse (Active low). XTAL1 Action Bit 0 - XTAL1 Action Bit 1 - Byte Select 2 ("0" selects low byte, "1" selects 2'nd high byte) - Program Memory and EEPROM data Page Load - Byte Select 1 (0" selects low byte, "1" selects high byte) XTAL1 (Clock input) Output Enable (Active low). 0: Device is busy programming, 1: Device is ready for new command. - Reset (Active low) - Parallel programming mode (+12V).
PAGEL / BS1
PB3 PB4
I I I O I
OE RDY / BSY +12V DATA
PB5 PB6 PB7 PA7-PA0
I/O Bi-directional Data bus (Output when OE is low).
Table 4-75.
Pin Values Used to Enter Programming Mode
Pin Symbol Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] Value 0 0 0 0
PAGEL / BS1 XA1 / BS2 XA0 WR
Table 4-76.
XA1 0 0 1 1
XA1 and XA0 Coding
XA0 0 1 0 1 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1). Load Data (High or Low data byte for Flash determined by BS1). Load Command No Action, Idle
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Table 4-77. Command Byte Bit Coding
Command Executed Chip Erase Write Fuse bits Write Lock bits Write Flash Write EEPROM Read Signature bytes and Calibration byte Read Fuse and Lock bits Read Flash Read EEPROM
Command Byte 1000 0000 b 0100 0000 b 0010 0000 b 0001 0000 b 0001 0001 b 0000 1000 b 0000 0100 b 0000 0010 b 0000 0011 b
4.22.7 4.22.7.1
Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between Vcc and GND. 2. Set RESET to "0" and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 4-75 on page 254 to "0000 b" and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100ns after +12V has been applied to RESET, will cause the device to fail entering programming mode. 5. Wait at least 50 s before sending a new command.
4.22.7.2
Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. * The command needs only be loaded once when writing or reading multiple memory locations. * Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. * Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading.
4.22.7.3
Chip Erase The Chip Erase will erase the Flash and EEPROM(Note:) memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed.
Note: The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
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Load Command "Chip Erase" 1. Set XA1, XA0 to "1,0 ". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "1000 0000 b". This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. 4.22.7.4 Programming the Flash The Flash is organized in pages, see Table 4-73 on page 253. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command "Write Flash" 1. Set XA1, XA0 to "1,0". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "0001 0000 b". This is the command for Write Flash. Give XTAL1 a positive pulse. This loads the command. B. Load Address Low byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "0". This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to "0,1". This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Load Data High Byte 1. Set BS1 to "1". This selects high data byte. 2. Set XA1, XA0 to "0,1". This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the data byte. E. Latch Data 1. Set BS1 to "1". This selects high data byte. 2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 4-100 for signal waveforms)
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F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded. While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 4-99 on page 257. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. G. Load Address High byte 1. Set XA1, XA0 to "0,0". This enables address loading. 2. Set BS1 to "1". This selects high address. 3. Set DATA = Address high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. H. Program Page 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high (See Figure 4-100 for signal waveforms). I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. Set XA1, XA0 to "1,0". This enables command loading. 2. Set DATA to "0000 0000 b". This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 4-99. Addressing the Flash Which is Organized in Pages
PCMSB PROGRAM COUNTER
PCPAGE
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
PCPAGE and PCWORD are listed in
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Figure 4-100. Programming the Flash Waveforms(1)
F A
DATA XA1 / BS2 XA0 PAGEL / BS1 XTAL1 WR RDY/BSY RESET +12V OE
0x10
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
G
ADDR. HIGH
H
XX
Note:
1. "XX" is don't care. The letters refer to the programming description above.
4.22.7.5
Programming the EEPROM The EEPROM is organized in pages, see Table 4-74 on page 253. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to "Programming the Flash" on page 256 for details on Command, Address and Data loading): A: Load Command "0001 0001 b". G: Load Address High Byte (0x00 - 0xFF). B: Load Address Low Byte (0x00 - 0xFF). C: Load Data (0x00 - 0xFF). E: Latch data (give PAGEL a positive pulse). K: Repeat A through E until the entire buffer is filled. L: Program EEPROM page 1. Set BS1 to "0". 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (See Figure 4-101 for signal waveforms).
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Figure 4-101. Programming the EEPROM Waveforms
K A
DATA XA1 / BS2 XA0 PAGEL / BS1 XTAL1 WR RDY/BSY RESET +12V OE
0x11
G
ADDR. HIGH
B
ADDR. LOW
C
DATA
E
XX
B
ADDR. LOW
C
DATA
E
XX
L
4.22.7.6
Reading the Flash The algorithm for reading the Flash memory is as follows (refer to "Programming the Flash" on page 256 for details on Command and Address loading): 1. A: Load Command "0000 0010 b". 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to "0", and BS1 to "0". The Flash word low byte can now be read at DATA. 5. Set BS1 to "1". The Flash word high byte can now be read at DATA. 6. Set OE to "1".
4.22.7.7
Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to "Programming the Flash" on page 256 for details on Command and Address loading): 1. A: Load Command "0000 0011 b". 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to "0", and BS1 to "0". The EEPROM Data byte can now be read at DATA. 5. Set OE to "1".
4.22.7.8
Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to "Programming the Flash" on page 256 for details on Command and Data loading): 1. A: Load Command "0100 0000 b". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high.
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4.22.7.9
Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to "Programming the Flash" on page 256 for details on Command and Data loading): 1. A: Load Command "0100 0000 b". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. Set BS1 to "1" and BS2 to "0". This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to "0". This selects low data byte.
4.22.7.10
Programming the Extended Fuse Bits The algorithm for programming the Extended Fuse bits is as follows (refer to "Programming the Flash" on page 256 for details on Command and Data loading): 1. A: Load Command "0100 0000 b". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. Set BS1 to "0" and BS2 to "1". This selects extended data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS2 to "0". This selects low data byte.
Figure 4-102. Programming the FUSES Waveforms
Write Fuse Low byte A
DATA XA1 / BS2 XA0 PAGEL / BS1 XTAL1 WR RDY/BSY RESET +12V OE
0x40
Write Fuse high byte A C
DATA XX
Write Extended Fuse byte A
0x40
C
DATA XX
C
DATA XX
0x40
4.22.7.11
Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to "Programming the Flash" on page 256 for details on Command and Data loading): 1. A: Load Command "0010 0000 b". 2. C: Load Data Low Byte. Bit n = "0" programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to re-program the Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high. 4. The Lock bits can only be cleared by executing Chip Erase.
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4.22.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to "Programming the Flash" on page 256 for details on Command loading): 1. A: Load Command "0000 0100 b". 2. Set OE to "0", BS2 to "0" and BS1 to "0". The status of the Fuse Low bits can now be read at DATA ("0" means programmed). 3. Set OE to "0", BS2 to "1" and BS1 to "1". The status of the Fuse High bits can now be read at DATA ("0" means programmed). 4. Set OE to "0", BS2 to "1", and BS1 to "0". The status of the Extended Fuse bits can now be read at DATA ("0" means programmed). 5. Set OE to "0", BS2 to "0" and BS1 to "1". The status of the Lock bits can now be read at DATA ("0" means programmed). 6. Set OE to "1". Figure 4-103. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
Fuse Low Byte 0
Extended Fuse Byte BS2 Lock Bits
1
0 DATA
0
1
Fuse High Byte BS2
1
BS1
4.22.7.13
Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to "Programming the Flash" on page 256 for details on Command and Address loading): 1. A: Load Command "0000 1000 b". 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to "0", and BS to "0". The selected Signature byte can now be read at DATA. 4. Set OE to "1".
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4.22.7.14
Reading the 8 MHz RC Oscillator Calibration Byte The algorithm for reading the 8 MHz RC Oscillator Calibration byte is as follows (refer to "Programming the Flash" on page 256 for details on Command and Address loading): 1. A: Load Command "0000 1000 b". 2. B: Load Address Low Byte, 0x00. 3. Set OE to "0", and BS1 to "1". The 8 MHz RC Oscillator Calibration byte can now be read at DATA. 4. Set OE to "1".
4.22.7.15
Reading the Temperature Sensor Parameter Bytes The algorithm for reading the Temperature Sensor parameter bytes is as follows (refer to "Programming the Flash" on page 256 for details on Command and Address loading): 1. A: Load Command "0000 1000 b". 2. B: Load Address Low Byte, 0x0003 or 0x0005. 3. Set OE to "0", and BS1 to "1". The Temperature Sensor parameter byte can now be read at DATA. 4. Set OE to "1".
4.22.8
Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed.
Note: In Table 4-78, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.
Figure 4-104. Serial Programming and Verify(1)
+2.7 - +5.5V Vcc MOSI MISO SCK PA4 PA2 PA5
RESET / PB7 GND
Note:
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin
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Table 4-78. Pin Mapping Serial Programming
Pin Name PA4 PA2 PA5 I/O I O I Function Serial Data In Serial Data Out Serial Clock
Symbol MOSI MISO SCK
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz 4.22.8.1 Serial Programming Algorithm When writing serial data to the Atmel(R) ATtiny87/167, data is clocked on the rising edge of SCK. When reading data from the Atmel ATtiny87/167, data is clocked on the falling edge of SCK. See Figure 4-104 and Figure 4-105 for timing details. To program and verify the Atmel ATtiny87/167 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 4-80 on page 265): 1. Power-up sequence: Apply power between Vcc and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to "0". 2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 5LSB of the address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction with the 6MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least t WD_FLASH before issuing the next page. (See Table 4-79) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming.
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5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least t WD_EEPROM before issuing the next byte. (See Table 4-79) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 6MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least t WD_EEPROM before issuing the next page (See Table 4-74). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to "1". Turn Vcc power off. Table 4-79. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol t WD_FLASH t WD_EEPROM t WD_ERASE t WD_FUSE Minimum Wait Delay 4.5ms 4.0ms 4.0ms 4.5ms
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4.22.8.2 Serial Programming Instruction set Table 4-80 on page 265 and Figure 4-105 on page 266 describes the Instruction set
Table 4-80.
Serial Programming Instruction Set
Instruction Format Byte 1 0xAC 0xAC 0xF0 0x4D 0x48 0x40 0xC1 0x28 0x20 0xA0 0x58 0x30 0x50 0x58 0x50 0x38 0x4C 0xC0 0xC2 0xAC 0xAC 0xAC 0xAC Byte 2 0x53 0x80 0x00 0x00 add. MSB add. MSB 0x00 add. MSB add. MSB 0x00 0x00 0x00 0x00 0x08 0x08 0x00 add. MSB 0x00 0x00 0xE0 0xA0 0xA8 0xA4 Byte 3 0x00 0x00 0x00 Extended add. add. LSB add. LSB 0000 000aa b add. LSB add. LSB 00aa aaaa 0x00 0000 000aa 0x00 0x00 0x00 0x00 add. LSB 00aa aaaa b 00aa aa00 b 0x00 0x00 0x00 0x00 Byte4 0x00 0x00 data byte out 0x00 high data byte in low data byte in data byte in high data byte out low data byte out data byte out data byte out data byte out data byte out data byte out data byte out data byte out 0x00 data byte in 0x00 data byte in data byte in data byte in data byte in
Instruction/Operation Programming Enable Chip Erase (Program Memory/EEPROM) Poll RDY/BSY Load Instructions Load Extended Address byte(1) Load Program Memory Page, High byte Load Program Memory Page, Low byte Load EEPROM Memory Page (page access) Read Instructions Read Program Memory, High byte Read Program Memory, Low byte Read EEPROM Memory Read Lock bits Read Signature Byte Read Fuse bits Read Fuse High bits Read Extended Fuse Bits Read Calibration Byte Write Instructions
(6)
Write Program Memory Page Write EEPROM Memory Write EEPROM Memory Page (page access) Write Lock bits Write Fuse bits Write Fuse High bits Write Extended Fuse Bits Notes: 2. a = address
1. Not all instructions are applicable for all parts. 3. Bits are programmed `0', unprogrammed `1'. 4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (`1'). 5. Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See http://www.atmel.com/avr for Application Notes regarding programming and programmers.
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If the LSB in RDY/BSY data byte out is `1', a programming operation is still pending. Wait until this bit returns `0' before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 4-105 on page 266. Figure 4-105. Serial Programming Instruction Example
Serial Programming Instruction
Load Program Memory Page (High/Low Byte) / Load EEPROM Memory Page (Page Access) Byte 1 Byte 2
Addr. MSB
Bit 15 B
Write Program Memory Page / Write EEPROM Memory Page Byte 4 Byte 1 Byte 2
Addr. MSB
0 Bit 15 B
Byte 3
Addr. LSB
Byte 3
Addr. MSB
0
Byte 4
Page Offset
Page Buffer
Page 0
Page 1
Page 2
Page Number
Page N-1
Program Memory / EEPROM Memory
4.22.9
Serial Programming Characteristics
Figure 4-106. Serial Programming Waveforms
SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK)
SAMPLE
MSB
LSB
MSB
LSB
For characteristics of the SPI module, see Section 4.23.10 "SPI Timing Characteristics" on page 276.
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4.23 Electrical Characteristics
Note: All Characteristics contained in this data sheet are based on simulation and characterization of Atmel(R) ATtiny87/167 AVR(R) microcontrollers manufactured in a typical process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual Automotive silicon.
4.23.1
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Operating Temperature Storage Temperature Voltage on any Pin except RESET with respect to Ground Voltage on RESET with respect to Ground Voltage on Vcc with respect to Ground DC Current per I/O Pin DC Current Vcc and GND Pins Injection Current at VCC = 0V to 5V Notes:
(2)
Value -40 to +125 -65 to +150 -0.5 to Vcc + 0.5 -0.5 to +13.0 -0.5 to 6.0 40.0 200.0 5
(1)
Unit C C V V V mA mA mA
1. Maximum current per port = 30mA 2. Functional corruption may occur
4.23.2
DC Characteristics
Test Conditions Except XTAL1 and RESET pins XTAL1 pin - External Clock Selected RESET pin RESET pin as I/O Except XTAL1 and RESET pins XTAL1 pin - External Clock Selected RESET pin RESET pin as I/O Symbol VIL VIL1 VIL2 VIL3 VIH VIH1 VIH2 VIH3 VOL VOH IIL IIH RRST Rpu 30 20 4.3 2.5 Min. -0.5 -0.5 -0.5 -0.5 0.7 Vcc
(3)
TA = -40C to +125C, Vcc = 2.7V to 5.5V (unless otherwise noted) Parameters Typ.(1) Max. 0.2 Vcc
(2)
Unit V V V V V V V V V V
Input Low Voltage
0.1 Vcc(2) 0.2 Vcc(2) 0.2 Vcc
(2)
Vcc + 0.5 Vcc + 0.5 Vcc + 0.5 Vcc + 0.5 0.6 0.5
Input High Voltage
0.8 Vcc(3) 0.9 Vcc(3) 0.7 Vcc
(3)
Output Low Voltage (Ports A, B,)
(4)
IOL = 10mA, Vcc = 5V IOL = 5mA, Vcc = 3V IOH = -10mA, Vcc = 5V IOH = -5mA, Vcc = 3V Vcc = 5.5V, pin low (absolute value) Vcc = 5.5V, pin high (absolute value)
Output High Voltage(5) (Ports A, B) Input Leakage Current I/O Pin Input Leakage Current I/O Pin Reset Pull-up Resistor I/O Pin Pull-up Resistor
< 0.05 < 0.05
1 1 60 50
A A k k
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4.23.2
DC Characteristics (Continued)
Test Conditions 16MHz, Vcc = 5V 8MHz, Vcc = 5V 8MHz, Vcc = 3V 4MHz, Vcc = 3V 16MHz, Vcc = 5V Symbol Min. Typ.(1) 10 5.5 2.8 1.8 3.5 ICC 1.8 1 0.5 7 0.18 5 0.15 VACIO IACLK tACID -10 -50 170 180 +10 Max. 13 7.0 3.5 2.5 5.0 2.5 1.5 0.8 100 70 70 45 +40 +50 Unit mA mA mA mA mA mA mA mA A A A A mV nA ns ns
TA = -40C to +125C, Vcc = 2.7V to 5.5V (unless otherwise noted) Parameters Power Supply Current(6) Active Mode (external clock)
Power Supply Current(6) Idle Mode (external clock)
8MHz, Vcc = 5V 8MHz, Vcc = 3V 4MHz, Vcc = 3V WDT enabled, Vcc = 5V
Power Supply Current(7) Power-down Mode
WDT disabled, Vcc = 5V WDT enabled, Vcc = 3V WDT disabled, Vcc = 3V Vcc = 5V Vin = Vcc/2 Vcc = 5V Vin = Vcc/2
Analog Comparator Input Offset Voltage Analog Comparator Input Leakage Current
Analog Comparator Propagation Vcc = 2.7V Delay Common Mode Vcc/2 Vcc = 5.0V Notes:
1. "Typ.", typical values at 25C. Maximum values are characterized values and not test limits in production. 2. "Max." means the highest value where the pin is guaranteed to be read as low. 3. "Min." means the lowest value where the pin is guaranteed to be read as high. 4. Although each I/O port can sink more than the test conditions (10mA at Vcc = 5V, 5mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: The sum of all IOL, for all ports, should not exceed 120mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 5. Although each I/O port can source more than the test conditions (10mA at Vcc = 5V, 5mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: The sum of all IOH, for all ports, should not exceed 120mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 6. Values using methods described in Section 4.6.8 "Minimizing Power Consumption" on page 68. Power Reduction is enabled (PRR = 0xFF) and there is no I/O drive. 7. BOD Disabled.
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4.23.3 Speed Grades Figure 4-107. Maximum Frequency versus Vcc, Atmel(R) ATtiny87/167
Frequency 16 MHz
8 MHz Safe Operating Area Voltage 2.7V 4.5V 5.5V
4.23.4 4.23.4.1
Clock Characteristics Calibrated Internal RC Oscillator Accuracy Table 4-81.
Factory Calibration
Calibration and Accuracy of Internal RC Oscillator
Frequency 8.0MHz Vcc 3V Temperature 25C Accuracy 2%
4.23.4.2
External Clock Drive Waveforms Figure 4-108. External Clock Drive Waveforms
V IH1 V IL1
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4.23.4.3
External Clock Drive
Table 4-82.
External Clock Drive
Vcc = 2.7 - 5.5V Vcc = 4.5 - 5.5V Min. 0 62.5 25 25 1.6 1.6 2 0.5 0.5 2 Max. 16 Units MHz ns ns ns ms ms %
Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL
Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Change in period from one clock cycle to the next
Min. 0 125 50 50
Max. 8
tCLCL
4.23.5 RESET Characteristics
Table 4-83.
Symbol VRST tRST VBG tBG IBG
External Reset Characteristics
Parameter RESET Pin Threshold Voltage Minimum pulse width on RESET Pin Bandgap reference voltage Bandgap reference start-up time Bandgap reference current consumption Condition VCC = 5V VCC = 5V VCC = 2.7V, TA = 25C VCC = 2.7V, TA = 25C VCC = 2.7V, TA = 25C 1.0 1.1 40 15 Min 0.1 Vcc Typ Max 0.9 Vcc 2.5 1.2 70 Unit V s V s A
Table 4-84.
Parameter
Power On Reset Characteristics
Symbol Min Typ 1.0 0.9 Max 1.4 1.3 0.4 -0.1 0.01 0.1 Vcc 0.9 Vcc Unit V V V V V/ms V
Power-on Reset Threshold Voltage (rising) Power-on Reset Threshold Voltage (falling)(1) VCC Max. start voltage to ensure internal Power-on Reset signal VCC Min. start voltage to ensure internal Power-on Reset signal VCC Rise Rate to ensure Power-on Reset RESET Pin Threshold Voltage Note:
VPOT VPORMAX VPORMIN VCCRR VRST
1. Before rising, the supply has to be between VPORMIN and VPORMAX to ensure a Reset.
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Table 4-85. BODLEVEL Fuse Coding
Min. VBOT(1) 1.7 2.5 4.1 Typ. VBOT 1.8 2.7 4.3 Max. VBOT 2.0 2.9 4.5 V Reserved Units 1 1 1b 1 1 0b 1 0 1b 1 0 0b 0 1 1b 0 1 0b 0 0 1b 0 0 0b Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to Vcc = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before Vcc drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 101 for Low Operating Voltage and BODLEVEL = 100 for High operating Voltage. BOD Disabled
BODLEVEL 2:0 Fuses
Table 4-86.
Parameter
Brown-out Characteristics
Symbol VHYST tBOD Min. Typ. 80 2 Max. Units mV s
Brown-out Detector Hysteresis Min Pulse Width on Brown-out Reset
4.23.6
Internal Voltage Characteristics
Table 4-87.
Symbol VBG tBG IBG
Internal Voltage Reference Characteristics
Parameter Bandgap reference voltage Bandgap reference start-up time Bandgap reference current consumption Condition Vcc = 4.5 TA = 25C Vcc = 4.5 TA = 25C Vcc = 4.5 TA = 25C Min. 1.0 Typ. 1.1 40 10 Max. 1.2 70 Units V s A
4.23.7
Current Source Characteristics
Table 4-88.
Symbol IISRC tISRC
Current Source Characteristics
Parameter Current Condition Vcc = 2.7 V / 5.5 V T = -40C / +125C Vcc = 4.5 TA = 25C Min. 94 60 Typ. Max. 106 Units A s
Current Source start-up time
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4.23.8
ADC Characteristics ADC Characteristics, Single Ended Channels (-40C/+125C)
Condition Single Ended Conversion Vcc = 4V, VRef = 4V, ADC clock = 200kHz Vcc = 4V, VRef = 4V, ADC clock = 200kHz Vcc = 4V, VRef = 4V, ADC clock = 200kHz Vcc = 4V, VRef = 4V, ADC clock = 200kHz Vcc = 4V, VRef = 4V, ADC clock = 200kHz -6.0 -3.5 2.56 38.5 2.4 2.56 32 100 2.7 Min Typ 10 2.0 0.6 0.3 -2.5 1.5 3.5 2.0 0.8 2.0 3.5 AVcc Max Units Bits LSB LSB LSB LSB LSB V kHz V k M
Table 4-89.
Symbol Parameter Resolution TUE INL DNL Absolute accuracy Integral Non Linearity Differential Non Linearity Gain error Offset error VREF VINT RREF RAIN Ref voltage Input bandwidth Internal voltage Reference input resistance Analog input resistance
Table 4-90.
Symbol
ADC Characteristics, Differential Channels (-40C/+125C)
Parameter Resolution Condition Differential conversion Gain = 8x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 20x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 8x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 20x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 8x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 20x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 8x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 20x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Min Typ 8 1.0 3.0 Max Units
1.5
3.5 LSB
TUE
Absolute accuracy
2.0
4.5
2.0
6.0
0.2
1.0
0.4
1.5 LSB
INL
Integral Non Linearity
0.5
2.0
1.6
5.0
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Table 4-90.
Symbol
ADC Characteristics, Differential Channels (-40C/+125C) (Continued)
Parameter Condition Gain = 8x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 20x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 8x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 20x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 8x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 20x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 8x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 20x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 8x or 20x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz Gain = 8x or 20x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200kHz -3.0 Min Typ 0.3 Max 0.8 Units
0.3
0.8 LSB
DNL
Differential Non Linearity
0.4
0.8
0.6
1.6
1.0
3.0
-4.0
1.5
4.0 LSB
Gain error
-5.0
-2.5
0.0
-4.0
-0.5
4.0
-2.0
0.5
2.0 LSB
Offset error
-2.0 2.56 -VREF/Gain Vcc - 0.3
0.5
2.0 AVCC - 0.5 +VREF/Gain Vcc + 0.3 AVcc +511 V V V V LSB kHz 2.7 V k M
VREF VDIFF AVcc VIN
Reference voltage Input differential voltage Analog supply voltage Input voltage ADC conversion output Input bandwidth Differential conversion Differential conversion
0 -511 4 2.4 2.56 32 100
VINT RREF RAIN
Internal voltage reference Reference input resistance Analog input resistance
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4.23.9
Parallel Programming Characteristics
Figure 4-109. Parallel Programming Timing, Including some General Timing Requirements
t XLWL XTAL1 t DVXH Data & Contol (DATA, XA0, XA1/BS2, PAGEL/BS1) t XHXL
t XLDX
t BVPH
t PLBX
t BVWL t WLWH
t WLBX
WR
t PLWL
t RLRH
RDY/BSY t WLRH
Figure 4-110. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE)
t XLXH
LOAD DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
XTAL1
PAGEL/BS1
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0 XA1/BS2
Note:
1. The timing requirements shown in Figure 4-109 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation.
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Figure 4-111. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)
LOAD ADDRESS (LOW BYTE)
t XLOL
READ DATA (LOW BYTE)
READ DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
XTAL1
t BVDV
PAGEL/BS1
t OLDV
OE
t OHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1/BS2
Note:
1. The timing requirements shown in Figure 4-109 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
Table 4-91.
Symbol VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tBVPH tPLBX tWLBX tPLWL tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL tBVDV tOLDV tOHDZ Notes:
Parallel Programming Characteristics, VCC = 5V 10%
Parameter Programming Enable Voltage Programming Enable Current Data and Control Valid before XTAL1 High XTAL1 Low to XTAL1 High XTAL1 Pulse Width High Data and Control Hold after XTAL1 Low XTAL1 Low to WR Low BS1 Valid before PAGEL High BS1 Hold after PAGEL Low BS2/1 Hold after WR Low PAGEL Low to WR Low BS1 Valid to WR Low WR Pulse Width Low WR Low to RDY/BSY Low WR Low to RDY/BSY High XTAL1 Low to OE Low BS1 Valid to DATA valid OE Low to DATA Valid OE High to DATA Tri-stated
(1)
Min 11.5 67 200 150 67 0 67 67 67 67 67 150 0 3.7 7.5 0 0
Typ
Max 12.5 250
Units V A ns ns ns ns ns ns ns ns ns ns ns
1 4.5 9 250 250 250
s ms ms ns ns ns ns
WR Low to RDY/BSY High for Chip Erase(2)
1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command.
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4.23.10
SPI Timing Characteristics See Figure 4-112 and Figure 4-113 for details.
Table 4-92.
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Note:
SPI Timing Parameters
Description SCK period SCK high/low Rise/Fall time Setup Hold Out to SCK SCK to out SCK to out high SS low to out SCK period SCK high/low
(1)
Mode Master Master Master Master Master Master Master Master Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave
Min.
Typ. See Table 4-43 50% duty cycle 3.6 10 10 0.5 * tsck 10 10 15
Max.
Unit
ns
4 * tck 2 * tck 1.6 10 tck 15 20 10 2 * tck ns s
Rise/Fall time Setup Hold SCK to out SCK to SS high SS high to tri-state SS low to SCK
In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12MHz - 3 tCLCL for fCK >12MHz
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Figure 4-112. SPI Interface Timing Requirements (Master Mode)
SS
6 1
SCK (CPOL = 0)
2 2
SCK (CPOL = 1)
4 5 3
MISO (Data Input)
MSB 7
...
LSB 8
MOSI (Data Output)
MSB
...
LSB
Figure 4-113. SPI Interface Timing Requirements (Slave Mode)
18
SS
9 10 16
SCK (CPOL = 0)
11 11
SCK (CPOL = 1)
13 14 12
MOSI (Data Input)
MSB 15
...
LSB 17
MISO (Data Output)
MSB
...
LSB
X
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4.24
Decoupling Capacitors
The operating frequency (i.e. system clock) of the processor determines in 95% of cases the value needed for microcontroller decoupling capacitors. The hypotheses used as first evaluation for decoupling capacitors are: * The operating frequency (fop) supplies itself the maximum peak levels of noise. The main peaks are located at fop and 2 x fop. * An SMC capacitor connected to 2 micro-vias on a PCB has the following characteristics: - 1.5 nH from the connection of the capacitor to the PCB, - 1.5 nH from the capacitor intrinsic inductance. Figure 4-114. Capacitor Description
1.5 nH 0.75 nH Capacitor 0.75 nH PCB
According to the operating frequency of the product, the decoupling capacitances are chosen considering the frequencies to filter, fop and 2 x fop. The relation between frequencies to cut and decoupling characteristics are defined by:
1 fop = --------------------2 LC 1 1 2 x fop = --------------------2 LC 2
and
where: - L: the inductance equivalent to the global inductance on the Vcc/GND lines. - C1 & C2: decoupling capacitors (C1 = 4 x C2). Then, in normalized value range, the decoupling capacitors become: Table 4-93. Decoupling Capacitors versus Frequency
C1 33nF 56nF 82nF 120nF 220nF 560nF C2 10nF 15nF 22nF 33nF 56nF 120nF 16MHz 12MHz 10MHz 8MHz 6MHz 4MHz
fop, Operating Frequency
These decoupling capacitors must to be implemented as close as possible to each pair of power supply pins: - 16-17 for logic sub-system, - 5-6 for analogical sub-system. Nevertheless, a bulk capacitor of 10-47F is also needed on the power distribution network of the PCB, near the power source. For further information, please refer to Application Notes AVR040 "EMC Design Considerations" and AVR042 "Hardware Design Considerations"on the Atmel web site.
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4.25 Typical Characteristics
The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*Vcc*f where CL = load capacitance, Vcc = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 4.25.1 Active Supply Current Figure 4-115. Active Supply Current versus Low Frequency (0.1 - 1.0MHz)
ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY
PRR = 0xFF / ATD ON 1.4 1.2 1 ICC (mA) 0.8 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1
6 5.5 5 4.5 4 3.6 3.3 3 2.7 2.4 2.1 2 1.8 1.6
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Figure 4-116. Active Supply Current versus Frequency ( 1MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
PRR=0xFF / ATD ON 16 14 12 10 ICC (mA) 8 6 4 2 0 0 2 4 6 8 10 Frequency (MHz) 12 14 16 18 20
6 5.5 5 4.5 4 3.6 3.3 3 2.7 2.4
Figure 4-117. Active Supply Current versus VCC (Internal RC Oscillator, 8MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR 8MHz (No ATD influence) 9 8 7 6 ICC (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 V CC (V) 4 4.5 5 5.5
150 125 85 25 -40
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Figure 4-118. Active Supply Current versus VCC (Internal RC Oscillator, 128kHz)
ACTIVE SUPPLY CURRENT vs. V CC
INTERNAL RC OSCILLATOR 128 KHz / ATD ON 0.2 0.18 0.16 0.14 ICC (mA) 0.12 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 V CC (V) 4 4.5 5 5.5
150 125 85 25 -40
4.25.2
Idle Supply Current Figure 4-119. Idle Supply Current versus Frequency ( 1MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
NO POWER REDUCTION ENABLED 10 9 8 7
6 5.5 5 4.5 4 3.6 3.3 3 2.7
0 2 4 6 8 10 Frequency (MHz) 12 14 16 18 20
ICC (mA)
6 5 4 3 2 1 0
2.4
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Figure 4-120. Idle Supply Current versus VCC (Internal RC Oscillator, 8MHz)
IDLE SUPPLY CURRENT vs. V CC
INTERNAL RC OSCILLATOR 8MHz 3
2.5
2 ICC (mA)
150 125 85 25 -40
1.5
1
0.5
0 1.5 2 2.5 3 3.5 V CC (V) 4 4.5 5 5.5
Figure 4-121. Idle Supply Current versus 5VCC (Internal RC Oscillator, 128kHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR 125 KHz 0.08 0.07 0.06 0.05 ICC (mA) 0.04 0.03 0.02 0.01 0 1.5 2 2.5 3 3.5 V CC (V) 4 4.5 5 5.5
150 125 85 25 -40
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4.25.3 Supply Current of I/O modules The table below can be used to calculate the additional current consumption for the different I/O modules Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See Section 4.6.9.3 "PRR - Power Reduction Register" on page 70 for details.
Table 4-94.
Module LIN/UART SPI TIMER-1 TIMER-0 USI ADC
Additional Current Consumption for the Different I/O Modules (Absolute Values)
Vcc = 5.0V Freq. = 16MHz 0.77 0.31 0.28 0.41 0.14 0.48 Vcc = 5.0V Freq. = 8MHz 0.37 0.14 0.13 0.20 0.05 0.22 Vcc = 3.0V Freq. = 8MHz 0.20 0.08 0.08 0.10 0.04 0.10 Vcc = 3.0V Freq. = 4MHz 0.10 0.04 0.04 0.05 0.02 0.05 Unit mA mA mA mA mA mA
4.25.4
Power-down Supply Current Figure 4-122. Power-down Supply Current versus VCC (Watchdog Timer Disabled)
POWER-DOWN SUPPLY CURRENT vs. V CC
WATCHDOG TIMER DISABLED 30
25
20 ICC (uA)
150 125 85 25 -40
15
10
5
0 1.5 2 2.5 3 3.5 V CC (V) 4 4.5 5 5.5
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Figure 4-123. Power-down Supply Current versus VCC (Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED 40 35 30 25
ICC (uA)
150 125 85 25 -40
20 15 10 5 0 1.5 2 2.5 3 3.5 V CC (V) 4 4.5 5 5.5
4.25.5
Pin Pull-up Figure 4-124. I/O Pin Pull-up Resistor Current versus Input Voltage (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7 V 90 80 70 60 50 IOP (uA) 40 30 20 10 0 -10 0 0.5 1 1.5 V OP (V) 2 2.5 3
150 125 85 25 -40
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Figure 4-125. I/O Pin pull-up Resistor Current versus Input Voltage (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5.0 V 160 140 120 100
IOP (uA)
150 125 85 25 -40
80 60 40 20 0 0 -20 V OP (V) 1 2 3 4 5 6
Figure 4-126. Reset Pull-up Resistor Current versus Reset Pin Voltage (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 2.7 V 70 60 50
150
IRESET (uA)
40 30 20 10 0 0 -10 V RESET (V) 0.5 1 1.5 2 2.5 3
125 85 25 -40
Figure 4-127. Reset Pull-up Resistor Current versus Reset Pin Voltage (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 5.0 V 120 100 80 IRESET (uA) 60 40 20 0 0 -20 V RESET (V) 1 2 3 4 5 6
150 125 85 25 -40
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4.25.6
Pin Driver Strength Figure 4-128. I/O Pin Output Voltage versus Sink Current (VCC = 3V)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
Vcc = 3.0 V 2 1.8 1.6 1.4 1.2 V OL (V) 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 IOL (mA) 10 12 14 16 18
150 125 85 25 -40
Figure 4-129. I/O Pin Output Voltage versus Sink Current (VCC = 5V)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
Vcc = 5.0V 1.2
1
150
0.8 V OL (V)
125 85 25 -40
0.6
0.4
0.2
0 0 5 10 IOL (mA) 15 20 25
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Figure 4-130. I/O Pin Output Voltage versus Source Current (VCC = 3V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
Vcc = 3.0 V
3
2.5
150
2
125 85 25 -40
V OH (V)
1.5
1
0.5
0 0 2 4 6 8 10 IOH (mA) 12 14 16 18 20
Figure 4-131. I/O Pin Output Voltage versus Source Current (VCC = 5V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
V cc = 5.0 V 5.1 4.9 4.7 4.5 4.3 4.1 3.9 3.7 0 2 4 6 8 10 IOH (mA) 12 14 16 18 20
150 125 85 25 -40
V OH (V)
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4.25.7
Internal Oscillator Speed Figure 4-132. Calibrated 8.0MHz RC Oscillator Frequency versus Vcc
Figure 4-133. Calibrated 8.0MHz RC Oscillator Frequency versus OSCCAL Value
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4.25.8 Current Consumption in Reset Figure 4-134. Reset Supply Current versus Vcc, Frequencies 0.1 - 1.0MHz (Excluding Current Through the Reset Pull-up)
RESET SUPPLY CURRENT vs. V CC
EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.3
0.25
6 5.5 5 4.5 4 3.6 3.3 3 2.7 2.4 2.1 2 1.8 1.6
0.2
ICC (mA)
0.15
0.1
0.05
0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1
Figure 4-135. Reset Supply Current versus Vcc, Frequencies 1MHz (Excluding Current Through the Reset Pull-up)
RESET SUPPLY CURRENT vs. V CC
EXCLUDING CURRENT THROUGH THE RESET PULLUP 4.5 4 3.5 3 ICC (mA) 2.5 2 1.5 1 0.5 0 0 2 4 6 8 10 Frequency (MHz) 12 14 16 18 20
6 5.5 5 4.5 4 3.6 3.3 3 2.7 2.4 2.1 2 1.8 1.6
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4.26
Register Summary
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5)
290
Atmel ATA6616/ATA6617
9132D-AUTO-12/10
Atmel ATA6616/ATA6617
4.26 Register Summary (Continued)
Name Reserved Reserved LINDAT LINSEL LINIDR LINDLR LINBRRH LINBRRL LINBTR LINERR LINENIR LINSIR LINCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved USIPP USIBR USIDR USISR USICR Reserved ASSR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved - EXCLK AS0 TCN0UB OCR0AUB - TCR0AUB TCR0BUB page 127 USIB7 USID7 USISIF USISIE USIB6 USID6 USIOIF USIOIE USIB5 USID5 USIPF USIWM1 USIB4 USID4 USIDC USIWM0 USIB3 USID3 USICNT3 USICS1 USIB2 USID2 USICNT2 USICS0 USIB1 USID1 USICNT1 USICLK USIPOS USIB0 USID0 USICNT0 USITC page 185 page 181 page 181 page 182 page 183 LDATA7 - LP1 LTXDL3 - LDIV7 LDISR LABORT - LIDST2 LSWRES LDATA6 - LP0 LTXDL2 - LDIV6 - LTOERR - LIDST1 LIN13 LDATA5 - LDATA4 - LDATA3 / LAINC LID3 LRXDL3 LDIV11 LDIV3 LBT3 LSERR LENERR LERR LENA LDATA2 LINDX2 LID2 LRXDL2 LDIV10 LDIV2 LBT2 LPERR LENIDOK LIDOK LCMD2 LDATA1 LINDX1 LID1 LRXDL1 LDIV9 LDIV1 LBT1 LCERR LENTXOK LTXOK LCMD1 LDATA0 LINDX0 LID0 LRXDL0 LDIV8 LDIV0 LBT0 LBERR LENRXOK LRXOK LCMD0 page 210 page 210 page 209 page 209 page 208 page 208 page 208 page 207 page 206 page 205 page 204 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
Address (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9)
LID5/LDL1 LID4/LDL0 LTXDL1 - LDIV5 LBT5 LOVERR - LIDST0 LCONF1 LTXDL0 - LDIV4 LBT4 LFERR - LBUSY LCONF0
291
9132D-AUTO-12/10
4.26
Register Summary (Continued)
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L TCCR1D TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 OCR1B15 OCR1B7 OCR1A15 OCR1A7 ICR115 ICR17 TCNT115 TCNT17 OC1BX FOC1A ICNC1 COM1A1 - ADC7D / AIN1D OCR1B14 OCR1B6 OCR1A14 OCR1A6 ICR114 ICR16 TCNT114 TCNT16 OC1BW FOC1B ICES1 COM1A0 - ADC6D / AIN0D OCR1B13 OCR1B5 OCR1A13 OCR1A5 ICR113 ICR15 TCNT113 TCNT15 OC1BV - - COM1B1 - ADC5D OCR1B12 OCR1B4 OCR1A12 OCR1A4 ICR112 ICR14 TCNT112 TCNT14 OC1BU - WGM13 COM1B0 - ADC4D OCR1B11 OCR1B3 OCR1A11 OCR1A3 ICR111 ICR13 TCNT111 TCNT13 OC1AX - WGM12 - - ADC3D OCR1B10 OCR1B2 OCR1A10 OCR1A2 ICR110 ICR12 TCNT110 TCNT12 OC1AW - CS12 - ADC10D ADC2D OCR1B9 OCR1B1 OCR1A9 OCR1A1 ICR19 ICR11 TCNT19 TCNT11 OC1AV - CS11 WGM11 ADC9D ADC1D OCR1B8 OCR1B0 OCR1A8 OCR1A0 ICR18 ICR10 TCNT18 TCNT10 OC1AU - CS10 WGM10 ADC8D ADC0D page 161 page 161 page 161 page 161 page 162 page 162 page 161 page 161 page 161 page 160 page 159 page 157 page 234 page 234, page 238 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
Address (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E)
292
Atmel ATA6616/ATA6617
9132D-AUTO-12/10
Atmel ATA6616/ATA6617
4.26 Register Summary (Continued)
Name Reserved ADMUX ADCSRB ADCSRA ADCH ADCL AMISCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved TIMSK1 TIMSK0 Reserved PCMSK1 PCMSK0 Reserved EICRA PCICR Reserved OSCCAL Reserved PRR CLKSELR CLKCSR CLKPR WDTCR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR - - - - RWWSB - BODS - SIGRD - BODSE - CTPB - PUD - RFLB - - WDRF PGWRT - - BORF PGERS - - EXTRF SPMEN - - PORF page 69, page 99 page 75 page 244 - - CLKCCE CLKPCE WDIF I SP15 SP7 - COUT - - WDIE T SP14 SP6 PRLIN CSUT1 - - WDP3 H SP13 SP5 PRSPI CSUT0 CLKRDY - WDCE S SP12 SP4 PRTIM1 CSEL3 CLKC3 CLKPS3 WDE V SP11 SP3 PRTIM0 CSEL2 CLKC2 CLKPS2 WDP2 N SP10 SP2 PRUSI CSEL1 CLKC1 CLKPS1 WDP1 Z SP9 SP1 PRADC CSEL0 CLKC0 CLKPS0 WDP0 C SP8 SP0 page 70 page 64 page 62 page 62 page 80 page 33 page 33 page 33 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 page 61 - - - - - - - - ISC11 - ISC10 - ISC01 PCIE1 ISC00 PCIE0 page 86 page 88 PCINT15 PCINT7 PCINT14 PCINT6 PCINT13 PCINT5 PCINT12 PCINT4 PCINT11 PCINT3 PCINT10 PCINT2 PCINT9 PCINT1 PCINT8 PCINT0 page 89 page 89 - - - - ICIE1 - - - - - OCIE1B - OCIE1A OCIE0A TOIE1 TOIE0 page 162 page 128 REFS1 BIN ADEN - / ADC9 ADC7 / ADC1 - REFS0 ACME ADSC - / ADC8 ADC6 / ADC0 - ADLAR ACIR1 ADATE - / ADC7 ADC5 / - MUX4 ACIR0 ADIF - / ADC6 ADC4 / - MUX3 - ADIE - / ADC5 ADC3 / - MUX2 ADTS2 ADPS2 - / ADC4 ADC2 / AREFEN MUX1 ADTS1 ADPS1 ADC9 / ADC3 ADC1 / XREFEN MUX0 ADTS0 ADPS0 ADC8 / ADC2 ADC0 / ISRCEN page 229 page 233, page 237 page 231 page 232 page 232 page 213 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
Address (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54)
293
9132D-AUTO-12/10
4.26
Register Summary (Continued)
Name SMCR Reserved DWDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved OCR0A TCNT0 TCCR0B TCCR0A Reserved GTCCR EEARH(1) EEARL EEDR EECR GPIOR0 EIMSK EIFR PCIFR Reserved Reserved Reserved Reserved TIFR1 TIFR0 Reserved Reserved PORTCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved - - BBMB BBMA - - PUDB PUDA page 99 - - - - ICF1 - - - - - OCF1B - OCF1A OCF0A TOV1 TOV0 page 129 page 129 TSM - EEAR7 EEDR7 - GPIOR07 - - - - - EEAR6 EEDR6 - GPIOR06 - - - - - EEAR5 EEDR5 EEPM1 GPIOR05 - - - - - EEAR4 EEDR4 EEPM0 GPIOR04 - - - - - EEAR3 EEDR3 EERIE GPIOR03 - - - - - EEAR2 EEDR2 EEMPE GPIOR02 - - - PSR0 - EEAR1 EEDR1 EEPE GPIOR01 INT1 INTF1 PCIF1 PSR1 EEAR8 EEAR0 EEDR0 EERE GPIOR00 INT0 INTF0 PCIF0 page 129, page 132 page 45 page 45 page 46 page 46 page 47 page 87 page 88 page 89 OCR0A7 TCNT07 FOC0A COM0A1 OCR0A6 TCNT06 - COM0A0 OCR0A5 TCNT05 - - OCR0A4 TCNT04 - - OCR0A3 TCNT03 - - OCR0A2 TCNT02 CS02 - OCR0A1 TCNT01 CS01 WGM01 OCR0A0 TCNT00 CS00 WGM00 page 127 page 126 page 126 page 124 SPD7 SPIF SPIE GPIOR27 GPIOR17 SPD6 WCOL SPE GPIOR26 GPIOR16 SPD5 - DORD GPIOR25 GPIOR15 SPD4 - MSTR GPIOR24 GPIOR14 SPD3 - CPOL GPIOR23 GPIOR13 SPD2 - CPHA GPIOR22 GPIOR12 SPD1 - SPR1 GPIOR21 GPIOR11 SPD0 SPI2X SPR0 GPIOR20 GPIOR10 page 171 page 171 page 169 page 47 page 47 DWDR7 ACD DWDR6 ACIRS DWDR5 ACO DWDR4 ACI DWDR3 ACIE DWDR2 ACIC DWDR1 ACIS1 DWDR0 ACIS0 page 241 page 237 Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 SM1 Bit 1 SM0 Bit 0 SE Page page 69
Address 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29)
294
Atmel ATA6616/ATA6617
9132D-AUTO-12/10
Atmel ATA6616/ATA6617
4.26 Register Summary (Continued)
Name Reserved Reserved Reserved PORTB DDRB PINB PORTA DDRA PINA PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 page 109 page 109 page 109 page 109 page 109 page 109 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
Address 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Notes:
1. Address bits exceeding EEAMSB (Table 4-74 on page 253) are don't care. 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 3. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR(R)s, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel(R) ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
295
9132D-AUTO-12/10
4.27
Instruction Set Summary
Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k k k k Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Operation Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF -Rd Rd 0x00 -Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd -1 Rd Rd * Rd Rd Rd Rd Rd 0xFF PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd -Rr Rd -Rr -C Rd -K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PC PC+k + 1 if (SREG(s) = 0) then PC PC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2
Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
296
Atmel ATA6616/ATA6617
9132D-AUTO-12/10
Atmel ATA6616/ATA6617
4.27 Instruction Set Summary (Continued)
Operands k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Description Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG Operation if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if (I = 1) then PC PC + k + 1 if (I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0) C,Rd(n+1)Rd(n),C Rd(7) Rd(7) C,Rd(n)Rd(n+1),C Rd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0) Rd(7..4),Rd(7..4) Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C 1 C 0 N 1 N 0 Z 1 Z 0 I 1 I 0 S 1 S 0 V 1 V 0 T 1 T 0 H 1 H 0 Flags None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H #Clocks 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Mnemonics BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH
BIT AND BIT-TEST INSTRUCTIONS
297
9132D-AUTO-12/10
4.27
Instruction Set Summary (Continued)
Operands Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Rd, Z Rd, Z+ Rd, P P, Rr Rr Rd Description Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Operation Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 1 1 1 N/A
Mnemonics MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK
DATA TRANSFER INSTRUCTIONS
MCU CONTROL INSTRUCTIONS
298
Atmel ATA6616/ATA6617
9132D-AUTO-12/10
Atmel ATA6616/ATA6617
5. Application
Figure 5-1. Typical LIN Slave Application
PVCC 100 nF C2 220pF PB7 PA4 PA3 10nF 33k WAKE
LIN
31
AGND AVCC PB7 PA7 PA6 PA5 PA4 LIN PB6 PB5 PB4 GND PA3
20
WAKE NTRIG EN
32
PVCC C1 100nF
19
PA3 PA4
10k
VS VBAT GND
VCC GND GND
Atmel ATA6616/17
WD_OSC NRES RXD TXD
VS VCC PVCC KL15 MODE TM
+ +
100nF 100nF 10F 10k 22F
GND
38
PB3 PB2
PB1
PB0
PA0
PA1
PA2
INH
13
1
12
PB7 PB7
47k KL15
PA2 PA5 PB7
1
PVCC PA4 INH 47k 10k
MODE
100nF
ISP
Note:
All open pins of the SiP can be used for application-specific purposes. AVR(R): Internal clock, TXD, RXD, NRES, EN and NTRIG connected for LIN Slave. The software must be appropriately programmed for the connection between the LIN-SBC and the AVR. SBC: LIN slave operation with watchdog enabled, 5V regulator and KL15 wake up RF emissions: best results for RF emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure 5-1.
299
9132D-AUTO-12/10
Figure 5-2.
Typical LIN Master Application
PVCC
100nF
22pF
C2
220pF PB7 PA4 PA3 10nF
LIN
XTAL
33k
WAKE
1k
31
PB7 PA7 PA6 PA5 PA4 AVCC PA3 LIN PB6 PB5 PB4 AGND GND
20
WAKE NTRIG EN
LIN Master pull-up
22pF
32
19
PA3 PA4
10k
VS VBAT GND
PVCC
C1
100nF
VCC GND GND GND
Atmel ATA6616/17
WD_OSC NRES RXD TXD PB1 PB0 PA0 PA1 PA2 INH
VS VCC PVCC KL15 MODE TM
+ +
100nF 100nF 10F 10k 22F
38
PB3 PB2
13
1
12
PB7 PB7
47k KL15
PA2 PA5 PB7
1
PVCC PA4 INH 47k 10k
MODE
100nF
ISP
Note:
All open pins of the SiP can be used for application-specific purposes. AVR(R): TXD, RXD, NRES and EN connected for LIN Master. The software must be appropriately programmed for the connection between the LIN-SBC and the AVR. System clock controlled by external crystal. LIN-SBC: Master application, 1k Master resistance connected via diode to VS, local wake up via pin WAKE; watchdog is enabled. RF emissions: best results for RF emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure 5-2.
300
Atmel ATA6616/ATA6617
9132D-AUTO-12/10
Atmel ATA6616/ATA6617
Figure 5-3. LIN Slave Application with Minimum External Components
100nF C2
PB7 PA3 220pF LIN
31
PB7 PA7 PA6 PA5 PA4 AGND AVCC PA3 LIN PB6 PB5 PB4 GND
20
WAKE NTRIG EN
32
PVCC
19
PA3
VS
C1
100nF
VCC GND GND
Atmel ATA6616/17
WD_OSC NRES RXD TXD
VS VCC PVCC KL15 MODE TM
VBAT
+
10F
PVCC 100nF
+
22F
GND
GND
38
PB3 PB2
PB1
PB0
PA0
PA1
PA2
INH
13
10k
1
12
PA2 PA5 PB7
1
PB7 PVCC PA4
ISP
Note:
All open pins of the SiP can be used for application-specific purposes. AVR(R): Internal clock, TXD, RXD, NRES and EN connected for LIN Slave. The software must be appropriately programmed for the connection between the LIN-SBC and the AVR. SBC: LIN slave operation with 5V regulator, watchdog disabled. RF emissions: best results for RF emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure 5-3.
301
9132D-AUTO-12/10
Figure 5-4.
Typical LIN Master Application 1k LIN Master Pull-up Switched Off during Sleep and Silent Mode
PVCC
100nF
22pF
C2
220pF PB7 PA4 PA3 10nF
LIN
XTAL
33k
WAKE
10k
31
PB7 PA7 PA6 PA5 PA4 AVCC PA3 LIN PB6 PB5 PB4 AGND GND
20
WAKE NTRIG EN
22pF
32
19
PA3 PA4
10 k
VS VBAT GND
PVCC
C1
100nF
VCC GND GND GND
Atmel ATA6616/17
WD_OSC NRES RXD TXD PB1 PB0 PA0 PA1 PA2 INH
VS VCC PVCC KL15 MODE TM
+ +
100nF 100nF 10F 10k 22F 1k LIN Master pull-up
38
PB3 PB2
13
1
12
PB7 PB7
47k KL15
PA2 PA5 PB7
1
PVCC PA4 47k 10k
MODE
100nF
ISP
Note:
All open pins of the SiP can be used for application-specific purposes. AVR(R): TXD, RXD, NRES and EN connected for LIN Master. The software must be appropriately programmed for the connection between the LIN-SBC and the AVR. System clock controlled by external crystal. LIN-SBC: Master application, 10k Master resistance connected via diode to VS, 1k master resistance will be switched off via pin INH during Sleep Mode, local wake up via pin WAKE; watchdog is enabled. RF emissions: best results for RF emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure 5-4.
302
Atmel ATA6616/ATA6617
9132D-AUTO-12/10
Atmel ATA6616/ATA6617
Figure 5-5. 3 x 3 LIN Slave Switch Module Matrix Decoder with the Atmel(R) ATA6616/ATA6617
Optional resistors for higher switch currents PA2 PA5 PB7
1
PVCC PA4
ISP
VCC
PVCC
100nF C2
220pF PB7 PA3 10nF 33k WAKE (if needed) LIN
AGND
AVCC
PB7
PA7
PA6
PA5
PA4
LIN
PB6 PB5 PB4
GND
PA3
S1
S2
S3 PVCC
31 32
20
WAKE NTRIG EN
19
PA3 PA4
10k
VS
C1
100nF
VCC GND GND GND
Atmel ATA6616/17
WD_OSC NRES RXD TXD PB1 PB0 PA0 PA1 PA2 INH
VS VCC PVCC KL15 MODE TM
+ +
100nF 100nF 10F 10k 22F
VBAT GND
S4
S5
S6
38
PB3 PB2
13
1
12
PB7 PB0 PB7
KL15 MODE 47k S7 S8 S9 10k 100nF 47k
Note:
Note: All open pins of the SiP can be used for application-specific purposes. AVR(R): TXD, RXD, NRES and EN connected for LIN Master. The software must be appropriately programmed for the connection between the LIN-SBC and the AVR. PA7 and PA2 are used as analog inputs. In addition, the application supports a 3 x 3 switch matrix. PA4, 5, 6 are used as PWM outputs to control the brightness of light emitting diodes. System clock controlled by external crystal. LIN-SBC: LIN slave application, 1k Master resistance connected via diode to VBAT, local wake up via pin WAKE; watchdog is enabled. RF emissions: best results for RF emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure 5-5.
303
9132D-AUTO-12/10
6. Ordering Information
Extended Type Number ATA6616-P3QW ATA6616-P3PW ATA6617-P3QW ATA6617-P3PW Program Memory 8-kB flash 8-kB flash 16-kB flash 16-kB flash Package QFN38, 5x 7 QFN38, 5x 7 QFN38, 5x 7 QFN38, 5x 7 MOQ 4,000 pieces 1,000 pieces 4,000 pieces 1,000 pieces
7. Package Information
Top View D 40 1
PIN 1 ID
E
technical drawings according to DIN specifications
Dimensions in mm
A1
Side View
A3 A
Bottom View D2 13 12 19 20 COMMON DIMENSIONS
(Unit of Measure = mm)
Symbol
MIN
0.8 0.0 0.15 4.9 3.45 6.9 5.45 0.3 0.16
NOM
0.9 0.02 0.2 5 3.6 7 5.6 0.4 0.23 0.5 BSC
MAX
1 0.05 0.25 5.1 3.75 7.1 5.75 0.5 0.3
NOTE
E2
A A1 A3
1 31 38 32 e
D D2 E E2 L
Z
L
Z 10:1
b e
b 08/22/08 DRAWING NO. REV. 6.543-5156.01-4 1
Package Drawing Contact: packagedrawings@atmel.com
TITLE Package: VQFN_5x7_38L Exposed pad 3.6x5.6
304
Atmel ATA6616/ATA6617
9132D-AUTO-12/10
Atmel ATA6616/ATA6617
8. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History * * * * * * * * * * * * * * * * * * * * * * * * * * * * Section 3.1 "Features" on page 4 changed Section 3.2 "Description" on page 4 changed Section 3.3.3 "Ground Pin" on page 6 changed Section 3.3.12 "Mode Input Pin (Mode)" on page 7 changed Figure 3.2 "Modes of Operation" on page 10 changed Section 3.4.4 "Fail-safe Mode" on page 12 changed Section 3.5.6 "Voltage Regulator" on pages 15 to 16 changed Section 3.8 "Electrical Characteristics" on pages 20 to 25 changed Section 3.3.1 "Physical Layer Compatibility" on page 6 changed Section 3.3.8 "TXD Dominant Time-out Function" on page 7 changed Section 3.3.10 "Enable Input Pin (EN)" on page 7 changed Section 3.4.1 "Normal Mode" on page 9 changed Section 3.4.2 "Silent Mode" on pages 10 to 11 changed Section 3.4.3 "Sleep Mode" on pages 11 to 12 changed Section 3.5.1 "Remote Wake-up via Dominant Bus State" on page 14 changed Section 3.5.2 "Local Wake-up via Pin WAKE" on page 14 changed Section 3.5.3 "Local Wake-up via Pin KL_15" on page 14 changed Section 3.5.6 "Voltage Regulator" on page 15 changed Section 3.9"Electrical Characteristics" number 10.4 on page 22 changed Section 4.1 "Features" on page 27 changed Section 4.2.1 "Comparison between Atmel ATtiny87 and Atmel ATtiny167" on page 28 changed Section 4.2.2 "Part Description" on pages 28 to 29 changed Section 4.17.1 "Features" on page 212 changed Section 4.18.9 "Temperature Measurement" on page 228 changed Section 4.18.10 "Manufacturing Calibration" on pages 228 to 229 changed Section 4.18.11 "Internal Voltage Reference Output" on page 229 changed Table 4-81 "Calibration and Accuracy of Internal RC Oscillator" on page 270 changed Table 4-86 "Brown-out Characteristics" on page 272 changed
9132D-AUTO-12/10
9132C-AUTO-05/10
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9132D-AUTO-12/10
9. Table of Contents
General Features .................................................................................... 1 1 2 Description ............................................................................................. 1 Atmel ATA6616/ATA6617 LIN System in Package Solution (SIP) ..... 2
2.1 2.2 Pinning Atmel ATA6616/ATA6617 .................................................................2 Absolute Maximum Ratings ............................................................................3
3
LIN System-basis-chip Block ............................................................... 4
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Features .........................................................................................................4 Description .....................................................................................................4 Functional Description ....................................................................................6 Modes of Operation ........................................................................................9 Wake-up Scenarios from Silent or Sleep Mode ...........................................14 Watchdog .....................................................................................................17 Absolute Maximum Ratings ..........................................................................19 Electrical Characteristics ..............................................................................20
4
Atmel ATtiny87/ATtiny167 Microcontroller Block for Atmel ATA6616/ATA6617 ............................................................................... 27
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 Features .......................................................................................................27 Description ...................................................................................................28 AVR CPU Core ............................................................................................31 AVR Memories .............................................................................................39 System Clock and Clock Options .................................................................48 Power Management and Sleep Modes ........................................................65 System Control and Reset ...........................................................................71 Interrupts ......................................................................................................82 External Interrupts ........................................................................................85 I/O-Ports .......................................................................................................90 8-bit Timer/Counter0 and Asynchronous Operation ...................................110 Timer/Counter1 Prescaler ..........................................................................130 16-bit Timer/Counter1 ................................................................................133 SPI - Serial Peripheral Interface .................................................................164 USI - Universal Serial Interface .................................................................173 LIN/UART - Local Interconnect Network Controller or UART .....................186 ISRC - Current Source ...............................................................................211
306
Atmel ATA6616/ATA6617
9132D-AUTO-12/10
Atmel ATA6616/ATA6617
4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 ADC - Analog to Digital Converter .............................................................214 AnaComp - Analog Comparator .................................................................236 DebugWIRE On-chip Debug System .........................................................240 Flash Programming ....................................................................................242 Memory Programming ................................................................................250 Electrical Characteristics ............................................................................267 Decoupling Capacitors ...............................................................................278 Typical Characteristics ...............................................................................279 Register Summary .....................................................................................290 Instruction Set Summary ............................................................................296
5 6 7 8 9
Application ......................................................................................... 299 Ordering Information ........................................................................ 304 Package Information ........................................................................ 304 Revision History ................................................................................ 305 Table of Contents .............................................................................. 306
307
9132D-AUTO-12/10
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(c) 2010 Atmel Corporation. All rights reserved. / Rev.: 9132D-AUTO-12/10 Atmel(R), Atmel logo and combinations thereof, AVR (R), AVR Studio (R) and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
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