 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 1/36 FEATURES o o o o o o o o o o o o 16 bidirectional input/output stages at 24 V Input/output mode programmable in 4-channel blocks Short-circuit-proof high-side drivers with diagnosis function 500 mA pulse and 150 mA permanent load driving capability Active flyback circuit Load diagnosis for driver current, output voltage and impedance (cable fractures, resistance and short circuits) 10-bit A/D converter for the generation of diagnosis measurement values Safety devices (voltage monitor, temperature sensor with warning and shutdown features, power output enable pin) Programmable interrupt generation with an events storage facility Variable digital filters for the debouncing of I/O signals Fast 8-bit parallel or serial SPITM-compatible C interface permits use in buses Logic supply from 3 V upwards APPLICATIONS o Industrial 24 V applications o Lamp switches with diagnostic features o Inductive load driver circuits for relays and valves etc. PACKAGES MQFP52 BLOCK DIAGRAM VDD D0-SI D1-SOC D2-SOB D3 VCC OUT1 PEN1 I/O STAGE 1 & & POE VB1 iC-JX CONTROL LOGIC & 0uA 200uA 600uA 2mA 0uA 200uA 600uA 2mA NIOL TOFF1 NIBBLE 0 SC1 NIOL D4 D5 D6 D7 A0 A1 A2 A3-SCLK A4 INTERFACE uC SCF0 Short Circuit Filter VBOK1 Short Circuit Monitor + - IO1 IN1 Input Filter VB-5.8V 74% VCC 150mA + IL(2:0) I/O LOGIC SELES(3:0) SELAD(2:0) VB-6V 6V ADC MUX TOFF2 + I/O LOGIC NCS NWR NRD NRES NIOL IL0 IL1 IL2 SCF0 FL(1:0) PN(01:00) I/O STAGE 2 I/O STAGE 3 I/O STAGE 4 IO2 IO3 IO4 VB2 IO5 IO6 IO7 IO8 VB3 I/O LOGIC I/O LOGIC NSP BUS CONTROL NIBBLE 1 I/O LOGIC I/O LOGIC I/O STAGE 5 I/O STAGE 6 I/O STAGE 7 I/O STAGE 8 NIOH VREF VREF INTERFACE IH0 IH1 IH2 SCF1 FH(1:0) PN(11:10) I/O LOGIC I/O LOGIC BLFQ FREQUENCY CLK DIVIDER NIBBLE 2 I/O LOGIC I/O LOGIC I/O STAGE 9 I/O STAGE 10 I/O STAGE 11 I/O STAGE 12 IO9 IO10 IO11 IO12 VB4 NIOL IL0 IL1 IL2 SCF2 FL(1:0) PN(21:20) I/O LOGIC I/O LOGIC RSET IBIAS VREFAD NINT NIBBLE 3 INTERRUPT I/O LOGIC I/O LOGIC I/O STAGE 13 I/O STAGE 14 I/O STAGE 15 I/O STAGE 16 VB(1:4) IO13 IO14 IO15 IO16 NIOH IH0 IH1 IH2 SCF3 FH(1:0) PN(31:30) I/O LOGIC I/O LOGIC MONITOR: VB,VCC GNDA,GNDD A/D Converter VBOK(1:4) POE GNDA GNDD Copyright (c) 2010 iC-Haus http://www.ichaus.com iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 2/36 DESCRIPTION iC-JX is a bidirectional I/O device with 4x4 high-side driver stages. The input or output function can be separately selected for blocks or nibbles of four I/O stages. Each block can also be individually programmed with various filtering options for the debouncing of I/O pin signals or overcurrent messages, with current sources for the defining of levels at the inputs (lowside sources) or for load diagnosis at the outputs (high-side sources) and also with a flash pulse function. To enable communication with the controller the device includes a parallel interface (with eight data, five address and three control pins) and also an SPIcompatible serial interface (with one pin for the clock, chip selection, data input and data output respectively). The type of interface is selected via pin NSP. I/O stages with an input function can record logic levels at 24 V where a programmable pull-down current source (of up to 2 mA) either defines the level for open inputs or supplies a bias current for external switch contacts. Connecting safety circuits with integrated serial/parallel resistors to the device also enables leakage currents and short circuits to be pinpointed. The contact status can be read out using the microcontroller interface. I/O stages with an output function drive various loads (such as lamps, cables or relays, for example) to a common ground with 150 mA of permanent current or 500 mA in pulse operation. Spikes and flyback currents are discharged by the integrated flyback circuits. For synchronous flash display, as used for indicator lamps in plugboards, for example, a flash pulse enable can be individually set for each output to offload the controller. A common inhibiting input (POE) permits the global shutdown of all outputs and can be operated by an autonomous watchdog circuit. All output stages are short-circuit-proof and protected against thermal destruction in the event of extreme power dissipation. Each stage has its own temperature sensor which is evaluated in two stages and generates interrupt messages for the controller. The latter is warned before the device is forcibly shutdown. A short circuit also triggers an interrupt message; the current status here can be read out by the controller. For the purpose of load diagnosis a programmable pull-up current source (of up to 2 mA) can be used to determine an initial load breakage or open loop (caused by a fractured cable, for example) before an output is switched on. The I/O pin status can always be read back via comparators. A load current measurement circuit then permits the load to be assessed; failed valves and faulty or wrongly implemented indicator lamps can be verified in this way. In addition, the analog measurement of voltage at the I/O pins allows safety switches to be analyzed with reference to ground, here without the driver function. All analog measurements for the load current (per stage), for the I/O pin voltage (per stage, either referenced to Ground or VB), for the driver supply (all VB pins) , for the internal voltage reference (VBG) and for the chip temperature are made available to the microcontroller as digital measurements by an integrated A/D converter which has 10 bits of resolution. An interrupt pipeline which limits the loss of interrupts allows reliable processing of interrupts by the microcontroller. Registers provide information as to current events; messages can be individually enabled for all available interrupt sources. iC-JX monitors all supply voltages and also the GNDD-GNDA connection to ground. Monitored separately, undervoltage in the range of 2.5V at analog supply VCC or even short disruption of digital supply VDD causes all registers to be reset and the output stages to be shutdown. Undervoltage at 24 V driver supply VB triggers a shutdown of the output stages without deleting the contents of the registers. Diodes protect all inputs and outputs against destruction by ESD. iC-JX is also immune to burst transients according to IEC 1000-4-4 (4 kV; previously IEC 8014). iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 3/36 PACKAGES MQFP52 to JEDEC Standard PIN CONFIGURATION MQFP52, pitch 0.65 mm Orientation of the package label ( is subject to change. JX code...) NRD NWR NCS VCC NSP GNDA RSET A3 / SCK A1 D7 D5 D3 D1 / SOC 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 CLK GNDD BLFQ NRES VDD A4 A2 A0 D6 D4 D2 / SOB D0 / SI NINT iC-JX ... ...yyww Code... 34 33 32 31 30 29 28 27 PIN FUNCTIONS No. Name Function 1 NRD Not Read Enable 2 NWR Not Write Enable 3 NCS Not Chip Select 4 VCC Supply Voltage (analog, 3...5.5 V) 5 NSP Not Serial / Parallel (Mode) 6 GNDA Ground (analog) 7 RSET Resistor Setting (10 k optional) 8 A3 Adress Bus 9 A1 Adress Bus 10 D7 Data Bus 11 D5 Data Bus 12 D3 Data Bus 13 D1 Data Bus 14 POE Power Output Enable 15 GNDA Ground (analog) 16 IO16 I/O Stage 17 IO15 I/O Stage 18 VB4 Supply Voltage for I/O Stages 13...16 19 IO14 I/O Stage 20 IO13 I/O Stage 21 IO12 I/O Stage PIN FUNCTIONS No. Name Function 22 IO11 I/O Stage 23 VB3 Supply Voltage for I/O Stages 9...12 24 IO10 I/O Stage 25 IO9 I/O Stage 26 GNDA Ground (analog) 27 NINT Not Interrupt 28 D0 Data Bus 29 D2 Data Bus 30 D4 Data Bus 31 D6 Data Bus 32 A0 Adress Bus 33 A2 Adress Bus 34 A4 Adress Bus 35 VDD Supply Voltage (logic, 3...5.5 V) 36 NRES Not Reset 37 BLFQ Blink Frequency 38 GNDD Ground (logic) 39 CLK Clock (optional) 40 GNDA Ground (analog) 41 IO1 I/O Stage 42 IO2 I/O Stage 43 VB1 Supply Voltage for I/O Stages 1...4 44 IO3 I/O Stage 45 IO4 I/O Stage 46 IO5 I/O Stage 47 IO6 I/O Stage 48 VB2 Supply Voltage for I/O Stages 5...8 49 IO7 I/O Stage 50 IO8 I/O Stage 51 GNDA Ground (analog) 52 VREF External Voltage Reference (optional) Additional Pin Function in SPI Mode (NSP = low) 3 8 9 13 28 29 32 33 34 NCS SCK A1 SOC SI SOB A0 A2 A4 Not Chip Select Serial Clock Device ID Bit 1 Serial Out Chain Serial In Serias Out Bus Device ID Bit 0 Select Chain / Bus Enable Interrupt Report SOC/SOB GNDA 51 52 50 44 42 41 46 49 48 21 45 22 43 47 14 16 20 24 17 18 19 23 15 POE IO16 IO14 IO13 IO12 IO11 VB4 IO10 VB3 GNDA IO15 IO9 25 Separate supply voltages at VB1..4 are possible. All GNDA pins must be connected up externally. GNDA must be connected to GNDD externally when just one voltage supply is available. VCC and VDD can be powered either mutually or separately. GNDA 26 40 GNDA VREF VB2 VB1 IO8 IO7 IO6 IO5 IO4 IO3 IO2 IO1 iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 4/36 ABSOLUTE MAXIMUM RATINGS Beyond these values damage may occur; device operation is not guaranteed. Absolute Maximum Ratings are no Operating Conditions. Integrated circuits with system interfaces, e.g. via cable accessible pins (I/O pins, line drivers) are per principle endangered by injected interferences, which may compromise the function or durability. The robustness of the devices has to be verified by the user during system development with regards to applying standards and ensured where necessary by additional protective circuitry. By the manufacturer suggested protective circuitry is for information only and given without responsibility and has to be verified within the actual system with respect to actual interferences. (Legend: x = 1..16, y = 1..4) Item No. Symbol Parameter Conditions Min. -0.3 -0.3 IOx = off; see additional remark 1 see Figure 1 IOx = hi, = 2 ms, T 2 s see Figure 2 -10 -500 -1.0 -100 -8 -20 100 8 20 Driver Supply Voltage Voltages at IO1...16 Current in IO1...16 Pulse current in IO1...16 Current in VCC, VDD Current in NCS, NWR, NRD, A0...4, D0...7 with input function D0...7, NRES, CLK, BLFQ, POE, NSP, RSET, VREF Current in D0...7, NINT, Pulse current in NCS, NWR, NRD, A0...4, D0...7, NRES, CLK, BLFQ, NINT, NSP, POE, IO1...16, RSET, VREF (latch up test) ESD-voltage, all pins Burst transients at IO1...16 Chip temperature Storage temperature D0...7 with output function Pulse width < 10 s, all inputs / outputs open Max. 6 40 40 150 V V V mA A mA A mA Unit G001 VCC, VDD Supply Voltage G002 VBy G003 V(IOx) G004 Idc(IOx) G005 Ipk(IOx) G006 Imax() G008 Ic() G007 Imax(VBy) Current in VB1...4 G009 I() G010 Ilu() -25 -100 25 100 mA mA G011 Vd() G012 Vb() G013 Tj G014 Ts 1) HBM 100 pF discharged over 1.5 k after IEC 1000-4-4 -40 -40 2 4 150 150 kV kV C C If the voltage supplies can not be guaranteed to be present at the time signals appear at the pins IO1..IO16, additional diodes or sufficient current limiting ohmic resistors have to be connected in series to the IO-pins to prevent reverse back biasing of the device. THERMAL DATA Operating conditions: VCC = VDD = 3 ... 5.5 V, VBy = 12 ... 36 V, GNDA = GNDD = 0 V, all inputs on defined logic states (high or low) Item No. T01 T02 Symbol Ta Rthja Parameter Ambient temperature Thermal resistance chip/ambient Conditions Min. extended temperature range on request package mounted on PCB -40 55 Typ. Max. 85 C K/W Unit All voltages are referenced to ground unless otherwise stated. All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative. iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 5/36 ELECTRICAL CHARACTERISTICS Operating conditions: VCC = VDD = 3 ... 5.5 V, VBy = 12 ... 36 V, GNDA = GNDD = 0 V, RSET = 10 k 1% . All inputs on defined logic states (high or low), Tj = -40 ... 125 C unless otherwise stated. Functionality and parameters beyond operating conditions (for example w.r. to independent voltage supplies) are to be verified within the individual application by FMEA methods. Item No. 001 002 003 004 005 006 Symbol Parameter Conditions Min. VCC I(VCC) I(VCC) VDD I(VDD) I(VDD) Permissible Supply Voltage VCC Supply Current in VCC Supply Current in VCC Permissible Supply Voltage VDD Supply Current in VDD (static) Supply Current in VDD (dynamic) Supply Current in VDD Supply Current in VDD Permissible Supply Voltage VB1...4 (operating range) Supply Current in VB1...4 Supply Current in VB1...4 ESD Clamp Voltage lo at VCC, VDD, VB1...4, RSET, VREF ESD Clamp Voltage hi at VCC, VDD ESD Clamp Voltage hi at VB1...4 ESD Clamp Voltage lo at IO1...16 ESD Clamp Voltage hi at IO1...16 POE = hi, IOx = hi, unbelastet IOx = off I() = -10 mA -1.4 all logic inputs lo = 0 V or hi=VDD continuous reading cycle all 200ns, data word `00' and `FF' is alternating read, CL(D0... 7) = 200 pF all logic inputs lo=0.8V all logic inputs hi=2.0V 12 7 5 3 5 36 20 10 -0.3 no supply voltage VBy 3 3 3 10 Typ. Max. 5.5 20 30 5.5 6 30 V mA mA V mA mA Unit General 007 008 009 010 011 012 I(VDD) I(VDD) VBy I(VBy) I(VBy) Vc()lo mA mA V mA mA V 013 014 015 016 017 Vc()hi Vc()hi Vc()lo Vc()lo Vc()hi I() = 10 mA I() = 10 mA I() = 10 mA, IOx = off I() = 10 mA 6 30 -25 30 0.4 55 -19 55 1.5 V V V V V ESD Clamp Voltage hi at Vc()hi = V() - VDD, NCS, NWR, NRD, A0...4, NRES, D0...7 as input, CLK, BLFQ, D0...7, NINT, POE, I() = 10 mA NSP ESD Clamp Voltage lo at D0...7 as input, NCS, NWR, NRD, A0...4, NRES, I() = -10 mA CLK, BLFQ, D0...7, NINT, POE, NSP Leakage Current of I/O Pins (x=1..16) beyond operating conditions Saturation Voltage hi Saturation Voltage hi Saturation Voltage hi for pulse load VCC = 0 V and VDD = 0 V, VBy = 2..30 V) Vs()hi = VBy - V(IOx), I(IOx) = -15 mA; see Fig. 1 Vs()hi = VBy - V(IOx), I(IOx) = -150 mA; see Fig. 1 Vs()hi = VBy -V(IOx), I(IOx)= -500 mA, = 2 ms, T 2 s; see Fig. 2 V(IOx) = 0 .. VBy - 3 V 018 Vc()lo -1.5 -0.4 V 019 Ifl(IOx) -0.2 mA I/O Stages: High-Side Driver IO1...16 101 102 103 Vs()hi Vs()hi Vs()hi 0.2 0.6 2 V V V 104 105 106 107 Isc()hi It()scs Vc()lo SR()hi Overcurrent Cut-off Threshold Current for Overcurrent Message -1.6 -1.2 -18 5 -0.51 -0.51 -12 17 A A V V/s Free-wheeling Clamp Voltage low I(IOx) = -150 mA Slew Rate hi CL = 0 ... 100 pF, I(IOx) = -150mA iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 6/36 ELECTRICAL CHARACTERISTICS Operating conditions: VCC = VDD = 3 ... 5.5 V, VBy = 12 ... 36 V, GNDA = GNDD = 0 V, RSET = 10 k 1% . All inputs on defined logic states (high or low), Tj = -40 ... 125 C unless otherwise stated. Functionality and parameters beyond operating conditions (for example w.r. to independent voltage supplies) are to be verified within the individual application by FMEA methods. Item No. 108 109 110 201 202 203 204 205 206 207 208 209 Symbol SR()lo tplh() tphl() Ipd() Ipd() Ipd() Ipu() Ipu() Ipu() tp()Ion tp()Ioff Ifu() Parameter Slew Rate lo Conditions Min. CL = 0 ... 100 pF, I(IOx) = -150mA 5 Propagation Delay until IOx: lo V(IOx) > V0(IOx) + 1 V hi Propagation Delay until IOx = off V(IOx) < 80 % (VBy - Vs(IOx)hi) Pull-down Current Source (200 A) Pull-down Current Source (600 A) Pull-up Current Source (200 A) Pull-up Current Source (600 A) Pull-up Current Source (2 mA) Turn-on Time Current Source aktiv Turn-off Time Current Source inaktiv Leakage Current V(IOx) = 3 V .. VBy; V(IOx) = 3 V .. VBy; 160 510 1.6 150 510 1.6 200 600 2 200 600 2 Typ. Max. 17 6 6 240 690 2.4 250 690 2.4 5 5 -50 70 V/s s s A A mA A A mA s s A Unit I/O Stages: Current Sources at IO1...16 Pull-down Current Source (2 mA) V(IOx) = 3 V .. VBy; IOx = off, V(IOx) = 0 V .. VBy - 3 V IOx = off, V(IOx) = 0 V .. VBy - 3 V IOx = off, V(IOx) = 0 V ..VBy - 3 V I(IOx) > 90 % Ipd(IOx) resp. I(IOx) > 90 %Ipu(IOx) I(IOx) < 10 % Ipd(IOx) resp. I(IOx) < 10 % Ipu(IOx) IOx with Input Function or Output Function with IOx = off; VBy = 30 V IL2 = IH2 = IL1 = IH1 = IL0 = IH0 = 0, V(IOx) = 0V .. VBy Conditions see Item-No. 209; V(IOx) = -10 V .. 0 V, VBy = 30 V Conditions see Item-No. 209; only Input Function V(IOx) = VBy ... VBy + 0.3 V Conditions see Item-No. 209; only Input Function V(IOx) = VBy + 0.3V ... VBy + 2V no supply voltages VBy V(IO)max = 36V IOx with input function IOx with input function IOx with input function, Vt()hys = Vt()hi - Vt()lo IOx with output function, Vt()hi = VBy - V(IOx) IOx with output function, Vt()lo = VBy - V(IOx) IOx with output function, Vt()hys = Vt()lo - Vt()hi I/O-Filter inaktive 210 211 Irb() Irb() Leakage Current Leakage Current -1.5 250 mA A 212 Irb() Leakage Current 1 mA 213 Irb() Leakage Current 5 mA I/O Stages: Comparator IO 1..16 301 302 303 304 305 306 307 Vt()hi Vt()lo Vt()hys Vt()hi Vt()lo Vt()hys Threshold voltage hi Threshold voltage lo Hysteresis Threshold voltage hi referenced to VBy Threshold voltage lo referenced to VBy Hysteresis 82 66 100 5.0 6.7 100 20 %VCC %VCC mV V V mV s tp(IOx-Dx) Propagation Delay Input IOx to Data Output Dx Toff1 Ton1 Thys1 Toff2 Ton2 Thys2 T Overtemperatur threshold level 1: warning Level 1 Release Level 1 Hysteresis Overtemperatur threshold level 2: shutdown Level 2 Release Level 2 Hysteresis Temperature Difference Level 2 to Level 1 Thermal Shutdown 401 402 403 404 405 406 407 120 115 Thys1 = Toff1 - Ton1 2 140 120 Thys2 = Toff2 - Ton2 T = Toff2 - Toff1 13 13 145 140 7 165 145 35 35 C C C C C C C iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 7/36 ELECTRICAL CHARACTERISTICS Operating conditions: VCC = VDD = 3 ... 5.5 V, VBy = 12 ... 36 V, GNDA = GNDD = 0 V, RSET = 10 k 1% . All inputs on defined logic states (high or low), Tj = -40 ... 125 C unless otherwise stated. Functionality and parameters beyond operating conditions (for example w.r. to independent voltage supplies) are to be verified within the individual application by FMEA methods. Item No. 501 502 503 504 505 506 Symbol Parameter Conditions Min. VCCon, VDDon VCCoff, VDDoff VCChys, VDDhys tmin()lv tpoff Vrefad Turn-on Threshold VCC, VDD (Power-on release) Undervoltage Threshold VCC, VDD (Power-down reset) Hysteresis Power Down Time required for low voltage detection Propagation Delay until Reset after Low Voltage at VCC, VDD Reference Voltage for A/DConverter ADC - Measurement Range 1 ADC - Measurement Range 2 ADC - Measurement Range 3 ADC - Measurement Range 4 Current and voltage measurement High at IO, SELAD = '0b001' resp. '0b010', EME = 0 Voltage measurement High at IO, SELAD = '0b010', EME = 1 Voltage measurement Low at IO, SELAD = '0b100', EME = 0 Voltage measurement Low at IO SELAD = '0b100'; VB or VBG measurement SELAD = '0b101' or. '0b110', EME = 1 Total voltage measurement range SELAD = '0b011' Temperature measurement SELAD = '0b111' EME = 0 EME = 1 SVREF = 0, TEMP = (774-Dtemp1)/TKtemp1 Tj = -40C Tj = 27C Tj = 95C SVREF = 0 SVREF = 1, V(VREF) = 2.5V 0.2% TEMP = (861-Dtemp2)/TKtemp2 Tj = -40C Tj = 27C Tj = 95C SVREF = 1, V(VREF) = 2.5V 0.2% 826 670 519 2.16 2.6 2.75 VCChys = VCCon - VCCoff, VDDhys = VDDon - VDDoff VCC = 0.8 V .. VCCoff, VDD = 0.8 V .. VDDoff 2.4 2.3 60 1 12 3.0 Typ. 2.6 2.5 100 Max. 2.9 2.8 140 V V mV s s V Unit Bias and Low Voltage Detection A/D-Converter 701 702 703 704 VR1 VR2 VR3 VR4 VBy 0.6 V VBy 5V 0 0 VBy VBy 0.6 5 V V V V 705 706 707 708 709 VR5 VR6 Vbitlo Vbithi Dtemp1 ADC - Measurement Range 5 ADC - Measurement Range 6 Bit-Equivalent of voltage Bit-Equivalent of voltage Digital value of temperature measurement 1 0 -40 0.6 5.4 863 712 563 2.22 VB 125 V C mV mV 900 755 608 2.27 1/C 710 711 TKtemp1 Dtemp2 Temperature coefficient 1 Digital value of temperature measurement 2 931 761 585 2.26 0.9 957 800 632 2.41 1.25 154 / fICLK 90 / fICLK 26 / fICLK 984 839 679 2.55 1.5 1/C MHz s s s 712 713 714 715 716 TKtemp2 fICLK tSAR1 tSAR2 tSAR3 Temperature coefficient 2 Internal oscillating frequency Conversion time SAR-converter 1 Current measurement SELAD = '0b001' Conversion time SAR-converter 2 Voltage measurement Low resp. High; SELAD = '0b010' resp. '0b100' Conversion time SAR-converter 3 Total voltage measurement SELAD = '0b011'; VBy voltage measurement SELAD = '0b101'; VBG voltage measurement SELAD = '0b110'; temperature measurement SELAD = '0b111' Digital value of VBG measurement (external reference) Digital value of VBy measurement (external reference) Relative value of VBy measurement (external reference) SELAD = '0b110', SVREF = 1 SVREF = 1, V(VBy) = 36 V, SELAD = '0b101' SVREF = 1; DRVBY,1 = DVBY,1 (V) / DVBY,1 V(VBy) = 24 V, SELAD = '0b101' V(VBy) = 12 V, SELAD = '0b101' 480 940 717 718 719 DVBG,1 DVBY,1 DRVBY,1 520 990 560 1022 64.6 31.3 66.6 33.3 68.6 35.2 % % iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 8/36 ELECTRICAL CHARACTERISTICS Operating conditions: VCC = VDD = 3 ... 5.5 V, VBy = 12 ... 36 V, GNDA = GNDD = 0 V, RSET = 10 k 1% . All inputs on defined logic states (high or low), Tj = -40 ... 125 C unless otherwise stated. Functionality and parameters beyond operating conditions (for example w.r. to independent voltage supplies) are to be verified within the individual application by FMEA methods. Item No. 720 721 Symbol D1IO,1 DR1IO,1 Parameter Digital value using VR1 range (external reference) Digital relative value using VR1 range (external reference) Conditions Min. SELAD = '0b010', EME = '0b0', SVREF = 1, V(IOx) = V(VBy) - 0.6V SELAD = '0b010', EME = '0b0', SVREF = 1; DR1IO,1 = D1IO,1 (V) / D1IO,1 ; V(IOx) = V(VBy) - 0.3 V V(IOx) = V(VBy) - 0.1 V 840 Typ. 900 Max. 1022 Unit 46 12 870 49 15 930 52 18 1022 % % 722 723 D2IO,1 DR2IO,1 Digital absolute value using VR2 SELAD = '0b010', EME = '0b1', SVREF = 1, range (external reference) V(IOx) = V(VBy) - 5.0 V Digital relative value using VR2 range (external reference) SELAD = '0b010', EME = '0b1', SVREF = 1; DR2IO,1 = D2IO,1 (V) / D2IO,1 ; V(IOx) = V(VBy) - 2.5 V V(IOx) = V(VBy) - 0.6 V 48 9.5 880 50 11.5 940 52 14 1022 % % 724 725 D3IO,1 DR3IO,1 Digital absolute value using VR3 SELAD = '0b100', EME = '0b0', SVREF = 1, range (external reference) V(IOx) = 0.6 V; Digital relative value using VR3 range (external reference) SELAD = '0b100', EME = '0b0', SVREF = 1; DR3IO,1 = D3IO,1 (V) / D3IO,1 ; V(IOx) = 0.3 V V(IOx) = 0.1 V 48 14.5 870 50 16 930 52 18.5 1022 % % 726 727 D4IO,1 DR4IO,1 Digital absolute value using VR4 SELAD = '0b100', EME = '0b1', SVREF = 1; range (external reference) V(IOx) = 5.0V Digital relative value using VR4 range (external reference) SELAD = '0b100', EME = '0b1', SVREF = 1; DR4IO,1 = D4IO,1 (V) / D4IO,1 V(IOx) = 2.5V V(IOx) = 0.6V 48 9.5 930 50 11.5 980 52 14 1022 % % 728 729 D5IO,1 DR5IO,1 Digital absolute value using VR5 SELAD = '0b011', SVREF = 1, V(IOx) = 36.0V range (external reference) Digital relative value using VR5 range (external reference) SELAD = '0b011', SVREF = 1; DR5IO,1 = D5IO,1 (V) / D5IO,1 V(IOx) = 24.0V V(IOx) = 5.0V 64.6 11.8 700 66.6 13.8 800 68.6 15.8 1022 % % 730 731 DCIO,1 DRCIO,1 Digital value of current measure- SELAD = '0b001',SVREF = 1, I(IOx) = 150mA ment (external reference) Relative value of current measurement (external reference) Digital value of VBG measurement (internal reference) Digital value of VBG measurement (internal reference) Relative value using VR1 range (internal reference) SELAD = '0b001', SVREF = 1; DRCIO,1 = DCIO,1 (I) / DCIO,1 I(IOx) = 75mA I(IOx) = 15mA SELAD = '0b110', SVREF = 0 SVREF = 0, V(VBy) = 36V, SELAD = '0b101' SVREF = 0, SELAD = '0b101; DRVBY,0 = DVBY,0 (V) / DVBY,0 V(VBy) = 24V V(VBy) = 12V SELAD = '0b010', EME = '0b0', SVREF = 0, V(IOx) = V(VBy) - 0.6V SELAD = '0b010', EME = '0b0', SVREF = 0; DR1IO,0 = D1IO,0 (V) / D1IO,0 V(IOx) = V(VBy) - 0.3V V(IOx) = V(VBy) - 0.1V SELAD = '0b010', EME = '0b1', SVREF = 0, V(IOx) = V(VBy) - 5.0V SELAD = '0b010', EME = '0b1', SVREF = 0; DR2IO,0 = D2IO,0 (V) / D2IO,0 V(IOx) = V(VBy) - 2.5V V(IOx) = V(VBy) - 0.6V SELAD = '0b100', EME = '0b0', SVREF = 0, V(IOx) = 0.6V 48 6.2 435 830 51 9.2 460 880 54 12.2 485 1022 % % 732 733 734 DVBg,0 DVBY,0 DRVBY,0 64.6 31.3 760 66.6 33.3 820 68.6 35.3 1022 % % 735 736 D1IO,0 DR1IO,0 Digital value using VR1 range (internal reference) Relative value using VR1 range (internal reference) 46 12 790 49 15 840 52 18 1022 % % 737 738 D2IO,0 DR2IO,0 Digital value using VR2 range (internal reference) Relative value using VR2 range (internal reference) 48 9.5 790 50 11.5 840 52 14 1022 % % 739 D3IO,0 Digital value using VR3 range (internal reference) iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 9/36 ELECTRICAL CHARACTERISTICS Operating conditions: VCC = VDD = 3 ... 5.5 V, VBy = 12 ... 36 V, GNDA = GNDD = 0 V, RSET = 10 k 1% . All inputs on defined logic states (high or low), Tj = -40 ... 125 C unless otherwise stated. Functionality and parameters beyond operating conditions (for example w.r. to independent voltage supplies) are to be verified within the individual application by FMEA methods. Item No. 740 Symbol DR3IO,0 Parameter Relative value using VR3 range (internal reference) Conditions Min. SELAD = '0b100', EME = '0b0', SVREF = 0; DR3IO,0 = D3IO,0 (V) / D3IO,0 V(IOx) = 0.3V V(IOx) = 0.1V SELAD = '0b100', EME = '0b1', SVREF = 0, V(IOx) = 5.0V SELAD = '0b100', EME = '0b1', SVREF = 0; DR4IO,0 = D4IO,0 (V) / D4IO,0 V(IOx) = 2.5V V(IOx) = 0.6V SELAD = '0b011', SVREF = 0 V(IOx) = 36.0V SELAD = '0b011', SVREF = 0; DR5IO,0 = D5IO,0 (V) / D5IO,0 V(IOx) = 24.0V V(IOx) = 5.0V Typ. Max. Unit 48 14.5 790 50 16 840 52 18.5 1022 % % 741 742 D4IO,0 DR4IO,0 Digital value using VR4 range (internal reference) Relative value using VR4 range (internal reference) 48 9.5 810 50 11.5 870 52 14 1022 % % 743 744 D5IO,0 DR5IO,0 Digital value using VR5 range (internal reference) Relative value using VR5 range (internal reference) 64.6 11.8 720 66.6 13.8 820 68.6 15.8 1022 % % 745 746 DCIO,0 DRCIO,0 Digital value of current measure- SELAD = '0b001', SVREF = 0, I(IOx) = 150mA ment (internal reference) Digital value of current SELAD = '0b001', SVREF = 0; measurement (internal reference) DRCIO,0 = DCIO,0 (I) / DCIO,0 I(IOx) = 75mA I(IOx) = 15mA Voltage at RSET Range value for RSET Input On-Threshold for burst recognition Input Off-Threshold for Burstrecognition Delay time to Reset after spike at Spike duration: 10 ns VCC, VDD Threshold voltage for open ciruit detection on pins GNDA, GNDD Minimum duration for open circuit V(GNDA,GNDD) = 0 V ... Vt()gnd detection Delay time to reset after open circuit detection at GNDA, GNDD Undervoltage message VB1...4 on Undervoltage message VB1...4 off Hysteresis Minimum duration for PowerDown detection Delay time for undervoltage message VB1...4 Threshold voltage High at D0...7 with input function Schmitt-Trigger-Inputs NCS, NWR, NRD, A0...4, NRES, CLK, BLFQ, D0...7, NSP, POE VByhys = VByon - VByoff VBy = 0.8 V ... VByoff 48 6.2 1.15 9 1.3 1.4 2 51 9.2 1.22 10 54 12.2 1.30 14 2.9 3 110 % % V k V V s Input RSET B01 B02 V(RSET) R(RSET) Burst-Indication C01 VSPon C02 VSPoff C03 tpoff Pin monitoring GNDA, GNDD H01 Vt()gnd H02 tmin()gnd H03 tpoff 35 1 15 65 mV s s Undervoltage detection VB I01 I02 I03 I04 I05 VByon VByoff VByhys tmin()lv tpoff 10.6 10.0 400 1 6 11.2 10.6 11.8 11.2 V V mV s s C-Intrface, I/O-Logic, Frequency divider, Interrupt K01 Vt()hi 2 V iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 10/36 ELECTRICAL CHARACTERISTICS Operating conditions: VCC = VDD = 3 ... 5.5 V, VBy = 12 ... 36 V, GNDA = GNDD = 0 V, RSET = 10 k 1% . All inputs on defined logic states (high or low), Tj = -40 ... 125 C unless otherwise stated. Functionality and parameters beyond operating conditions (for example w.r. to independent voltage supplies) are to be verified within the individual application by FMEA methods. Item No. K02 Symbol Vt()lo Parameter Conditions Min. Threshold voltage Low at D0...7 with input function Schmitt-Trigger-Inputs NCS, NWR, NRD, A0...4, NRES, CLK, BLFQ, D0...7, NSP, POE Schmitt-Trigger-Hysteresis at Vt()hys = Vt()hi - Vt()lo; inputs NCS, NWR, NRD, A0...4, D0...7 mit Eingangsfunktion NRES, CLK, BLFQ, D0...7, NSP, POE Saturation voltage high an NINT, Dx Saturation voltage low an NINT, Dx Pull Down current sources at A0...4, NRES, CLK, BLFQ, D0...7, POE Pull Up current sources at NSP, NCS, NWR, NRD Delay time output enable: POE to IOx disabled Permissible pulse width for enable/disable at POE Permissible burst pulse width at POE 200 Vs()hi = VDD - V( ); I( ) = -4 mA I( ) = 4 mA V() = 1V .. VDD 2 0.8 Typ. Max. V Unit K03 Vt()hys 150 mV K04 K05 K06 Vs()hi Vs()lo Ipd() 0.8 0.49 70 V V A K07 K08 K09 K10 K11 Ipu() tp(POEIOx) tw()lo tw() V() = 0V .. VDD - 1 V RL = 240 ... 1 k, POE: hi lo to V(IOx) < 80 % (VBy - Vs(IOx)hi) -70 2 6 A s ns 600 100 ns ns tmin()nres minimum duration for reset at NRES td() td() maximum frequency at CLK maximum frequency at BLFQ Frequency BLFQ, CLK P01 P02 TBD TBD MHz MHz Characteristics: Diagrams Figure 1: DC load Figure 2: Pulse load iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 11/36 OPERATING REQUIREMENTS: Parallel C Interface Operating Conditions: VCC = VDD = 3...5.5 V, VBy = 12...36 V, GNDA = GNDD = 0 V, RSET = 10 k 1 % Ta = 0...70 C, CL() = 150 pF, input level lo = 0.8 V, hi = 2.2 V, reference levels according to figure 3 Item No. Symbol Parameter Conditions Min. Setup Time: NCS, A0...4 set before NRD hi lo Hold Time: NCS, A0...4 set before NRD lo hi see Figure 4 see Figure 4 30 0 120 65 50 see Figure 4 see Figure 4 see Figure 4 see Figure 4 see Figure 4 30 100 10 10 50 Max. ns ns ns ns ns ns ns ns ns ns Unit Read Cycle I001 tAR1 , tAR2 I002 tRA I003 tRD I004 tDF I005 tRL Write Cycle I006 tAW1 , tAW2 Setup Time: NCS, A0...4 set before NWR lo hi I007 tDW I008 tWA I009 tWD I010 tWL Read/Write Timing I011 tcyc Recovery Time between cycles: NRD lo hi to NRD hi lo, NRD lo hi to NWR hi lo, NWR lo hi to NWR hi lo, NWR lo hi to NRD hi lo see Figure 4 165 ns Setup time : Data valid before NWR lo hi Hold time: NCS, A0...4 stable after NWR lo hi Hold time: Data valid after NWR lo hi Required Write Signal Duration at NWR Wait Time : Data valid after NRD hi see Figure 4 lo Hold Time: Data Bus high impedance after NRD lo hi Required Read Signal Duration at NRD see Figure 4 A(4:0) t cyc NCS t RA t WA V 2.4V 2.0V 0.8V 0.45V NRD Input/Output NWR t DF D(7:0) valid valid t AW1 t AW2 t DW t WL t WD 1 0 t t AR1 t AR2 t RD t RL Figure 3: Reference levels for displayed values of time Figure 4: Read and write cycle for the parallel interface iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 12/36 OPERATING REQUIREMENTS: Serial C Interface Operating Conditions: VCC = VDD = 3...5.5 V, VBy = 12...36 V, GNDA = GNDD = 0 V, RSET = 10 k 1 % Ta = 0...70 C, CL() = 150 pF, input level lo = 0.8 V, hi = 2.2 V, reference levels according to figure 3 Item No. Symbol Parameter Conditions Min. Setup time: NCS hi lo to SCK(A3) lo hi Setup time: SI(D0) stabil before SCK(A3) lo hi Hold time: SI(D0) stabil after SCK(A3) lo hi Clock duration SCK(A3) hi Clock duration SCK(A3) lo Pulse duration NCS hi Delay time: SOC(D1) resp. SOB(D2) stable after SCK(A3) hi lo Delay time: SOC(D1) resp. SOB(D2) high impedance after NCS lo hi see Figure 5 see Figure 5 see Figure 5 see Figure 5 see Figure 5 see Figure 5 see Figure 5 50 40 30 100 100 100 0 50 Max. ns ns ns ns ns ns ns Unit Gruppe 2.0 EN I111 tsCCL I112 tsDCL I113 thDCL I114 tCLh I115 tCLl I116 tCSh I117 tpCLD I118 tpCSD see Figure 5 0 50 ns tCSh NCS thDCL SCK tsDCL SI SOC, SOB MSB in LSB in tCLh tCLl tsCCL tpCLD MSB out tpCLD LSB out tpCSD Figure 5: C interface in SPI mode iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 13/36 PROGRAMMING Register Overview . . . . . . . . . . . . . . . . . . . . . . . . Page 14 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15 IN16...1 Input Register, Status I/O-Pin Change of Input Messages . . . . . . . . . . . . . . . Page 15 DCH16...1 Change of Input Messages Interrupt Messages . . . . . . . . . . . . . . . . . . . . . . . Page 16 DCHI Input Change Interrupt IET2...1 Overtemperatur Interrupt ISCS Overcurrent Interrupt ET2...1 SCS IEOC ISD IUSD IUSA EOC USD USA Overtemperatur Overcurrent ADC Interrupt Interrupt - Bursts on VDD Interrupt - Undervoltage at VDD Interrupt - Undervoltage at VCC ADC End-Of-Conversion Undervoltage VDD Undervoltage VCC PN1...0 Flash Frequency Settings SEBLQ Flash Frequency Reference SECLK1...0 System Clock Control Word 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 24 EOI End of Interrupt BYPSCF Bypass SC Filter SCF3...0 SC Filter Timing Control Word 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 24 SELES3...0 Select I/O-Stage for AD Converter Control Word 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 25 SELAD2...0 Settings for ADC-Measurements EME Extended Measurement Enable EW Enable ADC-Measurement SVREF Select VREF Interconnection Error, Device-ID . . . . . . . . . . Page 25 IBA Interconnection Error USVB Undervoltage VB NRESA NRES = '0' DID4...0 Device ID Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 17 ISCI16...1 Overcurrent-Messages, Interrupt SC16...1 Overcurrent-Status, actual A/D Converter Data . . . . . . . . . . . . . . . . . . . . . . . Page 18 D9...0 ADC-Measurement Value Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18 OUT16..0 Output Register High-Side Driver Flash Puls Enable . . . . . . . . . . . . . . . . . . . . . . . . . Page 18 PEN16...0 Enable Interrupt-Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19 IEN16...1 Input Change Enable SCEN16...1 Overcurrent Enable Control Word 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 20 BYP3...0 I/O-Filter-Bypass FL1...0 I/O-Filter FH1...0 I/O-Filter Control Word 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21 NIOH, NIOL I/O-Pin-Functions IL2...0 Current sources IH2...0 Current sources Control Word 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 23 iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 14/36 Register Overview Adress A(4...0) A4 A3 A2 A1 A0 Write Read 0x00 0 0 0 0 0Input Register A1,2 0x01 0 0 0 0 1Input Register B1,2 0x02 0 0 0 1 0Input Change Message A1,3 0x03 0 0 0 1 1Input Change Message B1,3 0x04 0 0 1 0 0Interrupt Message Register A 0x05 0 0 1 0 1Interrupt Message Register B 0x06 0 0 1 1 0Overcurrent Message A1,4 0x07 0 0 1 1 1Overcurrent Message B1,4 0x08 0 1 0 0 0Overcurrent Status A1 0x09 0 1 0 0 1Overcurrent Status B1 0x0A 0 1 0 1 0A/D-Converter Data 1 0x0B 0 1 0 1 1A/D-Converter Data 2 0x0C 0 1 1 0 1 Output Register A1 0x0D 0 1 1 1 0 Output Register B1 0x0E 0 1 1 1 1 Flash Pulse Enable A1 0x0F 1 0 0 0 0 Flash Pulse Enable B1 0x10 1 0 0 0 1 Interrupt-Enable Input Change A1,5 0x11 1 0 0 1 0 Interrupt-Enable Input Change B1,5 0x12 1 0 0 1 1 Interrupt-Enable Overcurrent A1 0x13 1 0 1 0 0 Interrupt-Enable Overcurrent B1 0x14 1 0 1 0 1 Control Word 1A (I/O Filter)1 0x15 1 0 1 1 0 Control Word 1B (I/O Filter)1 0x16 1 0 1 1 1 Control Word 2A (I/O Pin Functions)1 0x17 1 1 0 0 0 Control Word 2B (I/O Pin Functions)1 0x18 1 1 0 0 1 Control Word 3A (Flash Pulse Settings)1 0x19 1 1 0 1 0 Control Word 3B (Flash Pulse Settings)1 0x1A 1 1 0 1 1 Control Word 4 (Overcurrent Filter Settings) 0x1B 1 1 1 0 0 Control Word 5 (I/O Stage Selection for AD Converter 0x1C 1 1 1 0 1 Control Word 6 (AD Converter Settings) 0x1D 0 1 1 0 0Interconnection Error, Device-ID 0x1E 1 1 1 1 0 Test Register 1 0x1F 1 1 1 1 1 Test Register 2 Table 7: Register assignment 1. A: I/O-Stages 1...8, B: I/O-Stages 9...16 2. Reads the inpus or reads back the outputs, depending on I/O pin mode 3. For I/O pins in input mode (register is '0' in output mode) 4. For I/O pins in output mode (register is '0' in input mode) 5. Only writable in input mode iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 15/36 Input Register A (read only) reading of inputs / output feedback Bit Name Bit7...0 IN8...1 7 IN8 0 1 6 IN7 5 IN6 4 IN5 3 IN4 2 IN3 1 IN2 Adr. 0x00 reset entry: 0x00 0 IN1 (r) Input/Output IOx read '0' Input/Output IOx read '1' Input Register B (read only) reading of inputs / output feedback Bit Name Bit7...0 IN16...9 7 IN16 0 1 6 IN15 5 IN14 4 IN13 3 IN12 2 IN11 1 IN10 Adr. 0x01 reset entry: 0x00 0 IN9 (r) Input/Output IOx read '0' Input/Output IOx read '1' INx indicates the state for IOx (via I/O filter or bypass). Change-of-input Message A (read only) for I/O stages in input mode Bit Name Bit7...0 DCH8...1 7 DCH8 0 1 6 DCH7 5 DCH6 4 DCH5 3 DCH4 2 DCH3 1 DCH2 Adr. 0x02 reset entry: 0x00 0 DCH1 (r) No change of state at the input IOx or no interrupt enable Input IOx has had a change of state enabled for interrupt messages Change-of-input Message B (read only) for I/O stages in input mode Bit Name 7 DCH16 6 DCH15 5 DCH14 4 DCH13 3 DCH12 2 DCH11 Adr. 0x03 reset entry: 0x00 1 0 DCH10 DCH9 (r) Bit7...0 0 DCH16...9 1 No change of state at the input IOx or no interrupt enable Input IOx has had a change of state enabled for interrupt messages iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 16/36 Interrupt Status Register A (read only) Bit Name 7 DCHI 6 IET2 5 IET1 4 ISCI 3 2 ET2 1 ET1 Adr. 0x04 reset entry: 0x00 0 SCS Change-of-input data, overtemperatur, overcurrent (interrupts stored) Bit7 0 No message DCHI 1 Interrupt through change-of input message Bit6 0 No message IET2 1 Interrupt through excessive temperature level 2 Bit5 0 No message IET1 1 Interrupt through excessive temperature level 1 Bit4 0 No message ISCI 1 Interrupt through overcurrent message Excessive temperature status, overcurrent status (real time signals, at the time of readout) Bit2 0 No error message ET2 1 Excessive temperature level 2 (shutdown) Bit1 0 No error message ET1 1 Excessive temperature level 1 (warning) Bit0 0 No error message SCS 1 Overcurrent status (e.g. caused by low-side short circuit) Interrupt Status Register B (read only) Bit Name 7 IEOC 6 ISD 5 IUSD 4 IUSA 3 2 EOC 1 USD (r) (r) (r) (r) (r) (r) (r) Adr. 0x05 reset entry: 0x00 0 USA A/D-Converter, Bursts, Undervoltage (interrupts stored) Bit7 0 No message IEOC 1 Interrupt by the A/D-Converter Bit6 0 No message ISD 1 Interrupt caused by bursts at VDD Bit5 0 No message IUSD 1 Interrupt caused by undervoltage at VDD Bit4 0 No message IUSA 1 Interrupt caused by undervoltage at VCC A/D-Converter, Undervoltage (real time signals, at the time of readout) Bit2 0 No message EOC 1 A/D conversion completed (End of Conversion) Bit1 0 No message USD 1 Undervoltage at VDD Bit0 0 No message USA 1 Undervoltage at VCC (r) (r) (r) (r) (r) (r) (r) Read access gates off changes to the register; the register is reenabled only when reset via EOI. Any successive interrupts which occur at DCHI, IET2, IET1, ISCI, IEOC, ISD, IUSD und IUSA during the read-out phase and before a reset with EOI are trapped by an interrupt pipeline. If this happens, the message at NINT resp. D1/SOC or D2/SOB cannot be deletet by EOI, i.e. NINT resp. D1/SOC or D2/SOB constantly remains on low. In this instance, EOI fills the overcurrent message from the pipeline. iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 17/36 Overcurrent Message A (read only) Bit Name Bit7...0 SCI8...1 7 SCI8 0 1 6 SCI7 5 SCI6 4 SCI5 3 SCI4 2 SCI3 Adr. 0x06 reset entry: 0x00 1 0 SCI2 SCI1 No Message (r) Output IOx has had an overcurrent state enabled for interupt messages (short circuit) Adr. 0x07 reset entry: 0x00 1 0 SCI10 SCI9 Overcurrent Message B (read only) Bit Name Bit7...0 SCI16...9 7 SCI16 0 1 6 SCI15 5 SCI14 4 SCI13 3 SCI12 2 SCI11 No Message (r) Output IOx has had an overcurrent state enabled for interupt messages (short circuit) Read access gates off changes to the register; the register is reenabled only when reset via EOI. Any successive interrupts which occur during the read-out phase and before a reset with EOI are trapped by an interrupt pipeline. If this happens, the message at NINT resp. D1/SOC or D2/SOB cannot be deletet by EOI, i.e. NINT resp. D1/SOC or D2/SOB constantly remains on low. In this instance, EOI fills the overcurrent message from the pipeline. The SCIx bits may be erased selectable by reenabeling IENx after disable. '0' is output for IOx pins in input mode. SCIx reports for IOx. Overcurrent Status A (read only) Bit Name Bit7...0 SC8...1 7 SC8 0 1 6 SC7 5 SC6 4 SC5 3 SC4 2 SC3 Adr. 0x08 reset entry : 0x00 1 0 SC2 SC1 (r) No overcurrent Overcurrent in output IOx, e.g. through a low-side short circuit Overcurrent Status B (read only) Bit Name Bit7...0 SC16...9 7 SC16 0 1 6 SC15 5 SC14 4 SC13 3 SC12 2 SC11 Adr. 0x09 reset entry: 0x00 1 0 SC10 SC9 (r) No overcurrent Overcurrent in output IOx, e.g. through a low-side short circuit These signals act as error analysis and does not generate any interrupts (real time, no register). '0' is output for IOx pins in input mode. SCx reports for IOx. iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 18/36 A/D-Converter Data 1 (read only) Bit Name Bit7...0 D9...2 7 D9 0 1 6 D8 5 D7 4 D6 3 D5 2 D4 1 D3 Adr. 0x0A reset entry: 0x00 0 D2 (r) Bit value is 0 Bit value equals VREFi/1024 * 2n , with n = 9..2 A/D-Converter Data 2 (read only) Bit Name Bit7...0 D1...0 7 D1 0 1 6 D0 5 4 3 2 1 - Adr. 0x0B reset entry: 0x00 0 (r) Bit value is 0 Bit value equals VREFi/1024 * 2n , with n = 1..0 Digitized result of the analog measurement for load current, I/O voltage, driver supply, internal voltage reference or temperature measurement. During the current measurement, VREFi corresponds to the saturation voltage of the internal reference transistor, otherwise it is either the internal reference voltage V(Vrefad) (bit SVREF = ' 0 ', control word 6) or the voltage at the pin Vref (bit SVREF = ' 1 ', control word 6). Output-Register A for I/O stages with output function Bit Name Bit7...0 OUT8...1 7 OUT8 0 1 6 OUT7 5 OUT6 4 OUT5 3 OUT4 2 OUT3 1 OUT2 Adr. 0x0C reset entry: 0x00 0 OUT1 (r) High-side driver "OFF" High-side driver "ON", i.e. normally, IOx = 1 Output-Register B for I/O stages with output function Bit Name 7 OUT16 6 OUT15 5 OUT14 4 OUT13 3 OUT12 2 OUT11 Adr. 0x0D reset entry: 0x00 1 0 OUT10 OUT9 (r) Bit7...0 0 OUT16...9 1 High-side driver "OFF" High-side driver "ON", i.e. normally, IOx = 1 OUTx switches the high-side driver for IOx. Flash Pulse Enable A for I/O stages with output function Bit Name Bit7...0 PEN8...1 7 PEN8 0 1 6 PEN7 5 PEN6 4 PEN5 3 PEN4 2 PEN3 1 PEN2 Adr. 0x0E reset entry: 0x00 0 PEN1 (r) Flash pulse "DISABLED" Flash pulse "ENABLED" PENx enables the flash pulse for IOx. iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 19/36 Flash Pulse Enable B for I/O stages with output function Bit Name 7 PEN16 6 PEN15 5 PEN14 4 PEN13 3 PEN12 2 PEN11 Adr. 0x0F reset entry: 0x00 1 0 PEN10 PEN9 (r) Bit7...0 0 PEN16...9 1 Flash pulse "DISABLED" Flash pulse "ENABLED" PENx enables the flash pulse for IOx. Change-of-input Interrupt Enable A for I/O stages with input function Bit Name Bit7...0 IEN8...1 7 IEN8 0 1 6 IEN7 5 IEN6 4 IEN5 3 IEN4 2 IEN3 1 IEN2 Adr. 0x10 reset entry: 0x00 0 IEN1 (r) "DISABLED" for interrupt "ENABLED" for interrupt: A hi lo or lo hi change of state at the input IOx triggers an interrupt. Change-of-input Interrupt Enable B for I/O stages with input function Bit Name Bit7...0 IEN16...9 7 IEN16 0 1 6 IEN15 5 IEN14 4 IEN13 3 IEN12 2 IEN11 1 IEN10 Adr. 0x11 reset entry: 0x00 0 IEN9 (r) "DISABLED" for interrupt "ENABLED" for interrupt: A hi lo or lo hi change of state at the inut IOx triggers an interrupt. IENx enables the input IOx for interrupt. The outputs IOx can not be enabled for interrupt. The registers can only be modified in input mode. Overcurrent Interrupt Enable A Bit Name 7 SCEN8 6 SCEN7 5 SCEN6 4 SCEN5 3 SCEN4 2 SCEN3 Adr. 0x12 reset entry: 0x00 1 0 SCEN2 SCEN1 (r) Bit7...0 0 SCEN8...1 1 "DISABLED" for interrupt "ENABLED" for interrupt: a short-circuit at IOx triggers an interrupt. Overcurrent Interrupt Enable B Bit Name 7 SCEN16 6 SCEN15 5 SCEN14 4 SCEN13 3 SCEN12 2 SCEN11 Adr. 0x13 reset entry: 0x00 1 0 SCEN10 SCEN9 (r) Bit7...0 0 SCEN16...9 1 "DISABLED" for interrupt "ENABLED" for interrupt: a short-circuit at IOx triggers an interrupt. SCENx enables the output IOx for interrupt. iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 20/36 Control Word 1A (I/O filters) Nibble 1: I/O-Pins 5..8 7 6 BYP1 0 1 Nibble 0: I/O-Pins 1..4 3 2 BYP0 Adr. 0x14 reset entry: 0x00 Bit Name Nibble 1 Bit7 BYP1 Bit5..4 FH1..0 5 FH1 4 FH0 1 FL1 0 FL0 (r) I/O filters aktive Bypass for I/O filters: the I/O signals are reprocessed in their unfiltered state. FH1 FH0 Filter times1 0 0 14.5 tc(SECLK ) 1 tc(SECLK ) 0 1 896.5 tc(SECLK ) 64 tc(SECLK ) 1 0 3584.5 tc(SECLK ) 256 tc(SECLK ) 1 1 7168.5 tc(SECLK ) 512 tc(SECLK ) I/O filter aktive Bypass for I/O filters: the I/O signals are reprocessed in their unfiltered state. FL1 FL0 Filter times1 0 0 14.5 tc(SECLK ) 1 tc(SECLK ) 0 1 896.5 tc(SECLK ) 64 tc(SECLK ) 1 0 3584.5 tc(SECLK ) 256 tc(SECLK ) 1 1 7168.5 tc(SECLK ) 512 tc(SECLK ) (r) Nibble 0 Bit3 BYP0 Bit1..0 FL1..0 0 1 (r) (r) Control Word 1B (I/O filters) Nibble 3: I/O-Pins 13..16 7 6 BYP3 0 1 Nibble 2: I/O-Pins 9..12 3 2 BYP2 - Adr. 0x15 reset entry: 0x00 Bit Name Nibble 3 Bit7 BYP1 Bit5..4 FH1..0 5 FH1 4 FH0 1 FL1 0 FL0 (r) I/O filters aktive Bypass for I/O filters: the I/O signals are reprocessed in their unfiltered state. FH1 FH0 Filter times1 0 0 14.5 tc(SECLK ) 1 tc(SECLK ) 0 1 896.5 tc(SECLK ) 64 tc(SECLK ) 1 0 3584.5 tc(SECLK ) 256 tc(SECLK ) 1 1 7168.5 tc(SECLK ) 512 tc(SECLK ) I/O filters aktive Bypass for I/O filters: the I/O signals are reprocessed in their unfiltered state. FL1 FL0 Filter times1 0 0 14.5 tc(SECLK ) 1 tc(SECLK ) 0 1 896.5 tc(SECLK ) 64 tc(SECLK ) 1 0 3584.5 tc(SECLK ) 256 tc(SECLK ) 1 1 7168.5 tc(SECLK ) 512 tc(SECLK ) (r) Nibble 2 Bit3 BYP0 Bit1..0 FL1..0 0 1 (r) (r) 1. SECLK: see control word 3B on page 23 iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 21/36 Control Word 2A (I/O pin funktions) Nibble 1: I/O-Pins 5..8 7 6 NIOH IH2 0 1 Nibble 0: I/O-Pins 1..4 3 2 NIOL IL2 Adr. 0x16 reset entry: 0x11 Bit Name Nibble 1 Bit7 NIOH Bit6..4 IH2..0 5 IH1 4 IH0 1 IL1 0 IL0 (r) Input mode Output mode IH2 0 0 0 0 1 1 1 1 Input mode Output mode IL2 0 0 0 0 1 1 1 1 IH1 0 0 1 1 0 0 1 1 IH0 0 1 0 1 0 1 0 1 current sources 0A Pull-Down 200A Pull-Down 600A Pull-Down 2mA Pull-Down 0A Pull-Up 200A Pull-Up 600A Pull-Up 2mA Pull-Up (r) Nibble 0 Bit3 NIOL Bit2..0 IL2..0 0 1 (r) IL1 0 0 1 1 0 0 1 1 IL0 0 1 0 1 0 1 0 1 Current sources 0A Pull-Down 200A Pull-Down 600A Pull-Down 2mA Pull-Down 0A Pull-Up 200A Pull-Up 600A Pull-Up 2mA Pull-Up (r) iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 22/36 Control Word 2B (I/O-Pinfunktion) Nibble 3: I/O-Pins 13..16 7 6 NIOH IH2 0 1 Nibble 2: I/O-Pins 9..12 3 2 NIOL IL2 Adr. 0x17 reset entry: 0x11 Bit Name Nibble 3 Bit7 NIOH Bit6..4 IH2..0 5 IH1 4 IH0 1 IL1 0 IL0 (r) Input mode Output mode IH2 0 0 0 0 1 1 1 1 Input mode Output mode IL2 0 0 0 0 1 1 1 1 IH1 0 0 1 1 0 0 1 1 IH0 0 1 0 1 0 1 0 1 Current sources 0A Pull-Down 200A Pull-Down 600A Pull-Down 2mA Pull-Down 0A Pull-Up 200A Pull-Up 600A Pull-Up 2mA Pull-Up (r) Nibble 2 Bit3 NIOL Bit2..0 IL2..0 0 1 (r) IL1 0 0 1 1 0 0 1 1 IL0 0 1 0 1 0 1 0 1 Current sources 0A Pull-Down 200A Pull-Down 600A Pull-Down 2mA Pull-Down 0A Pull-Up 200A Pull-Up 600A Pull-Up 2mA Pull-Up (r) iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 23/36 Control Word 3A (flash pulse settings) Nibble 3: I/O-Pins 13..16 7 6 PN31 PN30 PN31 PN21 PN11 PN01 0 0 1 1 Nibble 2: I/O-Pins 9..12 5 4 PN21 PN20 PN30 PN20 PN10 PN00 0 1 0 1 Nibble 1: I/O-Pins 5..8 3 2 PN11 PN10 Adr. 0x18 Reset-Zustand : 0x00 Nibble 0: I/O-Pins 1..4 1 0 PN01 PN00 Bit Name Nibble 1 Nibble3, Bit7..6 Nibble2, Bit5..4 Nibble1, Bit3..2 Nibble0, Bit1..0 Flash frequency Flash frequency SEBLQ = 0 f(BLFQ) f(BLFQ/2) f(BLFQ/4) f(BLFQ/16) SEBLQ = 11 f(SECLK)/219 f(SECLK)/220 f(SECLK)/221 f(SECLK)/223 (r) 1. SEBLQ: see control word 3B Control Word 3B (reference clock) Bit Name Bit0 SEBLQ 7 SEBLQ 0 1 6 5 4 3 SECLK1 2 SECLK0 1 Adr. 0x19 reset entry: 0x00 0 SEBLQ Settings for flash frequency The flashing pulse is derived from the external clock signal at BLFQ The flashing pulse is derived from the system clock SECLK SECLK0 0 1 0 1 Settings for system clock SECLK Operation with the clock signal at CLK Operation with the internal clock signal ICLK Operation without the clock signal at CLK (filterung etc. deactivated) reserved (r) Bit3..2 SECLK1 SECLK1..0 0 0 1 1 (r) iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 24/36 Control Word 4 (filter settings for overcurrent message) Nibble3 3 SCF3 Nibble2 2 SCF2 Adr. 0x1A reset entry : 0x00 Nibble1 Nibble0 1 0 SCF1 SCF0 (r) Bit Name Bit7 EOI 7 EOI 0 1 6 - 5 - 4 BYPSCF No effect "DELETE"s the interrupt message (change-of-input message; interrupt status register, overcurrent message) accepts successive interrupts from the pipeline, deletes the messages at NINT resp. D1/SOC or D2/SOB when the pipeline is empty. Bit4 BYPSCF Bit3 SCF3 0 1 0 1 Bit2 SCF2 Bit1 SCF1 Bit1 SCF0 0 1 0 1 0 1 Bit automatically resets to '0'. Filters for the overcurrent message are active (r) Bypass for the filters: overcurrent messages are reprocessed in their unfiltered state. Nibble 3 Overcurrent message with 2.3ms filtering (r) Overcurrent message with 4.6ms filtering Gives the filter times with the clock frequency at SECLK 1 , i.e. 1.25MHz: 2.3ms aus (2689.5 192) tc(SECLK ) bzw. 4.6ms aus (5378.5 384) tc(SECLK ) Nibble 2 Overcurrent message with 2.3ms filtering (r) Overcurrent message with 4.6ms filtering Nibble 1 Overcurrent message with 2.3ms filtering (r) Overcurrent message with 4.6ms filtering Nibble 0 Overcurrent message with 2.3ms filtering (r) Overcurrent message with 4.6ms filtering 1. SECLK: see control word 3B on page 23 Control Word 5 (selects I/O stage for ADC-measurements) Bit Name Bit3..0 SELES3..0 7 SELES3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 6 SELES2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 5 SELES1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 4 SELES0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 SELES3 2 SELES2 Adr. 0x1B reset entry : 0x00 1 0 SELES1 SELES0 Selection of I/O stage I/O stage 1 I/O stage 2 I/O stage 3 I/O stage 4 I/O stage 5 I/O stage 6 I/O stage 7 I/O stage 8 I/O stage 9 I/O stage 10 I/O stage 11 I/O stage 12 I/O stage 13 I/O stage 14 I/O stage 15 I/O stage 16 (r) iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 25/36 Control Word 6 (ADC settings) Bit Name Bit2..0 SELAD2..0 7 6 5 SVREF 4 EW 3 EME 2 SELAD2 1 SELAD1 Adr. 0x1C reset entry : 0x00 0 SELAD0 Bit3 EME SELAD2 SELAD1 SELAD0 Settings for ADC measurements 0 0 0 A/D-Converter disabled 0 0 1 Current measurement IO1 0 1 0 Voltage measurement high at IO1 0 1 1 Overall voltage measurement range at IO1 1 0 0 Voltage measurement low at IO 1 1 0 1 VBy voltage measurement (y:1..4)2 1 1 0 VBG voltage measurement 1 1 1 Temperature measurement 0 Measurement range extention "OFF" (for voltages up to 0.6V) 1 Measurement range extention "ON" (for voltages up to 5V) For voltage measurements, the range extention can be either High or Low . A/D converter "OFF" A/D converter activated Bit automatically resets to '0'. Internal reference voltage V(VREFAD) is used External reference voltage at Pin VREF is used (r) (r) Bit4 EW Bit5 SVREF 0 1 0 1 (r) (r) 1. The corresponging I/O stage is selected via bit (3:0) of control word 5. 2. VBy is selected in control word via bits SELES(3:0). VB1 measurements apply to SELES(3:0) = 0x0...0x3, VB2 measurements apply to SELES(3:0) = 0x4...0x7, VB3 measurements apply to SELES(3:0) = 0x8...0xB and VB4 measurements apply to SELES(3:0) = 0xC...0xF. Interconnection Error, Device Identification (read only) Bit Name Bit7 IBA Bit6 USVB Bit5 NRESA Bit4..0 DID4..0 7 IBA 0 1 0 1 0 1 6 USVB 5 NRESA 4 DID4 3 DID3 2 DID2 Adr. 0x1D reset entry : 0x15 1 0 DID1 DID0 (r) (r) (r) (r) No message Interconnection error, broken bond wire at GNDA or GNDD No message Undervoltage at VB4, VB3, VB2 or VB1 No message NRES is 0 Device ID for iC-JX: 0b10101 '-' spare storage space with no funktion; '0' after reset. (r) reset entry iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 26/36 DESCRIPTION OF FUNCTIONS Interfaces iC-JX can be operated with either a serial or parallel interface. This is set using pin NSP. When this pin is connected to VDD the device works in parallel mode. With NSP connected to ground iC-JX operates in serial mode. Operation with a parallel interface The parallel interface in iC-JX consists of 8 data, 5 address and 3 control lines. Address lines A4...0 are used to select the registers in iC-JX. The addresses are accepted with the falling edge of chip select signal NCS. Control lines NRD and NWR govern read and write access. A circuit diagram of the parallel microcontroller interface is given in Figure 6. 5V C2 100nF 5V C1 100nF 24V 24V 24V 5V 5V VDD ADDRESS DECODER NWR NRD 0 1 2 3 4 A(7:0) 0 D0 D1 D2 D3 D4 D5 D6 D7 IO15 IO16 VB4 VCC POE VB1 NSP Nibble 0 NCS IO1 IO2 S1 S2 S3 S4 NWR IO3 NRD IO4 A0 VB2 A1 A2 A3 Nibble 1 IO5 IO6 IO7 S5 S6 S7 S8 R2 R3 R5 R1 C Interface A4 IO8 I/O Logic VB3 C 1 2 3 4 5 6 7 Nibble 2 S9 R4 IO9 R7 S10 R6 R9 S11 R8 S12 R10 I010 I011 I012 Nibble 3 IO13 IO14 D(7:0) LA1 NINT NRES CONTROL REGISTER A/D CONVERTER LA2 REL1 REL2 INT iC-JX MQFP52 NRES RSET VREF BLFQ CLK GNDA GNDD 5V 5V RESET CONTROLLER optional 1.25MHz 2.5V 10 Hz 5V Figure 6: Example application using a parallel interface Operation with a serial interface To reduce the number of lines running between the microcontroller and iC-JX and thus to economize on the use of optocouplers between the former and either one or several iCs in a unit, for example, an extended serial-peripheral interface (SPI) has been integrated into iC-JX. In order to ensure communication between the iC-JX and standard micro controllers, address and data words are both eight bit wide. A possible wiring is shown in Figure 7. iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 27/36 5V C2 100 nF 5V C1 100 nF 24V 24V 24V 5V VDD NSP Nibble 0 NCS NCS NWR IO3 VCC POE VB1 IO1 IO2 S1 S2 S3 S4 5V S1 S2 S3 NRD IO4 A0 VB2 A1 A2 A3 Nibble 1 IO5 IO6 IO7 S5 S6 S7 S8 R1 S9 R2 R3 R5 VB3 Nibble 2 IO9 I010 I011 D3 D4 D5 D6 D7 Nibble 3 VB4 IO13 IO14 IO15 IO16 LA1 LA2 REL1 REL2 I012 S10 R4 S11 R6 S12 R8 S13 R7 R9 R10 SCK S4 Opto Coupler MOSI MISO alternative MISO D0 SOC alternative SOB C optional NINT NRES optional NINTN NRES CONTROL REGISTER BLFQ CLK AD CONVERTER I/O Logic A4 C Interface IO8 iC-JX MQFP52 RSET VREF GNDA GNDD 5V 5V optional 1.25MHz 2.5V 5V RESET CONTROLLER 10 Hz Figure 7: Example application using a serial interface Several iC-JXs can be operated on an SPI. If the devices are to be configured as a chain, up to three can be placed in a row; with buses, four devices can be used. To this end iC-JX's SPI has both a clock input (SCK) and chip select input (NCS) and a data input (SI) and data output for chain operation (SOC, Serial Out Chain) and bus operation (SOB, Serial Out Bus). The configuration is set using pin A2. If this is at 0, the devices are in chain operation; if this is at '1', the chips switch to bus configuration. In chain configuration (see Figure 8, top) output SOC of a device is connected up to the SI data input of the following chip; output SOB is not used. During the addressing sequence (1 byte of communication) all iCJXs are switched through transparently so that all devices receive the transmitted address simultaneously. Only the addressed chip then goes into data transfer mode; the others remain transparent so that communication between the controller and addressed iC-JX can take place without delay. It must be noted here that even in transparent mode each iC-JX has a certain transmit time which has an effect on the maximum data frequency of the overall system. The advantage of this configuration lies in the fact that it is possible to read out the values of an address in all devices very quickly. In bus configuration (see Figure 8, bottom ) all SI inputs and SOB outputs are switched in parallel; the SOC outputs are not used. Addressing the devices ensures that only one of the chips outputs data to SOB; the outputs of the inactive iCs are switched to tristate. This type of configuration differs from chain configuration in that it permits higher clock rates and also allows up to four iC-JXs to be connected up to an SPI bus. iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 28/36 SI iC-JX SOC NCS SCLK SOB SI iC-JX SOC NCS SCLK SOB SI iC-JX SOC NCS SCLK SOB Microcontroller MOSI NCS SCK MISO Opto coupler SI iC-JX SOC NCS SCLK SOB SI iC-JX SOC NCS SCLK SOB SI iC-JX SOC NCS SCLK SOB SI iC-JX SOC NCS SCLK SOB Microcontroller MOSI NCS SCK MISO Opto coupler Figure 8: Possible SPI configurations If no communication takes place on the SPI the chips can send interrupts to the controller by switching the master MISO line to 0. To this end all iC-JXs in chain configuration are switched through transparently (see Figure 9). In bus configuration the relevant chip drives a 0 at its SOB output towards the pull-up resistors at the outputs of the other devices. Using pin A4 settings can be made as to whether interrupts are signaled to the master via the SOB or SOC (0 = no interrupt message; 1 = interrupt message). The message must be deactivated in bus configuration if further devices are present on the SPI bus as otherwise data can collide on the bus which is not desirable here. 3..5.5V 0V VDD GND A2 A1 A0 A2 A1 A0 A2 A4 A4 JX-Logic NINT JX-Logic NINT A4 A1 A0 JX-Logic NINT SEL Comparator Address JX1 SEL Comparator Address JX2 SEL Comparator Address JX3 Evaluation NERR Shift register Evaluation NERR Shift register Evaluation NERR Shift register D0/SI D1/ SOC D0/SI D1/ SOC D0/SI D1/ SOC & A3/SCK NCS A3/SCK NCS & A3/SCK NCS & Microcontroller MISO SCK NCS MOSI Opto coupler Figure 9: Addressing and interrupt messaging scheme in chain configuration The first byte of communication (see Figure 10) consists of the 2-bit chip address (BA1:0), the 5-bit register address (RA4:0) and a read-not-write (RNW) bit. The device ID is set for each chip using pins A(1:0). iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 29/36 Note must be taken here of the fact that in chain configuration the device ID 0b00 is not permissible. If it is set, the device acts as if it did not exist (and is permanently transparent). This makes it possible to test the deactivation of a chip without blocking the interface. Used in chain configuration, the address 0b00 addresses all iC-JXs simultaneously in a process known as broadcasting (see page ??); the other addresses are used to select an individual chip. In chain configuration up to three devices can thus be driven on an SPI master. In bus configuration address 0b00 has no special function, making it possible to address four iC-JXs with one NCS line. Figure 10: Addressing sequence Reading from an iC-JX (Figure 11): In both types of configuration one or more values can be read during a transmit cycle. The first byte sent by the controller (master) is the address the data is to be read out from. The activated iC-JX (slave) sends the address back in the next byte by way of verification while the master sends an NOP (no operating) byte. The slave then sends the required data. The master sends the number of bytes to be read out minus one (in this case the value 0). To increase security the number byte is split into two nibbles which are encoded with the original and inverted value (0 0b00001111). Figure 11: Reading a single register value If verification in whatever form is dispensed with, the master can end the read cycle at this point. The master otherwise sends the received data back to the slave which then returns the address of the read register (in this instance the start address) by way of verification. If this does not match the one originally sent by the master, the master can then abort communication and repeat if necessary. If the address is correct, in the next stage of the procedure the master transmits the control byte optimized for maximum error recognition (0b01011001). For its part the slave checks that the returned data is correct; if this is so, it then also transmits the control byte 0b01011001. In the event of error an inverted value of 0b10100110 is sent. During the transmission of this control byte the setup also checks whether the signals at SI and SOx are synchronous. If this is not the case (due to a spike occurring at SCK, for example), the slave transmits the inverted control byte as soon as it has detected the error. The master recognizes a correct transmission by the fact that the control byte has reached it without error. iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 30/36 If data from several consecutive registers is to be read out (see Figure 12), the autoincrement function enables an abbreviated transmission protocol to be run using iC-JX. Here the master does not send a 0 code after the address of the first register value and the NOP byte but the number of registers to be read out minus one (an entry of 1..15 results in a readout of 2..16 bytes). Here, too, the inverted value is transmitted in the second nibble of the byte. The addressed iC-JX then transmits the consecutive register values and after one byte checks the data returned from the master for errors. Once the required number of register values has been sent the slave transmits the address of the last register addressed, followed by the control byte 0b01011001 with error-free transmission or the inverted value 0b10100110 with an error in transmission. During transmission of the control byte the synchronism of the signals at SI and SOx is again checked; if these are not synchronous, on recognition of this fact the slave then transmits the inverted control byte. Figure 12: Reading several values of consecutive register addresses (autoincrement) Writing to an iC-JX (Figure 13, Figure 14): In the write process one or several registers can be written to during a transmit cycle. To this end the master first sends the start address and the numerical amount of data to be transmitted minus one. As in the read process this value is transmitted as two nibbles (non-inverted and inverted) to increase security. Data from consecutive addresses is then sent. iC-JX returns the master data with a delay of one byte, allowing the master to constantly monitor whether an error has occurred during the addressing sequence or data transmission. If an error is detected, the master can prevent the faulty data being accepted by the slave registers by ending communication. Figure 13: Writing one register value Figure 14: Writing several register values iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 31/36 Error handling In order to reduce processing time complex technology, such as CRC, etc., is not used for error handling. The transmitted addresses and data are instead returned by the recipient to the sender where they are compared to the original data transmitted. Should the master detect an error, it can abort communication in such a way so as to prevent incorrect values being written to the slaves. If an individually addressed slave determines that the data it has sent has been returned to it incorrectly or that the number of clock pulses is not a multiple of 8 bits, it can signal this error to the master by inverting the closing control byte. iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 32/36 RSET settings iC-JX can either generate an internal reference current or permit external current settings via pin RSET. Setting the current externally is the more precise option here; to this end it is recommended that pin RSET be linked up to a 10 k resistor connected to ground.. I/O stages in input mode funktion Input registers (add. 0x00 and 0x01: reading the inputs A high at IOx generates a high signal at bit INx. Any change to an input signal is accepted via digital filtering only after the selected filter time has expired. Here, the input comparator of each I/O stage reverses the count direction of a 3-bit counter. The counter output changes only when the final status has been reached. The counters are reset to a value of 3 by a low signal at reset input NRES. The counter is clocked externally by pin CLK or by clock ICLK, generated internally. The scaling factor for the clock frequency and the input filter bypass can be programmed separately for all four nibbles (see control word 1, addresses 0x14 and 0x15). Switching the bypass (BYP1...4) permits operation without an external clock signal (see below). Once the change-of-input message has been enabled in the change-of-input interrupt enable register (addresses 0x10 and 0x11) a change of level at one of the I/O pins is signaled to the microcontroller. If iCJX is operated at the parallel interface the level at pin NINT is set to 0. If the device is operated at the serial interface a change of level is indicated by a 0 at pin SO(D1) resp SOB (D2), depending upon configuration (see SPI interfacd, page 26). The microcontroller can determine which I/O stage has had a change of input by reading out the input register. I/O stages in output mode Input registers (addresses 0x00 and 0x01): reading the output feedback A high at IOx generates a high signal at INx. This allows the microcontroller to make a direct check of the switching state and, with the help of the programmable high-side current sources of 200 A, 600 A and 2 mA, to monitor the channel for any cable fractures. As with the reading of inputs the feedback signals can be output in their filtered or unfiltered state. The microcontroller can determine which I/O stage has had a change of input by reading out the input register. Programmable Current Sources (Adr. 0x16 und 0x17) The programmable pull-up- resp. pull-down current sources can be set independently of the I/O mode (either input or output mode). In both modes current values of 200 A, 600 A or 2 mA are available either as pull-up or pull down. ADC measurements ADC measurements: measuring current (Adr. 0x1C) In this mode the current in each output stage can be measured. Here, the saturation voltage from an internal reference transistor is used for comparison. Each output stage has its own reference transistor in order to guarantee a precise value. The reference voltage is equivalent to the saturation voltage of the output stage transistor with a nominal current of 150 mA; the output digital value thus corresponds to the current intensity in the output stage. To evaluate current variations in the output stage the controller must perform an initial measurement with a known reference current. Based on this value a monitoring of the load current can then be performed. The output stage thereby is selected via SELES(3:0) in control word 5 (Adr. 0x1B). ADC measurements: measuring voltage (Adr. 0x1C) iC-JX enables voltage at the I/O stage to be recorded. The range for voltage measured at the output stage lies between VB - 5 V and VB (bit EME = 1) and between VB - 0.6 V and VB (EME = 0). When measuring in conjunction with pull-up current sources the range lies between 0 V and 5 V (EME = 1) and between 0 V and 0.6 V (EME = 0). VIO VBy 5V 36V max. 0.6V VR1 VR2 VR5 5V 0 0.6V VR3 VR4 Figure 15: ADC measurement ranges The iC-JX measures voltages at the I/O stages in different ranges. The range "Voltage Measurement High at IO" is between VB - 5 V and VB (Bit EME = 1) resp. between VB - 0.6 V and VB (EME = 0). In the mode "Voltage Measurement Low at IO" the range is between 0 and 5 V (Bit EME = 1) resp. between 0 and 0.6 V and VB (EME = 0). iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 33/36 For the mode "Overall Voltage Measurement at IO" the voltage at the selected I/O stage is downscaled first by a factor of 1/15 using a resistive voltage divider to permit measurement of the full voltage range from rail to rail. The user must be aware of a input current drawn by the voltage divider of approimately V(IO)/200k. The selection of the I/O stage is done via control word 5 (Adr. 0x1B). ADC Measurements: VBy and VBG Measurements (Adr. 0x1C) The internal reference voltage VBG and the external supply voltages VB1 to VB4 can also be measured. For VB1 to VB4, the voltage is downscaled first by a factor of 1/15. Selection is done via SELES (3:0) in control word 5 (Adr. 0x1B) as described in the following table. SELES(3:0) VB - Messung 0x0 .. 0x3 VB1 0x4 .. 0x7 VB2 0x8 .. 0xB VB3 0xC .. 0xF VB4 ADC Measurements: Temperature Measurement (Adr. 0x1C) In this feature the internal chip temperature can be determined. ADC Measurements: External Vref (Adr. 0x1C) To improve accuracy of the A/D conversion, an external reference voltage at pin VREF can be used by setting the bit SVREF to '0b1'. The value of the external voltage reference should be about 2.5V 0.2%. ADC Measurements: Output A 10 bit digital value as a result of A/D convertion is available for output currents and output voltages at a selected I/O stage, for chip temperature and supply voltages Vby and the internal bandgap voltage VBG. Except for the current measurement, the internal voltage V(VREFAD) (for Bit SVREF = '0') or an external voltage at pin Vref (for Bit SVREF = '1') are used as reference. The end of A/D conversion is signalled by a low signal '0' at NINT resp. D1/SOC or D2/SOB. Output register (Adr. 0x0C und 0x0D): Switches the various output stages on and off (for POE = 1). Flash pulse enable (addresses 0x0E und 0x0F): Enables flash mode This function enables each of the various output stages to be set to flash mode, providing the value of the corresponding output register is 1. The flash frequency is derived from BLFQ or, alternatively, can be generated from CLK or from the internally generated ICLK (via SEBLQ in control word 3B, address 0x1A). Different flash frequencies can be set for all four nibbles. Interrupts Interrupt readings at NINT can be triggered by a change of (filtered) input signal, by an overcurrent message signaled at an I/O pin (due to a short circuit, for example), by undervoltage at VCC or VDD, by bursts at VDD, by the end of A/D conversion or by exceeding maximum temperature thresholds (2 stages). Interrupt outputs for each individual I/O stage can be caused by a change of input, or, with stages in output mode, by a short circuit. The relevant interrupt enables determine which messages are stored and which are displayed. The display of interrupt messages caused by excessive temperature, A/D conversion, undervoltage or bursts is not maskable; this particular function is permanently enabled. When an event occurs which is enabled to produce an interrupt message pin NINT is set to 0 when a parallel interface is used. If the device is being operated with a serial interface outputs D1/SOC or D2/SOB are set to 0 when an interrupt occurs if no communication is made via the interface itself and pin A4 ist set to '1' . By reading out the interrupt status register (addresses 0x04 and 0x05) the nature of the message can be determined and the I/O stage causing the interrupt located. Thus with a change-of-input message the problematic I/O stage is shown in the corresponding register (addresses 0x02 and 0x03); with an overcurrent interrupt the overcurrent status register (addresses 0x06 and 0x07) pinpoints the I/O stage with a short circuit. Interrupts are deleted by simply setting EOI in control word 4 (address 0x1A). This bit then automatically resets to 0. If during operation the I/O mode is switched, i.e. from input to output mode, all interrupt messages are deleted via EOI. To avoid interrupt messages caused by other sources in the time between the readout of a status register and the deletion of the current interrupt being overlooked successive interrupts are stored in a pipeline. If successive interrupts occur outputs NINT resp. D1/SOC or D2/SOB remain at 0 after the present interrupt has been deleted using EOI. The new interrupt source is displayed in the interrupt status register and in the specific status registers. Overcurrent messages If an overload occurs at one of the outputs the current in IOx is limited. In this instance an interrupt message is triggered, providing relevant interrupt enables have been set for overcurrent messages (addresses 0x12 and 0x13) and the filter time set with control word 4 (address 0x1A) has elapsed. ISCI is then set in the interrupt status register (address 0x04) and the relevant bit for the I/O stage causing the problem is set iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 34/36 in the overcurrent message register (addresses 0x06 and 0x07). At addresses 0x08 and 0x09 the actual, unfiltered overcurrent status of each I/O stage can be read; a global scan of all I/O stages is also possible via bit SCS in the interrupt status register. This shows whether any of the I/O stages have overcurrent at the time of the readout. This short-circuit messaging allows permanent monitoring of the output transistors and clear allocation of error message to affected I/O stage. Filtering of the overcurrent message can be shutdown using a bypass; this bypass can be activated for all I/O stages together using BYPSCF in control word 4 (address 0x1A). Temperature monitoring iC-JX has a two-stage temperature monitor circuit. Stage 1: A warning interrupt is generated if the first temperature threshold (Toff1 at ca. 132 C) is exceeded. Suitable measures to decrease the power dissipation of the driver can be implemented using the microcontroller. Stage 2: If the second temperature threshold is exceeded (Toff2 at ca. 152 C), a second interrupt is generated. At the same time the output transistors and the I/O stage current sources are shutdown and the output register and flash pulse enable deleted. Once the temperature has returned to below the level of Toff1 the current sources are reactivated. The output register and flash pulse enable have to be respecified to reactivate the output stages The interrupt status register (address 0x04) provides information as to the temperature interrupt stage but also on the current status of the temperature monitor. ET2 and ET1 statically indicate when Toff2 and Toff1 are exceeded, whereby stored interrupt messages IET2 and IET1 and the display at NINT via EOI = 1 can be deleted (control word 4, address 0x1A). Undervoltage detection: VCC and VDD When the supply voltage at VCC or VDD is switched on the output transistors are only released by the undervoltage detector after power-on enables VCCon or VDDon have been reached. Should the supply voltage drop to VCCoff or VDDoff during operation the I/O stages are disabled, i.e. the output transistors are turned off and the device reset. At the same time interrupt outputs are set. USD and USA in interrupt status register B (address 0x05) statically indicate undervoltage at VCC and VDD. Stored interrupt messages IUSD and IUSA and the display at NINT or SO(D1) can be deleted by setting EOI to 1 in control word 4 (address 0x1A). Should the supply voltage then again rise to VCCon or VDDon, iC-JX assumes a reset state. Undervoltage detection: VB1...4 In order to guarantee the fail-safe operation of connected loads voltage VB is also monitored. If the voltage drops below threshold VBoff the I/O outputs are disabled. Neither a device reset nor an interrupt message to the microcontroller are then triggered. Once voltage VB again rises above VBon the I/O outputs are re-enabled. The microcontroller can read out the status of voltage VB at bit DID1 in the device ID register (address 0x0C). In the event of error (VB < VBoff) this bit is set to 1. Pin monitoring GNDD and GNDA iC-JX includes a pin watchdog circuit which monitors the connection between the two ground pins GNDA and GNDD. The microcontroller can detect a possible error, such as a disconnected iC lead, for example, by reading bit IBA in the device ID register. In the event of error this is set to 1. If such a case of an error is present, then the potential of the missing ground pin is raised, which can lead to the shift of the trigger levels. Burst detection at VDD As in principle bursts at VDD can influence the contents of registers iC-JX monitors spikes in the supply. If any hazard is detected interupt outputs are set to 0. Stored interrupt message ISD (interrupt status register B, address 0x05) can be deleted by setting EOI to 1 in control word 4 (address 0x1A). Device identification An identification code has been introduced to enable identification of iC-JX. Bit pattern 0b10101 can be read out at address 0x0D. Reset A reset (NRES = 0) sets the register entries to the reset values given in the tables. Operation without the BLFQ signal Should no clock signal be available at pin BLFQ iC-JX can generate an internal flash pulse from the external clock signal at pin CLK or from clock signal ICLK which is generated internally. For the flash frequency to be derived from the system clock pulse bit SEBLQ in control word 3B (address 0x19) must be set to 1. The flash period is then calculated by dividing by 2 19 . Operation without the CLK signal iC-JX can also be operated without a clock pulse at pin CLK. Using control word 3B (address 0x1A) the device can be set to an internally generated clock frequency; In this instance all filter functions remain fully available. iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 35/36 Via SECLK(1:0) in control word 3B the clocked filtering for the I/O signals and overcurrent messaging can also be deactivated. The same behavior can be obtained by setting BYP0, BYP1, BYP2 and BYP3 in control word 1 (addresses 0x14 and 0x15) together with BYPSCF in control word 4 (address 0x1A); all filters are avoided by way of a bypass circuit. Here it must be noted that interferences in the line can lead to the unwanted display of interrupts. Forced shutdown of output stages The output stages can be forcibly shutdown at input POE. A '1' enables logic access to the drivers; a '0' disables this. This function allows a processorindependent watchdog to lock the outputs in the event of error, for example. An integrated pull-down resistor increases safety. DESIGN REVIEW: Notes On Chip Functions iC-JX X2 (and previous) No. Function, Parameter/Code Description and Application Hints 1 Leakage current beyond operating conditions (Elec- During operation, supply voltages VCC, VDD and trical Characteristics Item No. 019 VB1..VB4 must already be present and stable to avoid elevated leakage currents at pins IOx (x=1..16). Table 8: Notes on chip functions regarding iC-JX chip version X2 and previous versions iC-JX X3 No. Function, Parameter/Code Description and Application Hints 1 Leakage current beyond operating conditions (Elec- Leakage currents < 200 A trical Characteristics Item No. 019 Table 9: Notes on chip functions regarding iC-JX version X3 iC-Haus expressly reserves the right to change its products and/or specifications. An Infoletter gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by email. Copying - even as an excerpt - is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to. iC-JX 16-FOLD 24 V HIGH-SIDE DRIVER WITH C INTERFACE Rev C1, Page 36/36 ORDERING INFORMATION Type iC-JX Evaluation Board Package MQFP52 - Order Designation iC-JX MQFP52 iC-JX EVAL JX2D For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com Appointed local distributors: http://www.ichaus.com/sales_partners |
Price & Availability of IC-JXEVALJX2D
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |