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PWM Controller and Transformer Driver with Quad-Channel Isolators ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
FEATURES
Isolated PWM controller Integrated transformer driver Regulated adjustable output: 3.3 V to 24 V 2 W output power 70% efficiency at guaranteed load of 400 mA at 5.0 V output Quad dc-to-25 Mbps (NRZ) signal isolation channels 20-lead SSOP package High temperature operation: 105C High common-mode transient immunity: >25 kV/s 200 kHz to 1 MHz adjustable oscillator frequency Soft start function at power-up Pulse-by-pulse overcurrent protection Thermal shutdown 2500 V rms isolation
VCC
FUNCTIONAL BLOCK DIAGRAMS
T1 RECT VREG VISO
X1
X2
VDD1
ADuM3470/ADuM3471/ ADuM3472/ADuM3473/ ADuM3474
CONVERTER PRIMARY DRIVER FB
REG
VDD2 5V
SECONDARY CONTROLLER CHA
FB OC
VDDA I/OA I/OB I/OC I/OD GND1 GND2 CHB PRIMARY DATA I/O 4CH SECONDARY DATA I/O 4CH I/OA I/OB I/OC I/OD
CHC
CHD
APPLICATIONS
RS-232/RS-422/RS-485 transceivers Industrial field bus isolation Power supply startup bias and gate drives Isolated sensor interfaces Process controls
Figure 1. Functional Block Diagram
ADuM3470 ADuM3471
GENERAL DESCRIPTION
The ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 devices1 are quad-channel, digital isolators with an integrated PWM controller and transformer driver for an isolated dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler(R) technology, the dc-to-dc converter provides up to 2 W of regulated, isolated power at 3.3 V to 24 V from a 5.0 V input supply or from a 3.3 V supply. This eliminates the need for a separate, isolated dc-to-dc converter in 2 W isolated designs. The iCoupler chip-scale transformer technology is used to isolate the logic signals, and the integrated transformer driver with isolated secondary side control provides higher efficiency for the isolated dc-to-dc converter. The result is a small form factor, total isolation solution. The ADuM347x isolators provide four independent isolation channels in a variety of channel configurations and data rates. (The x in ADuM347x throughout this data sheet stands for the ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474.)
ADuM3472
ADuM3473
ADuM3474
Figure 2. Block Diagrams of I/O Channels
1
Protected by U.S. Patents 5,952,849; 6,873,065; and 7075 329 B2. Other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
09369-003
09369-001
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics--5 V Primary Input Supply/5 V Secondary Isolated Supply .......................................................... 3 Electrical Characteristics--3.3 V Primary Input Supply/3.3 V Secondary Isolated Supply .......................................................... 5 Electrical Characteristics--5 V Primary Input Supply/3.3 V Secondary Isolated Supply .......................................................... 7 Electrical Characteristics--5 V Primary Input Supply/15 V Secondary Isolated Supply .......................................................... 9 Package Characteristics ............................................................. 11 Regulatory Approvals................................................................. 11 Insulation and Safety-Related Specifications .......................... 11 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 12 Recommended Operating Conditions .................................... 12 Absolute Maximum Ratings.......................................................... 13 ESD Caution ................................................................................ 13 Pin Configurations and Function Descriptions ......................... 14 Typical Performance Characteristics ........................................... 19 Terminology .................................................................................... 24 Applications Information .............................................................. 25 Theory of Operation .................................................................. 25 Application Schematics ............................................................. 25 Transformer Design ................................................................... 26 Transformer Turns Ratio ........................................................... 26 Transformer ET Constant ......................................................... 26 Transformer Primary Inductance and Resistance ................. 26 Transformer Isolation Voltage .................................................. 27 Switching Frequency .................................................................. 27 Transient Response .................................................................... 27 Component Selection ................................................................ 27 Printed Circuit Board (PCB) Layout ....................................... 28 Thermal Analysis ....................................................................... 28 Propagation Delay-Related Parameters ................................... 28 DC Correctness and Magnetic Field Immunity........................... 29 Power Consumption .................................................................. 30 Power Considerations ................................................................ 30 Insulation Lifetime ..................................................................... 31 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32
REVISION HISTORY
10/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS--5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
4.5 V (VDD1 = VDDA) 5.5 V; VDD2 = VREG = VISO = 5.0 V; fSW = 500 kHz; all voltages are relative to their respective grounds; see the application schematic in Figure 38. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = VDDA = 5.0 V, VDD2 = VREG = VISO = 5.0 V. Table 1.
Parameter DC-TO-DC CONVERTER POWER SUPPLY Isolated Output Voltage Feedback Voltage Setpoint Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency Symbol VISO VFB VISO (LINE) VISO (LOAD) VISO (RIP) VISO (N) fSW 192 Switch On-Resistance Undervoltage Lockout, VCC, VDD2 Supplies Positive Going Threshold Negative Going Threshold Hysteresis iCoupler DATA CHANNELS DC to 2 Mbps Data Rate 1 Maximum Output Supply Current 2 Efficiency at Maximum Output Supply Current 3 ICC Supply Current, No VISO Load ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 25 Mbps Data Rate (CRWZ Grade Only) ICC Supply Current, No VISO Load ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 Available VISO Supply Current 4 ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 ICC Supply Current, Full VISO Load I/O Input Currents Logic High Input Threshold Logic Low Input Threshold RON VUV+ VUV- VUVH Min 4.5 1.15 Typ 5.0 1.25 1 1 50 100 1000 200 318 0.5 2.8 2.6 0.2 Max 5.5 1.35 10 2 Unit V V mV/V % mV p-p mV p-p kHz kHz kHz V V V Test Conditions/Comments IISO = 0 mA, VISO = VFB x (R1 + R2)/R2 IISO = 0 mA IISO = 50 mA, VCC = 4.5 V to 5.5 V IISO = 50 mA to 200 mA 20 MHz bandwidth, COUT = 0.1 F||47 F, IISO = 100 mA 20 MHz bandwidth, COUT = 0.1 F||47 F, IISO = 100 mA ROC = 50 k ROC = 270 k VOC = VDD2 (open loop)
515
IISO (MAX)
400 70
mA %
f 1 MHz, VISO = 5.0 V IISO = IISO (MAX), f 1 MHz IISO = 0 mA, f 1 MHz
ICC (Q) 14 15 16 17 18 ICC (D) 44 46 48 50 52 IISO (LOAD) 390 388 386 384 382 550 -20 2.0 +0.01 +20 0.8 mA mA mA mA mA mA A V V mA mA mA mA mA 30 30 30 30 30 mA mA mA mA mA
ICC (MAX) IIA, IIB, IIC, IID VIH VIL
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz fSW = 500 kHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 0 pF, f = 0 MHz, VDD = 5 V, IISO = 400 mA
Rev. 0 | Page 3 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Parameter Logic High Output Voltages Symbol VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL Min VCC - 0.3, VISO - 0.3 VCC - 0.5, VISO - 0.3 Logic Low Output Voltages Typ 5.0 4.8 0.0 0.0 AC SPECIFICATIONS ADuM347xARWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM347xCRWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching, Codirectional Channels Channel-to-Channel Matching, Opposing Directional Channels Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate
1 2
Max
Unit V V V V
Test Conditions/Comments IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
0.1 0.4
PW 1 tPHL, tPLH PWD tPSK tPSKCD/tPSKOD PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD tR/tF |CMH| |CML| fr 2.5 35 35 1.0 25 30 45 5 55
1000 100 40 50 50 40 60 6 15 6 15
ns Mbps ns ns ns ns ns Mbps ns ns ps/C ns ns ns ns kV/s kV/s Mbps
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, V = 1000 V, transient magnitude = 800 V
25 25
The contributions of supply current values for all four channels are combined at identical data rates. The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels was not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate.
Rev. 0 | Page 4 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ELECTRICAL CHARACTERISTICS--3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
3.0 V (VDD1 = VDDA) 3.6 V; VDD2 = VREG =VISO = 3.3 V; fSW = 500 kHz; all voltages are relative to their respective grounds; see the application schematic in Figure 38. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = VDDA = 3.3 V, VDD2 = VREG = VISO = 3.3 V. Table 2.
Parameter DC-TO-DC CONVERTER POWER SUPPLY Isolated Output Voltage Feedback Voltage Setpoint Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency Symbol VISO VFB VISO (LINE) VISO (LOAD) VISO (RIP) VISO (N) fSW 192 Switch On-Resistance Undervoltage Lockout, VCC, VDD2 Supplies Positive Going Threshold Negative Going Threshold Hysteresis iCoupler DATA CHANNELS DC to 2 Mbps Data Rate 1 Maximum Output Supply Current 2 Efficiency at Maximum Output Supply Current 3 ICC Supply Current, No VISO Load ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 25 Mbps Data Rate (CRWZ Grade Only) ICC Supply Current, No VISO Load ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 Available VISO Supply Current 4 ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 ICC Supply Current, Full VISO Load I/O Input Currents Logic High Input Threshold Logic Low Input Threshold RON VUV+ VUV- VUVH Min 3.0 1.15 Typ 3.3 1.25 1 1 50 100 1000 200 318 0.6 2.8 2.6 0.2 Max 3.6 1.35 10 2 Unit V V mV/V % mV p-p mV p-p kHz kHz kHz V V V Test Conditions/Comments IISO = 0 mA, VISO = VFB x (R1 + R2)/R2 IISO = 0 mA IISO = 50 mA, VCC = 3.0 V to 3.6 V IISO = 20 mA to 100 mA 20 MHz bandwidth, COUT = 0.1 F||47 F, IISO = 100 mA 20 MHz bandwidth, COUT = 0.1 F||47 F, IISO = 100 mA ROC = 50 k ROC = 270 k VOC = VDD2 (open loop)
515
IISO (MAX)
250 70
mA %
f 1 MHz, VISO = 3.3 V IISO = IISO (MAX), f 1 MHz IISO = 0 mA, f 1 MHz
ICC (Q) 9 10 11 11 12 ICC (D) 28 29 31 32 34 IISO (LOAD) 244 243 241 240 238 350 -10 1.6 +0.01 +10 0.4 mA mA mA mA mA mA A V V mA mA mA mA mA 20 20 20 20 20 mA mA mA mA mA
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 0 pF, f = 0 MHz, VDD = 3.3 V, IISO = 250 mA
ICC (MAX) IIA, IIB, IIC, IID VIH VIL
Rev. 0 | Page 5 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Parameter Logic High Output Voltages Symbol VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL Min VCC - 0.2, VISO - 0.2 VCC - 0.5, V1SO - 0.5 Logic Low Output Voltages Typ 5.0 4.8 0.0 0.0 AC SPECIFICATIONS ADuM347xARWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM347xCRWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching, Codirectional Channels Channel-to-Channel Matching, Opposing Directional Channels Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate
1 2
Max
Unit V V V V
Test Conditions/Comments IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
0.1 0.4
PW 1 tPHL, tPLH PWD tPSK tPSKCD/tPSKOD PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD tR/tF |CMH| |CML| fr 2.5 35 35 1.0 25 30 60 5 60
1000 100 40 50 50 40 75 8 45 8 15
ns Mbps ns ns ns ns ns Mbps ns ns ps/C ns ns ns ns kV/s kV/s Mbps
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, V = 1000 V, transient magnitude = 800 V
25 25
The contributions of supply current values for all four channels are combined at identical data rates. The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels was not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate.
Rev. 0 | Page 6 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ELECTRICAL CHARACTERISTICS--5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
4.5 V (VDD1 = VDDA) 5.5 V; VDD2 = VREG = VISO = 3.3 V; fSW = 500 kHz; all voltages are relative to their respective grounds; see the application schematic in Figure 38. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = VDDA = 5.0 V, VDD2 = VREG = VISO = 3.3 V. Table 3.
Parameter DC-TO-DC CONVERTER POWER SUPPLY Isolated Output Voltage Feedback Voltage Setpoint Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency Symbol VISO VFB VISO (LINE) VISO (LOAD) VISO (RIP) VISO (N) fSW 209 Switch On-Resistance Undervoltage Lockout, VCC, VDD2 Supplies Positive Going Threshold Negative Going Threshold Hysteresis iCoupler DATA CHANNELS DC to 2 Mbps Data Rate 1 Maximum Output Supply Current 2 Efficiency at Maximum Output Supply Current 3 ICC Supply Current, No VISO Load ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 25 Mbps Data Rate (CRWZ Grade Only) ICC Supply Current, No VISO Load ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 Available VISO Supply Current 4 ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 ICC Supply Current, Full VISO Load I/O Input Currents Logic High Input Threshold Logic Low Input Threshold RON VUV+ VUV- VUVH Min 3.0 1.15 Typ 3.3 1.25 1 1 50 100 1000 200 318 0.5 2.8 2.6 0.2 Max 3.6 1.35 10 2 Unit V V mV/V % mV p-p mV p-p kHz kHz kHz V V V Test Conditions/Comments IISO = 0 mA, VISO = VFB x (R1 + R2)/R2 IISO = 0 mA IISO = 50 mA, VCC = 4.5 V to 5.5 V IISO = 50 mA to 200 mA 20 MHz bandwidth, COUT = 0.1 F||47 F, IISO = 100 mA 20 MHz bandwidth, COUT = 0.1 F||47 F, IISO = 100 mA ROC = 50 k ROC = 270 k VOC = VDD2 (open loop)
515
IISO (MAX)
400 70
mA %
f 1 MHz, VISO = 3.3 V IISO = IISO (MAX), f 1 MHz IISO = 0 mA, f 1 MHz
ICC (Q) 9 9 10 10 10 ICC (D) 33 33 33 33 33 IISO (LOAD) 393 392 390 389 388 375 -20 2.0 +0.01 +20 0.8 mA mA mA mA mA mA A V V mA mA mA mA mA 30 30 30 30 30 mA mA mA mA mA
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 0 pF, f = 0 MHz, VDD = 5 V, IISO = 400 mA
ICC (MAX) IIA, IIB, IIC, IID VIH VIL
Rev. 0 | Page 7 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Parameter Logic High Output Voltages Symbol VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL Min VCC - 0.3, VISO - 0.3 VCC - 0.5, VISO - 0.3 Logic Low Output Voltages Typ 5.0 4.8 0.0 0.0 AC SPECIFICATIONS ADuM347xARWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM347xCRWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching, Codirectional Channels Channel-to-Channel Matching, Opposing Directional Channels Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate
1 2
Max
Unit V V V V
Test Conditions/Comments IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
0.1 0.4
PW 1 tPHL, tPLH PWD tPSK tPSKCD/tPSKOD PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD tR/tF |CMH| |CML| fr 2.5 35 35 1.0 25 30 50 5 55
1000 100 40 50 50 40 70 8 15 8 15
ns Mbps ns ns ns ns ns Mbps ns ns ps/C ns ns ns ns kV/s kV/s Mbps
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, V = 1000 V, transient magnitude = 800 V
25 25
The contributions of supply current values for all four channels are combined at identical data rates. The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels was not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate.
Rev. 0 | Page 8 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ELECTRICAL CHARACTERISTICS--5 V PRIMARY INPUT SUPPLY/15 V SECONDARY ISOLATED SUPPLY
4.5 V (VDD1 = VDDA) 5.5 V; VREG = VISO = 15 V; VDD2 = 5.0 V; fSW = 500 kHz; all voltages are relative to their respective grounds; see the application schematic in Figure 39. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = VDDA = 5.0 V, VREG = VISO = 15 V, VDD2 = 5.0 V. Table 4.
Parameter DC-TO-DC CONVERTER POWER SUPPLY Isolated Output Voltage Feedback Voltage Setpoint VDD2 Linear Regulator Regulator Voltage Dropout Voltage Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency Symbol VISO VFB VDD2 VDD2DO VISO (LINE) VISO (LOAD) VISO (RIP) VISO (N) fSW 192 Switch On-Resistance Undervoltage Lockout, VCC, VDD2 Supplies Positive Going Threshold Negative Going Threshold Hysteresis iCoupler DATA CHANNELS DC to 2 Mbps Data Rate 1 Maximum Output Supply Current 2 Efficiency at Maximum Output Supply Current 3 ICC Supply Current, No VISO Load ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 25 Mbps Data Rate (CRWZ Grade Only) ICC Supply Current, No VISO Load ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 Available VISO Supply Current 4 ADuM3470 ADuM3471 ADuM3472 ADuM3473 ADuM3474 ICC Supply Current, Full VISO Load I/O Input Currents Logic High Input Threshold Logic Low Input Threshold RON VUV+ VUV- VUVH Min 13.8 1.15 4.6 Typ 15 1.25 5.0 0.5 1 1 200 500 1000 200 318 0.5 2.8 2.6 0.2 Max 16.2 1.35 5.4 1.5 10 3 Unit V V V V mV/V % mV p-p mV p-p kHz kHz kHz V V V Test Conditions/Comments IISO = 0 mA, VISO = VFB x (R1 + R2)/R2 IISO = 0 mA VREG = 7 V to 15 V, IDD2 = 0 mA to 50 mA IDD2 = 50 mA IISO = 50 mA, VCC = 4.5 V to 5.5 V IISO = 20 mA to 100 mA 20 MHz bandwidth, COUT = 0.1 F||47 F, IISO = 100 mA 20 MHz bandwidth, COUT = 0.1 F||47 F, IISO = 100 mA ROC = 50 k ROC = 270 k VOC = VDD2 (open loop)
515
IISO (MAX)
100 70
mA %
f 1 MHz, VISO = 5.0 V IISO = IISO (MAX), f 1 MHz IISO = 0 mA, f 1 MHz
ICC (Q) 25 27 29 31 33 ICC(D) 73 83 93 102 112 IISO (LOAD) 91 89 86 83 80 425 -20 2.0 +0.01 +20 0.8 mA mA mA mA mA mA A V V mA mA mA mA mA 45 45 45 45 45 mA mA mA mA mA
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 0 pF, f = 0 MHz, VDD = 5 V, IISO = 100 mA
ICC (MAX) IIA, IIB, IIC, IID VIH VIL
Rev. 0 | Page 9 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Parameter Logic High Output Voltages Symbol VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL Min VCC - 0.3, VISO - 0.3 VCC - 0.5, VISO - 0.3 Logic Low Output Voltages Typ 5.0 4.8 0.0 0.0 AC SPECIFICATIONS ADuM347xARWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM347xCRWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching, Codirectional Channels Channel-to-Channel Matching, Opposing Directional Channels Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate
1 2
Max
Unit V V V V
Test Conditions/Comments IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
0.1 0.4
PW 1 tPHL, tPLH PWD tPSK tPSKCD/tPSKOD PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD tR/tF |CMH| |CML| fr 2.5 35 35 1.0 25 30 45 5 55
1000 100 40 50 50 40 60 6 15 6 15
ns Mbps ns ns ns ns ns Mbps ns ns ps/C ns ns ns ns kV/s kV/s Mbps
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, V = 1000 V, transient magnitude = 800 V
25 25
The contributions of supply current values for all four channels are combined at identical data rates. The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels was not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate.
Rev. 0 | Page 10 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
PACKAGE CHARACTERISTICS
Table 5.
Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 Input Capacitance 2 IC Junction to Ambient Thermal Resistance Thermal Shutdown Thermal Shutdown Threshold Thermal Shutdown Hysteresis
1 2 3
Symbol RI-O CI-O CI JA
Min
Typ 1012 2.2 4.0 50.5
Max
Unit pF pF C/W
Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces 3 TJ rising
TSSD TSSD-HYS
150 20
C C
The device is considered a 2-terminal device: Pin 1 to Pin 8 is shorted together; and Pin 9 to Pin 16 is shorted together. Input capacitance is from any input data pin to ground. See the Thermal Analysis section for thermal model definitions.
REGULATORY APPROVALS (PENDING)
Table 6.
UL Recognized under the UL 1577 component recognition program 1 Single protection, 2500 V rms isolation voltage File E214100
1
CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 600 V rms (848 V peak) maximum working voltage File 205078
VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 2 Reinforced insulation, 560 V peak
File 2471900-4880-0001
In accordance with UL 1577, each ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 is proof tested by applying an insulation test voltage of 3000 V rms for 1 sec (current leakage detection limit = 10 A). 2 In accordance with DIN V VDE V 0884-10, each of the ADuM347x is proof tested by applying an insulation test voltage of 1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 7.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Symbol L(I01) L(I02) Value 2500 >5.1 >5.1 Unit V rms mm mm Test Conditions/Comments 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group
0.017 min mm >400 V II
Rev. 0 | Page 11 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval. Table 8.
Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety Limiting Values Case Temperature Side 1 Current Insulation Resistance at TS Test Conditions/Comments Symbol Characteristic I to IV I to III I to II 40/105/21 2 560 1050 Unit
VIORM x 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM x 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM x 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 sec Maximum value allowed in the event of a failure (see Figure 3)
VIORM VPR VPR
V peak V peak
896 672 VTR 4000
V peak V peak V peak
VIO = 500 V
TS IS1 RS
150 1.25 >109
C A
1.50
SAFE OPERATING VCC CURRENT (mA)
1.25
1.00
0.75
0.50
0.25
0
0
50 100 150 AMBIENT TEMPERATURE (C)
200
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 9.
Parameter Operating Temperature Supply Voltages 1 VCC at VISO = 3.3 V VCC at VISO = 5.0 V VCC at VISO = 5.0 V Minimum Load
1
Symbol TA VCC VCC VCC IISO (MIN)
Min -40 3.0 3.0 4.5 10
09369-002
Max +105 3.6 3.6 5.5
Unit C V V V mA
All voltages are relative to their respective grounds.
Rev. 0 | Page 12 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25C, unless otherwise noted. Table 10.
Parameter Storage Temperature Range (TST) Ambient Operating Temperature Range (TA) Supply Voltages VDD1, VDDA, VDD2 1 VREG, X1, X21 Input Voltage (VIA, VIB, VIC, VID)1, 2 Output Voltage (VOA, VOB, VOC, VOD)1, 2 Average Output Current per Pin 3 Common-Mode Transients 4
1 2
Rating -55C to +150C -40C to +105C
-0.5 V to +7.0 V -0.5 V to +20.0 V -0.5 V to VDDI + 0.5 V -0.5 V to VDDO + 0.5 V -10 mA to +10 mA -100 kV/s to +100 kV/s
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 11. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1
Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation DC Voltage Basic Insulation
1
All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the Printed Circuit Board (PCB) Layout section. 3 See Figure 3 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage.
Max 565
Unit V peak
Applicable Certification All certifications
848
V peak
Working voltage per IEC 60950-1 Working voltage per IEC 60950-1
848
V peak
Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
ESD CAUTION
Rev. 0 | Page 13 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
X1 1 *GND1 2 VDD1 3 X2 4 VIA 5 VIB 6 VIC 7 VID 8 VDDA 9 *GND1 10
20 VREG 19 GND2* 18 VDD2 17 FB 16 VOA 15 VOB 14 VOC 13 VOD 12 OC 11 GND2*
ADuM3470
TOP VIEW (Not to Scale)
*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 4. ADuM3470 Pin Configuration
Table 12. ADuM3470 Pin Function Descriptions
Pin No. 1 2, 10 3 4 5 6 7 8 9 11, 19 12 Mnemonic X1 GND1 VDD1 X2 VIA VIB VIC VID VDDA GND2 OC Description Transformer Driver Output 1. Ground 1. Ground reference for isolator primary. Transformer Driver Supply Voltage 3.0 V to 5.5 V. Connect to VDDA pin. Connect a 10 F bypass capacitor from VDD1 to GND1. Transformer Driver Output 2. Logic Input A. Logic Input B. Logic Input C. Logic Input D. Primary Supply Voltage 3.0 V to 5.5 V. Connect to VDD1 pin. Connect a 0.1 F bypass capacitor from VDDA to GND1. Ground Reference for Isolator Side 2. Oscillator Control Pin. When OC = logic high = VDD2, the secondary controller runs open-loop. To regulate the output voltage, connect a resistor between the OC pin and GND2, and the secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. Logic Output D. Logic Output C. Logic Output B. Logic Output A. Feedback Input from the Secondary Output Voltage VISO. Use a resistor divider from VISO to the FB pin to make the VFB voltage equal to the 1.25 V internal reference level using the VISO = VFB x (R1 + R2)/R2 formula. The resistor divider is required even in open-loop mode to provide soft start. The Internal Supply Voltage Pin for the Secondary Side Controller and Side 2 Data Channels. When a sufficient external voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the 3.0 V to 5.5 V range. Connect a 0.1 F bypass capacitor from VDD2 to GND2. The Input of the Internal Regulator to Power the Secondary Side Controller and Side 2 Data Channels. VREG should be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
13 14 15 16 17
VOD VOC VOB VOA FB
18
VDD2
20
VREG
Rev. 0 | Page 14 of 32
09369-004
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
X1 1 *GND1 2 VDD1 3 X2 4 VIA 5 VIB 6 VIC 7 VOD 8 VDDA 9 *GND1 10
20 VREG 19 GND2* 18 VDD2 17 FB 16 VOA 15 VOB 14 VOC 13 VID 12 OC 11 GND2*
ADuM3471
TOP VIEW (Not to Scale)
*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 5. ADuM3471 Pin Configuration
Table 13. ADuM3471 Pin Function Descriptions
Pin No. 1 2, 10 3 4 5 6 7 8 9 11, 19 12 Mnemonic X1 GND1 VDD1 X2 VIA VIB VIC VOD VDDA GND2 OC Description Transformer Driver Output 1. Ground 1. Ground reference for isolator primary. Transformer Driver Supply Voltage 3.0 V to 5.5 V. Connect to VDDA pin. Connect a 10 F bypass capacitor from VDD1 to GND1. Transformer Driver Output 2. Logic Input A. Logic Input B. Logic Input C. Logic Output D. Primary Supply Voltage 3.0 V to 5.5 V. Connect to VDD1 pin. Connect a 0.1 F bypass capacitor from VDDA to GND1. Ground Reference for Isolator Side 2. Oscillator Control Pin. When OC = logic high = VDD2, the secondary controller runs open-loop. To regulate the output voltage, connect a resistor between the OC pin and GND2, and the secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. Logic Input D. Logic Output C. Logic Output B. Logic Output A. Feedback Input from the Secondary Output Voltage VISO. Use a resistor divider from VISO to the FB pin to make the VFB voltage equal to the 1.25 V internal reference level using the VISO = VFB x (R1 + R2)/R2 formula. The resistor divider is required even in open-loop mode to provide soft start. The Internal Supply Voltage Pin for the Secondary Side Controller and Side 2 Data Channels. When a sufficient external voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the 3.0 V to 5.5 V range. Connect a 0.1 F bypass capacitor from VDD2 to GND2. The Input of the Internal Regulator to Power the Secondary Side Controller and Side 2 Data Channels. VREG should be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
13 14 15 16 17
VID VOC VOB VOA FB
18
VDD2
20
VREG
Rev. 0 | Page 15 of 32
09369-005
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
X1 1 *GND1 2 VDD1 3 X2 4 VIA 5 VIB 6 VOC 7 VOD 8 VDDA 9 *GND1 10
20 VREG 19 GND2* 18 VDD2 17 FB 16 VOA 15 VOB 14 VIC 13 VID 12 OC 11 GND2*
ADuM3472
TOP VIEW (Not to Scale)
*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 6. ADuM3472 Pin Configuration
Table 14. ADuM3472 Pin Function Descriptions
Pin No. 1 2, 10 3 4 5 6 7 8 9 11, 19 12 Mnemonic X1 GND1 VDD1 X2 VIA VIB VOC VOD VDDA GND2 OC Description Transformer Driver Output 1. Ground 1. Ground reference for isolator primary. Transformer Driver Supply Voltage 3.0 V to 5.5 V. Connect to VDDA pin. Connect a 10 F bypass capacitor from VDD1 to GND1. Transformer Driver Output 2. Logic Input A. Logic Input B. Logic Output C. Logic Output D. Primary Supply Voltage 3.0 V to 5.5 V. Connect to VDD1 pin. Connect a 0.1 F bypass capacitor from VDDA to GND1. Ground Reference for Isolator Side 2. Oscillator Control pin. When OC = logic high = VDD2, the secondary controller runs open-loop. To regulate the output voltage, connect a resistor between the OC pin and GND2, and the secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. Logic Input D. Logic Input C. Logic Output B. Logic Output A. Feedback Input from the Secondary Output Voltage VISO. Use a resistor divider from VISO to the FB pin to make the VFB voltage equal to the 1.25 V internal reference level using the VISO = VFB x (R1 + R2)/R2 formula. The resistor divider is required even in open-loop mode to provide soft start. The Internal Supply Voltage Pin for the Secondary Side Controller and Side 2 Data Channels. When a sufficient external voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the 3.0 V to 5.5 V range. Connect a 0.1 F bypass capacitor from VDD2 to GND2. The Input of an Internal Regulator to Power the Secondary Side Controller and Side 2 Data Channels. VREG should be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
13 14 15 16 17
VID VIC VOB VOA FB
18
VDD2
20
VREG
Rev. 0 | Page 16 of 32
09369-006
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
X1 1 *GND1 2 VDD1 3 X2 4 VIA 5 VOB 6 VOC 7 VOD 8 VDDA 9 *GND1 10
20 VREG 19 GND2* 18 VDD2 17 FB 16 VOA 15 VIB 14 VIC 13 VID 12 OC 11 GND2*
ADuM3473
TOP VIEW (Not to Scale)
*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 7. ADuM3473 Pin Configuration
Table 15. ADuM3473 Pin Function Descriptions
Pin No. 1 2, 10 3 4 5 6 7 8 9 11, 19 12 Mnemonic X1 GND1 VDD1 X2 VIA VOB VOC VOD VDDA GND2 OC Description Transformer Driver Output 1. Ground 1. Ground reference for isolator primary. Transformer Driver Supply Voltage 3.0 V to 5.5 V. Connect to VDDA pin. Connect a 10 F bypass capacitor from VDD1 to GND1. Transformer Driver Output 2. Logic Input A. Logic Output B. Logic Output C. Logic Output D. Primary Supply Voltage 3.0 V to 5.5 V. Connect to VDD1 pin. Connect a 0.1 F bypass capacitor from VDDA to GND1. Ground Reference for Isolator Side 2. Oscillator Control Pin. When OC = logic high = VDD2, the secondary controller runs open-loop. To regulate the output voltage, connect a resistor between the OC pin and GND2, and the secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. Logic Input D. Logic Input C. Logic Input B. Logic Output A. Feedback Input from the Secondary Output Voltage VISO. Use a resistor divider from VISO to the FB pin to make the VFB voltage equal to the 1.25 V internal reference level using the VISO = VFB x (R1 + R2)/R2 formula. The resistor divider is required even in open-loop mode to provide soft start. The Internal Supply Voltage Pin for the Secondary Side Controller and Side 2 Data Channels. When a sufficient external voltage is supplied to VREG,the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the 3.0 V to 5.5 V range. Connect a 0.1 F bypass capacitor from VDD2 to GND2. The Input of an Internal Regulator to Power the Secondary Side Controller and Side 2 Data Channels. VREG should be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
13 14 15 16 17
VID VIC VIB VOA FB
18
VDD2
20
VREG
Rev. 0 | Page 17 of 32
09369-007
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
X1 1 *GND1 2 VDD1 3 X2 4 VOA 5 VOB 6 VOC 7 VOD 8 VDDA 9 *GND1 10
20 VREG 19 GND2* 18 VDD2 17 FB 16 VIA 15 VIB 14 VIC 13 VID 12 OC 11 GND2*
ADuM3474
TOP VIEW (Not to Scale)
*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 8. ADuM3474 Pin Configuration
Table 16. ADuM3474 Pin Function Descriptions
Pin No. 1 2, 10 3 4 5 6 7 8 9 11, 19 12 Mnemonic X1 GND1 VDD1 X2 VOA VOB VOC VOD VDDA GND2 OC Description Transformer Driver Output 1. Ground 1. Ground reference for isolator primary. Transformer Driver Supply Voltage 3.0 V to 5.5 V. Connect to VDDA pin. Connect a 10 F bypass capacitor from VDD1 to GND1. Transformer Driver Output 2. Logic Output A. Logic Output B. Logic Output C. Logic Output D. Primary Supply Voltage 3.0 V to 5.5 V. Connect to VDD1 pin. Connect a 0.1 F bypass capacitor from VDDA to GND1. Ground Reference for Isolator Side 2. Oscillator Control Pin. When OC = logic high = VDD2, the secondary controller runs open-loop. To regulate the output voltage, connect a resistor between the OC pin and GND2, and the secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. Logic Input D. Logic Input C. Logic Input B. Logic Input A. Feedback Input from the Secondary Output Voltage VISO. Use a resistor divider from VISO to the FB pin to make the VFB voltage equal to the 1.25 V internal reference level using the VISO = VFB x (R1 + R2)/R2 formula. The resistor divider is required even in open-loop mode to provide soft start. The Internal Supply Voltage Pin for the Secondary Side Controller and Side 2 Data Channels. When a sufficient external voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the 3.0 V to 5.5 V range. Connect a 0.1 F bypass capacitor from VDD2 to GND2. The input of an internal regulator used to power the secondary side controller and Side 2 data channels. VREG should be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
13 14 15 16 17
VID VIC VIB VIA FB
18
VDD2
20
VREG
Table 17. Truth Table (Positive Logic)
VIx Input 1 High Low
1
VCC State Powered Powered
VDD2 State Powered Powered
VOxOutput1 High Low
Notes Normal operation, data is high Normal operation, data is low
VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
Rev. 0 | Page 18 of 32
09369-008
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 TYPICAL PERFORMANCE CHARACTERISTICS
1500 1400 1300 1200 1100
EFFICIENCY (%)
80 70 60 50 40 30 20 10
09369-009
1000
fSW (kHz)
900 800 700 600 500 400 300 200 100 0 0 50 100 150 200 250 ROC () 300 350 400 450 500
-40C 25C 105C 0 50 100 150 200 250 300 350 400 450 500
09369-012
0 LOAD CURRENT (mA)
Figure 9. Switching Frequency (fSW) vs. ROC Resistance
80 70 60
EFFICIENCY (%)
Figure 12. 5 V In to 5 V Out Efficiency over Temperature with Coilcraft Transformer at 500 kHz fSW
80 70 60
EFFICIENCY (%) 1MHz 700kHz 500kHz 200kHz
09369-010
50 40 30 20 10 0 0 50 100 150 200 250 300 350 400 450 500 LOAD CURRENT (mA)
50 40 30 20 10 0 0 50 100 150 200 250 300 350 400 450 500 LOAD CURRENT (mA) 5V IN TO 5V OUT 5V IN TO 3.3V OUT 3.3V IN TO 3.3V OUT
09369-013 09369-014
Figure 10. Typical Efficiency at 5 V In to 5 V Out at Various Switching Frequencies with Coilcraft Transformer
80 70 60
Figure 13. Single-Supply Efficiency with Coilcraft Transformer at 500 kHz fSW
80 70 60
EFFICIENCY (%)
EFFICIENCY (%)
50 40 30 20 10 0 0 50 100 150 200 250 300 350 400 450 500 LOAD CURRENT (mA) 1MHz 700kHz 500kHz 200kHz
09369-011
50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 LOAD CURRENT (mA) 1MHz 700kHz 500kHz 200kHz
Figure 11. Typical Efficiency at 5 V In to 5 V Out at Various Switching Frequencies with Halo Transformer
Figure 14. 5 V In to 15 V Out Efficiency at Various Switching Frequencies with Coilcraft Transformer
Rev. 0 | Page 19 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
80 70 60 15
EFFICIENCY (%)
10 50 40 30 5 20 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 LOAD CURRENT (mA) 1MHz 700kHz 500kHz 200kHz
09369-026
ICH (mA)
VCC = 5V, VISO = 5V VCC = 5V, VISO = 3.3V VCC = 3.3V, VISO = 3.3V 0 5 10 15 20 25
09369-029
09369-031
0 DATA RATE (Mbps)
Figure 15. 5 V In to 15 V Out Efficiency at Various Switching Frequencies with Halo Transformer
80 70 60
Figure 18. Typical Single-Supply ICH Supply Current per Forward Data Channel (15 pF Output Load)
15
EFFICIENCY (%)
10 50 40 30 5 20 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 LOAD CURRENT (mA) -40C 25C 105C
09369-027
ICH (mA)
VCC = 5V, VISO = 5V VCC = 5V, VISO = 3.3V VCC = 3.3V, VISO = 3.3V 0 5 10 15 20 25
09369-030
0 DATA RATE (Mbps)
Figure 16. 5 V In to 15 V Out Efficiency over Temperature with Coilcraft Transformer at 500 kHz fSW
80 70
Figure 19. Typical Single-Supply ICH Supply Current per Reverse Data Channel (15 pF Output Load)
5 VCC = 5V, VISO = 5V VCC = 5V, VISO = 3.3V VCC = 3.3V, VISO = 3.3V
4
60
EFFICIENCY (%)
IISO (D) (mA)
5V IN TO 15V OUT 5V IN TO 12V OUT
09369-028
50 40 30 20
3
2
1
10 0 0 10 20 30 40 50 60 70 80
0 0 5 10 15 20 25 DATA RATE (Mbps)
90 100 110 120 130 140
LOAD CURRENT (mA)
Figure 17. Double-Supply Efficiency with Coilcraft Transformer at 500 kHz fSW
Figure 20. Typical Single-Supply IISO (D) Dynamic Supply Current per Output Channel (15 pF Output Load)
Rev. 0 | Page 20 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
5 VCC = 5V, VISO = 5V VCC = 5V, VISO = 3.3V VCC = 3.3V, VISO = 3.3V 5 VCC = 5V, VISO = 15V VCC = 5V, VISO = 12V 4
4
IISO (D) (mA)
IISO (D) (mA)
09369-032
3
3
2
2
1
1
0
5
10
15
20
25
0
5
10
15
20
25
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 21. Typical Single Supply IISO (D) Dynamic Supply Current per Input Channel
30 VCC = 5V, VISO = 15V VCC = 5V, VISO = 12V
Figure 24. Typical Double Supply IISO (D) Dynamic Supply Current per Output Channel (15 pF Output Load)
5 VCC = 5V, VISO = 15V VCC = 5V, VISO = 12V 4
25
20
IISO (D) (mA) ICH (mA)
3
15
2
10 1
5
09369-033
0
5
10
15
20
25
0
5
10
15
20
25
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 22. Typical Double Supply ICH Supply Current per Forward Data Channel (15 pF Output Load)
30 VCC = 5V, VISO = 15V VCC = 5V, VISO = 12V
Figure 25. Typical Double Supply IISO (D) Dynamic Supply Current per Input Channel
6
25
5
20
ICH (mA) VISO (V)
4
15
3
10
2
5
1
VISO AT 10mA VISO AT 50mA VISO AT 400mA 0 5 10 15 TIME (ms) 20 25 30
09369-037
0
5
10
15
20
25
DATA RATE (Mbps)
Figure 23. Typical Double Supply ICH Supply Current per Reverse Data Channel (15 pF Output Load)
09369-034
0
0
Figure 26. Typical VISO Startup 5 V In to 5 V Out with 10 mA, 50 mA, and 400 mA Output Load
Rev. 0 | Page 21 of 32
09369-036
0
0
09369-035
0
0
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
5 6.0 5.5 4
VISO (V)
COUT = 47F, L1 = 47H
5.0 4.5
3
VISO (V)
6.0 5.5 COUT = 47F, L1 = 100H
2
5.0 4.5
1
ILOAD (A)
VISO AT 10mA VISO AT 50mA VISO AT 400mA
09369-038
1.0 0.5 0 -2 0 90% LOAD 10% LOAD
09369-041 09369-044 09369-042
0 0 5 10 15 TIME (ms) 20 25 30
2
4
6 TIME (ms)
8
10
12
14
Figure 27. Typical VISO Startup 5 V In to 3.3 V Out with 10 mA, 50 mA, and 400 mA Output Load
5
Figure 30. Typical VISO Load Transient Response 5 V In to 5 V Out at 10% to 90% of 400 mA Load at 500 kHz fSW
4.0 COUT = 47F, L1 = 47H 3.5
4
VISO (V)
3.0
3
VISO (V)
4.0 COUT = 47F, L1 = 100H 3.5
2
3.0
VISO AT 10mA VISO AT 50mA VISO AT 250mA 0 5 10 15 TIME (ms) 20 25 30
09369-039
ILOAD (A)
1
1.0 0.5 0 -2 90% LOAD 10% LOAD
0
0
2
4
6 TIME (ms)
8
10
12
14
Figure 28. Typical VISO Startup 3.3 V In to 3.3 V Out with 10 mA, 50 mA, and 250 mA Output Load
18 16 14 12
VISO (V)
Figure 31. Typical VISO Load Transient Load Response 5 V In to 3.3 V Out at 10% to 90% Load of 400 mA Load at 500 kHz fSW
4.0 COUT = 47F, L1 = 47H 3.5 3.0
VISO (V)
4.0 COUT = 47F, L1 = 100H 3.5 3.0
10 8 6 4 2 0 0 5 10 15 TIME (ms) 20 25 30 VISO AT 10mA VISO AT 20mA VISO AT 100mA
09369-040
ILOAD (A)
1.0 0.5 0 -2 90% LOAD 10% LOAD
0
2
4
6 TIME (ms)
8
10
12
14
Figure 29. Typical VISO Startup 5 V In to 15 V Out with 10 mA, 20 mA, and 100 mA Output Load
Figure 32. Typical VISO Load Transient Response 3.3 V In to 3.3 V Out at 10% to 90% of 250 mA Load at 500 kHz fSW
Rev. 0 | Page 22 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
18 16 14
VISO (V)
COUT = 47F, L1 = 47H, L2 = 47H
3.34
12 18 16 14 12 COUT = 47F, L1 = 100H, L2 = 100H
VISO (V)
3.32
3.30
3.28 20
X1 (V)
ILOAD (A)
200 100 0 -2 10% LOAD 90% LOAD
X2 ON 10 X1 ON
09369-047 09369-048
0
2
4
6 TIME (ms)
8
10
12
14
09369-043
0 -2
-1
0 TIME (s)
1
2
Figure 33. Typical VISO Load Transient Response 5 V In to 15 V Out at 10% to 90% of 100 mA Load at 500 kHz fSW
5.04
Figure 36. Typical VISO Output Ripple 3.3 V In to 3.3 V Out at 250 mA Load at 500 kHz fSW
15.4
5.02
VISO (V) VISO (V)
15.2
15.0
5.00
14.8 4.98 14.6 20
X1 (V)
X2 ON
X1 (V)
20
X2 ON
10 X1 ON
09369-045
10
X1 ON
0 -2
-1
0 TIME (s)
1
2
0 -2
-1
0 TIME (s)
1
2
Figure 34. Typical VISO Output Ripple 5 V In to 5 V Out at 400 mA Load at 500 kHz fSW
3.34
Figure 37. Typical VISO Output Ripple 5 V In to 15 V Out at 100 mA Load at 500 kHz fSW
3.32
VISO (V)
3.30
3.28 20 X2 ON
X1 (V)
10
X1 ON
-1
0 TIME (s)
1
2
Figure 35. Typical VISO Output Ripple 5 V In to 3.3 V Out at 400 mA Load at 500 kHz fSW
09369-046
0 -2
Rev. 0 | Page 23 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 TERMINOLOGY
ICC (Q) ICC (Q) is the minimum operating current drawn at the VCC power input when there is no external load at VISO and the I/O pins are operating below 2 Mbps, requiring no additional dynamic supply current. ICC (D) ICC (D) is the typical input supply current with all channels simultaneously driven at a maximum data rate of 25 Mbps with the full capacitive load representing the maximum dynamic load conditions. Treat resistive loads on the outputs separately from the dynamic load. ICC (MAX) ICC (MAX) is the input current under full dynamic and VISO load conditions. tPHL Propagation Delay tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH Propagation Delay tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. Propagation Delay Skew (tPSK) tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Channel-to-Channel Matching Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. Minimum Pulse Width The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Maximum Data Rate The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
Rev. 0 | Page 24 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 APPLICATIONS INFORMATION
THEORY OF OPERATION
The dc-to-dc converter section of the ADuM347x uses a secondary side controller architecture with isolated pulse-width modulation (PWM) feedback. VCC power is supplied to an oscillating circuit that switches current to the primary of an external power transformer using internal push-pull switches at the X1 and X2 pins. Power transferred to the secondary side of the transformer is full-wave rectified with external Schottky diodes (D1 and D2), filtered with the L1 inductor and COUT capacitor, and regulated to the isolated power supply voltage from 3.3 V to 15 V. The secondary (VISO) side controller regulates the output by using a feedback voltage VFB from a resistor divider on the output and creating a PWM control signal that is sent to the primary (VCC) side by a dedicated iCoupler data channel labeled VFB. The primary side PWM converter varies the duty cycle of the X1 and X2 switches to modulate the oscillator circuit and control the power being sent to the secondary side. This feedback allows for significantly higher power and efficiency. The ADuM347x implement undervoltage lockout (UVLO) with hysteresis on the VCC power input. This feature ensures that the converter does not go into oscillation due to noisy input power or slow power-on ramp rates. A minimum load current of 10 mA is recommended to ensure optimum load regulation. Smaller loads can generate excess noise on the output due to short or erratic PWM pulses. Excess noise generated this way can cause regulation problems, in some circumstances.
1 X1 2 GND1 3 VDD1 4 X2 5 I/OA 6 I/OB 7 I/OC 8 I/OD VCC 0.1F 9 VDDA 10 GND1
D1 T1
L1 47H COUT 47F
VISO = +3.3V TO +15V R1
VCC CIN D2
1 X1 2 GND1 3 VDD1 4 X2 5 I/OA 6 I/OB 7 I/OC 8 I/OD VCC 0.1F 9 VDDA 10 GND1
20 VREG 19 GND2 18 VDD2 17 FB 16 I/OA 15 I/OB 14 I/OC 13 I/OD 12 OC 11 GND2
0.1F +5V VFB R2
ADuM3470/ ADuM3471/ ADuM3472/ ADuM3473/ ADuM3474
ROC 100k
VISO = VFB x (R1+R2)/R2 FOR VISO = 3.3V OR 5V CONNECT VREG , VDD2 , AND VISO.
Figure 38. Single Power Supply
D1 T1 47H VCC CIN D2 L2 47H COUT2 47F D3 R1 47F COUT1 L1 VISO = +12V TO +24V UNREGULATED +6V TO +12V
D4
20 VREG 19 GND2 18 VDD2 17 FB 16 I/OA 15 I/OB 14 I/OC 13 I/OD 12 OC 11 GND2
09369-016
ADuM3470/ ADuM3471/ ADuM3472/ ADuM3473/ ADuM3474
0.1F +5V VFB R2
APPLICATION SCHEMATICS
The ADuM347x has three main application schematics, as shown in Figure 38 to Figure 40. Figure 38 has a center-tapped secondary and two Schottky diodes providing full wave rectification for a single output, typically for power supplies of 3.3 V, 5 V, 12 V, and 15 V. For single supplies when VISO = 3.3 V or VISO = 5 V, see the note in Figure 38 about connecting together VREG, VDD2, and VISO. Figure 39 is a voltage doubling circuit that can be used for a single supply whose output exceeds 15 V, which is the largest supply that can be connected to the regulator input VREG (Pin 20) of the part. With Figure 39, the output voltage can be as high as 24 V and the VREG pin only about 12 V. Figure 40, which also uses a voltage doubling secondary circuit, is shown as an example of a coarsely regulated, positive power supply and an unregulated, negative power supply, for outputs of approximately 5 V, 12 V, and 15 V. For any circuit in Figure 38, Figure 39, or Figure 40, the isolated output voltage (VISO) can be set using the voltage dividers, R1 and R2 (values 1 k to 100 k), in the application schematics using the following equation:
ROC 100k
VISO = VFB x (R1 + R2)/R2 FOR VISO = 15V OR LESS, VREG CAN CONNECT TO VISO.
Figure 39. Doubling Power Supply
D1 T1 47H VCC CIN D2 L2 47H R1 D4 COUT2 47F D3 UNREGULATED -5V TO -15V 47F COUT1 L1 VISO = COARSELY REGULATED +5V TO 15V
1 X1 2 GND1 3 VDD1 4 X2 5 I/OA 6 I/OB 7 I/OC 8 I/OD VCC 0.1F 9 VDDA 10 GND1
20 VREG 19 GND2
V ISO
R1 + R2 = V FB x R2
ADuM3470/ ADuM3471/ ADuM3472/ ADuM3473/ ADuM3474
18 VDD2 17 FB 16 I/OA 15 I/OB 14 I/OC 13 I/OD 12 OC 11 GND2
0.1F +5V VFB R2
ROC 100k
09369-017
where VFB is the internal feedback voltage, which is approximately 1.25 V.
VISO = VFB x (R1 + R2)R2
Figure 40. Positive and Unregulated Negative Supply
Rev. 0 | Page 25 of 32
09369-015
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
TRANSFORMER DESIGN
Transformers have been designed for use in the circuits shown in Figure 38, Figure 39, and Figure 40 and are listed in Table 18. The design of a transformer for the ADuM347x can differ from some isolated dc-to-dc converter designs that do not regulate the output voltage. The output voltage is regulated by a PWM controller in the ADuM347x that varies the duty cycle of the primary side switches in response to a secondary side feedback voltage, VFB, received through an isolated digital channel. The internal controller has a limit of 40% maximum duty cycle.
For Figure 40, the circuit also uses double windings and diode pairs to create a doubler circuit; however, because a positive and negative output voltage is created, VISO is used in the equation. VISO + VD NS = N P VCC ( MIN ) x D x 2 where: N is the primary to secondary turns ratio. VISO is the isolated output supply voltage and is used in the equation because the circuit uses two pairs of diodes creating a doubler circuit with a positive and negative output. VD is the Schottky diode voltage drop (0.5 V maximum). VCC (MIN) is the minimum input supply voltage, and a multiplier factor of 2 is used for the push-pull switching cycle. A higher duty cycle of D = 0.35 for a 35% typical duty cycle (40% is maximum) was used in the Figure 40 circuit to reduce the maximum voltages seen by the diodes for a 15 V supply. For Figure 40, the +5 V to 15 V reference design in Table 18, with VCC (MIN) = 4.5 V, the turns ratio is NS/NP = 5.
TRANSFORMER TURNS RATIO
To determine the transformer turns ratio, and taking into account the losses for the primary switches and the losses for the secondary diodes and inductors, the external transformer turns ratio for the ADuM347x can be calculated by
NS V ISO + VD = N P VCC ( MIN ) x D x 2 where: NS/NP is the primary to secondary turns ratio. VISO is the isolated output supply voltage. VD is the Schottky diode voltage drop (0.5 V maximum). VCC (MIN) is the minimum input supply voltage. D is the duty cycle = 0.30 for a 30% typical duty cycle, 40% is maximum, and a multiplier factor of 2 is used for the push-pull switching cycle. For Figure 38, the 5 V to 5 V reference design in Table 18, with VCC (MIN) = 4.5 V, the turns ratio is NS/NP = 2. For a similar 3.3 V to 3.3 V single power supply and with VCC (MIN) = 3.0 V, the turns ratio is also NS/NP = 2. Therefore, the same transformer turns ratio NS/NP = 2 can be used for the three single power applications (5 V to 5 V, 5 V to 3.3 V, and 3.3 V to 3.3 V). For Figure 39, the circuit uses double windings and diode pairs to create a doubler circuit; therefore, half the output voltage, VISO/2, is used in the equation. V ISO NS NP = 2 VCC ( MIN ) x D x 2 + VD
TRANSFORMER ET CONSTANT
The next transformer design factor to consider is the ET constant. This constant determines the minimum V x s constant of the transformer over the operating temperature. ET values of 14 V x s and 18 V x s were selected for the ADuM347x designs listed in Table 18 using the following equation:
ET ( Min) = VCC ( MAX ) f SW ( MIN ) x 2
where: VCC (MAX) is the maximum input supply voltage. fSW (MIN) is the minimum primary switching frequency = 300 kHz in startup, and a multiplier factor of 2 is used for the push-pull switching cycle.
TRANSFORMER PRIMARY INDUCTANCE AND RESISTANCE
Another important characteristic of the transformer for designs with the ADuM347x is the primary inductance. Transformers for the ADuM347x are recommended to have between 60 H to 100 H of inductance per primary winding. Values of primary inductance in this range are needed for smooth operation of the ADuM347x pulse-by-pulse current-limit circuit, which can help protect against build up of saturation currents in the transformer. If the inductance is specified for the total of both primary windings, for example, as 400 H, the inductance of one winding is 1/4 of two equal windings, or 100 H. Another important characteristic of the transformer for designs with the ADuM347x is primary resistance. Primary resistance as low as is practical (less than 1 ) helps reduce losses and improves efficiency. The dc primary resistance can be measured and specified, and is shown for the transformers in Table 18.
NS/NP is the primary to secondary turns ratio. VISO/2 is used in the equation because the circuit uses two pairs of diodes creating a doubler circuit. VD is the Schottky diode voltage drop (0.5 V maximum). VCC (MIN) is the minimum input supply voltage. D is duty cycle which equals 0.30 for a 30% typical duty cycle, 40% is maximum, and a multiplier factor of 2 is used for the push-pull switching cycle. For Figure 39, the 5 V to 15 V reference design in Table 18, with VCC (MIN) = 4.5 V, the turns ratio is NS/NP = 3.
Rev. 0 | Page 26 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Table 18. Transformer Reference Designs
Part No. JA4631-BL JA4650-BL KA4976-AL TGSAD-260V6LF TGSAD-290V6LF TGSAD-292V6LF TGAD-260NARL TGAD-290NARL TGAD-292NARL Manufacturer Coilcraft Coilcraft Coilcraft Halo Electronics Halo Electronics Halo Electronics Halo Electronics Halo Electronics Halo Electronics Turns Ratio, PRI:SEC 1CT:2CT 1CT:3CT 1CT:5CT 1CT:2CT 1CT:3CT 1CT:5CT 1CT:2CT 1CT:3CT 1CT:5CT ET Constant (V x s Min) 18 18 18 14 14 14 14 14 14 Total Primary Inductance (H) 255 255 255 389 389 389 389 389 389 Total Primary Resistance () 0.2 0.2 0.2 0.8 0.8 0.8 0.8 0.8 0.8 Isolation Voltage (rms) 2500 2500 2500 2500 2500 2500 1500 1500 1500 Isolation Type Basic Basic Basic Supplemental Supplemental Supplemental Functional Functional Functional Reference Figure 38 Figure 39 Figure 40 Figure 38 Figure 39 Figure 40 Figure 38 Figure 39 Figure 40
TRANSFORMER ISOLATION VOLTAGE
Isolation voltage and isolation type should be determined for the requirements of the application and then specified. The transformers in Table 18 have been specified for 2500 V rms for supplemental or basic isolation and for 1500 V rms functional isolation. Other isolation levels and isolation voltages can be specified and requested from the manufacturers in Table 18 or from other manufacturers.
TRANSIENT RESPONSE
The load transient response of the output voltage of the ADuM347x for 10% to 90% of the full load is shown in Figure 30 to Figure 33 for the application schematics in Figure 38 and Figure 39. The response shown is slow but stable and can have more output change than desired for some applications. The output voltage change with load transient has been reduced, and the output has been shown to remain stable by adding more inductance to the output circuits, as shown in the second VISO output waveform in Figure 30 to Figure 33.
SWITCHING FREQUENCY
The ADuM347x switching frequency can be adjusted from 200 kHz to 1 MHz by changing the value of the ROC resistor shown in Figure 38, Figure 39, and Figure 40. The value of the ROC resistor needed for the desired switching frequency can be determined from the switching frequency vs. ROC resistance curve shown in Figure 9. The output filter inductor value and output capacitor value for the ADuM347x application schematics have been designed to be stable over the switching frequency range from 500 kHz to 1 MHz, when loaded from 10% to 90% of the maximum load. The ADuM347x also has an open-loop mode where the output voltage is not regulated and is dependent on the transformer turns ratio, NS/NP, and the conditions of the output including output load current and the losses in the dc-to-dc converter circuit. This open-loop mode is selected when the OC pin is connected high to the VDD2 pin. In open-loop mode, the switching frequency is 318 kHz.
COMPONENT SELECTION
The ADuM347x digital isolators with 2 W dc-to-dc converters require no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins. Note that a low ESR ceramic bypass capacitor of 0.1 F is required on Side 1 between Pin 9 and Pin 10, and on Side 2 between Pin 18 and Pin 19, as close to the chip pads as possible. The power supply section of the ADuM347x uses a high oscillator frequency to efficiently pass power through the external power transformer. In addition, normal operation of the data section of the iCoupler introduces switching transients on the power supply pins. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. To suppress noise and reduce ripple, large-valued ceramic capacitors of X5R or X7R dielectric type are recommended. The recommended capacitor value is 10 F for VDD1 and 47 F for VISO. These capacitors have a low ESR and are available in moderate 1206 or 1210 sizes for voltages up to 10 V. For output voltages larger than 10 V, two 22 F ceramic capacitors can be used in parallel. See Table 19 for recommended components.
Rev. 0 | Page 27 of 32
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Inductors must be selected based on the value and supply current needed. Most applications with switching frequencies between 500 kHz and 1 MHz and load transients between 10% and 90% of full load are stable with the 47 H inductor value listed in Table 19. Values as large as 200 H can be used for power supply applications with a switching frequency as low as 200 kHz to help stabilize the output voltage or for improved load transient response (see Figure 30 to Figure 33). Inductors in a small 1212 or 1210 size are listed in Table 19 with a 47 H value and a 0.41 A current rating to handle the majority of applications below a 400 mA load, and with a 100 H value and a 0.34 A current rating to handle a load to 300 mA. Schottky diodes are recommended for their low forward voltage to reduce losses and their high reverse voltage of up to 40 V to withstand the peak voltages available in the doubling circuit shown in Figure 39 and Figure 40.
Table 19. Recommended Components
Part Number GRM32ER71A476KE15L GRM32ER71C226KEA8L GRM31CR71A106KA01L MBR0540T1-D LQH3NPN470MM0 ME3220-104KL Manufacturer Murata Murata Murata ON Semiconductor Murata Coilcraft Value 47 F, 10 V, X7R, 1210 22 F, 16 V, X7R, 1210 10 F, 10 V, X7R, 1206 0.5 A, 40 V, Schottky, SOD-123 47 H, 0.41 A, 1212 100 H, 0.34 A, 1210
The ADuM347x are power devices that dissipate about 1 W of power when fully loaded and running at maximum speed. Because it is not possible to apply a heat sink to an isolation device, the devices primarily depend on heat dissipation into the PCB through the GND pins. If the devices are used at high ambient temperatures, care must be taken to provide a thermal path from the GNDx pins to the PCB ground plane. The board layout shows enlarged pads for the GNDx pins (Pin 2 and Pin 10) on Side 1 and (Pin 11 and Pin 19) on Side 2. Large diameter vias should be implemented from the pad to the ground planes and power planes to increase thermal conductivity and to reduce inductance. Multiple vias in the thermal pads can significantly reduce temperatures inside the chip. The dimensions of the expanded pads are left to the discretion of the designer and the available board space.
THERMAL ANALYSIS
The ADuM347x parts consist of two internal die attached to a split lead frame with two die attach paddles. For the purposes of thermal analysis, the die are treated as a thermal unit, with the highest junction temperature reflected in the JA from Table 5. The value of JA is based on measurements taken with the parts mounted on a JEDEC standard, 4-layer board with fine width traces and still air. Under normal operating conditions, the ADuM347x devices operate at full load across the full temperature range without derating the output current. However, following the recommendations in the Printed Circuit Board (PCB) Layout section decreases thermal resistance to the PCB, allowing increased thermal margins in high ambient temperatures. The ADuM347x has an thermal shutdown circuit that shuts down the dc-to-dc converter and the outputs of the ADuM347x when a die temperature of about 160C is reached. When the die cools below about 140C, the ADuM347x dc-to-dc converter and outputs turn on again.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
Note that the total lead length between the ends of the low ESR capacitor and the VDDx and GNDx pins must not exceed 2 mm. Installing the bypass capacitor with traces more than 2 mm in length can result in data corruption. See Figure 41 for the recommended PCB layout.
X1 GND1 VDD1 X2 VIA/VOA VIB/VOB VIC/VOC VID/VOD VDDA GND1 VREG GND2 VDD2 FB VOA/VIA VOB/VIB VOC/VIC VOD/VID OC GND2
09369-025
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see Figure 42). The propagation delay to a logic low output may differ from the propagation delay to a logic high output.
INPUT (VIx) 50%
tPLH
OUTPUT (VOx)
tPHL
50%
09369-018
Figure 42. Propagation Delay Parameters
Figure 41. Recommended PCB Layout
In applications involving high common-mode transients, take care to ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins, exceeding the absolute maximum ratings specified in Table 10, thereby leading to latch-up and/or permanent damage.
Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM347x component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM347x components operating under the same conditions.
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ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 1 s, periodic sets of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 17) by the watchdog timer circuit. This situation should occur in the ADuM347x devices only during power-up and power-down operations. The limitation on the ADuM347x magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3.3 V operating condition of the ADuM347x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude of >1.0 V. The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (-d/dt)rn2; n = 1, 2, ... , N where: is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM347x and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 43.
100
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGauss)
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM347x transformers. Figure 44 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 44, the ADuM347x are extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example, a 0.5 kA current needs to be placed 5 mm away from the ADuM347x to affect component operation.
1k
MAXIMUM ALLOWABLE CURRENT (kA)
DISTANCE = 1m 100
10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 44. Maximum Allowable Current for Various Current-to-ADuM347x Spacings
10
In combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
1
0.1
0.01
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 43. Maximum Allowable External Magnetic Flux Density
Rev. 0 | Page 29 of 32
09369-019
0.001 1k
09369-020
0.01
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
POWER CONSUMPTION
The VCC power supply input provides power to the iCoupler data channels, as well as to the power converter. For this reason, the quiescent currents drawn by the data converter and the primary and secondary I/O channels cannot be determined separately. All of these quiescent power demands have been combined into the ICC (Q) current, as shown in Figure 45. The total ICC supply current is equal to the sum of the quiescent operating current; the dynamic current, ICC (D), demanded by the I/O channels; and any external IISO load.
ICC (Q) ICC (D) CONVERTER PRIMARY FB CONVERTER SECONDARY IISO
The preceding analysis assumes a 15 pF capacitive load on each data output. If the capacitive load is larger than 15 pF, the additional current must be included in the analysis of IDD1 and IISO (LOAD).
POWER CONSIDERATIONS
Soft Start Mode and Current-Limit Protection
When the ADuM347x first receives power from VCC, it is in soft start mode, and the output voltage VISO is increased gradually while it is below the startup threshold. In soft start mode, the width of the PWM signal is increased gradually by the primary converter to limit the peak current during VISO power-up. When the output voltage is larger than the startup threshold, the PWM signal can be transferred from the secondary controller to the primary converter, and the dc-to-dc converter switches from soft start mode to the normal PWM control mode. If a short circuit occurs, the push-pull converter shuts down for about 2 ms and then enters soft start mode. If, at the end of soft start, a short circuit still exists, the process is repeated, which is called hiccup mode. If the short circuit is cleared, the ADuM347x enters normal operation. The ADuM347x also has a pulse-by-pulse current limit, which is active in startup and normal operation, and protects the primary switches, X1 and X2, from exceeding approximately 1.2 A peak and also protects the transformer windings.
IDDP(D)
IISO(D)
PRIMARY DATA I/O 4CH
SECONDARY DATA I/O 4CH
09369-024
Figure 45. Power Consumption Within the ADuM347x
Dynamic I/O current is consumed only when operating a channel at speeds higher than the refresh rate of fr. The dynamic current of each channel is determined by its data rate. Figure 18 and Figure 22 show the current for a channel in the forward direction, meaning that the input is on the VCC side of the part. Figure 19 and Figure 23 show the current for a channel in the reverse direction, meaning that the input is on the VISO side of the part. Figure 18, Figure 19, Figure 22, and Figure 23 assume a typical 15 pF output load. The following relationship allows the total IDD1 current to be ICC = (IISO x VISO)/(E x VCC) + ICHn; n = 1 to 4 (1) where: ICC is the total supply input current. IISO is the current drawn by the secondary side external load. E is the power supply efficiency at the given output load from Figure 13 or Figure 17 at the VISO and VCC condition of interest. ICHn is the current drawn by a single channel determined from Figure 18, Figure 19, Figure 22, or Figure 23, depending on channel direction. The maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load. IISO (LOAD) = IISO (MAX) - IISO (D)n; n = 1 to 4 (2) where: IISO (LOAD) is the current available to supply an external secondary side load. IISO (MAX) is the maximum external secondary side load current available at VISO. IISO (D)n is the dynamic load current drawn from VISO by an output or input channel, as shown for a single supply in Figure 20 or Figure 21 or for a double supply in Figure 24 or Figure 25.
Data Channel Power Cycle
The ADuM347x data input channels on the primary side and the data input channels on the secondary side are protected from premature operation by UVLO circuitry. Below the minimum operating voltage, the power converter holds its oscillator inactive, and all input channel drivers and refresh circuits are idle. Outputs are held in a low state. This is to prevent transmission of undefined states during power-up and power-down operations. During application of power to VCC, the primary side circuitry is held idle until the UVLO preset voltage is reached. At that time, the data channels are initialized to their default low output state until they receive data pulses from the secondary side. The primary side input channels sample the input and send a pulse to the inactive secondary output. The secondary side converter begins to accept power from the primary, and the VISO voltage starts to rise. When the secondary side UVLO is reached, the secondary side outputs are initialized to their default low state until data, either a transition or a dc refresh pulse, is received from the corresponding primary side input. It can take up to 1 s after the secondary side is initialized for the state of the output to correlate with the primary side input. Secondary side inputs sample their state and transmit it to the primary side. Outputs are valid one propagation delay after the secondary side becomes active. Because the rate of charge of the secondary side is dependent on the soft start cycle, loading conditions, input voltage, and output voltage level selected, care should be taken in the design to allow the converter to stabilize before valid data is required.
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ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
When power is removed from VCC, the primary side converter and coupler shut down when the UVLO level is reached. The secondary side stops receiving power and starts to discharge. The outputs on the secondary side hold the last state that they received from the primary until either the UVLO level is reached, and the outputs are placed in their default low state, or the outputs detect a lack of activity from the inputs, and the outputs are set to their default value before the secondary power reaches UVLO. Bipolar ac voltage is the most stringent environment. A 50-year operating lifetime under the bipolar ac condition determines the Analog Devices recommended maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 11 can be applied while maintaining the 50-year minimum lifetime, provided that the voltage conforms to either the unipolar ac or dc voltage cases. Treat any crossinsulation voltage waveform that does not conform to Figure 47 or Figure 48 as a bipolar ac waveform, and limit its peak voltage to the 50-year lifetime voltage value listed in Table 11.
RATED PEAK VOLTAGE 0V
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INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. Analog Devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM347x. Accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest. The values shown in Table 11 summarize the peak voltages for 50 years of service life in several operating conditions. In many cases, the working voltage approved by agency testing is higher than the 50-year service life voltage. Operation at working voltages higher than the service life voltage listed leads to premature insulation failure. The insulation lifetime of the ADuM347x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, dc, or unipolar ac. Figure 46, Figure 47, and Figure 48 illustrate these different isolation voltage waveforms.
Figure 46. Bipolar AC Waveform
RATED PEAK VOLTAGE
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0V
Figure 47. DC Waveform
RATED PEAK VOLTAGE
0V NOTES: 1. THE VOLTAGE IS SHOWN SINUSOIDAL FOR ILLUSTRATION PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLRTAGE WAVEFORM VARYING BETWEEN 0 AND SOME LIMITING VALUE. THE LIMITING VALUE CAN BE POSTIVE OR NEGATIVE, BUT THE VOLTAGE CANNOT CROSS 0V.
Figure 48. Unipolar AC Waveform
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09369-022
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 OUTLINE DIMENSIONS
7.50 7.20 6.90
20
11
5.60 5.30 5.00
1 10
8.20 7.80 7.40
2.00 MAX
1.85 1.75 1.65 0.38 0.22 SEATING PLANE 8 4 0
0.25 0.09
0.05 MIN COPLANARITY 0.10 0.65 BSC
0.95 0.75 0.55
060106-A
COMPLIANT TO JEDEC STANDARDS MO-150-AE
Figure 49. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2 ADuM3470ARSZ ADuM3470CRSZ ADuM3471ARSZ ADuM3471CRSZ ADuM3472ARSZ ADuM3472CRSZ ADUM3473ARSZ ADuM3473CRSZ ADuM3474ARSZ ADuM3474CRSZ
1 2
Number of Inputs, VCC Side 4 4 3 3 2 2 1 1 0 0
Number of Inputs, VISO Side 0 0 1 1 2 2 3 3 4 4
Maximum Data Rate (Mbps) 1 25 1 25 1 25 1 25 1 25
Maximum Propagation Delay, 5 V (ns) 100 60 100 60 100 60 100 60 100 60
Maximum Pulse Width Distortion (ns) 40 6 40 6 40 6 40 6 40 6
Temperature Range (C) -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105
Package Description 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP
Package Option RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20
Tape and reel are available. The addition of an RL7 suffix designates a 7" (500 units) tape and reel option. Z = RoHS Compliant Part.
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09369-0-10/10(0)
Rev. 0 | Page 32 of 32

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