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EM681FV16A
Document Title
512K x 16 bit Low Power and Low Voltage Full CMOS Static RAM
Low Power, 512Kx16 SRAM
Revision History
Revision No.
0.0
History
Initial Draft
Draft Date
Nov. 14, 2007
Remark
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Emerging Memory & Logic Solutions Inc.
Zip Code : 690-719
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1
EM681FV16A
FEATURES - Process Technology : 0.15m Full CMOS - Organization : 512K x 16 bit - Power Supply Voltage => EM681FV16A : 2.7V ~ 3.6V - Low Data Retention Voltage : 1.5V (Min.) - Three state output and TTL Compatible - Packaged product designed for 45/55/70ns GENERAL PHYSICAL SPECIFICATIONS - Backside die surface of polished bare silicon - Typical Die Thickness = 725um +/-15um - Typical top-level metallization : => Metal (Ti/AlCu/TiN/ARC SiON/SiO2) : 5.2K Angstroms - Topside Passivation : => Passivation (HDP/pNIT/PIQ) : 5.4K Angstroms - Wafer diameter : 8 inch PAD DIAGRAM
Low Power, 512Kx16 SRAM
EM681FV16A (Single C/S)
y
(0, 0)
+x
28
EMLSI LOGO
PAD DESCRIPTION
Name CS OE WE A0~A18 Function Chip select input Output Enable input Write Enable input Address Inputs Name Vcc Vss UB LB NC Function Power Supply
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
Row Select
Ground Upper Byte (I/O8~15) Lower Byte (I/O0~7) No Connected
I/O0~I/O15 Data Inputs/outputs
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
29
VCC VSS
Memory Array 2048 x 4096
I/O0 ~ I/O7 I/O8 ~ I/O15
Data Cont
Data Cont
I/O Circuit Column Select
A11 A12 A13 A14 A15 A16 A17 A18
WE OE UB LB CS
Control Logic
BONDING INSTRUCTIONS The 8M full CMOS LP SRAM die has total 56pads. Refer to the bond pad location and identification table for X, Y coordinates. EMLSI recommends using a bond wire on back side of die onto Vss bond pad for improved noise immunity. 2
56
1
EM681FV16A
ABSOLUTE MAXIMUM RATINGS * Parameter
Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature
Low Power, 512Kx16 SRAM
Symbol
VIN, VOUT VCC PD TA
Minimum
-0.2 to 4.0V -0.2 to 4.0V 1.0 -40 to 85
Unit
V V W
o
C
* Stresses greater than those listed above "Absolute Maximum Ratings" may cause permanent damage to the device. Functional oper-
ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS H X L L L L L L L L OE X X H H L L L X X X WE X X H H H H H L L L LB X H L X L H L L H L UB X H X L H L L H L L I/O0-7 High-Z High-Z High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In I/O8-15 High-Z High-Z High-Z High-Z High-Z Data Out Data Out High-Z Data In Data In Mode Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Stand by Active Active Active Active Active Active Active Active
Note: X means don't care. (Must be low or high state)
3
EM681FV16A
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter Supply voltage Ground Input high voltage Input low voltage
1. 2. 3. 4.
Low Power, 512Kx16 SRAM
Symbol VCC VSS VIH VIL
Min 2.7 0 2.2 -0.23)
Typ 3.3 0 -
Max 3.6 0 VCC + 0.22) 0.6
Unit V V V V
TA= -40 to 85oC, otherwise specified Overshoot: VCC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item Input capacitance Input/Ouput capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Parameter Input leakage current Output leakage current Operating power supply Symbol ILI ILO ICC ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current (TTL) VOL VOH ISB
VIN=VSS to VCC CS=VIH or OE=VIH or WE=VIL or LB=UB=VIH VIO=VSS to VCC IIO=0mA, CS=VIL, WE=VIH, VIN=VIH or VIL Cycle time=1s, 100% duty, IIO=0mA, CS<0.2V, LB<0.2V or/and UB<0.2V, VIN<0.2V or VIN>VCC-0.2V Cycle time = Min, IIO=0mA, 100% duty, CS=VIL, LB=VIL or/and UB=VIL , VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA CS=VIH, Other inputs=VIH or VIL CS>VCC-0.2V Other inputs=0 ~ VCC (Typ. condition : VCC=3.3V @ 25oC) (Max. condition : VCC=3.6V @ 85oC)
Test Conditions
Min -1 -1 45ns 55ns 70ns
Typ -
Max 1 1 2 4 45 35 25 0.4 0.5
Unit uA uA mA mA
2.2 -
-
mA V V mA
Standby Current (CMOS)
ISB1
LF
-
2
15
uA
NOTES 1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested. 4
EM681FV16A
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4 to 2.4V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL1) = 100pF + 1 TTL (70ns) CL1) = 30pF + 1 TTL (45ns/55ns) 1. Including scope and Jig capacitance 2. R1=3070 ohm, R2=3150 ohm 3. VTM=2.8V 4. CL = 5pF + 1 TTL (measurement with tLZ, tHZ, tOLZ, tOHZ, tWHZ)
Low Power, 512Kx16 SRAM
VTM3) R12)
CL1)
R22)
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Read cycle time Address access time Chip select to output Output enable to valid output UB, LB access time Chip select to low-Z output UB, LB enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB, LB disable to how-Z output Output disable to high-Z output Output hold from address change
Symbol
tRC tAA tco tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH
45ns Min 45 Max 45 45 30 45 5 5 5 0 0 0 10 20 20 20 5 5 5 0 0 0 10 Min 55 -
55ns Max 55 55 35 55 5 5 5 20 20 20 0 0 0 10 Min 70 -
70ns Max 70 70 35 70 25 25 25 -
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Write cycle time Chip select to end of write Address setup time Address valid to end of write UB, LB valid to end of write Write pulse width Write recovery time Write to ouput high-Z Data to write time overlap Data hold from write time End write to output low-Z
Symbol
tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW
45ns Min 45 45 0 45 45 45 0 0 25 0 5 Max 20 Min 55 45 0 45 45 45 0 0 30 0 5
55ns Max 20 Min 70 60 0 60 60 55 0 0 30 0 5
70ns Max 25
Unit
ns ns ns ns ns ns ns ns ns
-
ns ns
5
EM681FV16A
TIMING DIAGRAMS
Low Power, 512Kx16 SRAM
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS=OE=VIL, UB or/and LB=VIL)
tRC Address tAA tOH Data Out
Previous Data Valid Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC Address tAA tOH
CS
tCO tBA
tHZ
UB,LB tOE OE tOLZ Data Out High-Z tBLZ tLZ
Data Valid
tBHZ
tOHZ
NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
6
EM681FV16A
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC Address tCW(2) CS tAW tBW UB,LB tWP(1) WE tAS(3) Data in High-Z tWHZ Data out Data Undefined tDW
Data Valid
Low Power, 512Kx16 SRAM
tWR(4)
tDH High-Z tOW
TIMING WAVEFORM OF WRITE CYCLE(2) (CS CONTROLLED)
tWC Address tAS(3) CS tAW tBW UB,LB tWP(1) WE tDW Data in High-Z
Data Valid
tCW(2)
tWR(4)
tDH
Data out
High-Z
7
EM681FV16A
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
tWC Address tCW(2) CS tAS(3) tAW tBW UB,LB tWP(1) WE tDW Data in Data out High-Z
Data Valid
Low Power, 512Kx16 SRAM
tWR(4)
tDH
High-Z
NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
8
EM681FV16A
DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time NOTES
Low Power, 512Kx16 SRAM
Symbol
VDR IDR tSDR tRDR
Test Condition
ISB1 Test Condition (Chip Disabled)1) VCC=1.5V, ISB1 Test Condition (Chip Disabled) 1) See data retention wave form
Min
1.5 0 tRC
Typ
-
Max
3.6 4.0 -
Unit
V uA
ns
1. See the ISB1 measurement condition of data sheet page 4.
DATA RETENTION WAVE FORM CS Controlled
Vcc 2.7V tSDR
Data Retention Mode
tRDR
2.2V VDR CS GND
CS > Vcc-0.2V
9
EM681FV16A
SRAM PART CODING SYSTEM
Low Power, 512Kx16 SRAM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory 2. Product Type 3. Density 4. Function 5. Technology 6. Operating Voltage
1. Memory Component EM --------------------- Memory 2. Product Type 6 ------------------------ SRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 3 ------------- Single CS / LBB, UBB(tBA=tOE) 4 ------------- Single CS / LBB, UBB(tBA=tCO) 5 ------------- Dual CS / LBB, UBB(tBA=tOE) 6 ------------- Dual CS / LBB, UBB(tBA=tCO) 5. Technology F ------------------------- Full CMOS 6. Operating Voltage T ------------------------- 5.0V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V
11. Power 10. Speed
9. Package 8. Generation 7. Organization
7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 8. Generation Blank ----------------- 1st generation A ----------------------- 2nd generation B ----------------------- 3rd generation C ----------------------- 4th generation D ----------------------- 5th generation E ----------------------- 6th generation F ----------------------- 7th generation G ---------------------- 8th generation 9. Package Blank ---------------- KGD, 48&36FpBGA S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 V ---------------------- 32 SOP 10. Speed 45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ---------------------45ns 55ns 70ns 85ns 100ns 120ns
11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free & Green) L ---------------------- Low Power S ---------------------- Standard Power
10

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