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| PCF8533 Universal LCD driver for low multiplex rates Rev. 04 -- 5 March 2010 Product data sheet 1. General description The PCF8533 is a peripheral device which interfaces to almost any LCD1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 80 segments and can easily be cascaded for larger LCD applications. The PCF8533 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremental addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). 2. Features and benefits Single-chip LCD controller and driver Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing Selectable display bias configuration: static, 12, or 13 Internal LCD bias generation with voltage follower buffers 80 segment outputs allowing to drive: 40 8-segment alphanumeric characters 21 15-segment alphanumeric characters Any graphics of up to 320 elements 80 x 4 bit RAM for display data storage Auto-incremental display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide LCD supply range for low-threshold LCDs, for guest-host LCDs and high-threshold (automobile) twisted nematic LCDs from 2.5 V to 6.5 V Low power consumption 400 kHz I2C-bus interface TTL/CMOS compatible Compatible with 4-bit, 8-bit, or 16-bit microprocessors or microcontrollers May be cascaded for large LCD applications (up to 5120 elements possible) No external components required Compatible with Chip-On-Glass (COG) technology Manufactured using silicon gate CMOS process 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18. NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Package Name PCF8533U/2/F2 PCF8533U/2DA/2 [1] Type number Description bare die; 99 bumps; 5.28 x 1.4 x 0.38 mm bare die; 99 bumps; 5.28 x 1.4 x 0.38 mm Delivery form[1] chip with soft bumps in tray Version - PCF8533-2 PCF8533-2 chip with hard bumps in tray - Bump hardness see Table 20. 4. Marking Table 2. Marking codes Marking code PC8533-2 PC8533-2 Type number PCF8533U/2/F2 PCF8533U/2DA/2 5. Block diagram BP0 BP1 BP2 BP3 S0 to S79 80 VLCD BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS LCD VOLTAGE SELECTOR DISPLAY REGISTER DISPLAY CONTROL OUTPUT BANK SELECT AND BLINK CONTROL VSS LCD BIAS GENERATOR PCF8533 CLK SYNC CLOCK SELECT AND TIMING BLINKER TIMEBASE DISPLAY RAM OSC OSCILLATOR POWER-ON RESET COMMAND DECODE WRITE DATA CONTROL DATA POINTER AND AUTO INCREMENT SCL SDA INPUT FILTERS I2C-BUS CONTROLLER SUBADDRESS COUNTER SA0 SDAACK VDD A0 A1 A2 mgl743 Fig 1. Block diagram of PCF8533 PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 2 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 6. Pinning information 6.1 Pinning D6 D5 S67 S12 D4 D3 S11 D1 D2 mgl759 SDA SCL CLK SDAACK SYNC OSC VDD SA0 VLCD S79 BP3 BP1 BP2 BP0 S0 S1 S2 A0 A1 A2 VSS . . . . . . PCF8533 y x 0, 0 D7 D8 S68 . . . . . . . . . . . . Viewed from active side. For mechanical details, see Figure 25. Fig 2. Pinning of PCF8533 6.2 Pin description Table 3. Symbol SDAACK SDA SCL CLK VDD SYNC OSC A0, A1 and A2 SA0 VSS VLCD Pin description overview Pin 1 2 and 3 4 and 5 6 7 8 9 10 to 12 13 14 15 Type output input/output input input/output supply input/output input input input supply supply output output Description I2C-bus acknowledge I2C-bus serial data I2C-bus serial clock clock input/output supply voltage cascade synchronization oscillator select subaddress I2C-bus slave address ground supply voltage LCD supply voltage LCD backplane output LCD segment output dummy pins BP0, BP1, BP2 and BP3 17, 99, 16 and 98 S0 to S79 D1, D2, D3, D4, D5, D6, D7, D8, 18 to 97 PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 3 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 7. Functional description The PCF8533 is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 80 segments. The display configurations possible with the PCF8533 depend on the number of active backplane outputs required. A selection of display configurations is given in Table 4; all of these configurations can be implemented in the typical system shown in Figure 3. Table 4. Number of Backplanes 4 3 2 1 Elements 320 240 160 80 Selection of display configurations 8-segment alphanumeric Digits 40 30 20 10 Indicator symbols 40 30 20 10 15-segment alphanumeric Characters 20 16 10 5 Indicator symbols 40 16 20 10 320 (4 x 80) 240 (3 x 80) 160 (2 x 80) 80 (1 x 80) Dot matrix VDD R tr 2Cb SDAACK VDD SDA SCL OSC VLCD 80 segment drives HOST MICROPROCESSOR/ MICROCONTROLLER LCD PANEL (up to 320 elements) PCF8533 4 backplanes A0 VSS A1 A2 SA0 VSS mgl744 Fig 3. Typical system configuration The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCF8533. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to VSS. The only other connections required to complete the system are the power supplies (pins VDD, VSS and VLCD) and the LCD panel selected for the application. 7.1 Power-on reset At power-on the PCF8533 resets to the following starting conditions: 1. All backplane outputs are set to VLCD. 2. All segment outputs are set to VLCD. 3. The selected drive mode is: 1:4 multiplex with 13 bias. 4. Blinking is switched off. 5. Input and output bank selectors are reset. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 4 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 6. The I2C-bus interface is initialized. 7. The data pointer and the subaddress counter are cleared (set to logic 0). 8. The display is disabled. Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors connected between pins VLCD and VSS. The center resistor is bypassed by switch if the 12 bias voltage level for the 1:2 multiplex drive mode configuration is selected. 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command (see Table 10) from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D) are given in Table 5. Table 5. LCD drive mode static Biasing characteristics Number of: LCD bias Backplanes Levels configuration 1 2 3 4 4 4 static 1 1 1 1 2 3 3 3 V off ( RMS ) -----------------------V LCD 0 0.354 0.333 0.333 0.333 V on ( RMS -----------------------) V LCD 1 0.791 0.745 0.638 0.577 V on ( RMS ) D = -----------------------V off ( RMS ) 2.236 2.236 1.915 1.732 1:2 multiplex 2 1:2 multiplex 2 1:3 multiplex 3 1:4 multiplex 4 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1:3 and 1:4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 Bias is calculated by ------------ , where the values for a are 1+a a = 1 for 12 bias a = 2 for 13 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: V on ( RMS ) = a 2 + 2a + n ----------------------------2 n x (1 + a) (1) V LCD where the values for n are PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 5 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off ( RMS ) = a 2 - 2a + n ----------------------------2 n x (1 + a) (2) V LCD Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on ( RMS ) D = ---------------------- = V off ( RMS ) (a + 1) + (n - 1) ------------------------------------------2 (a - 1) + (n - 1) 2 (3) Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with 1 1 2 bias 2 bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with 21 is ---------- = 1.528 . 3 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: * 1:3 multiplex (12 bias): V LCD = 6 x V off ( RMS ) = 2.449V off ( RMS ) --------------------* 1:4 multiplex (12 bias): V LCD = ( 4 x 3 ) = 2.309V off ( RMS ) 3 These compare with V LCD = 3V off ( RMS ) when 13 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 6 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BP0) and segment drive (Sn) waveforms for this mode are shown in Figure 4. Tfr VLCD BP0 VSS VLCD Sn VSS VLCD state 1 (on) state 2 (off) LCD segments Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V -VLCD VLCD state 2 0V -VLCD (b) Resultant waveforms at LCD segment. mgl745 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn+1)(t) - VBP0(t). Voff(RMS) = 0 V. Fig 4. Static drive mode waveforms PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 7 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 7.4.2 1:2 multiplex drive mode The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of 12 bias or 13 bias as shown in Figure 5 and Figure 6. Tfr VLCD BP0 VLCD / 2 VSS state 1 VLCD BP1 VLCD / 2 VSS VLCD Sn VSS VLCD state 2 LCD segments Sn+1 VSS (a) Waveforms at driver. VLCD VLCD / 2 state 1 0V -VLCD / 2 -VLCD VLCD VLCD / 2 state 2 0V -VLCD / 2 -VLCD (b) Resultant waveforms at LCD segment. mgl746 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.354VLCD. Fig 5. Waveforms for the 1:2 multiplex drive mode with 12 bias PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 8 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD (b) Resultant waveforms at LCD segment. mgl747 LCD segments state 1 state 2 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. Fig 6. Waveforms for the 1:2 multiplex drive mode with 13 bias PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 9 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 7.4.3 1:3 multiplex drive mode The 1:3 multiplex drive mode is used when three backplanes are provided in the LCD as shown in Figure 7. Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD Sn+2 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD state 1 state 2 LCD segments Sn+1 (b) Resultant waveforms at LCD segment. mgl748 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. Fig 7. Waveforms for the 1:3 multiplex drive mode with 13 bias PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 10 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 7.4.4 1:4 multiplex drive mode The 1:4 multiplex drive mode is used when four backplanes are provided in the LCD as shown in Figure 8. Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD BP3 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD state 1 state 2 LCD segments Sn Sn+1 Sn+2 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 Sn+3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD (b) Resultant waveforms at LCD segment. mgl749 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. Fig 8. Waveforms for the 1:4 multiplex drive mode with 13 bias PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 11 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 7.5 Oscillator The internal logic and the LCD drive signals of the PCF8533 are timed by a frequency fclk, which either is derived from the built-in oscillator frequency fosc or equals an external clock frequency fclk(ext). f osc f clk = ------64 The clock frequency fclk determines the LCD frame frequency ffr (see Table 6) and is calculated as follows: f clk f fr = ------24 Table 6. 1536 LCD frame frequency LCD frame frequency (Hz) 64 Nominal clock frequency (Hz) 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output from pin CLK provides the clock signal for cascaded PCF8533s in the system. 7.5.2 External clock Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. 7.6 Timing The PCF8533 timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between the PCF8533s in the system. The timing also generates the LCD frame signal (ffr) whose frequency is derived as an integer division of the clock frequency fclk (see Table 6), applied to pin CLK from either the internal or an external clock. 7.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display register, the LCD segment outputs and each column of the display RAM. 7.8 Segment outputs The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display register. If less than 80 segment outputs are required, the unused segment outputs must be left open-circuit. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 12 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 7.9 Backplane outputs The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated based on the selected LCD drive mode. * In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD. If less than four backplane outputs are required the unused outputs can be left open-circuit. * In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. * In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same signals and can also be paired to increase the drive capabilities. * In static drive mode: The same signal is carried by all four backplane outputs; and they can be connected in parallel for very high drive requirements. 7.10 Display RAM The display RAM is a static 80 x 4 bit RAM which stores LCD data. A logic 1 in the RAM bit map indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off state. There is a one-to-one correspondence between the RAM addresses and the segment outputs and between the individual bits of a RAM word and the backplane outputs. The display RAM bit map Figure 9 shows rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment outputs S0 to S79. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively. display RAM addresses (columns) / segment outputs (S) 0 0 display RAM bits 1 (rows) / backplane outputs 2 (BP) 3 mgl750 1 2 3 4 75 76 77 78 79 Fig 9. Display RAM bit map showing direct relationship between RAM address and segment outputs and also between RAM word bits and backplane outputs When display data is transmitted to the PCF8533, the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples or quadruples. To illustrate the filling order, an example of a 8-segment numeric display showing all drive modes is given in Figure 10; the RAM filling organization depicted applies equally to other LCD types. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 13 of 45 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 04 -- 5 March 2010 14 of 45 PCF8533_4 NXP Semiconductors drive mode LCD segments LCD backplanes display RAM filling order columns display RAM address/segment outputs (s) byte1 transmitted display byte Sn+2 Sn+3 static Sn+4 Sn+5 Sn+6 e d f a b g c Sn+1 Sn Sn+7 DP BP0 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 n c x x x n+1 b x x x n+2 a x x x n+3 f x x x n+4 g x x x n+5 e x x x n+6 d x x x n+7 DP x x x MSB cba f LSB g e d DP BP0 Sn 1:2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. a f g b columns display RAM address/segment outputs (s) byte1 byte2 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 n a b x x n+1 f g x x n+2 e c x x n+3 d DP x x MSB ab f LSB g e c d DP Sn+1 multiplex Sn+2 Sn+3 e d c BP1 DP Sn+1 1:3 Sn+2 f a b g BP0 Sn n rows display RAM 0 b rows/backplane 1 DP outputs (BP) 2c 3x columns display RAM address/segment outputs (s) byte1 byte2 byte3 n+1 a d g x n+2 f e x x MSB b DP c a d g f LSB Universal LCD driver for low multiplex rates multiplex e d c BP1 DP BP2 e Sn 1:4 f a b g columns display RAM address/segment outputs (s) byte1 byte2 byte3 byte4 byte5 BP0 BP2 n rows display RAM 0 a rows/backplane 1c BP3 outputs (BP) 2 b 3 DP n+1 f e g d MSB a c b DP f LSB egd multiplex e c d BP1 DP PCF8533 Sn+1 001aaj646 x = data bit unchanged. Fig 10. Relationship between LCD layout, drive mode, display RAM storage order and display data transmitted over the I2C-bus NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates The following applies to Figure 10: * In static drive mode the eight transmitted data bits are placed into row 0 of eight successive 4-bit RAM words. * In 1:2 multiplex mode the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. * In 1:3 multiplex mode the eight bits are placed in triples into row 0, 1, and 2 of three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address, but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted. * In the 1:4 multiplex mode the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 of two successive 4-bit RAM words. 7.11 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Table 11). Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in Figure 10. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode: * * * * In static drive mode by eight. In 1:2 multiplex drive mode by four. In 1:3 multiplex drive mode by three. In 1:4 multiplex drive mode by two. If an I2C-bus data access terminates early, the state of the data pointer is unknown. Consequently, the data pointer must be rewritten prior to further RAM accesses. 7.12 Subaddress counter The storage of display data is conditioned by the content of the subaddress counter. Storage is allowed only when the content of the subaddress counter match with the hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined by the device-select command (see Table 12). If the content of the subaddress counter and the hardware subaddress do not match, then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. In cascaded applications each PCF8533 in the cascade must be addressed separately. Initially, the first PCF8533 is selected by sending the device-select command matching the first device's hardware subaddress. Then the data pointer is set to the preferred display RAM address by sending the load-data-pointer command. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 15 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates Once the display RAM of the first PCF8533 has been written, the second PCF8533 is selected by sending the device-select command again. This time however the command matches the second device's hardware subaddress. Next the load-data-pointer command is sent to select the preferred display RAM address of the second PCF8533. This last step is very important because during writing data to the first PCF8533, the data pointer of the second PCF8533 is incremented. In addition, the hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface. 7.13 Output bank selector The output bank selector (see Table 13) selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. * In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by the contents of row 1, 2, and then 3 * In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially * In 1:2 multiplex mode, rows 0 and 1 are selected * In static mode, row 0 is selected The SYNC signal resets these sequences to the following starting points: bit 3 for 1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex, and bit 0 for static mode. The PCF8533 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In the 1:2 mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it, once it is assembled. 7.14 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The input bank selector functions independently to the output bank selector. 7.15 Blinker The PCF8533 has a very versatile display blinking capability. The whole display can blink at a frequency selected by the blink-select command. Each blink frequency is a fraction of the clock frequency. The ratio between the clock frequency and blink frequency depends on the blink mode selected, as shown in Table 7. The entire display can be blinked at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit E at the required rate using the mode-set command. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 16 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates An additional feature allows an arbitrary selection of LCD segments to be blinked in the static and 1:2 drive modes. This is implemented without any communication overheads by the output bank selector which alternates the displayed data between the data in the display RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can also be implemented by the blink-select command. In the 1:3 and 1:4 drive modes, where no alternate RAM bank is available, groups of LCD elements can be blinked by selectively changing the display RAM data at fixed time intervals. Table 7. Blink frequencies Normal operating mode ratio f clk -------768 f clk ----------1536 f clk ----------3072 Nominal blink frequency of fclk Unit typical fclk = 1.536 kHz blinking off 2 Hz Hz Blink mode Off 1 2 1 Hz 3 0.5 Hz PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 17 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 8. I2C-bus interface 8.1 Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. By connecting pin SDAACK to pin SDA on the PCF8533, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAACK pin to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the PCF8533 will not be able to create a valid logic 0 level. By separating the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDAACK pin to the system SDA line to guarantee a valid LOW level. The following definition assumes SDA and SDAACK are connected and refers to the pair as SDA. 8.1.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal; see Figure 11. SDA SCL data line stable; data valid change of data allowed mba607 Fig 11. Bit transfer 8.1.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S); see Figure 12. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 18 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates SDA SDA SCL S START condition P STOP condition SCL mbc622 Fig 12. Definition of START and STOP conditions 8.1.2 System configuration A device generating a message is a transmitter; a device receiving a message is a receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves; see Figure 13. MASTER TRANSMITTER/ RECEIVER SDA SCL SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER mga807 Fig 13. System configuration 8.1.3 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. * A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. * A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. * The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). * A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 14. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 19 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement mbc602 1 2 8 9 Fig 14. Acknowledgement on the I2C-bus 8.1.4 I2C-bus controller The PCF8533 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8533 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, the transferred command data and the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1, and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that no two devices with a common I2C-bus slave address have the same hardware subaddress. 8.1.5 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 8.1.6 I2C-bus protocol Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8533. The least significant bit of the slave address is bit R/W. The PCF8533 is a write-only device. It will not respond to a read access, so this bit should always be logic 0. The second bit of the slave address is defined by the level tied at input SA0. Two displays controlled by PCF8533 can be recognized on the same I2C-bus which allows: * Up to 16 PCF8533s on the same I2C-bus for very large LCD applications * The use of two types of LCD multiplex drive mode on the same I2C-bus The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the available PCF8533 slave addresses. All PCF8533s with the same SA0 level acknowledge in parallel to the slave address. All PCF8533s with the alternative SA0 level ignore the whole I2C-bus transfer. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 20 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates R/W = 0 slave address S CR S011100A0A OS 0 control byte RAM/command byte M AS B L SP B EXAMPLES a) transmit two bytes of RAM data S S011100A0A01 0 A RAM DATA A RAM DATA AP b) transmit two command bytes S S011100A0A10 0 A COMMAND A00 A COMMAND AP c) transmit one command byte and two RAM date bytes S S011100A0A10 0 A COMMAND A01 A RAM DATA A RAM DATA AP mgl752 Fig 15. I2C-bus protocol After acknowledgement, the control byte is sent defining if the next byte is a RAM or command information. The control byte also defines if the next byte is a control byte or further RAM or command data (see Figure 16 and Table 8). In this way it is possible to configure the device and then fill the display RAM with little overhead. MSB 7 6 5 4 3 2 1 LSB 0 CO RS not relevant mgl753 Fig 16. Control byte format Table 8. Bit 7 Control byte description Symbol CO 0 1 6 RS 0 1 5 to 0 Value Description continue bit last control byte control bytes continue register selection command register data register not relevant The command bytes and control bytes are also acknowledged by all addressed PCF8533s connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter; see Section 7.11 and Section 7.12. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 21 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed PCF8533. After the last (display) byte, the I2C-bus master asserts a STOP condition (P). Alternatively a START may be asserted to RESTART an I2C-bus access. 8.2 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. The five commands available to the PCF8533 are defined in Table 9. Table 9. Command mode-set load-data-pointer device-select bank-select blink-select Table 10. Bit 7 to 4 3 Definition of commands Operation code 1 0 1 1 1 1 P6 1 1 1 0 P5 1 1 1 0 P4 0 1 1 E P3 0 1 0 B P2 A2 0 A M1 P1 A1 I BF1 M0 P0 A0 O BF0 Reference Table 10 Table 11 Table 12 Table 13 Table 14 Mode-set command bit description Symbol E Value 1100 Description fixed value display status the possibility to disable the display allows implementation of blinking under external control 0 1 disabled (blank) enabled LCD bias configuration 0 1 1 1 3 2 2 B bias bias 1 to 0 M[1:0] 01 10 11 00 LCD drive mode selection static; 1 backplane 1:2 multiplex; 2 backplanes 1:3 multiplex; 3 backplanes 1:4 multiplex; 4 backplanes Table 11. Load-data-pointer command bit description See Section 7.11. Bit 7 6 to 0 Symbol P[6:0] Value 0 0000000 to 1001111 Description fixed value immediate data 7-bit binary value of 0 to 79, transferred to the data pointer to define one of 80 display RAM addresses PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 22 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates Table 12. Device-select command bit description See Section 7.12. Bit 7 to 3 2 to 0 Symbol A[2:0] Value 11100 000 to 111 Description fixed value immediate data 3-bit binary value of 0 to 7, transferred to the subaddress counter to define one of 8 hardware subaddresses Table 13. Bank-select command bit description[1] See Section 7.10, Section 7.11, Section 7.13, Section 7.14 and Section 7.12. Bit 7 to 2 1 Symbol I 0 1 0 O 0 1 [1] Value 111110 Description Static fixed value Input bank selection: storage of arriving display data RAM bit 0 RAM bit 2 RAM bit 0 RAM bit 2 RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 1:2 multiplex Output bank selection: retrieval of LCD display data The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes. Table 14. Blink-select command bit description See Section 7.15. Bit 7 to 3 2 Symbol A 0 1 1 to 0 BF[1:0] 00 01 10 11 [1] [2] Value 11110 Description fixed value blink mode selection[1] normal blinking blinking by alternating display RAM banks blink mode selection[2] off 1 2 3 Only normal blinking can be selected in multiplexer 1:3 or 1:4 drive modes. For the blink frequency see Table 7 8.3 Display controller The display controller executes the commands identified by the command decoder. It contains the device's status registers and co-ordinates their effects. The display controller is also responsible for loading display data into the display RAM as required by the filling order. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 23 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 9. Internal circuitry VDD VDD SA0, CLK, SYNC, OSC, A0, A1, A2 VSS VSS SCL, SDA, SDAACK VLCD BP0, BP1, BP2, BP3, S0 to S79 VSS VLCD VSS VSS 013aaa281 Fig 17. Device protection diagram PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 24 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VLCD Vi(n) Vo(n) II IO IDD ISS IDD(LCD) Ptot P/out VESD Ilu Tstg Tamb [1] [2] [3] [4] Parameter supply voltage LCD supply voltage voltage on any input voltage on any output input current output current supply current ground supply current LCD supply current total power dissipation power dissipation per output Conditions Min -0.5 -0.5 Max +6.5 +7.5 +6.5 +7.5 +10 +10 +50 +50 +50 400 100 5000 200 100 +150 +85 Unit V V V V mA mA mA mA mA mW mW V V mA C C VDD related inputs VLCD related outputs -0.5 -0.5 -10 -10 -50 -50 -50 [1] [2] [3] [4] electrostatic discharge voltage HBM MM latch-up current storage temperature ambient temperature -65 -40 Pass level; Human Body Model (HBM), according to Ref. 6 "JESD22-A114" Pass level; Machine Model (MM), according to Ref. 7 "JESD22-A115". Pass level; latch-up testing according to Ref. 8 "JESD78" at maximum ambient temperature (Tamb(max)). According to the NXP store and transport requirements (see Ref. 10 "NX3-00092") the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 25 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 11. Static characteristics Table 16. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Supplies VDD VLCD VPOR IDD IDD(LCD) Logic VI VIL VIH VO VOH VOL IL IOL input voltage LOW-level input voltage HIGH-level input voltage output voltage HIGH-level output voltage LOW-level output voltage leakage current LOW-level output current on pins OSC, CLK, SCL, SDA, A0 to A2, SA0; VI = VDD or VSS output sink current; on pins CLK, SYNC; VOL = 0.4 V; VDD = 5 V output source current; on pin CLK; VOH = 4.6 V; VDD = 5 V [4] Conditions Min 1.8 2.5 1.0 Typ 1.3 - Max 5.5 6.5 1.6 20 60 Unit V V V A A supply voltage LCD supply voltage power-on reset voltage supply current LCD supply current fclk(ext) = 1536 Hz fclk(ext) = 1536 Hz [1][2] [1][3] - VSS - 0.5 on pins CLK, SYNC, OSC, A0 to A2, SA0 on pins CLK, SYNC, OSC, A0 to A2, SA0 VSS 0.7VDD -0.5 0.8VDD -1 1 - VDD + 0.5 V 0.3VDD VDD V V VDD + 0.5 V 0.2VDD +1 V V A mA IOH CI I2C-bus HIGH-level output current input capacitance 1 - - 7 mA pF Input on pins SDA and SCL VI VIL VIH ILI CI IOL(SDA) input voltage LOW-level input voltage HIGH-level input voltage input leakage current input capacitance LOW-level output current on pin SDA VOL = 0.4 V; VDD = 5 V VI = VDD or VSS [4] VSS - 0.5 VSS 0.7VDD -1 3 - 5.5 0.3VDD 5.5 +1 7 - V V V A pF mA LCD outputs Output pins BP0, BP1, BP2 and BP3 VBP RBP voltage on pin BP resistance on pin BP Cbpl = 35 nF VLCD = 5 V [5] [6] -100 - 1.5 +100 10 mV k PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 26 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates Table 16. Static characteristics ...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Output pins S0 to S79 VS RS [1] [2] [3] [4] [5] [6] [7] Conditions Csgm = 5 nF VLCD = 5 V [7] [6] Min -100 - Typ 6.0 Max +100 13.5 Unit mV k voltage on pin S resistance on pin S LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. For typical values, see Figure 18. For typical values, see Figure 19. Not tested, design specification only. Cbpl = backplane capacitance. Outputs measured individually and sequentially. Csgm = segment capacitance. 5 IDD (A) 4 001aal523 3 2 1 0 2 3 4 5 VDD (V) 6 Tamb = 30 C; 1:4 multiplex; VLCD = 6.5 V; fclk(ext) = 1.536 kHz; all RAM written with logic 1; no display connected; I2C-bus inactive. Fig 18. Typical IDD with respect to VDD PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 27 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 20 IDD(LCD) (A) 16 001aal524 12 8 4 0 3 5 7 VLCD (V) 9 Tamb = 30 C; 1:4 multiplex; fclk(ext) = 1.536 kHz; all RAM written with logic 1; no display connected. Fig 19. Typical IDD(LCD) with respect to VLCD 12. Dynamic characteristics Table 17. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Clock fclk(int) fclk(ext) tclk(H) tclk(L) tr tf tPD(SYNC_N) tSYNC_NL tPD(drv) I2C-bus: Pin SCL fSCL tLOW tHIGH Pin SDA tSU;DAT tHD;DAT data set-up time data hold time 100 0 ns ns SCL clock frequency LOW period of the SCL clock HIGH period of the SCL clock 1.3 0.6 400 kHz s s internal clock frequency external clock frequency HIGH-level clock time LOW-level clock time rise time fall time SYNC propagation delay SYNC LOW time driver propagation delay timing[2]; see Figure 21 VLCD = 5 V [1][3] [1][3] Parameter Conditions Min 960 797 130 130 1 - Typ 1536 1536 30 - Max 3046 3046 30 Unit Hz Hz s s ns ns ns s s Synchronization: input pin SYNC Outputs: pins BP0 to BP3 and S0 to S79 PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 28 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates Table 17. Dynamic characteristics ...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tBUF tSU;STO tHD;STA tSU;STA tr tf Cb tw(spike) [1] [2] [3] Parameter bus free time between a STOP and START condition set-up time for STOP condition hold time (repeated) START condition set-up time for a repeated START condition rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line spike pulse width Conditions Min 1.3 0.6 0.6 0.6 - Typ - Max 0.3 0.3 400 50 Unit s s s s s s pF ns Pins SCL and SDA on bus - Typical output duty cycle of 50 %. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. The corresponding frame frequency is f fr = f clk 24 . 1 / fCLK tclk(H) CLK tclk(L) 0.7 VDD 0.3 VDD SYNC tPD(SYNC_N) tSYNC_NL 0.7 VDD 0.3 VDD 0.5 V BP0 to BP3, and S0 to S79 tPD(drv) (VDD = 5 V) 0.5 V 001aag591 Fig 20. Driver timing waveforms PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 29 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 21. I2C-bus timing waveforms PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 30 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 13. Application information 13.1 Cascaded operation Large display configurations of up to sixteen PCF8533s can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). Table 18. Cluster 1 Addressing cascaded PCF8533 Bit SA0 0 Pin A2 0 0 0 0 1 1 1 1 2 1 0 0 0 0 1 1 1 1 Pin A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pin A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Device 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Cascaded PCF8533s are synchronized. They can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8533s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 22). PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 31 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates SDAACK VDD SDA SCL SYNC CLK OSC A0 VLCD VDD tr 2Cb SDAACK VDD SDA SCL SYNC CLK OSC VLCD 80 segment drives VLCD 80 segment drives PCF8533 BP0 to BP3 (open-circuit) LCD PANEL (up to 5120 elements) A1 A2 SA0 VSS R HOST MICROPROCESSOR/ MICROCONTROLLER PCF8533 4 backplanes BP0 to BP3 mgl754 VSS A0 A1 A2 SA0 VSS Fig 22. Cascaded PCF8533 configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8533s. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments, or by the definition of a multiplex mode when PCF8533s with different SA0 levels are cascaded). SYNC is organized as an input/output pin; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCF8533 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCF8533 to assert SYNC. The timing relationships between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8533 are shown in Figure 23. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 32 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates Tfr = 1 ffr BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 (1/3 bias) SYNC (d) 1:4 multiplex drive mode. mgl755 Fig 23. Synchronization of the cascade for the various PCF8533 drive modes The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high then the device will not be able to synchronize properly. This is particularly applicable to COG applications. Table 19 shows the limiting values for contact resistance. Table 19. 2 3 to 5 6 to 10 11 to 16 SYNC contact resistance Maximum contact resistance 6000 2200 1200 700 Number of devices PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 33 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 14. Bare die description 14.1 Gold bump hardness Table 20. Gold bump hardness Min 60 35 Max 120 80 Unit[1] HV HV Type number PCF8533U/2/F2 PCF8533U/2DA/2 [1] Pressure of diamond head: 10 g to 50 g. 14.2 Alignment marks REF REF C2 C1 F REF mgl756 The positions of the alignment marks are shown in Figure 2 and Figure 25. Fig 24. Alignment marks of PCF8533 Table 21. Symbol C1 C2 F Alignment mark locations X (m) 2300.5 -2320.2 -2208.3 Y (m) 55.0 107.0 -165.4 14.3 Bump locations Table 22. Bump locations All x/y coordinates represent the position of the centre of each bump with respect to the center (x/y = 0) of the chip; see Figure 25. Symbol SDAACK SDA SDA SCL SCL CLK VDD SYNC OSC PCF8533_4 Bump 1 2 3 4 5 6 7 8 9 X (m) -839.20 -759.20 -599.20 -519.20 -414.80 -284.80 4.20 119.20 Y (m) [1] [1] [1] Description I2C-bus acknowledge output I2C-bus serial data input I2C-bus serial clock input clock input/output supply voltage cascade synchronization input/output oscillator select (c) NXP B.V. 2010. All rights reserved. -1079.20 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 04 -- 5 March 2010 34 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates Table 22. Bump locations All x/y coordinates represent the position of the centre of each bump with respect to the center (x/y = 0) of the chip; see Figure 25. Symbol A0 A1 A2 SA0 VSS VLCD BP2 BP0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 Bump 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 X (m) 249.20 379.20 581.20 711.20 841.20 1099.60 1277.60 1357.60 1437.60 1517.60 1597.60 1677.60 1757.60 1837.60 1917.60 1997.60 2077.60 2157.60 2237.60 2317.60 2357.60 2277.60 2197.60 2117.60 2037.60 1957.60 1877.60 1797.60 1717.60 1637.60 1557.60 1477.60 1317.60 1237.60 1157.60 1077.60 997.60 917.60 Y (m) -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 LCD segment output I2C-bus slave address input; bit 0 ground supply voltage LCD supply voltage LCD backplane output Description subaddress input PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 35 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates Table 22. Bump locations All x/y coordinates represent the position of the centre of each bump with respect to the center (x/y = 0) of the chip; see Figure 25. Symbol S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 Bump 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 X (m) 837.60 757.60 677.60 597.60 437.60 357.60 277.60 197.60 117.60 37.60 -42.40 -122.40 -202.40 -282.40 -362.40 -442.40 -602.40 -682.40 -762.40 -842.40 -922.40 Y (m) 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 594.40 Description LCD segment output -1002.40 594.40 -1082.40 594.40 -1162.40 594.40 -1242.40 594.40 -1322.40 594.40 -1402.40 594.40 -1562.40 594.40 -1642.40 594.40 -1722.40 594.40 -1802.40 594.40 -1882.40 594.40 -1962.40 594.40 -2042.40 594.40 -2122.40 594.40 -2202.40 594.40 -2282.40 594.40 PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 36 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates Table 22. Bump locations All x/y coordinates represent the position of the centre of each bump with respect to the center (x/y = 0) of the chip; see Figure 25. Symbol S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 BP3 BP1 D1 D2 D3 D4 D5 D6 D7 D8 [1] [2] Bump 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 - X (m) Y (m) Description LCD segment output -2362.40 594.40 -2322.40 -594.40 -2242.40 -594.40 -2162.40 -594.40 -2082.40 -594.40 -2002.40 -594.40 -1922.40 -594.40 -1842.40 -594.40 -1762.40 -594.40 -1682.40 -594.40 -1602.40 -594.40 -1522.40 -594.40 -1442.40 -594.40 -1362.40 -594.40 -1282.40 -594.40 2469.70 2549.70 2517.60 2437.60 -594.40 -594.40 594.40 594.40 [2] [2] LCD backplane output dummy bump -2442.30 594.40 -2522.30 594.40 -2554.40 -594.40 -2474.40 -594.40 For most applications SDA and SDAACK are shorted together; see Section 8.1. The dummy bumps are connected to the adjacent segments but are not tested. PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 37 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 15. Bare die outline Bare die; 99 bumps; 5.28 x 1.4 x 0.38 mm PCF8533-2 D 85 30 X y PC8533-2 0,0 x E 99 1 Y 29 b e e1 A A1 L detail Y detail X 0 Dimensions Unit mm A A1 b D E e(1) e1(1) L 1 scale 2 mm max 0.020 0.053 0.289 0.093 nom 0.381 0.017 0.050 5.276 1.402 0.090 min 0.014 0.047 0.08 0.087 PCF8533-2_do Note 1. Dimension not drawn to scale Outline version PCF8533-2 References IEC JEDEC JEITA European projection Issue date 09-09-08 10-01-28 Fig 25. Bare die outline of PCF8533-2 PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 38 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 17. Packing information A C 1.1 1.2 1.3 2.1 2.2 3.1 x.1 D F B 1.y y E x 001aai623 Fig 26. Tray details for PCF8533 PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 39 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates PCF8533 mgl758 Fig 27. Tray alignment of PCF8533 Table 23. Tray dimensions See Figure 26. Symbol A B C D E F N M Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction number of pockets, x direction number of pockets, y direction Value 7.37 mm 3.68 mm 5.50 mm 1.60 mm 50.8 mm 50.8 mm 6 12 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to Figure 25 for the orientation and position of the type name on the die surface. 18. Abbreviations Table 24. Acronym CDM CMOS ESD HBM IC LCD MM RAM TTL Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Integrated Circuit Liquid Crystal Display Machine Model Random Access Memory Transistor-Transistor Logic PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 40 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 19. References [1] [2] [3] [4] [5] [6] [7] [8] [9] AN10170 -- Design guidelines for COG modules with NXP monochrome LCD drivers AN10706 -- Handling bare die IEC 60134 -- Rating systems for electronic tubes and valves and analogous semiconductor devices IEC 61340-5 -- Protection of electronic devices from electrostatic phenomena IPC/JEDEC J-STD-020D -- Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices JESD22-A114 -- Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-A115 -- Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) JESD78 -- IC Latch-Up Test JESD625-A -- Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [10] NX3-00092 -- NXP store and transport requirements [11] UM10204 -- I2C-bus specification and user manual PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 41 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 20. Revision history Table 25. Revision history Release date 20100305 Data sheet status Product data sheet Change notice Supersedes PCF8533_3 Document ID PCF8533_4 Modifications: * * * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added product with soft bumps Product data sheet PCF8533_2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Miscellaneous changes to text, tables and graphics throughout "Soldering" section deleted Product specification Product specification PCF8533_SDS_1 - PCF8533_3 Modifications: 20080424 * * * * PCF8533_2 PCF8533_SDS_1 19990730 19990312 PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 42 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 21. Legal information 21.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 21.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the (c) NXP B.V. 2010. All rights reserved. 21.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or PCF8533_4 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 04 -- 5 March 2010 43 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Bare die -- All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. 21.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCF8533_4 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 5 March 2010 44 of 45 NXP Semiconductors PCF8533 Universal LCD driver for low multiplex rates 23. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 8 8.1 8.1.1 8.1.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.2 8.3 9 10 11 12 13 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 4 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 5 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 5 LCD drive mode waveforms . . . . . . . . . . . . . . . 7 Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 7 1:2 multiplex drive mode. . . . . . . . . . . . . . . . . . 8 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 10 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 11 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 12 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Display register . . . . . . . . . . . . . . . . . . . . . . . . 12 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 12 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 13 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Subaddress counter . . . . . . . . . . . . . . . . . . . . 15 Output bank selector . . . . . . . . . . . . . . . . . . . 16 Input bank selector . . . . . . . . . . . . . . . . . . . . . 16 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 18 I Characteristics of the I2C-bus. . . . . . . . . . . . . 18 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 START and STOP conditions . . . . . . . . . . . . . 18 System configuration . . . . . . . . . . . . . . . . . . . 19 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 20 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 20 Command decoder . . . . . . . . . . . . . . . . . . . . . 22 Display controller . . . . . . . . . . . . . . . . . . . . . . 23 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 24 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 25 Static characteristics. . . . . . . . . . . . . . . . . . . . 26 Dynamic characteristics . . . . . . . . . . . . . . . . . 28 Application information. . . . . . . . . . . . . . . . . . 31 13.1 14 14.1 14.2 14.3 15 16 17 18 19 20 21 21.1 21.2 21.3 21.4 22 23 Cascaded operation. . . . . . . . . . . . . . . . . . . . Bare die description . . . . . . . . . . . . . . . . . . . . Gold bump hardness . . . . . . . . . . . . . . . . . . . Alignment marks . . . . . . . . . . . . . . . . . . . . . . Bump locations . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 34 34 34 34 38 39 39 40 41 42 43 43 43 43 44 44 45 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 March 2010 Document identifier: PCF8533_4 |
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