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| SSM9960(G)H,J N-CHANNEL ENHANCEMENT-MODE POWER MOSFET Low gate-charge Simple drive requirement Fast switching G D BV DSS R DS(ON) ID 40V 16m 42A S Description The SSM9960H is in a TO-252 package, which is widely used for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. The through-hole version, the SSM9960J in TO-251, is available for low-footprint vertical GD S TO-252 (H) This device is available with Pb-free lead finish (second-level interconnect) as SSM9960GH or SSM9960GJ. G D S TO-251 (J) Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=100C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current 1 Rating 40 20 42 26 195 45 0.36 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-c Rthj-a Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 2.8 110 Unit C/W C/W 11/16/2004 Rev.2.1 www.SiliconStandard.com 1 of 5 SSM9960(G)H,J Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol BVDSS BV DSS/ Tj Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 40 1 - Typ. 0.032 Max. Units 16 25 3 1 25 100 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Static Drain-Source On-Resistance VGS=10V, ID=20A VGS=4.5V, ID=18A VDS=VGS, ID=250uA VDS=10V, ID=20A 30 18 6 12 9 110 23 10 1500 250 180 Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=150 C) o o VDS=40V, VGS=0V VDS=32V ,VGS=0V VGS= 20V ID=20A VDS=20V VGS=4.5V VDS=20V ID=20A RG=3.3 , VGS=10V RD=1 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage 2 Test Conditions IS=45A, VGS=0V IS=20A, VGS=0V dI/dt = 100A/us Min. - Typ. 22 27.4 Max. Units 1.3 V Reverse Recovery Time Reverse Recovery Charge ns nC Notes: 1.Pulse width limited by safe operating area. 2.Pulse width <300us , duty cycle <2%. 11/16/2004 Rev.2.1 www.SiliconStandard.com 2 of 5 SSM9960(G)H,J 200 140 T C =25 o C 10.0V 8.0V ID , Drain Current (A) 120 T C =150 o C 10V 8.0V ID , Drain Current (A) 150 100 6.0V 100 80 6.0V 60 40 50 V G =4.0V 20 V G =4.0V 0 0.0 1.5 3.0 4.5 0 0 1 2 3 4 5 6 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 60 1.80 I D =20A T C =25C Normalized RDS(ON) 40 I D =20A 1.60 V G =10V 1.40 RDS(ON) (m ) 1.20 20 1.00 0.80 0 0 4 8 12 16 0.60 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 2.5 1000 100 2 VGS(th) (V) IS(A) 10 1.5 T j =150 o C T j =25 C o 1 1 0.5 0 0.0 0.4 0.8 1.2 1.6 -50 25 100 175 V SD (V) T j , Junction Temperature ( C ) o Fig 5. Forward Characteristic of Reverse Diode Fig 6. Gate Threshold Voltage vs. Junction Temperature 11/16/2004 Rev.2.1 www.SiliconStandard.com 3 of 5 SSM9960(G)H,J 14 10000 f=1.0MHz 12 VGS , Gate to Source Voltage (V) I D =20A V DS =12V V DS =16V V DS =20V Ciss 1000 10 C (pF) 8 6 Coss Crss 100 4 2 0 0 10 20 30 40 10 1 8 15 22 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 1000 1 Normalized Thermal Response (Rthjc) DUTY=0.5 0.2 100 10us 0.1 0.1 ID (A) 0.05 100us 10 0.02 0.01 1ms 0.01 Single Pulse PDM T c =25 o C Single Pulse 1 0.1 1 10 t 10ms 100ms 100 T Duty factor = t/T Peak Tj = PDM x Rthjc + Tc 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance RD VDS TO THE D VDS TO THE OSCILLOSCOPE 0.5 x RATED VDS D OSCILLOSCOPE G S VGS 0.5x RATED VDS RG + 10V - G + S VGS 1~ 3 mA IG ID Fig 11. Switching Time Circuit Fig 12. Gate Charge Circuit 11/16/2004 Rev.2.1 www.SiliconStandard.com 4 of 5 SSM9960(G)H,J Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 11/16/2004 Rev.2.1 www.SiliconStandard.com 5 of 5 |
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