 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| M66592FP/WG ASSP (USB2.0 Peripheral Controller) REJ03F0111-0100Z Rev1.00 2004.10.01 1 Overview 1.1 Overview The M66592 is a USB 2.0 peripheral controller that is compliant with USB (Universal Serial Bus) specification Rev. 2.0 for both Hi-Speed and Full-Speed transfers. This controller has a built-in USB transceiver and supports all of the transfer types defined by the USB specification. The compact package and low power consumption make it ideal for use in mobile devices. The M66592 has a 5 kB built-in buffer memory for data transfers and enables use of up to eight pipes. For pipes 1 to 7, any end point numbers can be assigned, based on the user's system. The M66592 can be connected to the CPU using either a separate bus or a multiplex bus. Moreover, a split bus interface (dedicated DMA interface) is provided independent of the CPU bus interface, making this an ideal choice for systems that require transfer of large volumes of data at high speed. 1.2 Features 1.2.1 USB Rev. 2.0 Hi-Speed supported Compliant with USB specification Rev. 2.0 Both Hi-Speed transfer(480 Mbps)and Full-Speed transfer (12 Mbps) are supported Built-in Hi-Speed / Full-Speed USB transceiver Can be operated as a Hi-Speed / Full-Speed peripheral controller 1.2.2 Reduced power consumption 1.5 V core power supply Low power consumption makes this ideal for mobile devices Low-power mode (power-saving sleep state) supported to reduce power consumption during suspended operation 1.2.3 Space-saving installation supported Few external elements are used, so less space is required for mounting * VBUS signal can be connected directly to the controller pin * Built-in D+ pull-up resistor * Built-in D+ and D- terminating resistors (for Hi-Speed operation) * Built-in D+ and D- output resistors (for Full-Speed operation) Compact 64-pin package used 1.2.4 Isochronous transfer supported All types of USB transfers supported * Control transfers * Bulk transfers * Interrupt transfers (High-Bandwidth transfers are not supported) * Isochronous transfers (High-Bandwidth transfers are not supported) Rev1.00 2004.10.01 page 1 of 125 M66592FP/WG 1.2.5 Bus interfaces The user can select either a 1.8 V or 3.3 V bus interface power supply 16-bit CPU bus interface * 16-bit separate bus and 16-bit multiplex bus supported * 8-bit and 16-bit DMA interface (slave function) supported 8-bit split bus (dedicated external DMA interface) supported DMA interface has two channels built into it. DMA transfer enables high-speed access of 40 MB/sec. 1.2.6 Pipe configuration Internal 5 KB buffer memory for USB communication built in Up to 8 pipes(endpoints) can be selected (including the default control pipe for endpoint 0) Programmable pipe configuration End point numbers can be assigned flexibly to PIPE1to PIPE7. Transfer conditions that can be set for theeach pipe * Pipe 0: Control transfer, continuous transfer mode, 256-byte fixed single buffer * PIPE1 and PIPE2: Bulk transfer / isochronous transfer, continuous transfer mode, programmable buffer size (up to 2 KB; double buffer can be specified) * PIPE 3 to PIPE5: Bulk transfer, continuous transfer mode, programmable buffer size (up to 2 KB; double buffer can be specified) * PIPE6 and PIPE7: Interrupt transfer, 64-byte fixed single buffer 1.2.7 Other functions Automatic recognition of Hi-Speed operation or Full-Speed operation based on automatic response to the reset handshake Byte endian swap function when using 16-bit data transfers Transaction count function when using DMA transfers DMA transfer termination function using external trigger (DEND pin) Control transfer stage control function Device state control function Auto response function for SET_ADDRESS request SOF interpolation function SOF pulse output function Three types of input clocks can built into the PLL and are available for selection * Input clocks of 48 MHz / 24 MHz / 12 MHz can be selected Zero-Length packet addition function (DEZPM) when ending DMA transfers using the DEND pin BRDY interrupt event notification timing change function (BFRE) Function that automatically clears the buffer memory after the data for the pipe specified at the DxFIFO port has been read (DCLRM) Function to automatically supply a clock from the low-power sleep state (ATCKM) NAK setting function for response PID generated by end of transfer (SHTNAK) NAK response assignment function (NRDY) 1.2.8 Applications Digital video cameras, digital still cameras, printers, external storage devices, portable information terminals, USB audio devices Also: GeneralOrdinary PC peripheral devices equipped with Hi-Speed USB Rev1.00 2004.10.01 page 2 of 125 M66592FP/WG 1.3 Pin layout diagram Figure 1.1 shows the pin layout diagram (top view) of the controller. DGND VDD SD5 SD4 SD3 SD2 SD1 SD0 D15 D14 D13 D12 D10 34 D11 VIF 48 47 46 45 44 43 42 41 40 39 38 37 36 35 33 32 31 30 29 28 SD6 SD7 INT_N SOF_N RD_N WR0_N WR1_N CS_N DREQ0_N DACK0_N DEND0_N DREQ1_N DACK1_N/DSTB0_N DEND1_N RST_N VIF 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 12 13 14 15 16 11 1 2 3 4 5 6 7 8 9 D9 D8 D7 D6/AD6 D5/AD5 D4/AD4 D3/AD3 D2/AD2 D1/AD1 D0 A6/ ALE A5 A4 A3 A2 A1 MPBUS M66592FP (TOP VIEW) 27 26 25 24 23 22 21 20 19 18 17 XOUT VIF AFED33V AFEA15V AFEA33V AFEA15G AFED33G AFEA33G AFED15V VBUS REFRIN *The "_N" in the signal name indicates that the signal is in the "L" active state. Package M66592FP : 64pinLQFP (0.5mm pitch) Figure 1.1 Pin layout diagram of M66592FP Rev1.00 2004.10.01 page 3 of 125 AFED15G TEST DP XIN DM M66592FP/WG M66592WG(TOP VIEW) 8 SD6 SD4 SD2 DGND VDD D13 D10 D9 7 SD7 SD5 SD3 VIF D15 D12 D8 D7 6 RD_N SOF_N INT_N SD0 D14 D11 D6/AD6 D5/AD5 5 CS_N WR1_N WR0_N SD1 D2/AD2 D1/AD1 D4/AD4 D3/AD3 4 DEND0_N DREQ1_N DREQ0_N DACK0_N A5 A2 A6/ALE D0 3 DACK1_N /DSTB0_N RST_N VIF DEND1_N AFEA15V AFEA33G AFEA33V A3 A4 2 AFED33V VBUS AFEA15G XOUT AFED15G TEST A1 1 AFED33G A DM B DP C REFRIN D XIN E AFED15V F VIF G MPBUS H *The "_N" in the signal name indicates that the signal is in the "L" active state. Package M66592WG : 64pin FBGA (0.8mm pitch) Figure 1.2 Pin layout diagram of M66592WG Rev1.00 2004.10.01 page 4 of 125 M66592FP/WG 1.4 Description of pins Table 1.1 describes the controller pins. Table 1.1 Pin descriptions Category Pin name Name I/O Function Pin State of pin *7) count RST_N=" RST_N PCUT=1 L" goes "H" (Pin nos.) CPU bus D15-0 interface AD6-1 Data Bus Multiplex Address Bus Address Bus Address Latch Enable Chip Select Read Strobe I/O I/O This is a 16-bit data bus. 16 *4) (24-39) *4) Input (Hi-z) A6-1 ALE CS_N RD_N WR0_N WR1_N MPBUS*3 IN IN IN IN D7-0 Byte Write IN Strobe D15-8 Byte Write IN Strobe Bus Mode IN Selection Split bus SD7-0 interface DMA bus DREQ0_N*1 interface DREQ1_N*1 DACK0_N*1 DACK1_N*1 DSTB0_N*2 Split Data Bus DMA Request DMA Acknowledge Data Strobe 0 I/O OUT IN IN DEND0_N*1 DMA Transfer DEND1_N*1 End I/O Interrupt/ INT_N SOF output SOF_N Clock XIN XOUT Interrupt OUT SOF pulse output OUT Oscillation input IN Oscillation output OUT When a multiplex bus is specified, this group of pins is used on a time-shared basis for some of the data buses (D6-D1), or for 6 bits of the address bus (A6-A1). This is a 6-bit address bus. 6 Because the data bus consists of 16 bits, (18-23) there is no A0. When a multiplex bus is specified, the A6 pin is used as the ALE signal. Setting this to the "L" level selects this 1 controller. (56) Setting this to the "L" level reads data 1 from the controller registers. (53) At the rising edge, D7-D0 are written to 1 the registers of the controller. (54) At the rising edge, D15-D8 are written to 1 the registers of the controller. (55) Setting this to the "L" level selects a 1 separate bus. (17) Setting this to the "H" level selects a multiplex bus. This should be fixed at either the "H" or "L" level. If a split bus is selected, this functions as 8 the data bus for the split bus. (43-50) This notifies the system of a D0FIFO port 2 or D1FIFO port DMA transfer request. (57, 60) Input the DMA Acknowledge signal for the 2 D0FIFO or D1FIFO port. (58, 61) This functions as the data strobe signal for the D0FIFO port. Because it is also used for the DMA Acknowledge signal of the D1FIFO port, the DSTB0_N function cannot be used if the DACK1_N function is being used. Input *5) Input Input *6) Input Input *6) Input *6) Input *3) Input *5) Input Input *6) Input Input *6) Input *6) Input *3) Input (Hi-z) Input Input Input Input Input Input *3) Input (Hi-z) H Input Input (Hi-z) H Input Input (Hi-z) H/L *8) Input Input (Hi-z) Input (Hi-z) Input (Hi-z) H H H H H H Rev1.00 2004.10.01 page 5 of 125 M66592FP/WG Category Pin name Name I/O Function Pin State of pin *7) count RST_N=" RST_N PCUT=1 L" goes "H" (Pin nos.) System control RST_N TEST Reset signal Test signal USB D+ data USB D- data VBUS input IN IN I/O I/O IN USB bus DP interface DM VBUS monitor input VBUS Reference REFRIN resistance Reference input IN Transceiver unit analog power supply Transceiver unit analog GND Transceiver unit digital power supply Transceiver unit digital GND Transceiver unit analog 1.5 V power supply Transceiver unit analog GND Transceiver unit digital 1.5 V power supply Transceiver unit digital GND Core power supply IO power supply Digital GND - Power supply / GND AFEA33V AFEA33G AFED33V AFED33G AFEA15V AFEA15G AFED15V AFED15G VDD VIF DGND 1 (63) This should be fixed at "L" or open. 1 (16) This should be connected to the D+ pin of 1 the USB bus. (4) This should be connected to the D- pin of 1 the USB bus. (3) This should be connected directly to the 1 Vbus of the USB bus. The connected or (5) disconnected state of the Vbus can be detected. If This pin is not connectted with Vbus of a USB bus, connect it with 5V. This should be connected to AFEA33G 1 through a 5.6 k1% resistance. (8) This should be connected to 3.3 V. 1 (12) 1 (9) 1 (2) 1 (1) 1 (6) 1 (7) 1 (13) At "L" level, the controller is initialized. Input (L) Input (Hi-z) Input (Hi-z) Input (Hi-z) Input (H) Input (Hi-z) Input (Hi-z) Input (Hi-z) Input (H) Input (Hi-z) Input (Hi-z) Input (Hi-z) This should be connected to 3.3 V. This should be connected to 1.5 V. This should be connected to 1.5 V. 1 (14) This should be connected to 1.5 V. 1 (40) This should be connected to 3.3 V or 1.8 3 V. (15, 42, 64) 1 (41) *1) The "L" active and "H" active states of these pins can be specified using the control program for the user system. "_N" indicates that the "L" active state is the default state. *2) DSTB0_N and DACK1_N are assigned to the same pin, so the functions of one or the other are valid. *3) The input level of the MPBUS pin needs to be established just before the end of H/W reset. Also, this should not be switched during operation. *4) When CS_N and RD_N are "L", these pins output "H" or "L". *5) If MPBUS is "H", these pins can be made to open. *6) CS_N, WR0_N, and WR1_N should be kept as (a) or (b) during RST_N="L" (from RST_N goes "L" to right after RST_N goes "H"). (a) CS_N="H" (b) WR0_N="H" and WR1_N="H" *7) Discription of "State of pin" (a) Input : Pins are Hi-z state. Please do not make it "open" on a board. (b) Input(Hi-z) : Pins are Hi-z state. Pins can be "open" on a board. (c) H, L, H/L : Output states is shown. *8) These pins are in an inactive state. Rev1.00 2004.10.01 page 6 of 125 M66592FP/WG Table 1.2 The example of not used pins Category SPLIT bus interface DMA bus interface Pin name SD7-0 DREQ0_N DREQ1_N DACK0_N DACK1_N/DSTB0_N DEND0_N DEND1_N SOF_N TEST VBUS Description "Open" "Open" "Open" Fix to "H" *1) Fix to "H" *1) "Open" *2) "Open" *2) "Open" Fix to "L" or "Open" Fix to 5V *3) SOF output System control VBUS monitor input *9) When DACKn_N pin is not used, please set DACKA bit of DMAnCFG register as "0" (n=0,1). *10) When DENDx_N pin is not used, please set DENDA bit of DMAnCFG register as "0" (n=0,1). *11) If this pin is not connected with Vbus of a USB bus, fix to 5V. Rev1.00 2004.10.01 page 7 of 125 M66592FP/WG 1.5 Pin function configuration Figure 1.3 shows a diagram of the pin function configuration of the controller. CPU bus interface D15-7,D6-1(/AD6-1),D0 A6/ALE,A5-1 CS_N RD_N WR0_N WR1_N MPBUS Interrupt / SOF output INT_N SOF_N 16 6 M66592 DMA interface DREQ0_N DACK0_N DEND0_N DREQ1_N DACK1_N/DSTB0_N DEND1_N Split bus SD7-0 System control RST_N TEST Clock XIN XOUT VBUS monitor input VBUS 8 2 USB interface DP, DM Reference resistance REFRIN Figure 1.3 Pin function configuration diagram Rev1.00 2004.10.01 page 8 of 125 M66592FP/WG 1.6 Block diagram The controller is configured with an analog front end unit (AFE), a protocol engine unit (Prtcl_Eng) that includes an SIE, a pipe control unit (Pipe_Ctrl), a FIFO port unit (FIFO_Port), a buffer memory unit (Buf_Mem), an interrupt control unit (Int_Ctrl), a bus interface unit (BIU), and a CPU interface register unit (CPU_IF_Reg). Figure 1.4 shows a block diagram of the controller. When data is being sent and received between the controller and a host controller connected on the USB bus, a buffer memory assigned to each of the pipes is used. Two-way communication is possible by the controller changing data stored in the buffer memory into USB data packets and outputting them to the USB bus using serial output, and by inputting data packets on the USB bus which are then stored in the buffer memory. I/O power supply VIF Core power supply VDD AFE power supply AFEA33V, AFED33V AFEA15V, AFED15V Interrupt /SOF output INT_N, SOF_N BIU Int_Ctrl CPU bus interface A6(/ALE), A5-1, D15-7, D6-1(/AD6-1), D0, CS_N, RD_N, WR0_N,WR1_N MPBUS CPU_IF_Reg Pipe_Ctrl Clock XIN, XOUT Prctl_Eng VBUS monitor input VBUS AFE FIFO_Port DMA interafce DREQ0_N, DREQ1_N DACK0_N, DACK1_N/DSTB0_N, DEND0_N, DEND1_N SPLIT bus SD7-0 System control RST_N, TEST Buf_Mem SIE USB interface DP, DM Renerence registor REFRIN Ground DGND AFE Ground AFEA33G,AFED33G AFEA15G,AFED15G Figure 1.4 Block diagram Rev1.00 2004.10.01 page 9 of 125 M66592FP/WG 1.7 An overview of functions 1.7.1 Bus interfaces The controller supports the bus interfaces noted below. 1.7.1.1 External bus interface The controller uses a CPU bus interface to access control registers. The bus interface with the CPU supports the two access methods noted below. The Chip Select pin (CS_N) and the three strobe pins (RD_N, WR0_N and WR1_N) should be used for access. (1) (16-bit separate bus The six address buses (A6-1) and the 16 data buses (D15-0) are used. (2) 16-bit multiplex bus The ALE pin (ALE) and the 16 data buses (D15-0) are used. The data buses are used for addresses and data on a time-shared basis. The separate bus and multiplex bus are selected based on the MPBUS pin signal level when the H/W reset is canceled. 1.7.1.2 Accessing the buffer memory The controller supports the two methods described below to access the USB data transfer buffer memory. (1) CPU access Addresses and control signals should be used to write data to the buffer memory or read it from the buffer memory. (2) DMA access Data should be written to the buffer memory of the controller, or read from the buffer memory, from the DMAC in the CPU or a dedicated DMAC. USB data communication is done using Little Endian. There is a byte Endian swap function for FIFO port access, and when using 16-bit access, the Endian can be switched using the register settings. 1.7.1.3 DMA access methods When using DMA access to access the buffer memory, the two access methods noted below can be selected. (1) Method using a bus shared with the CPU (2) Method using a dedicated bus (split bus) 1.7.2 USB events The controller notifies the user's system of USB operation events by means of interrupts. Moreover, with a pipe for which the DMA interface has been selected, the system is notified that the buffer memory of the controller can be accessed by asserting the DREQ signal. There are eight types of interrupts and 35 causes for interrupts being generated. The user can select whether or not interrupt notification is permitted for each type and each cause, using settings in the control program for the user system. Rev1.00 2004.10.01 page 10 of 125 M66592FP/WG 1.7.3 USB data transfers The controller is capable of all types of transfers: USB communication control transfers, bulk transfers, and interrupt transfers, as well as isochronous data transfers. The pipes noted below can be used with data transfers for various types of communication. (1) Dedicated control transfer pipe (2) Two dedicated interrupt transfer pipes (3) Three dedicated bulk transfer pipes (4) Two pipes for which bulk transfers or isochronous transfers can be selected The settings necessary for USB transfers, such as the transfer type, end point number, and maximum packet size, should be set for each pipe, in conjunction with the user system. Also, the controller has a built-in 5 kB buffer memory. For a dedicated bulk transfer pipe and the pipes for which bulk transfers or isochronous transfers can be selected, settings such as the buffer memory assignment and buffer operation mode which are based on the user system should be entered. The buffer operation mode setting can be set to enable high-speed data transfers with few interrupts, using the double-buffer configuration and data packet continuous transfer function. Access to the buffer memory from the control CPU of the user's system and the DMA controller is done through the three FIFO port registers. 1.7.4 DMA interface The DMA (Direct Memory Access) interface consists of data transfers between the user system and the controller using the DxFIFO port, and is a type of data transfer in which the CPU is not involved. The controller is equipped with a 2-channel DMA interface and has the following functions. (1) A transfer end notification function using the Transfer End signal (DEND signal) (2) An auto-clear function activated when a Zero-Length packet is received (3) A "send addition" function used to send a Zero-Length packet based on input of the Transfer End signal (DEND signal) (4) A transfer end function using a transaction counter function The controller supports the two types of DMA interfaces noted below. (1) Cycle steal transfer With this type of transfer, the DREQ pin is repeatedly asserted and negated each time a data transfer (1 byte / 1 word) is carried out. (2) Burst transfer With this type of transfer, the DREQ pin remains asserted for the pipe buffer area assigned to the pertinent FIFO port, or until the transfer is ended by the DEND signal, without ever being negated. Also, the following can be selected as the DMA interface handshake signal (pin): CS_N, RD_N, or WR_N, or DACK_N. With DMA transfers using a split bus, high-speed DMA transfers are possible by changing the data setup timing, by operating the OBUS bit of the DMAxCFG register. 1.7.5 SOF pulse output function An SOF pulse output function is provided that notifies the system of the timing at which SOF packets are received. This function outputs pulses at fairly regular intervals, using an SOF interpolation timer, even if an SOF packet is damaged. Rev1.00 2004.10.01 page 11 of 125 M66592FP/WG 1.7.6 External elements integration The controller has the following external elements built into it. Also, because the VBUS pin can withstand 5 V, the user system can input the VBUS signal directly to the controller. (1) Resistors necessary for D+ and D- line control This makes it possible to configure the system without adding an external resistor. (2) 48 MHz and 480 MHz PLL One of three external clocks (12 MHz / 24 MHz / 48 MHz) can be selected and Hi-Speed and Full-Speed operation carried out. Providing this many external elements in the controller and using a 64-pin compact package mean that less space is required for mounting in the user system. 1.7.7 Low-power sleep state function The controller is equipped with a low-power sleep state that reduces current consumption. The low-power sleep state functions effectively under the following circumstances. (1) When there is no host controller connected (2) When the device state is shifted to the suspended state, and USB data transfer is not necessary The system is returned from the low-power sleep state to the normal operating state using a designated interrupt, or by dummy writing to the controller. Rev1.00 2004.10.01 page 12 of 125 M66592FP/WG 2 Registers Reading the table of registers Bit no. Status after reset Each register is connected to a 16-bit internal bus. Odd-numbered addresses will use b15 to b8, and even-numbered addresses b7 to b0. This indicates the default state of the register immediately after a reset operation, and after recovering from the low-power sleep state. H/W Reset is the default state when an external reset signal has been input from the RST_N pin. S/W Reset is the default state when the user system has carried out a bit operation using the USBE bit. USB Reset is the default state when the controller has detected a USB bus reset. Low-power Sleep is the default state when the controller has recovered from the low-power sleep state. Items that require particular attention during a reset operation are noted under " Notes". "-" indicates a state in which there is no operation by the controller, and the user setting is retained. "?" indicates that a value is undecided. S/W Access Condition This is the condition in effect if the user system control program is accessing a register. H/W Access Condition This is the condition in effect if the controller is accessing a register during any operation other than a reset. R ...... Read Only W ...... Write Only R/W ...... Read / Write R(0) ...... "0"Read Only W(1) ...... "1"Write Only Note Bit Name Function Description This is the number of detailed explanations and the number of notes. This indicates the bit symbol and bit name. This describes active items and notes. Nothing is placed in shaded sections. These should be fixed at "0". Low-power sleep state 15 ? ? ? ? 14 13 12 A bit B bit C bit 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 14 13 12 Name Function Nothing is placed here. It should be fixed at "0". A bit 0 : Operation disabled AAA enabled 1 : Operation enabled B bit 0 : "L"output BBB operation 1 : "H"output C bit 0 : ....... CCC control 1 : ....... S/W R/W R R(0)/ W(1) H/W R W R Note 2.3.1 *1 2.3.2 *1 2.3.2 Note *1) If the A bit and B bit are being accessed in succession for writing, an access cycle of 300 ns is necessary. Rev1.00 2004.10.01 page 13 of 125 M66592FP/WG 2.1 Table of registers Table 2.1 shows the controller registers. Table 2.1 Registers Address 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E 40 42 44 46 48 4A 4C 4E 50 52 54 56 58 5A 5C 5E Rev1.00 Symbol SYSCFG SYSSTS DVSTCTR TESTMODE PINCFG DMA0CFG DMA1CFG CFIFO D0FIFO D1FIFO Name System configuration control register System configuration status register Device state control register Test mode register Data pin configuration register DMA0 pin configuration register DMA1 pin configuration register CFIFO port register D0FIFO port register D1FIFO port register Index 2.3 2.3 2.4 2.4 2.5 2.5 2.5 2.6 2.6 2.6 CFIFOSEL CFIFOCTR CFIFOSIE D0FIFOSEL D0FIFOCTR D0FIFOTRN D1FIFOSEL D1FIFOCTR D1FIFOTRN INTENB0 INTENB1 BRDYENB NRDYENB BEMPENB SOFCFG INTSTS0 CFIFO port selection register CFIFO port control register CFIFO port SIE register D0FIFO port selection register D0FIFO port control register D0 transaction counter register D1FIFO port selection register D1FIFO port control register D1 transaction counter register Interrupt enable register 0 Interrupt enable register 1 BRDY interrupt enable register NRDY interrupt enable register BEMP interrupt enable register SOF pin configuration register Interrupt status register 0 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.7 2.7 2.7 2.7 2.7 2.8 2.9 BRDYSTS NRDYSTS BEMPSTS FRMNUM UFRMNUM RECOVER USBREQ USBVAL USBINDX USBLENG DCPCFG DCPMAXP page 14 of 125 BRDY interrupt status register NRDY interrupt status register BEMP interrupt status register Frame number register Micro frame number register USB address / low-power status recovery register USB request type register USB request value register USB request index register USB request length register DCP configuration register DCP maximum packet size register 2.9 2.9 2.9 2.10 2.10 2.11 2.12 2.12 2.12 2.12 2.13 2.13 2004.10.01 M66592FP/WG Address 60 62 64 66 6E 6A 6C 6E 70 72 74 76 78 7A 7C 7E Symbol DCPCTR PIPESEL PIPECFG PIPEBUF PIPEMAXP PIPEPERI PIPE1CTR PIPE2CTR PIPE3CTR PIPE4CTR PIPE5CTR PIPE6CTR PIPE7CTR DCP control register Pipe window selection register Pipe configuration register Pipe buffer setting register Pipe maximum packet size register Pipe period control register Pipe 1 control register Pipe 2 control register Pipe 3 control register Pipe 4 control register Pipe 5 control register Pipe 6 control register Pipe 7 control register Name Index 2.13 2.14 2.14 2.14 2.14 2.14 2.14 2.14 2.14 2.14 2.14 2.14 2.14 Nothing is placed in addresses that are shaded. These addresses should not be accessed. Rev1.00 2004.10.01 page 15 of 125 M66592FP/WG 2.2 Table of bit symbols Table 2.2shows the controller bit symbols. Table 2.2 Bit symbols Addr Register name 15 XTAL 14 Odd-numbered addresses 13 12 11 10 XCKE RCKE PLLC SCKE 9 8 ATCKM WKUP 7 HSE 6 Even-numbered addresses 5 4 3 2 DPRPU 1 PCUT LNST RHST UTST 0 USBE 00 SYSCFG 02 SYSSTS 04 DVSTCTR 06 TESTMODE 08 0A PINCFG 0C DMA0CFG 0E DMA1CFG 10 CFIFO 12 14 D0FIFO 16 18 D1FIFO 1A 1C 1E CFIFOSEL 20 CFIFOCTR 22 CFIFOSIE 24 D0FIFOSEL LDRV DREQA BURST DREQA BURST DACKA DACKA BIGEND DFORM DFORM CFPORT D0FPORT D1FIPORT DENDA PKTM DENDA PKTM DENDE DENDE OBUS OBUS RCNT BVAL TGL RCNT REW BCLR SCLR REW BCLR REW BCLR RSME FRDY SBUSY DCLRM DREQE FRDY MBW ISEL DTLN CURPIPE MBW TRENB TRCLR DEZPM DTLN TRNCNT CURPIPE 26 D0FIFOCTR BVAL 28 D0FIFOTRN 2A D1FIFOSEL RCNT 2C D1FIFOCTR BVAL 2E D1FIFOTRN 30 INTENB0 32 INTENB1 34 36 BRDYENB 38 NRDYENB 3A BEMPENB 3C SOFCFG 3E 40 INTSTS0 42 44 46 BRDYSTS 48 NRDYSTS 4A BEMPSTS 4C FRMNUM 4E UFRMNUM 50 RECOVER 52 54 USBREQ 56 USBVAL 58 USBINDX 5A USBLENG 5C DCPCFG 5E DCPMAXP 60 DCPCTR 62 BSTS OVRN VBINT VBSE DCLRM DREQE FRDY MBW TRENB TRCLR DEZPM DTLN TRNCNT CURPIPE SOFE DVSE CTRE BEMPE NRDYE BRDYE URST SADR SCFG SUSP WDST RDST BRDYM CMPL INTL SERR PCSE PIPEBRDYE PIPENRDYE PIPEBEMPE SOFM RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS DVSQ VALID CTSQ PIPEBRDY PIPENRDY PIPEBEMP CRCE SOFRM STSRECOV bRequest wValue wIndex wLength CNTMD MXPS SQCLR SQSET SQMON CCPL PID FRNM UFRNM USBADDR bmRequestType Rev1.00 2004.10.01 page 16 of 125 M66592FP/WG Register name Odd-numbered addresses 13 12 11 10 BFRE BUFSIZE MXPS IFIS BSTS INBUFM BSTS INBUFM BSTS INBUFM BSTS INBUFM BSTS INBUFM BSTS BSTS ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON IITV PID PID PID PID PID PID PID Addr 15 TYPE 14 9 DBLB 8 7 6 Even-numbered addresses 5 4 3 2 DIR BUFNMB EPNUM 1 PIPESEL 0 64 PIPESEL 66 PIPECFG 68 PIPEBUF 6A PIPEMAXP 6C PIPEPERI 6E 70 PIPE1CTR 72 PIPE2CTR 74 PIPE3CTR 76 PIPE4CTR 78 PIPE5CTR 7A PIPE6CTR 7C PIPE7CTR 7E CNTMD SHTNAK Rev1.00 2004.10.01 page 17 of 125 M66592FP/WG 2.3 System control System configuration control register [SYSCFG] 15 XTAL 0 0 14 13 XCKE 0 1 12 RCKE 0 0 11 PLLC 0 0 10 SCKE 0 0 9 ? ? ? ? 8 ATCKM 0 7 HSE 0 6 ? ? ? ? 5 ? ? ? ? 4 DPRPU 0 3 ? ? ? ? 2 ? ? ? ? 1 PCUT 0 0 0 USBE 0 - Bit 15-14 XTAL Clock selection Name 00: 12 MHz input 01: 24 MHz input 10: 48 MHz input 11: Reserved Function S/W R/W H/W R Note 3.1.5 13 XCKE 0: Oscillation buffer operation disabled R/W R/W(1) 3.1.5 Oscillation buffer enabled 1: Oscillation buffer operation enabled *2) 12 RCKE 0: Reference clock supply stopped R/W R 3.1.5 Reference clock enabled 1: Reference clock supply enabled 11 PLLC 0: PLL operation disabled R/W R 3.1.5 PLL operation enabled 1: PLL operation enabled 10 SCKE 0: Internal clock supply stopped R/W R 3.1.5 Internal clock enabled 1: Internal clock supply enabled 9 Nothing is placed here. It should be fixed at "0". The clock is supplied from the low-power sleep R/W R 8 ATCKM 3.1.6.6 Auto clock supply function enabled state or clock stop state. 0: Auto clock supply function disabled 1: Auto clock supply function enabled 7 HSE This enables Hi-Speed operation. R/W R 3.1.3 Hi-Speed operation enabled 0: Hi-Speed operation disabled (Full-Speed) *1) 1: Hi-Speed operation enabled (detected by controller) 6-5 Nothing is placed here. These should be fixed at "0". 4 DPRPU Issues notification of connection to host R/W R 3.1.4 D+ line pull-up control controller. 0: Pull-up disabled 1: Pull-up enabled 3-2 Nothing is placed here. These should be fixed at "0". 1 PCUT 0: Normal operation state R/W(1) R/W(0) 3.1.6 Low-power sleep state enabled 1: Low-power sleep state 0 USBE 0: USB block operation disabled (S/W Reset) R/W R 2.3.1 USB block operation enabled 1: USB block operation enabled 3.1.1 Notes *1) The Hi-Speed operation enabled((HSE) bit should be set beforethe DPRPU bit is set to "1". *2) When the system returns from the low-power sleep state to the normal operation state, the controller sets "XCKE = 1". Rev1.00 2004.10.01 page 18 of 125 M66592FP/WG System configuration status register [SYSSTS] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 ? ? ? ? 6 ? ? ? ? 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 ? ? ? ? 1 LNST ? ? ? ? ? ? ? ? 0 Bit Name Function S/W R H/W W Note 2.3.2 15-2 Nothing is placed here. These should be fixed at "0". 1-0 LNST Please see the detailed explanation concerning USB data line status this item. Notes None in particular 2.3.1 USB block operation enabled The USBE bit of the SYSCFG register should be used to enable USB block operation. The same bit can be used to carry out an S/W reset of the controller. When software is set to "USBE=0", the controller resets the register targeted for S/W reset initialization to the default setting value. As long as "USBE=0" is set, no data can be written by software to the bit targeted for S/W reset initialization. "USBE=1" should be set following an S/W reset to enable controller operation. 2.3.2 Line status monitor Table 2.3 shows the USB data bus line statuses of the controller. The controller monitors the line status (D+ line and D- line) of the USB data bus using the LNST bit of the SYSSTS register. The LNST bit is configured of two bits. For the meaning of each of the bits, please refer to the table below. The timing at which the LNST bit becomes valid differs depending on the selected controller function. In the normal operating state, the line status can be monitored on an ongoing basis, but in the low-power sleep state, the line status cannot be monitored. Table 2.3 USB data bus line statuses During Full-Speed During Hi-Speed operation During chirp operation operation 0 0 SE0 Squelch Squelch 0 1 J State not Squelch Chirp J 1 0 K State Invalid Chirp K 1 1 SE1 Invalid Invalid Chirp: The reset handshake protocol is being executed in the Hi-Speed operation enabled state (HSE = "1"). Squelch: SE0 or Idle state not Squelch: Hi-Speed J state or Hi-Speed K state Chirp J: Chirp J state Chirp K: Chirp K state LNST [1] LNST [0] Rev1.00 2004.10.01 page 19 of 125 M66592FP/WG 2.4 USB signal control Device state control register [DVSTCTR] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 WKUP 0 0 0 0 7 ? ? ? ? 6 ? ? ? ? 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 ? ? ? ? 1 RHST 0 0 0 0 0 0 0 Bit Name Function S/W H/W Note 15-9 Nothing is placed here. These should be fixed at "0". 8 WKUP 0: Non-output Wakeup output 1: Remote wakeup signal output 7-2 Nothing is placed here. These should be fixed at "0". 1-0 RHST 00: Communication speed not decided Reset handshake 01: Reset handshake being processed 10: Full-Speed operation established 11: Hi-Speed operation established R/W(1) R/W(0) 2.4.1 *1), *2) R W 2.4.2 Notes *1) "1" should never be written to the WKUP bit unless "Suspended" is set for the device state ("DVSQ = 1x") and a remote wakeup from the USB host is enabled. *2) When the WKUP bit is set to "1", software should not disable oscillation buffer operation. Test mode register [TESTMODE] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 ? ? ? ? 6 ? ? ? ? 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 0 0 0 1 UTST 0 0 0 0 0 0 0 Bit Name Function S/W H/W R Note 2.4.3 *3) 15-4 Nothing is placed here. These should be fixed at "0". 3-0 UTST Please see the detailed explanation concerning R/W Test mode this item. Note *3) The UTST bit is valid only during Hi-Speed operation. Check to make sure the "RHST=11" before using it. Rev1.00 2004.10.01 page 20 of 125 M66592FP/WG 2.4.1 USB data bus control Each bit of the DVSTCTR register can be used to control and confirm the state of the USB data bus based on the user system. The WKUP bit handles control of remote wakeup signal output to the USB bus. The controller controls the output time for remote wakeup signals. 2ms after a software has set "1" for the WKUP bit, the controller outputs a 10 ms "K-State" then it transfers the bus state to idle. When the bus state is transferred to the idle state, the controller sets "WKUP=0". According to the USB specification, USB idle state must be kept longer than 5ms. Thus if the software set "WKUP=1" right after detection of Suspend state, the controller will assert "K-State" after 2ms. 2.4.2 Communication speed discrimination Software is able to confirm the USB speed at which communication is being carried out with the host controller (the communication bit rate), using the RHST bit. If Hi-Speed operation has been set to the disabled state ("HSE=0") by software, the controller immediately establishes Full-Speed operation ("RHST=10") after a USB bus reset has been detected, without executing the reset handshake protocol. If Hi-Speed operation has been set to the enabled state ("HSE=1"), the controller executes the reset handshake protocol ("RHST=01" during execution of the protocol), and feeds back the execution results to the RHST bit ("RHST=11" : Hi-Speed operation, or "RHST=10" : Full-Speed operation). 2.4.3 Test mode Table 2.4 shows the test mode operation of the controller. The UTST bit of the TESTMODE register controls the USB test signal output during Hi-Speed operation. Table 2.4 Test mode operation Test mode Normal operation Test_J Test_K Test_SE0_NAK Test_Packet Reserved UTST bit setting 000 001 010 011 100 101-111 Rev1.00 2004.10.01 page 21 of 125 M66592FP/WG 2.5 External input/output control Data pin configuration register [PINCFG] 15 LDRV 0 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 BIGEND 7 ? ? ? ? 6 ? ? ? ? 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 ? ? ? ? 1 ? ? ? ? 0 ? ? ? ? 0 0 Bit Name Function S/W R/W H/W R Note 2.5.1 15 LDRV 0: When VIF=1.6-2.0 V Output pins drive current control 1: When VIF=2.7-3.6 V 14-9 Nothing is placed here. These should be fixed at "0". 8 BIGEND 0: Little Endian FIFO port Endian 1: Big Endian 7-0 Nothing is placed here. These should be fixed at "0". R/W R 2.5.2 *1) Note *1) The BIGEND bit is common to all of the FIFO ports and available for the FIFO ports only. The BIGEND bit doesn't affects register acess. Rev1.00 2004.10.01 page 22 of 125 M66592FP/WG The DMA0CFG register controls the input/output pins used for the DMA0 interface and the D0FIFO port, and the DMA1CFG register controls the input/output pins used for the DMA1 interface and the D1FIFO port. DMA0 pin configuration register [DMA0CFG] DMA1 pin configuration register [DMA1CFG] 15 ? ? ? ? 14 13 DREQA BURST 0 0 0 12 ? ? ? ? 11 ? ? ? ? 10 DACKA 0 0 9 0 0 8 DFORM 0 0 7 0 0 6 5 4 DENDA PKTM DENDE 0 0 0 0 0 0 3 ? ? ? ? 2 OBUS 0 0 1 ? ? ? ? 0 ? ? ? ? Bit Name Function S/W R/W H/W R Note - 15 Nothing is placed here. This should be fixed at "0". 14 DREQA This specifies the active state for the DREQx_N DREQx_N signal polarity selection pin. 0: Low active 1: High active 13 BURST 0: Cycle steal transfer Burst mode 1: Burst transfer 12-11 Nothing is placed here. These should be fixed at "0". 10 DACKA This specifies the active state for the DACKx_N DACKx_N signal polarity selection pin. 0: Low active 1: High active 9-7 DFORM 011: Only the DACKx_N signal is used (CPU DMA transfer signal selection bus). 000: The Address signal + the RD_N/WRx_ signals are used (CPU bus). 010: The DACKx_N + the RD_N/WRx_N signals are used (CPU bus). 100: The DACKx_N signal is used (split bus). 110: The DACK0_N + the DSTB0_N signal are used (split bus). 001, 101, 111: Reserved 6 DENDA This specifies the active state of the DENDx_N DEND0_N signal polarity selection pin. 0: Low active 1: High active 5 PKTM 0: The DENDx_N signal is asserted in transfer Packet mode units. 1: The DENDx_N signal is asserted each time an amount of data corresponding to the buffer size is transferred. 4 DENDE 0: The DENDx_N signal is disabled (Hi-Z DENDx_N signal enabled output). 1: The DENDx_N signal is enabled. 3 Nothing is placed here. It should be fixed at "0". 2 OBUS 0: The OBUS mode is enabled. OBUS operation disabled 1: The OBUS mode is disabled. 1-0 Nothing is placed here. These should be fixed at "0". R/W R 2.5.3 R/W R - R/W R 3.4.3.2 *3) R/W R - R/W R 2.5.3 3.4.3.4 *2) 2.5.3 3.4.3.4 3.5 R/W R R/W R Notes *2) The PKTM bit is valid only when the data receiving direction (reading from the buffer memory) is set. If the DxFIFO port is being used in the data writing direction, "PKTM=0" should be set. *3) The "DFORM=110" setting is valid only when the DMA channel 0 is set. Also, the following should not be set: "DFORM=001","DFORM=101" and"DFORM=111". Rev1.00 2004.10.01 page 23 of 125 M66592FP/WG 2.5.1 Output pins drive current control The output pins drive capability should be set using the LDRV bit of the PINCFG register, to match the VIF power supply. The output pins are the SD7-0, D15-0, INT_N, DREQx_N, DENDx_N, and SOF_N pins. 2.5.2 FIFO port access Endian Table 2.5 and Table 2.6 show the byte Endian operation of the controller. (The controller uses Little Endian.) When the CPU of user-system is Big-endian, software should be set the BIGEND bit to "1" of the PINCFG register. Table 2.5 Endian operation when using 16-bit access BIGEND 0 1 b15 - b8 Odd-numbered addresses Even-numbered addresses b7 - b0 Even-numbered addresses Odd-numbered addresses Table 2.6 Endian operation when using 8-bit access BIGEND 0 1 b15 - b8 Writing: invalid Reading: invalid Writing: valid Reading: valid b7 - b0 Writing: valid Reading: valid Writing: invalid Reading: invalid 2.5.3 DMA signal control When transferring data using the DMA interface, the DMA operations (assertion and negation of the DREQx_N and DENDx_N signals, and the DMA transfer mode) should be specified to match the user system, using the BURST, PKTM, DENDE, and OBUS bits of the DMAxCFG register. The DMA signals are valid for the selected pipe(s) as long as DMA transfers are enabled using the DREQE bit of the DxFIFOSEL register, which will be explained later. The DREQx_N pin is asserted when the buffer memory of the pipe is in the Buffer Ready (BRDY) state. Rev1.00 2004.10.01 page 24 of 125 M66592FP/WG 2.6 FIFO ports The transmission and reception buffer memory of the controller uses the FIFO configuration. The FIFO port registers should be used to access the buffer memory. There are three FIFO ports: the CFIFO port, D0FIFO port, and D1FIFO port. Each FIFO port is configured of a port register that handles reading of data from the buffer memory, as well as writing of data to the memory, a selection register used to select the pipe assigned to the FIFO port, a control register, and registers used specifically for port functions (an SIE register used exclusively for the CFIFO port, and a transaction counter register used exclusively for the DxFIFO port). The Notes noted below apply to each of the FIFO ports. For more detailed information, please refer to Chapter 3.4, Buffer memory. (1) The DCP buffer memory can only be accessed through the CFIFO port. (2) Accessing the buffer memory using DMA transfer can be done only through the DxFIFO port. (3) Accessing the DxFIFO port using the CPU has to be done in conjunction with the functions and restrictions of the DxFIFO port. (Using the transaction counter, etc.) (4) When using functions specific to the FIFO port, the selected pipe cannot be changed. (Using the transaction counter, signal input/output through DMA-related pins, etc.) (5) Registers corresponding to a FIFO port never affect other FIFO ports. (6) The same pipe should not be assigned to two or more FIFO ports. (7) There are two sorts of buffer memory states; the access right is on the CPU side and it is on the SIE side. When the buffer memory access right is on the SIE side, the memory cannot be properly accessed from the CPU. (8) The pipe configuration,i.e. PIPECFG, PIPEBUF, PIPEMAXP, PIPEPERI, PIPE1CTR registers of the pipe selected by the CURPIPE bit should not be changed. CFIFO port register [CFIFO] D0FIFO port register [D0FIFO] D1FIFO port register [D1FIFO] 15 0 0 0 14 0 0 0 13 0 0 0 12 0 0 0 11 0 0 0 10 0 0 0 9 0 0 0 8 7 FIFOPORT 0 0 0 0 0 0 6 0 0 0 5 0 0 0 4 0 0 0 3 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit 15-0 FIFOPORT FIFO port Name Function S/W H/W R/W Note 3.4 *1) This handles reading of received data from the R/W buffer memory, or writing of the sent data to the buffer memory. Note *1) Only the CFIFO port can be used for DCP access of the buffer memory. Accessing the buffer memory using DMA transfers can only be done through the D0FIFO and D1FIFO ports. Rev1.00 2004.10.01 page 25 of 125 M66592FP/WG CFIFO port selection register [CFIFOSEL] D0FIFO port selection register [D0FIFOSEL] D1FIFO port selection register [D1FIFOSEL] 15 RCNT 0 0 0 14 13 12 REW DCLRM DREQE 0 0 0 0 0 0 0 0 0 11 ? ? ? ? 10 9 8 7 MBW TRENB TRCLR DEZPM 0 0 0 0 0 0 0 0 0 0 0 0 6 ? ? ? ? 5 ISEL 0 0 0 4 ? ? ? ? 3 ? ? ? ? 2 0 0 0 1 CURPIPE 0 0 0 0 0 0 0 Bit Name Function 0: The DTLN bit is cleared when all of the reception data has been read. 1: The DTLN bit is decremented when the reception data is read. 0:Invalid. 1: The buffer pointer is rewound. 0: The Auto Buffer Clear mode is disabled. 1: The Auto Buffer Clear mode is enabled. S/W R/W H/W R Note 3.4.2 15 RCNT Read Count mode 14 REW Buffer pointer rewind 13 DCLRM This is the Auto Buffer Memory clear mode accessed after the data for the specified pipe has been read. 12 DREQE 0: Output is disabled. DREQ signal output enabled 1: Output is enabled. 11 Nothing is placed here. This should be fixed at "0". 10 MBW 0: 8-bit width FIFO port access bit width 1: 16-bit width 9 TRENB 0: The transaction counter function is invalid. Transaction counter enabled 1: The transaction counter function is valid. 8 TRCLR 0: Invalid Transaction counter clear 1: The current count is cleared. 7 DEZPM 0: No packet is added. Zero-Length Packet Added mode 1: The packet is added. 6 Nothing is placed here. This should be fixed at "0". 0: This selects reading from the buffer memory. 5 ISEL Access direction of the FIFO port when 1: This selects writing to the buffer memory. DCP is selected 4-3 Nothing is placed here. These should be fixed at "0". 2-0 CURPIPE 000: DCP / No specification FIFO port access pipe specification 001: Pipe 1 010: Pipe 2 011: Pipe 3 100: Pipe 4 101: Pipe 5 110: Pipe 6 111: Pipe 7 R(0)/W R/W(0) 3.4.2 R/W R 3.4.3 *2) 3.4.3 *2), 3.4.2 *4) 3.4.2 *2) 3.4.2 *2) 3.4.3 *2) 3.4 *3) 3.4 *5) R/W R R/W R/W R(0)/ W(1) R/W R R R R R/W R R/W R Notes *2) The DCLRM, DREQE, TRENB, TRCLR and DEZPM bits are valid for the D0/D1FIFOSEL registers. The DCLRM, TRENB and TRCLR bits are valid when the receiving direction (reading from the buffer memory) has been set for the pipe specified by the CURPIPE bit. The DEZPM bit is valid when the sending direction (writing to the buffer memory) has been set for the pipe specified by the CURPIPE bit. *3) The ISEL bit is valid only when DCP is selected using the CFIFO port selection register. Software should set the ISEL bit according to the folowing (a) or (b) (a) The setting to CURPIPE bit to DCP ("CURPIPE="0") and setting to ISEL bit should be done at the same time. (b) First software sets CURPIPE bit to DCP ("CURPIPE="0"), then it sets ISEL bit after 200ns or more. *4) Once reading from the buffer memory has begun, the access bit width of the FIFO port cannot be changed until all of the data has been read. Also, the bit width cannot be changed from the 8-bit width to the 16-bit width while data is being written to the buffer memory. *5) Specifying"CURPIPE=0"using the D0/D1FIFOSEL register will be interpreted as no pipe having been specified. Also, the pipe number should not be changed while DREQ output is enabled. Rev1.00 2004.10.01 page 26 of 125 M66592FP/WG CFIFO port control register [CFIFOCTR] D0FIFO port control register [D0FIFOCTR] D1FIFO port control register [D1FIFOCTR] 15 BVAL 0 0 0 14 BCLR 0 0 0 13 FRDY 0 0 0 12 ? ? ? ? 11 0 0 0 10 0 0 0 9 0 0 0 8 0 0 0 7 0 0 0 6 DTLN 0 0 0 0 0 0 0 0 0 5 4 3 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function S/W H/W Note 15 BVAL 0: Invalid R/ W(1) R/W 3.4.2 Buffer Memory Valid flag 1: Writing ended *6) 14 BCLR 0: Invalid R(0)/ R/W(0) 3.4 CPU Buffer Clear 1: Clears the buffer memory on the CPU side. W(1) *7), *8) 13 FRDY 0: FIFO port access is disabled. R W 3.4 FIFO Port Ready 1: The FIFO port can be accessed. *9) 12 Nothing is placed here. This should be fixed at "0". 11-0 DTLN The length of the reception data can be R W 3.4.2 Reception Data Length confirmed. 3.4.4 *7) Notes *6) Writing "1" to the BVAL bit is valid when the direction of the data packet is the sending direction (when data is being written to the buffer memory). When the direction is the receiving direction, "BVAL=0" should be set. *7) The BCLR bit and DTLN bit are valid for the buffer memory on the CPU side. Software should set "BCLR=1" or refer DTLN bit after making sure that "FRDY=1". *8) Using the BCLR bit to clear the buffer should be done with the pipe invalid state by the pipe configuration ("PID=NAK"). When DCP is selected, the BCLR bit has the same function as the ACLRM bit of the PIPExCTR register. *9) The FRDY bit requires an access cycle of at least 450 ns after the pipe has been selected. CFIFO port SIE register [CFIFOSIE] 15 TGL 0 0 0 14 13 SCLR SBUSY 0 0 0 0 0 0 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 ? ? ? ? 6 ? ? ? ? 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 ? ? ? ? 1 ? ? ? ? 0 ? ? ? ? Bit Name Function S/W H/W Note 0: Invalid 15 TGL Access Right Switch 1: Switches access right 14 SCLR 0: Invalid SIE Buffer Clear 1: Clears buffer memory on SIE side 13 SBUSY 0: SIE is not being accessed. SIE Buffer Busy 1: SIE is being accessed. 12-0 Nothing is placed here. These should be fixed at "0". R(0)/ R/W(0) 3.4.2 W(1) *10) R(0)/ R/W(0) 3.4 W(1) *11) R W 3.4.2 Note *10) The function of the TGL bit is to set the buffer memory on the SIE side to the CPU side. Set "PID=NAK" and check the SBUSY bit to make sure the SIE is not accessing the buffer ("SBUSY=0"). Then write the TGL bit (toggle operation). This bit is valid only for pipes for which the reception direction (reading from the buffer memory) has been set. *11) The function of the SCLR bit is to clear the buffer memory on the SIE side. Set "PID=NAK" and check the SBUSY bit to make sure the SIE is not accessing the buffer ("SBUSY=0"). Then clear the buffer. This bit is valid only for pipes for which the sending direction (writing to the buffer memory) has been set. Rev1.00 2004.10.01 page 27 of 125 M66592FP/WG D0 transaction counter register [D0FIFOTRN] D1 transaction counter register [D1FIFOTRN] 15 0 0 0 14 0 0 0 13 0 0 0 12 0 0 0 11 0 0 0 10 0 0 0 9 0 0 0 8 7 TRNCNT 0 0 0 0 0 0 6 0 0 0 5 0 0 0 4 0 0 0 3 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function Writing: Sets the number of DMA transfer transactions. Reding: Reads the number of transactions. S/W R/W H/W R Note 3.4.2 *12) 15-0 TRNCNT Transaction counter Note *12) The transaction counter is valid when data is being read from the buffer memory. The number of transactions can be read while counting is taking place only if the TRENB bit of the DxFIFOSEL register is "1". If "TRENB=0", the set number of transactions can be read. Rev1.00 2004.10.01 page 28 of 125 M66592FP/WG 2.7 Interrupts enabled Interrupts enabled register 0[INTENB0] 15 VBSE 0 0 14 RSME 0 0 13 SOFE 0 0 0 12 DVSE 0 0 0 11 10 9 8 7 CTRE BEMPE NRDYE BRDYE URST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 SADR 0 0 0 5 SCFG 0 0 0 4 SUSP 0 0 0 3 WDST 0 0 0 2 RDST 0 0 0 1 CMPL 0 0 0 0 SERR 0 0 0 Bit Name Function 0: Interrupt output disabled 1: Interrupt output enabled 0: Interrupt output disabled 1: Interrupt output enabled S/W R/W H/W R Note 3.2.8 2.7.1 2.7.4 3.2.9 2.7.1 2.7.4 3.2.7 2.7.1 3.2.5 2.7.1 2.7.2 3.2.6 2.7.1 2.7.3 3.2.4 2.7.1 3.2.3 2.7.1 3.2.2 2.7.1 3.2.5 2.7.2 3.2.5 2.7.2 3.2.5 2.7.2 3.2.5 2.7.2 3.2.6 2.7.3 3.2.6 2.7.3 3.2.6 2.7.3 3.2.6 2.7.3 15 VBSE VBUS interrupts enabled 14 RSME Resume interrupts enabled R/W R 13 SOFE 0: Interrupt output disabled Frame number refresh interrupts enabled 1: Interrupt output enabled 12 DVSE 0: Interrupt output disabled Device state transition interrupts enabled 1: Interrupt output enabled 11 CTRE 0: Interrupt output disabled Control transfer stage transition interrupts 1: Interrupt output enabled enabled 10 BEMPE 0: Interrupt output disabled Buffer Empty interrupts enabled 1: Interrupt output enabled 9 NRDYE 0: Interrupt output disabled Buffer Not Ready response interrupts 1: Interrupt output enabled enabled 8 BRDYE 0: Interrupt output disabled Buffer Ready interrupts enabled 1: Interrupt output enabled 7 URST 0: DVST interrupt disabled at transition to Default state transition notifications default state enabled 1: DVST interrupt enabled at transition to default state 0: DVST interrupt disabled at transition to 6 SADR Address state transition notifications address state enabled 1: DVST interrupt enabled at transition to address state 5 SCFG 0: DVST interrupt disabled at transition to Configuration state transition notifications configuration state enabled 1: DVST interrupt enabled at transition to configuration state 4 SUSP 0: DVST interrupt disabled. at transition to Suspend state transition notifications suspend state enabled 1: DVST interrupt enabled at transition to suspend state 3 WDST 0: CTST interrupt disabled at transition to status Control write transfer status stage stage of control write transfer transition notifications enabled 1: CTST interrupt enabled at transition to status stage of control write transfer 2 RDST 0: CTST interrupt disabled at transition to status Control read transfer status stage stage of control read transfer transition notifications enabled 1: CTST interrupt enabled at transition to status stage of control read transfer 1 CMPL 0: CTST interrupt are disabled at end of control Control transfer end notifications enabled transfer 1: CTST interrupt enabled at end of control transfer 0 SERR 0: CTST interrupt disabled at detection of Control transfer sequence error control transfer sequence error notifications enabled 1: CTST interrupt enabled at detection of control transfer sequence error R/W R/W R R R/W R R/W R/W R/W R/W R R R R R/W R R/W R R/W R R/W R R/W R R/W R R/W R Rev1.00 2004.10.01 page 29 of 125 M66592FP/WG Note None in particular Rev1.00 2004.10.01 page 30 of 125 M66592FP/WG Interrupt enabled register 1[INTENB1] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 ? ? ? ? 6 ? ? ? ? 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 BRDYM 0 0 1 INTL 0 0 0 PCSE 0 0 - Bit Name Function S/W R/W R/W R/W H/W R R R Note 3.2.2 *1) 3.2.1 3.2.5 *2) 15-3 Nothing is placed here. These should be fixed at "0". 2 BRDYM 0: Software clears BRDY interrupt status BRDY interrupt status clear timing control 1: The controller clears BRDY interrupt status 1 INTL 0: Edge sensing Interrupt output sensing control 1: Level sensing 0 PCSE 0: USB resume detectionm, VBUS interrupt returning fact selection from low-power detection during suspend, or CS_N signal sleep mode input 1: USB resume detectionm, or VBUS interrupt detection during suspend Note *1) When software sets "BRDYM=1", it will set "INTL=1" also. *2) PCSE bit shoud be set after "USBE=1" setting. Rev1.00 2004.10.01 page 31 of 125 M66592FP/WG BRDY interrupt enabled register [BRDYENB] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 0 0 0 6 0 0 0 5 0 0 0 4 3 PIPEBRDYE 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function S/W R/W H/W R Note 3.2.2 2.7.1 *3) 15-8 Nothing is placed here. These should be fixed at "0". 7-0 PIPEBRDYE 0: Interrupt output disabled BRDY interrupts for each pipeis enabled. 1: Interrupt output enabled Note *3) The bit numbers correspond to the pipe numbers. NRDY interrupt enabled register [NRDYENB] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 0 0 0 6 0 0 0 5 0 0 0 4 3 PIPENRDYE 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function S/W R/W H/W R Note 3.2.3 2.7.1 *4) 15-8 Nothing is placed here. These should be fixed at "0". 7-0 PIPENRDYE 0: Interrupt output disabled NRDY interrupts for each pipe is enabled. 1: Interrupt output enabled Note *4) The bit numbers correspond to the pipe numbers. BEMP interrupt enabled register [BEMPENB] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 0 0 0 6 0 0 0 5 0 0 0 4 3 PIPEBEMPE 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function S/W R/W H/W R Note 3.2.4 2.7.1 *5) 15-8 Nothing is placed here. These should be fixed at "0". 7-0 PIPEBEMPE 0: Interrupt output disabled BEMP interrupts for each pipe is enabled. 1: Interrupt output enabled Note *5) The bit numbers correspond to the pipe numbers. Rev1.00 2004.10.01 page 32 of 125 M66592FP/WG 2.7.1 Interrupt masks The VBSE, RSME, SOFE, DVSE, CTRE, BEMPE, NRDYE, and BRDYE bits of the INTENB0 register operate as interrupt mask bits. Each of the bits should be used to specify whether interrupt signal output is enabled or disabled for the INT_N pin. The BRDYENB register, NRDYENB register and BEMPENB register operate as the BRDY interrupt mask bit, the NRDY interrupt mask bit, and the BEMP interrupt mask bit, respectively, for each corresponding pipe. For detailed information, please refer to 3.2 Interrupt functions. 2.7.2 Device state transition interrupts The URST, SADR, SCFG, and SUSP bits of the INTENB0 register operate as interrupt mask bits for the device state transition interrupt (DVST). If a factor is disabled, no device state transition interrupt is issued in response to the pertinent factor. However, the device state (DVSQ) transits in keeping with the circumstances. For detailed information, please refer to 3.2 Interrupt functions. 2.7.3 Control transfer stage transition interrupts The WDST, RDST, CMPL and SERR bits of the INTENB0 register operate as interrupt mask bits for the control transfer stage transition interrupt (CTRT). If a factor is disabled, no control transfer stage transition interrupts are issued in response to the pertinent factor. For detailed information, please refer to 3.2 Interrupt functions. 2.7.4 Operations in the low-power sleep state For VBSE and RSME, interrupts are issued in the low-power sleep state as well. Rev1.00 2004.10.01 page 33 of 125 M66592FP/WG 2.8 SOF control register SOF pin configuration register [SOFCFG] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 ? ? ? ? 6 ? ? ? ? 5 ? ? ? ? 4 ? ? ? ? 3 SOFM 0 0 0 0 ? ? ? ? ? ? ? ? 2 1 0 Bit Name Function S/W R/W H/W R Note 3.10.1 *1), *2) 15-4 Nothing is placed here. These should be fixed at "0". 3-2 SOFM This selects the SOF pulse output mode. SOF pin function setting 00: SOF output disabled 01: SOF output in units of 1 ms 10: uSOF output in units of 125 us 11: Reserved 1-0 Nothing is placed here. These should be fixed at "0". Notes *1) With Full-Speed operation, (when "HSE=0" has been set, or the RHST bit indicates "RHST=0" as the result of the reset handshake), "SOFM=10" should not be set. *2) This bit should be set after a reset handshake has been completed, or when recovering from the low-power sleep state, and should not be changed during subsequent USB communication. Rev1.00 2004.10.01 page 34 of 125 M66592FP/WG 2.9 Interrupt statuses Interrupt status register 0[INTSTS0] 15 14 VBINT RESM 0 0 0 0 13 SOFR 0 0 0 12 DVST 0 0 1 0 11 CTRT 0 0 0 10 BEMP 0 0 0 9 NRDY 0 0 0 8 7 BRDY VBSTS ? 0 0 ? 0 6 0 0 0 0 5 DVSQ 0 0 0 0 4 0 0 1 0 3 VALID 0 0 0 2 0 0 0 1 CTSQ 0 0 0 0 0 0 0 Bit Name Function S/W H/W W W W W W Note 3.2.8 *3) 3.2.9 *3) 3.2.7 *3) 3.2.5 *3) 3.2.6 *3) 3.2.4 *1)*2) 3.2.3 *1) 3.2.2 *1) 3.2.8 *2) 3.2.5 15 VBINT VBUS interrupt status 14 RESM Resume interrupt status 13 SOFR Frame number refresh interrupt status 12 DVST Device state transition interrupt status 11 CTRT Control transfer stage transition interrupt status 10 BEMP Buffer Empty interrupt status 9 NRDY Buffer Not Ready interrupt status 8 BRDY Buffer Ready interrupt status 7 VBSTS VBUS input status 6-4 DVSQ Device state 0: VBUS interrupts not issued R/W 1: VBUS interrupts issued 0: Resume interrupts not issued R/W 1: Resume interrupts issued 0: SOF interrupts not issued R/W(0) 1: SOF interrupts issued 0: Device state transition interrupts not issued R/W(0) 1: Device state transition interrupts issued 0: Control transfer stage transition interrupts not R/W(0) issued 1: Control transfer stage transition interrupts issued 0: BEMP interrupts not issued R 1: BEMP interrupts issued 0: NRDY interrupts not issued R 1: NRDY interrupts issued 0: BRDY interrupts not issued R 1: BRDY interrupts issued 0: VBUS pin is "L" level R 1: VBUS pin is "H" level 000: Powered state R 001: Default state 010: Address state 011: Configured state 1xx: Suspended state 0: Not detected 1: Setup packet reception 000: Idle or setup stage 001: Control read data stage 010: Control read status stage 011: Control write data stage 100: Control write status stage 101: Control write (NoData) status stage 110: Control transfer sequence error 111: Reserved R/W(0) R W W W W W VALID Setup packet reception 2-0 CTSQ Control transfer stage 3 W W 3.6.1 3.2.6 Note *1) The BEMP, BRDY and NRDY bits are cleared when all of the factors for each pipe on correcponding registers have been eliminated, i.e. BEMPSTS, BRDYSTS and NRDYSTS. *2) The VBUS input status based on the VBSTS bit requires that chattering be eliminated using software. *3) If multiple factors are being generated among the VBINT, RESM, SOFR, DVST, and CTRT bits, an access cycle of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously. Rev1.00 2004.10.01 page 35 of 125 M66592FP/WG BRDY interrupt status register [BRDYSTS] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 0 0 0 6 0 0 0 5 0 0 0 4 3 PIPEBRDY 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function S/W H/W Note 3.2.2 *4) 15-8 Nothing is placed here. These should be fixed at "0". 7-0 PIPEBRDY 0: Interrupts are not issued. BRDY interrupt status for theeach pipe 1: Interrupts are issued. R/W(0) W(1) Note *4) The bit numbers correspond to the pipe numbers. Also, if factors are being generated for more than one pipe, an access cycle of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously. NRDY interrupt status register [NRDYSTS] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 0 0 0 6 0 0 0 5 0 0 0 4 3 PIPENRDY 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function S/W H/W Note 3.2.3 *5) 15-8 Nothing is placed here. These should be fixed at "0". 7-0 PIPENRDY 0: Interrupts are not issued. NRDY interrupt for the each pipe 1: Interrupts are issued. R/W(0) W(1) Note *5) The bit numbers correspond to the pipe numbers. Also, if factors are being generated for more than one pipe, an access cycle of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously. BEMP interrupt status register [BEMPSTS] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 0 0 0 6 0 0 0 5 0 0 0 4 3 PIPEBEMP 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function S/W H/W Note 3.2.4 *6) 15-8 Nothing is placed here. These should be fixed at "0". 7-0 PIPEBEMP 0: Interrupts are not issued. BEMP interrupt for the each pipe 1: Interrupts are issued. R/W(0) W(1) Note *6) The bit numbers correspond to the pipe numbers. Also, if factors are being generated for more than one pipe, an access cycle of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously. Rev1.00 2004.10.01 page 36 of 125 M66592FP/WG 2.10 Frame number register Frame number register [FRMNUM] 15 14 OVRN CRCE 0 0 0 0 0 0 13 ? ? ? ? 12 ? ? ? ? 11 SOFRM 0 0 0 10 0 0 0 9 0 0 0 8 0 0 0 7 0 0 0 6 0 0 0 5 FRNM 0 0 0 4 0 0 0 3 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function S/W R/W(0) R/W(0) H/W W W Note 2.10.1 2.10.1 15 OVRN 0: No error Overrun / Underrun 1: Error issued 14 CRCE 0: No error Reception data error 1: Error issued 13-12 Nothing is placed here. These should be fixed at "0". 11 SOFRM 0: Interrupt asserted upon SOF reception and Frame number update interrupt output timer interpolation. mode 1: Interrupt asserted if SOF is damaged or missing. 10-0 FRNM The frame number can be confirmed. Frame number R/W R 2.10.2 3.2.7 *1) 2.10.2 R W Note *1) Frame number update interrupts are not issued for uSOF packet detection other than "UFRNM=0". micro frame number register [UFRMNUM] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 ? ? ? ? 6 ? ? ? ? 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 0 0 0 1 UFRNM 0 0 0 0 0 0 0 Bit Name Function S/W R H/W W Note 2.10.2 3.10 *2) 15-3 Nothing is placed here. These should be fixed at "0". 2-0 UFRNM The micro frame number can be confirmed. micro frame Note *2) When using Full-Speed operation, "000" is normally read with this bit. Rev1.00 2004.10.01 page 37 of 125 M66592FP/WG 2.10.1 Isochronous errors With this controller, data transfer errors that occur in isochronous transfers can be confirmed using the OVRN bit and the CRCE bit of the FRMNUM register. In isochronous transfers, error notification by the NRDY interrupt can be differentiated using the OVRN bit and the CRCE bit between data buffer errors and packet errors. Table 2.7and Table 2.8 show the conditions under which the OVRN bit and CRCE bit areset to "1". Table 2.7 Error information when an NRDY interrupt is issued in an isochronous out transfer Bit status "OVRN=1" "CRCE=1" Issued when: Data packet is received Data packet is received Issue conditions A new data packet is received before reading of buffer memory is completed A CRC error, or, a bit stuffing error is detected Detected error Reception data buffer overrun Received packet error Operation The new data packet is thrown out The new data packet is thrown out Table 2.8 Error information when an NRDY interrupt is issued in an isochronous in transfer Bit status "OVRN=1" "CRCE=1" Issued when: IN token is received Not issued Issue conditions Detected error An in-token is received before Transmission data buffer writing to buffer memory is underrun completed Operation Zero-Length packet transmission 2.10.2 SOF interrupts and frame numbers The SOFR interrupt operation mode should be selected using the SOFRM bit of the FRMNUM register. Also, the current frame number can be confirmed using the FRNM bit of the FRMNUM register and the UFRNM bit of the UFRNUM register. With this controller, the frame numbers are refreshed at the timing at which SOF packets are received. If the controller is unable to detect an SOF packet because the packet has beencorrupted, or for another reason, the FRNM value is retained until a new SOF packet is received. At that point, the FRNM bit based on the SOF interpolation timer is not refreshed. Also, the UFRNM bit is incremented in response to a uSOF packet being received. Rev1.00 2004.10.01 page 38 of 125 M66592FP/WG 2.11 USB address((low-power recovery) USB address/low-power status recovery register [RECOVER] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 0 0 9 STSRECOV 0 0 8 0 0 7 ? ? ? ? 6 0 0 0 0 5 0 0 0 0 4 0 0 0 0 3 USBADDR 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit Name Function S/W R/W H/W R Note 3.1.5 *1) 15-11 Nothing is placed here. These should be fixed at "0". 10-8 STSRECOV Status recovery after the low-power sleep state Status recovery 000: reserved 001: Full-Speed Default state 010: Full-Speed Address state 011: Full-Speed Configured state 100: reserved 101: Hi-Speed Default state 110: Hi-Speed Address state 111: Hi-Speed Configured state 7 Nothing is placed here. This should be fixed at "0". 6-0 USBADDR USB address confirmation and recovery USB address R/W R/W 3.1.5 *1) Note *1) When a recovery has been made from the low-power sleep state to the normal mode, the communication speed, device state and USB address have to be returned to the values backed up bysoftware. "STSRECOV=x00" should not be set. 2.12 USB request register The USB request register is used to store setup requests for control transfers. The values of USB requests that have been received are stored here. USB request type register [USBREQ] 15 0 0 0 0 14 0 0 0 0 13 0 0 0 0 12 11 Brequest 0 0 0 0 0 0 0 0 10 0 0 0 0 9 0 0 0 0 8 0 0 0 0 7 0 0 0 0 6 0 0 0 0 5 0 0 0 0 4 3 bmRequestType 0 0 0 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit 15-8 bRequest Request 7-0 bmRequestType Request type Note None in particular Name Function The USB request bRequest value is stored here. The USB request bmRequestType is stored here. S/W R R H/W W W Note 3.6.1 3.6.1 Rev1.00 2004.10.01 page 39 of 125 M66592FP/WG USB request value register [USBVAL] 15 0 0 0 0 14 0 0 0 0 13 0 0 0 0 12 0 0 0 0 11 0 0 0 0 10 0 0 0 0 9 0 0 0 0 8 wValue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit 15-0 wValue Value Note None in particular Name Function The USB request wValue value is stored here. S/W R H/W W Note 3.6.1 USB request index register [USBINDX] 15 0 0 0 0 14 0 0 0 0 13 0 0 0 0 12 0 0 0 0 11 0 0 0 0 10 0 0 0 0 9 0 0 0 0 8 7 Windex 0 0 0 0 0 0 0 0 6 0 0 0 0 5 0 0 0 0 4 0 0 0 0 3 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit 15-0 wIndex Index Note None in particular Name Function The USB request wIndex value is stored here. S/W R H/W W Note 3.6.1 USB request length register [USBLENG] 15 0 0 0 0 14 0 0 0 0 13 0 0 0 0 12 0 0 0 0 11 0 0 0 0 10 0 0 0 0 9 0 0 0 0 8 7 wLength 0 0 0 0 0 0 0 0 6 0 0 0 0 5 0 0 0 0 4 0 0 0 0 3 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit 15-0 wLength Length Note None in particular Name Function The USB request wLength value is stored here. S/W R H/W W Note 3.6.1 Rev1.00 2004.10.01 page 40 of 125 M66592FP/WG 2.13 DCP configuration When data communication is being carried out using control transfers, the default control pipe should be used. DCP configuration register [DCPCFG] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 CNTMD 0 0 0 7 ? ? ? ? 6 ? ? ? ? 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 ? ? ? ? 1 ? ? ? ? 0 ? ? ? ? Bit Name Function S/W R/W H/W R Note 3.4.1 *1) 15-9 Nothing is placed here. These should be fixed at "0". 8 CNTMD 0: Non-continuous transfer mode Continuous transfer mode 1: Continuous transfer mode 7-0 Nothing is placed here. These should be fixed at "0". Note *1) Because the DCP buffer memory is used for both control read transfers and control write transfers, the CNTMD bit will serve as the bit common to both, regardless of the transfer direction. DCP maximum packet size register [DCPMAXP] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 ? ? ? ? 6 1 1 1 5 0 0 0 4 0 0 0 3 MXPS 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function S/W R/W H/W R Note 3.3.3 *2) 15-7 Nothing is placed here. These should be fixed at "0". 6-0 MXPS This specifies the maximum packet size for the Maximum packet size DCP. Note *2) This should not be set to anything other than the USB specification. Also, because b2-b0 are fixed at "0", writing to these is invalid. Rev1.00 2004.10.01 page 41 of 125 M66592FP/WG DCP control register [DCPCTR] 15 BSTS 0 0 0 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 7 6 SQCLR SQSET SQMON 1 0 0 1 0 0 1 0 0 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 CCPL 0 0 0 0 1 PID 0 0 0 0 0 0 0 0 0 Bit Name Function S/W R H/W W Note 3.4.1 *3) 3.3.6 *3), *5), *6) 3.3.6 *3), *5), *6) 3.3.6 *3), *5), *7) 15 BSTS 0: Buffer access is disabled. Buffer Status 1: Buffer access is enabled. 14-9 Nothing is placed here. These should be fixed at "0". 8 SQCLR 0: Invalid Toggle Bit Clear 1: Specifies DATA0 7 SQSET Toggle Bit Set SQMON Toggle Bit Confirm 0: Invalid 1: Specifies DATA1 0: DATA0 1: DATA1 R(0)/ W(1) R(0)/ W(1) R R R 6 W 5-3 Nothing is placed here. These should be fixed at "0". 2 CCPL 0: Invalid Control Transfer End enabled 1: The control transfer is ended. 1-0 PID 00: NAK response Response PID 01: BUF response (in keeping with the buffer state) 10: STALL response 11: STALL response R(0)/ R/W(0) 3.6 W(1) *4) R/W R/W 3.3.4 *8) Notes *3) The direction of buffer access, writing or reading, is depend on setting of ISEL bit. For detailed information, please refer to Chapter 3. *4) The CCPL bit is cleared to "0" right after the SETUP token has been received. *5) If the SQSET bits and the SQCLR bits of the DCPCTR register and the PIPExCTR registers are being changed in succession (the PID sequence toggle bits of multiple pipes are being changed in succession), an access cycle of at least 200 ns is required. *6) The SQCLR bit and SQSET bit should not both be set to "1" at the same time. Before operating either bit, "PID=NAK" should be set. *7) The SQMON bit is initialized to "1" by the controller right after the SETUP token of the control transfer has been received. *8) The PID bit is cleared to "00" right after the SETUP token has been received. Rev1.00 2004.10.01 page 42 of 125 M66592FP/WG 2.14 Pipe configuration register The PIPE1-7 settings should be set using the PIPESEL, PIPECFG, PIPEBUF, PIPEMAXP, PIPEPERI, and PIPExCTR registers. After selecting the pipe using the PIPESEL register, set the functions of the pipe using the PIPECFG, PIPEBUF, PIPEMAXP, and PIPEPERI registers. The PIPExCTR register can be set separately from the pipe selection specified with the PIPESEL register, with no relation between them. For an H/W reset, S/W reset, USB bus reset, and when shifting to the low-power sleep state, the pertinent bits for not only the selected pipe, but all of the pipes are initialized. Pipe window selection register [PIPESEL] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 ? ? ? ? 6 ? ? ? ? 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 0 0 0 1 PIPESEL 0 0 0 0 0 0 0 Bit Name Function S/W R/W H/W R Note 3.3 *1) 15-3 Nothing is placed here. These should be fixed at "0". 2-0 PIPESEL 000: Not selected Pipe window selection 001: Pipe 1 010: Pipe 2 011: Pipe 3 100: Pipe 4 101: Pipe 5 110: Pipe 6 111: Pipe 7 Note *1) When"PIPESEL=000"is set, "0" is read from all of the bits of the five related registers noted above. Rev1.00 2004.10.01 page 43 of 125 M66592FP/WG Pipe configuration register [PIPECFG] 15 TYPE 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? 14 13 12 11 10 BFRE 0 0 0 9 8 7 DBLB CNTMD SHTNAK 0 0 0 0 0 0 0 0 0 6 ? ? ? ? 5 ? ? ? ? 4 DIR 0 0 0 3 0 0 0 2 1 EPNUM 0 0 0 0 0 0 0 0 0 0 Bit 15-14 TYPE Transfer type Name Function 00: Pipe use disabled 01: Bulk transfer 10: Interrupt transfer 11: Isochronous transfer S/W R/W H/W R Note 3.3.1 *2) 13-11 Nothing is placed here. These should be fixed at "0". 10 BFRE 0: BRDY interrupt upon sending or receiving of BRDY interrupt operation specified data 1: BRDY interrupt upon reading of data 9 DBLB 0: Single buffer Double buffer mode 1: Double buffer 8 CNTMD 0: Non-continuous transfer mode Continuous transfer mode 1: Continuous transfer mode 7 SHTNAK 0: Pipe continued at end of transfer Pipe disabled at end of transfer 1: Pipe disabled at end of transfer 6-5 Nothing is placed here. These should be fixed at "0". 4 DIR 0: Receiving (OUT transfer) Transfer direction 1: Sending (IN transfer) 3-0 EPNUM Specifies the end point number for the pertinent End point number pipe R/W R/W R/W R/W R R R R 3.2.2 *3) 3.4.1 *4) 3.4.1 *5) 3.3.7 R/W R/W R R 3.4.1 3.3.2 Notes *2) The valid value for the TYPE bit depends on the setting for the PIPESEL bit of the PIPESEL register. For detailed information, please refer to 3.3.1. *3) If "BFRE=1" is set, BRDY interrupts are not generated when the buffer is set to the data writing direction. *4) The DBLB bit is valid when PIPE1-5 are selected. The procedure to change the DBLB bit for a PIPE is as following; (a) Single buffer to double buffer ("DBLB=0" to "DBLB="1"); Set the PID bit to "NAK" for the pertinent pipe "ACLRM=1" (wait at least 100ns) "ACLRM=0" "DBLB="1" Set the PID bit to "BUF" for the pipe (b) Double buffer to singlee buffer ("DBLB=1" to "DBLB="0"); Set the PID bit to "NAK" for the pertinent pipe "DBLB="0" "ACLRM=1" (wait at least 100ns) "ACLRM=0" Set the PID bit to "BUF" for the pipe *5) The CNTMD bit is valid when bulk transfer ("TYPE=01") is selected using PIPE1-5. "CNTMD=1" should not be set when isochronous transfer has been selected ("TYPE=11"). The CNTMD bit should not be set "1" for PIPE6-7. Rev1.00 2004.10.01 page 44 of 125 M66592FP/WG Pipe buffer setting register [PIPEBUF] 15 ? ? ? ? 14 0 0 0 13 0 0 0 12 BUFSIZE 0 0 0 11 0 0 0 10 0 0 0 9 ? ? ? ? 8 ? ? ? ? 7 0 0 0 6 0 0 0 5 0 0 0 4 3 BUFNMB 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function S/W R/W H/W R Note 3.4 *6) 3.4 *7) 15 Nothing is placed here. This should be fixed at "0". 14-10 BUFSIZE Specifies the size of the pertinent pipe. Buffer Size (from 0: 64 bytes to 0x1F: 2KB) 9-8 Nothing is placed here. These should be fixed at "0". 7-0 BUFNMB Specifies the buffer number for the pertinent Buffer Number pipe. (From 0x4 to 0x4F) R/W R Notes *6) The valid value for the BUFSIZE bit depends on the selected PIPE by the PIPESEL bit of the PIPESEL register. When using PIPE1-5, any value from 0 to 0x1F is valid. When using PIPE6-7, writing to this bit is invalid. *7) The BUFNMB bit can be set to match the user system when PIPE1-5 are selected. "BUFNMB=0-3" is used exclusively for the DCP. "BUFNMB=4-5" is allocated to PIPE6-7. When using PIPE6, writing to this bit is invalid, and "BUFNMB=4" is always used for reading. When using PIPE7, writing to this bit is invalid, and "BUFNMB=5" is always used for reading. Rev1.00 2004.10.01 page 45 of 125 M66592FP/WG Pipe maximum packet size register [PIPEMAXP] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 0 0 0 9 0 0 0 8 0 0 0 7 0 0 0 5 MXPS 0 0(1) *9) 0 0(1) 0 0(1) 6 4 0 0 0 3 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 Bit Name Function S/W R/W H/W R Note 3.3.3 *8), *9) 15-11 Nothing is placed here. These should be fixed at "0". 10-0 MXPS Specifies the maximum packet size for the Maximum Packet Size pertinent pipe. Note *8) The MXPS bit should be set to"0x00", or the setting defined by the USB specification should be used. *9) The default value of MXPS bit is "0x0" when "PIPSEL=0", and "0x40" when "PIPESEL>0". Pipe timing control register [PIPEPERI] 15 ? ? ? ? 14 ? ? ? ? 13 ? ? ? ? 12 IFIS 0 0 0 11 ? ? ? ? 10 ? ? ? ? 9 ? ? ? ? 8 ? ? ? ? 7 ? ? ? ? 6 ? ? ? ? 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 0 0 0 1 IITV 0 0 0 0 0 0 0 Bit Name Function S/W R/W H/W R Note 3.9.5 15-13 Nothing is placed here. These should be fixed at "0". 12 IFIS 0: The buffer is not flushed. Isochronous IN buffer flush 1: The buffer is flushed. 11-3 Nothing is placed here. These should be fixed at "0". 2-0 IITV Specifies the interval timing as IITV-th power of Interval error detection spacing 2. R/W R 3.9 *10) Note *10) The IITV bit is valid only when isochronous transfer is selected. In other words, it can be set only when PIPE1-2 are selected. For OUT-direction: An interval error occurs upon a NRDY interrupt caused by a token not having been issued. For IN-direction: When the controller doesn't receive IN-token until the time indicated by IITV bit, it detects an interval error and flushs the buffer. Rev1.00 2004.10.01 page 46 of 125 M66592FP/WG PIPE1 control register [PIPE1CTR] PIPE2 control register [PIPE2CTR] PIPE3 control register [PIPE3CTR] PIPE4 control register [PIPE4CTR] PIPE5 control register [PIPE5CTR] PIPE6 control register [PIPE6CTR] PIPE7 control register [PIPE7CTR] 15 14 BSTS INBUFM 0 0 0 0 0 0 13 ? ? ? ? 12 ? ? ? ? 11 ? ? ? ? 10 ? ? ? ? 9 8 7 6 ACLRM SQCLR SQSET SQMON 0 0 0 0 0 0 0 0 0 0 0 0 5 ? ? ? ? 4 ? ? ? ? 3 ? ? ? ? 2 ? ? ? ? 1 PID 0 0 0 0 0 0 0 0 0 Bit Name Function S/W R R H/W W W Note 3.4.1 *11) *12), *13) 15 BSTS 0: Buffer access is disabled. Buffer Status 1: Buffer access is enabled. 14 INBUFM 0: No data in IN-direction buffer IN buffer monitor 1: There is sending data in IN-direction buffer 13-10 Nothing is placed here. These should be fixed at "0". 0: Disabled 9 ACLRM Auto Buffer Clear mode 1: Enabled (all buffers are initialized) 8 SQCLR 0: Invalid Toggle Bit Clear 1: Specifies DATA0 7 SQSET Toggle Bit Set 0: Invalid 1: Specifies DATA1 SQMON 0: DATA0 Toggle Bit Confirm 1: DATA1 5-2 Nothing is placed here. These should be fixed at "0". 1-0 PID 00: NAK response Response PID 01: BUF response (in keeping with the buffer state) 10: STALL response 11: STALL response 6 R(0)/W( R/W(0) 3.4.1 1) *14) R(0)/W( R 3.3.6 1) *15), *16) R(0)/W( R 3.3.6 1) *15), *16) R W 3.3.6 *15) R/W R/W 3.3.4 *16), *17) Notes *11) The direction of buffer access, writing or reading, is depend on setting of the DIR bit of the PIPECFG register. For detailed information, please refer to Chapter 3. *12) The INBUFM bit is valid when softwware sets the DIR bit to Sending-direction. *13) The INBUFM bit is valid for PIPE1-5. *14) Software should not set "ACLRM=1" for the PIPE whith selected by the PIPESEL bit of the PIPESEL register. *15) If the SQCLR bits and the SQSET bits of the DCPCTR register and the PIPExCTR registers are being used to change the data PID sequence toggle bit for several pipes in succession, an access cycle of at least 200 ns is required. *16) The SQCLR bit and SQSET bit should not both be set to "1" at the same time. Before operating either bit, "PID=NAK" should be set. *17) If an excessive packet size error is detected, "PID=STALL" is set by the controller. Rev1.00 2004.10.01 page 47 of 125 M66592FP/WG 3 Description of Operation 3.1 System control and oscillation control This chapter describes the register operations that are necessary to the default settings of the controller, and the registers necessary for power consumption control. 3.1.1 Resets Table 3.1 shows a table of controller resets. For information on the initialized states of the registers following the various reset operations, please refer to Chapter 2, Registers. Table 3.1 Types of resets Name H/W reset S/W reset USB bus reset Operation "L" level input from the RST_N pin Operation using the USBE bit of the SYSCFG register Automatically detected by the controller from the D+ and D- lines 3.1.2 Bus interface settings Table 3.2 shows the bus interface settings for the controller. Table 3.2 Bus interface settings Register name PINCFG PINCFG DMAxCFG DMAxCFG DMAxCFG DMAxCFG INTENB1 Bit name LDRV BIGEND DREQA DACKA DENDA OBUS INTL Setting contents Control setting for the drive current Byte Endian setting for the CPU being connected Active setting for the DREQ_N pin Active setting for the DACK_N pin Active setting for the DEND_N pin OBUS mode setting Output sensing setting for the INT_N pin 3.1.3 Enabling Hi-Speed operation With this controller, either Hi-Speed operation or Full-Speed operation can be selected as the USB communication speed (communication bit rate), using software. To enable Hi-Speed operation for the controller, set the HSE bit of the SYSCFG register to "1". Changing the HSE bit should be done with the internal clock stopped ("SCKE=0"). If Hi-Speed operation has been enabled, the controller executes the reset handshake protocol, and the USB communication speed is set automatically. The results of the reset handshake can be confirmed using the RHST bit of the DVSTCTR register. If Hi-Speed operation has been disabled, the controller will use Full-Speed operation. Rev1.00 2004.10.01 page 48 of 125 M66592FP/WG 3.1.4 USB data bus resistor control Figure 3.1 shows a diagram of the connections between the controller and the USB connectors. The controller has a built-in pull-up resistor for the D+ signal. "1" should be set for the DPRPU bit of the SYSCFG register, then the D+ line is pulled up. The pull-up power supply is AFE33V. Also, the controller has a built-in terminal resistor for use when the D+ and D- signals are operating at Hi-Speed, and a built-in output resistor for Full-Speed operation. The controller automatically switches the built-in resistor after connection with the PC, by means of reset handshake, suspended state and resume detection. If a disconnection from the PC is detected, the H/W should be initialized by means of an S/W reset (USBE=0). If "0" is set for the DPRPU bit of the SYSCFG register, the pull-up resistor (or the terminal resistor) of the USB data line is disabled, making it possible to notify the host controller of the device disconnection. The capacitance of 1 to 10 F stipulated by the USB specification is necessary for the VBUS signal. Impedance control has to be taken into consideration when designing the D+ and D- lines. M66592FP/WG VBUS 1~10F DM DP RERFIN 5.6K 1 2 3 4 Vbus DD+ GND USB connector Figure 3.1 UBS connector connections 3.1.5 Clock supply control Figure 3.2 shows a block diagram of the controller clock control. Frequency of the input clock for the XIN pin should be selected using the XTAL bit of the SYSCFG register, while the oscillation buffer is enabled using the XCKE bit and the clock supply is controlled using the RCKE, PLLC, and SCKE bits. For information on the register control timing, please refer to 3.1.7, State transition timing. Clock control unit XCKE (bit13) RCKE (bit12) PLLC, SCKE (bit11, bit10) Input clock Oscillation buffer Low-power control Divider circuit Auto clock supply PLL Internal clock PCUT (bit1) ATCKM (bit8) Figure 3.2 Clock control block Rev1.00 2004.10.01 page 49 of 125 M66592FP/WG 3.1.6 Low power consumption control 3.1.6.1 Overview of low-power sleep state In order to reduce power consumption, the controller is equipped with a function for setting a low-power sleep state. Controlling the clock and the low-power sleep state enables reduced power consumption when communication is not being carried out, such as in the suspended state or disconnected state. In order to coordinate the relationship between the controller clock supply being enabled and disabled in low-power sleep state, the values shown in Table 3.3 indicate the correspondence between the controller state and the value of the SYSCFG register, while Figure 3.3 shows the transitions in the controller state. For the timing at which the transitions between the various states take place, and the register control timing, please refer to 3.1.7. Table 3.3 Correspondence between the controller state and SYSCFG register value Controller state H/W reset Normal operating state Low-power sleep state Values of the various SYSCFG register bits XTAL=0, XCKE=0, RCKE=0, PLLC=0, SCKE=0, ATCKM=0, HSE=0, DPRPU=0, PCUT=0, USBE=0 XTAL=xx *1), XCKE=1, RCKE=1, PLLC=x*1), SCKE=1, ATCKM=x*1), HSE=x*1), DPRPU=x*1), PCUT=0, USBE=1 XTAL=xx *1), XCKE=0, RCKE=0, PLLC=0, SCKE=0, ATCKM=x *1), HSE= x *1), DPRPU=x *1), PCUT=1, USBE=1 Explanation In this state, the clock is supplied to the controller, and USB communication is enabled. In this state, USB communication is not carried out, such as when communication is suspended or a cable is disconnected. *1) x indicates that the value is set by the user is retained. H/W reset Default setting Attached Normal operating state Resume, attached Figure 3.3 Controller state transitions (using low-power sleep state) Suspended, detached Low-power sleep Rev1.00 2004.10.01 page 50 of 125 M66592FP/WG 3.1.6.2 Overvew of Clock stop state This controller is equipped with the setting function of the low power consumption state by clock stop as well as M66291, M66591, and M66592. Software is transplantable for this controller from M66291, M66591, and M66592 by fewer changes. In the states where the controller is not communicating such as suspend and a not connect state, low power consumption by clock stop is realized. Correspondence of the state of the controller and the value of a SYSCFG register is shown in Table 3.4. The transitions in the controller state is shown inFigure 3.4. For the timing at which the transitions between the various states take place, and the register control timing, please refer to 3.1.7. Moreover, when you use the low power consumption state by clock stop, please use the auto clock supply function ("ATCKM=1"). Table 3.4 Correspondence between the controller state and SYSCFG register value Controller state H/W reset Normal operating state Clock stop state Values of the various SYSCFG register bits XTAL=0, XCKE=0, RCKE=0, PLLC=0, SCKE=0, ATKCM=0, HSE=0, DPRPU=0, PCUT=0, USBE=0 XTAL=xx *1), XCKE=1, RCKE=1, PLLC=x *1), SCKE=1, ATKCM=x *1), HSE=x *1), DPRPU=x *1), PCUT=0, USBE=1 XTAL=xx *1), XCKE=0, RCKE=0, PLLC=0, SCKE=0, ATCKM=1, HSE= x *1), DPRPU=x *1), PCUT=0, USBE=1 Explanation In this state, the clock is supplied to the controller, and USB communication is enabled. In this state, USB communication is not carried out, such as when communication is suspended or a cable is disconnected. *1) x indicates that the value is set by the user is retained. H/W reset Default setting Attached Normal operating state Resume, attached Figure 3.4 Controller state transitions (using clock stop state) Suspended, detached Clock stop Rev1.00 2004.10.01 page 51 of 125 M66592FP/WG 3.1.6.3 Low-power sleep state The low-power sleep state is set by setting "1" for the PCUT bit of the SYSCFG register. For information on the sequence in which settings are entered for the low-power sleep state, please refer to 3.1.7.2, and for information on register control timing, please refer to the timing diagram noted later (Figure 3.6 Transition control timing). In the low-power sleep state, of the registers set bysoftware, only registers other than those noted below are initialized. After returning to the normal operating state, the settings must be re-entered usingsoftware. Table 3.5 shows the registers that are not initialized when the controller is in the low-power sleep state. Table 3.5 Registers that are not initialized in the low-power sleep state Register SYSCFG Bit XTAL ATCKM HSE DPRPU USBE LDRV DREQA VBSE / VBINT RSME / RESM Description This is retained as system information. This is retained as system information. This is retained as system information. This is retained as system information. This is retained as system information. The state of the output pins drive current settings is retained. The polarity of the DREQ0_N pin and the DREQ1_N pin are retained. When "VBSE=1", if there was any change to the VBUS signal in the low-power sleep state, the INT_N pin is asserted and notification is made to the CPU. When "RSME=1", if there was any change to the USB data bus in the low-power sleep state, the INT_N pin is asserted and notification is made to the CPU. PINCFG DMAxCFG INTENB0/ INTSTS0 3.1.6.4 Recovering from the low-power sleep state If any of the events noted below occurs from the low-power sleep state, the controller notifies the CPU through the INT_N pin. The interrupt factor related to those events should be enabled, before sofware sets the controller to the low-power sleep state. (1) VBUS detection : If a change in the VBUS pin was detected in the low-power sleep state (2) RESUME detection : If a change in the state of the USB bus (J-State to K-State or SE0) was detected when the state shifted to the low-power sleep state during the suspended state. When the PCSE bit of INTENB1 register is set to "0", the low-power sleep state is also canceled by the operations noted below, and the controller returns to the normal operating state. (1) Dummy writing to the 0x7E address of the controller (no actual writing is done to this address). When the system has returned from the low-power sleep state to the normal state, some of the controller registers need to be returned to the values in effect prior to the transition to the low-power sleep state. Of the registers for which the settings have to be returned, special registers are available that are used for re-setting data in the read-only registers. Table 3.6 shows the re-settings for the read-only registers for which the settings have to be returned. Table 3.6 Re-settings for read-only registers for which settings have to be returned Method for re-setting registers Setting the USB communication speed and device state using the STSRECOV bit of the RECOVER register before shifting to the low-power sleep state recovers the values for the RHST bit and DVSQ bit. RECOVER USBADDR The USB device address prior to the shift to the low-power sleep state is set in the USBADDR bit of the RECOVER register. PIPExCTR SQMON The sequence toggle bits for the various pipes prior to the low-power sleep state are set using the SQSET bit or the SQCLR bit of PIPExCTR. *1) *1) The SQMON bit of the DCPCTR register is initialized when the SETUP stage ends, so it is not necessary to return to the state in effect prior to the normal operating state. RHST DVSQ Register DVSTCTR INTSTS0 Bit Rev1.00 2004.10.01 page 52 of 125 M66592FP/WG 3.1.6.5 Recovering from the clock stop state If any of the events noted below occurs from the clock stop state, the controller notifies the CPU through the INT_N pin. The interrupt factor related to those events should be enabled, before sofware sets the controller to the low-power sleep state. (1) VBUS detection : If a change in the VBUS pin was detected in the clock stop state (2) RESUME detection : If a change in the state of the USB bus (J-State to K-State or SE0) was detected when the state shifted to the low-power sleep state during the suspended state. 3.1.6.6 Auto clock supply function This controller is equipped with an auto clock supply function. With the auto clock supply function, the controller automatically implements a series of sequence control operations, from the oscillation stabilization standby timing to the supply of the internal clock, when the system is returning from the low-power sleep state or from the clock stop mode to the normal operating state. This function is enbaled by setting "1" for the ATCKM bit of the SYSCFG register. For information on specific register control, please refer to3.1.7.3. Rev1.00 2004.10.01 page 53 of 125 M66592FP/WG 3.1.7 State transition timing 3.1.7.1 Starting the internal clock supply (from the H/W reset state to the normal operating state) Figure 3.5 shows a diagram of the clock supply start control timing of the controller. The transition from the H/W reset state to the normal operating state should be done through operation of the bits at the timing noted below. (1) Software enables the oscillation buffer. "XCKE=1" (2) Software waits for oscillation to stabilize. (The oscillation stabilization time varies depending on the oscillator.) (3) Software enables the reference clock suppliance "RCKE=1", "PLLC=1" and the PLL operation (4) Software waits for the PLL to lock. (A waiting time of at least 8.3 us is necessary.) (5) Software enables the internal clock suppliance. "SCKE=1" Start of internal clock supply procedure XCKE RCKE PLLC SCKE PCUT (1) (2) Approximately 1.5 ms (varies depending on oscillation probe) (3) (4) min 8.3us (5) Figure 3.5 Clock supply start control timing 3.1.7.2 Stopping the internal clock supply (from the normal operating state to the low-power sleep state) Figure 3.6 shows a diagram of the low-power control timing from the normal operating state to the low-power sleep state. The transition from the normal operating state to the low-power sleep state should be done through operation of the bits at the timing noted below. (1) Software disables the internal clock suppliance. "SCKE=0" (2) Software waits until the internal clock stops. (A waiting time of at least 300 ns is necessary.) (3) Software disables the PLL. "PLLC=0" (4) Software waits for the PLL to stop. (A waiting time of at least 300 ns is necessary.) (5) Software disables reference clock suppliance. "RCKE=0" (6) Software waits until the reference clock stops. (A waiting time of at least 300 ns is necessary.) (7) Software sets the bit for low-power sleep state. "PCUT=1" (8) The controller disables the oscillation buffer. "XCKE=0(H/W)" *1) *1) Software must not set the XCKE bit to "0". Start of transit to (1) the low power state XCKE(H/W) RCKE PLLC SCKE PCUT (3) (2) min 300ns (4) min 300ns (5) (6) min 300ns (7) (8) Figure 3.6 Transition control timing to the low-power sleep state Rev1.00 2004.10.01 page 54 of 125 M66592FP/WG 3.1.7.3 Starting the internal clock supply (from the low-power sleep state to the normal operating state) Figure 3.7 shows a diagram of the timing at which the transition from the low-power sleep state to the normal operating state takes place when the auto clock supply function is enabled ("ATCKM=1"). When the auto clock supply function is enabled, the controller carries out register control, so after an interrupt is generated, the transition to the normal operating state is completed simply by waiting for the amount of time that access is disabled. No operation of the registers using software is necessary. When operation has been resumed from the suspended state using the USB Bus Reset signal, it is necessary to recover to the normal operating state within 3 ms after the data line change has been detected so that the controller can begin the reset handshake protocol. When the auto clock supply function is enabled, the controller waits automatically for oscillation to stabilize and then carries out clock supply control and handles the reset handshake. Because there is a signal output time of 10 ms for the USB Bus Reset signal and of 20 ms for the Resume signal, software is provided with plenty of allowance to process the recovery to the normal state. The recovery sequence when the auto clock supply function is enabled is as shown below. (1) An interrupt is generated to recover from the low-power sleep state, and the INT_N pin is asserted. *1) (Or, the control program writes dummy data to the 0x7E address to cause the controller to recover.) (2) At the same time, the controller automatically enables. "XCKE=1(H/W)" the oscillation buffer (3) Software waits until access is enabled. (A waiting time of at least 2.5 ms is necessary.) (4) The controller automatically enables RCKE, PLLC, and SCKE. (5) Software resets the registers that have been in the held state before going into the low-power sleep state. *2) *1) When the system has recovered from the low-power sleep state to the normal operating state, the USB communication speed and the device state recovery settings have to be set in the STSRECOV bit of the RECOVER register, and the USB address in the USBADDR bit of that register, for recovery to take place. *2) If the auto clock supply function has been enabled, however, the recovery settings for the above bits should be entered after the DVSQ bit has been confirmed. This is because, if recovery has been made using the USB Bus Reset signal, there is a possibility that the controller has initialized the device state and the USB address to the default state, in which case rewriting the register values to the waiting state will cause erroneous operation. The recovery settings are written to the RECOVER register using the procedure outlined below. (a) If "DVSQ=000", recovery is made by a method other than the USB Bus Reset signal. The USB communication speed, device state, and USB address should be returned to the state they were in prior to shifting to the low-power sleep state, by writing to the RECOVER register. (b) If "DVSQ=001", recovery is made using the USB Bus Reset signal. In this case, software should not restore backup value to the RECOVER register. Also, in the low-power sleep state, there are registers that are initialized by the controller. When recovery has been made to the normal operating state, the initialized registers should be reset to match the user system. Low-power sleep state recovery (1),(2) (3) 2.5ms (access disabled) (4) (5) XCKE(H/W) RCKE(H/W) PLLC(H/W) SCKE(H/W) PCUT(H/W) INT_N Event CS_N Rev1.00 2004.10.01 page 55 of 125 M66592FP/WG Figure 3.7 Recovery control timing from the low power sleep state with "ATCKM=1" Rev1.00 2004.10.01 page 56 of 125 M66592FP/WG 3.1.7.4 Stopping the internal clock supply (from the normal operating state to the clock stop state) The timing diagram of the transition from the normal operating state to the clock stop state is shown in Figure 3.8. The transition should be operated according to the following sequence. (1) Software disables the internal clock suppliance. "SCKE=0" (2) Software waits until the internal clock stops. (A waiting time of at least 300 ns is necessary.) (3) Software disables the PLL. "PLLC=0" (4) Software waits for the PLL to stop. (A waiting time of at least 300 ns is necessary.) (5) Software disables reference clock suppliance. "RCKE=0" (6) Software waits until the reference clock stops. (A waiting time of at least 300 ns is necessary.) (7) Software disables the oscillation buffer. "XCKE=0" Start of transit to (1) the clock stop state XCKE RCKE PLLC SCKE (3) (2) min 300ns (4) min 300ns (5) (6) min 300ns (7) Figure 3.8 Transition control timing to the clock stop state 3.1.7.5 Starting the internal clock supply (from the clock stop state to the normal operating state : with "ATCKM=1") The timing diagram from the clock stop state to the normal operation state is shown in Figure 3.9. The diagram is in the case of the auto clock supply function is enabled ("ATCKM=1"; recommended setting). In this case, the controller operates registers when resume signal is detected. The controller changes to the normal operation state by waiting for access prohibition time after resume interrupt is generated. The register operation by software is not required. If VBUS interrupt is occurs, the softwear need to enable the oscillation, "XCKE=1" (1) The controller detects the resume signal or VBUS changes on a USB bus by detachment the cable, and the INT_N pin is asserted. (2) When resume signal is received, the controller automatically enables the oscillation buffer. When VBUS change occurs, softwear needs to enable the oscillation buffer. (3) Software waits until access is enabled. (4) The controller automatically enables RCKE, PLLC, and SCKE during (3). (5) Software operates the process depending on the interrupt factor, resume or attachment. "XCKE=1(H/W)" "XCKE=1" (A waiting time of at least 2.5 ms is necessary.) Rev1.00 2004.10.01 page 57 of 125 M66592FP/WG Clock stop recovery (1),(2) (3) 2.5ms (access disabled) (4) (5) XCKE(H/W) RCKE(H/W) PLLC(H/W) SCKE(H/W) INT_N Event Figure 3.9 Recovery control timing from the clock stop state with "ATCKM=1" Rev1.00 2004.10.01 page 58 of 125 M66592FP/WG 3.1.7.6 Starting the internal clock supply (from the clock stop state to the normal operating state : with "ATCKM=0") The timing diagram from the clock stop state to the normal operation state is shown in Figure 3.10. The diagram is in the case of the auto clock supply function is disabled ("ATCKM=0"). When the auto clock supply function is disabled, register control is performed by software. Software should operate registers according to the following sequence. . (1) The controller detects the resume on a USB bus or attachment of the USB cable, and the INT_N pin is asserted (2) At the same time, the controller automatically enables. "XCKE=1(H/W)" the oscillation buffer (3) Software waits for oscillation to stabilize.*1) (The oscillation stabilization time varies depending on the oscillator.) (4) Software enables the reference clock suppliance "RCKE=1", "PLLC=1" and the PLL operation (5) Software waits for the PLL to lock. (A waiting time of at least 8.3 us is necessary.) (6) Software enables the internal clock suppliance. "SCKE=1" (7) Software performs processing depending on the interrupt factor, resume or attachment. *1) When it returns with a USB bus reset signal from the suspend state, it is necessary to return to the normal operation state less than 3ms and the controller start a reset handshake protocol. For this reason, when an auto clock supply function is disabled, it is necessary to perform a processings to oscillation stability waiting and clock supply by software within 3ms. Clock stop recovery (1),(2) (3) (4) (5) min 8.3us (6) XCKE(H/W) RCKE(H/W) PLLC(H/W) SCKE(H/W) INT_N Event Figure 3.10 Recovery control timing from the clock stop stete with "ATCKM=0" Rev1.00 2004.10.01 page 59 of 125 M66592FP/WG Rev1.00 2004.10.01 page 60 of 125 M66592FP/WG 3.2 Interrupt functions 3.2.1 An overview of interrupt functions Table 3.7 shows the interrupt functions of the controller. Table 3.7 Interrupt functions Bit VBINT RESM SOFR Interrupt name VBUS interrupt Resume interrupt Frame No. Refresh interrupt Device State Transition interrupt Control Transfer Stage Transition interrupt Cause of interrupt When a change in the state of the VBUS input pin has been detected (change in bothedge, "L""H", "H" "L") When a change in the state of the USB bus has been detected in the suspended state (J-StateK-State or J-StateSE0) When "SOFRM=0" : When an SOF packet with a different frame number has been received When "SOFRM=1" : When the controller detects a corruption of an SOF packet When a device state transition has been detected USB bus reset detected Suspend state detected Set Address request received Set Configuration request received When a stage transition has been detected in a control transmission Setup stage completed Control write transfer status stage transition Control read transfer status stage transition Control transfer completed Control transfer sequence error occurred When transmission of all of the data in the buffer memory has been completed When an excessive maximum packet size error has been detected When an IN token has been received and there is no data that can be sent to the buffer memory When an OUT token has been received and there is no area in which data can be stored in the buffer memory, so reception is not possible When a CRC error or bit stuffing error occurred in isochronous transfer When the buffer is ready (reading or writing is enabled) Related status VBSTS Note 3.2.8 3.2.9 3.2.7 DVST DVSQ 3.2.5 CTRT CTSQ 3.2.6 BEMP Buffer Empty interrupt Buffer Not Ready interrupt PIPEBEMP 3.2.4 NRDY PIPENRDY 3.2.3 BRDY Buffer Ready interrupt PIPEBRDY 3.2.2 Rev1.00 2004.10.01 page 61 of 125 M66592FP/WG Table 3.8 shows the INT_N pin operations of the controller. If multiple interrupt causes have occurred, the method used for INT_N pin output can be set using the INTL bit of the INTENB1 register. The operation setting for the INT_N pin should be set to match the user system. Table 3.8 INT_N pin operations INT_N pin operation INTL setting Edge sensing ("INTL=0") Level sensing ("INTL=1") When one interrupt cause occurred When multiple interrupt causes occurred "L" level output until the cause has been eliminated "L" level output until the cause has been eliminated When one cause is eliminated, the 32 clock time is negated ("H" pulse output) at 48 MHz. "L" level is output until all of the causes have been eliminated. Cause 1 occurs Cause 2 occurs Cause 1 cleared Cause 2 cleared Interrupt cause 1 Interrupt cause 2 INT_N pin Negated interval Cause 1 occurs Cause 2 occurs Cause 1 cleared Cause 2 cleared Interrupt cause 1 Interrupt cause 2 INT_N pin Figure 3.11 INT_N pin operation Rev1.00 2004.10.01 page 62 of 125 M66592FP/WG Figure 3.12 shows a diagram relating to controller interrupts. INTENB0 URST INTENB0 VBSE INTSTS0 VBINT USB reset detected SADR SCFG SUSP WDST Transition state to Address Configured INT_N Edge / Level Generation Circuit RSME RESM SOFE SOFR DVSE DVST CTRE CTRT BEMPE BEMP NRDYE NRDY BRDYE BRDY Transition to state detected Suspended state detected Completion of Control Data Stage Completion of Control Data Stage Control Transfer End Control Transfer Sequence Error Control Transfer Setup Receive RDST CMPL SERR BEMPENB b7 ... b1 b0 BEMPSTS . . b7 . . . b1 b0 NRDYENB b7 ... b1 b0 NRDYSTS . . b7 . . . b1 b0 BRDYENB b7 ... b1 b0 BRDYSTS b7 . . . . . b1 b0 Figure 3.12 Items relating to interrupts Rev1.00 2004.10.01 page 63 of 125 M66592FP/WG 3.2.2 BRDY interrupt Table 3.9 shows the conditions under which the controller sets "1" to a pertinent bit of the BRDYSTS register. Under above condition, the controller generats BRDY interrupt, if software enables PIPERDYE bit of the BRDYENB register and BRDYE bit of the INTENB0 register. Figure 3.13 shows the timing at which BRDY interrupts are generated. The conditions for elimination the BRDY bit of the INTSTS0 register are depend on the setting of the BRDYM bit of the INTENB1 register. Table 3.10 shows the conditions. Under the conditions noted below, a Zero-Length packet is sent for an IN token, and the BRDY interrupt is not generated. (1) When "0x000" is set in the MXPS bit of the PIPEMAXP register for a pipe, and the transfer type of the pertinent pipe is bulk IN. Table 3.9 Conditions under which a BRDY interrupt is generated Access direction Reading Transfer direction Receive Pipe DCP 1-7 BFRE 0 DBLB 0 0 Conditions under which a BRDY interrupt is generated (1) or (2) bellow; (1) Short packet reception including , Zero-Length packet reception (2) Buffer is full by reception (1) or (2) bellow; (1) Short packet reception including , Zero-Length packet reception (2) Buffer is full by reception (3) Transaction Counter End when buffer is not full (1), (2) or (3) bellow (1) One of (a) to (c) conditions is occur when both buffers are waiting for receiption (a) a short packet reception including a Zero-Length packet reception (b) One buffer of two is full by reception (c) Transaction Counter End when a buffer is not full (2) Reading is complete of a buffer, when both buffer are waiting for reading (3) Software set "BCLR=1" to clear a buffer, when both buffer are waiting for reading (1), (2) or (3) bellow (1) Zero-Length packet reception (2) After a short packet reception, reading data of the packet is complete. (3) After Transaction Counter End reading data of the last packet is complete,. Doesn't take place (1), (2), (3) or (4) bellow; (1) Software set direction of transfer to transmitting (2) Packet transmission is completed (3) Software set "ACLRM=1", when there are data waiting to transmitted (4) Software set "SCLR=1", when there are data waiting to transmitte (1), (2), (3), (4) or (5) bellow; (1) Software set direction of transfer to transmitting (2) Data is enabled to be transmitted, when there are no buffer waiting to be transmitted. (3) Data is enabled to be transmitted,, when there are no buffer waiting to be transmitted. (a) A buffer is full by writing (b) Software set "BVAL=1" to enable the buffer is ready to tarnsmit (c) DMAC asserts DEND signal to make a buffer be ready to transmit (4) Software set "ACLRM=1", when there are data waiting to transmitted (5) Software set "SCLR=1", when there are data waiting to transmitte Doesn't take place 1 1 Don't Care Writing Transmit DCP 1-7 0 0 1-7 0 1 1 Rev1.00 2004.10.01 page 64 of 125 Don't Care M66592FP/WG With PIPE1-PIPE7, if DMA transfer is being carried out in the reading direction, interrupts can be generated in transfer units, by setting the BFRE bit of the PIPECFG register. Also, if a Zero-Length packet has been received, the pertinent bit of the BRDYSTS register goes to "1", but the data of the pertinent packet cannot be read. The buffer should be cleared ("BCLR=1") after clearing the BRDYSTS register. Zero-Length packet reception Data packet reception using BFRE = 0 (Short Packet / Transaction Counter / Buffer Full) USB bus Token Packet Zero-Length Packet / Short Data Packet / Data Packet (Full) (Transaction Count) ACK Handshake BRDY interrupt A BRDY interrupt is generated because reading from the buffer is enabled. Data packet reception using BFRE = 1 (Short Packet / Transaction Counter) USB bus Token Packet Short Data Packet / Data Packet (Transaction Count) ACK Handshake Buffer Read A BRDY interrupt is generated because the transfer has ended. BRDY interrupt Packet transmission USB bus Buffer Write BRDY interrupt A BRDY interrupt is generated because writing to the buffer is enabled. Token Packet Data Packet ACK Handshake Figure 3.13 Timing at which BRDY interrupts are generated Table 3.10 Conditions for elimination of the BRDY bit BRDYM 0 1 Conditions for elimination of the BRDY bit When software clears all enabled bits of the BRDYSTS register, the controller clears the BRDY bit. When the controller clears all BSTS bits which corresponding to BRDY interrupt enebled pipe, the controller clears the BRDY bit. Rev1.00 2004.10.01 page 65 of 125 M66592FP/WG 3.2.3 NRDY interrupt If a pipe is under the conditions such as (1), (2)(a), or (2)(b) bellow, the controller sets "1" to a pertinent bit of the NRDYSTS register. In this case, the controller generats NRDY interrupt, if software enables PIPENRDYE bit of the NRDYENB register and NRDYE bit of the INTENB0 register. When software clears all enabled bits of the NRDYSTS register, the controller clears the NRDY bit. (1) For data transmission If an IN token has been received (data underrun) when the the PID bit of the PIPExCTR register is in the "PID=BUF" and there is no data to be sent in the buffer memory (6) For data is reception (a) If an OUT token or a PING token has been received (data overrun) when the PID bit of the PIPExCTR register is in the "PID=BUF" and there is no area in the buffer memory where data can be stored (b) In a bulk transfer, when the maximum packet size has not been set ("MXPS=0") and an OUT token or a PING token has been received (c) When a CRC error or bit stuffing error has occurred during an isochronous transfer Figure 3.14 shows the timing at which NRDY interrupts are generated. (1) Data transmiton USB bus NRDY interrupt (2) Data reception ; OUT token reception USB bus NRDY interrupt (CRC error, etc.) (3) Data reception ; PING token reception USB bus NRDY interrupt PING Packet NAK Handshake OUT Token Packet Data Packet NAK Handshake IN Token Packet NAK Handshake Figure 3.14 Timing at which NRDY interrupts are generated Rev1.00 2004.10.01 page 66 of 125 M66592FP/WG 3.2.4 BEMP interrupt The table below shows the conditions under which BEMP interrupts are generated. The cause of a BEMP for the various pipes should be confirmed using the pertinent bit of the BEMPSTS register. If an interrupt has been disabled using the BEMPE bit of the INTENB0 register, the interrupt request is set in the pertinent bit of the BEMPSTS register. When all of the bits of the BEMPSTS register are cleared using the user system control program, the controller clears the BEMP bit of the INTSTS0 register. If a pipe is under the conditions such as (1)(a), (1)(b), or (2) bellow, the controller sets "1" to a pertinent bit of the BEMPSTS register. In this case, the controller generats BEMP interrupt, if software enables PIPENBEMPE bit of the BEMPENB register and BEMPE bit of the INTENB0 register. When software clears all enabled bits of the BEMPSTS register, the controller clears the BEMP bit. (1) When the sending direction (writing to the buffer memory) has been set When all of the data stored in the buffer memory has been sent If a double buffer is being used for the buffer memory, however, the following conditions are observed. (a) A BEMP interrupt is generated if the buffer on one side is empty and sending of data from the buffer on the opposite side has been completed. (b) A BEMP interrupt is generated if data consisting of less than eight bytes is being written to the buffer on one side and sending of data from the buffer on the opposite side has been completed. (c) A BEMP interrupt is not generated if data consisting of eight bytes or more is being written to the buffer on one side and sending of data from the buffer on the opposite side has been completed. (2) When the receiving direction (reading of the buffer memory) has been set If the size of the data packet that was received exceeded the maximum packet size At this point, if the other maximum packet size parameters were set to a value other than "0" ("MXPS0"), the controller sets the PID bit of the pertinent pipe to "STALL". Figure 3.15 shows the timing at which BEMP interrupts are generated. (1) Data transmission USB bus BEMP interrupt IN Token Packet Data Packet ACK Handshake (2) data reception USB bus BEMP interrupt OUT Token Packet Data Packet STALL Handshake Figure 3.15 Timing at which BEMP interrupts are generated Rev1.00 2004.10.01 page 67 of 125 M66592FP/WG 3.2.5 Device state transition interrupt Figure 3.16 shows a diagram of the controller device state transitions. The controller controls device states and generates device state transition interrupts. However, recovery from the suspended state (Resume signal detection) is detected by means of the Resume interrupt. The device state transition interrupt can be set when interrupts are enabled or disabled individually, using the INTENB0 register. Also, the device state that underwent a transition can be confirmed using the DVSQ bit of the INTSTS0 register. When making a transition to the default state, the device state transition interrupt is generated after the reset handshake protocol has been completed. Suspended state detection (When SUSP="1", DVST is set to "1") Powered State (DVSQ="000") Suspended State (DVSQ="100") Resume (RESM is set to "1") USB bus reset detection (When URST="1", DVST is set to "1") USB bus reset detection (When URST="1", DVST is set to "1") Suspended state detection (When SUSP="1", DVST is set to "1") Default State (DVSQ="001") Suspended State (DVSQ="101") Resume (RESM is set to "1") SetAddress execution (Address=0) (When URST="1", DVST is set to "1") SetAddress execution (When SADR="1", DVST is set to "1") Suspended state detection (When SUSP="1", DVST is set to "1") Address State (DVSQ="010") Suspended State (DVSQ="110") Resume (RESM is set to "1") SetConfiguration execution (ConfigurationValue=0) (When SADR="1", DVST is set to "1") SetConfiguration execution (ConfigurationValue?0) (When SCFG="1", DVST is set to "1") Suspended state detection (When SUSP="1", DVST is set to "1") Suspended State (DVSQ="111") Configured State (DVSQ="011") Resume (RESM is set to "1") Note: The URST, SADR, SCFG and SUSP bits in parentheses are enable bits that permit if the controller sets the DVST bit to "1" when the pertinent stage transition is detected (These enable bits are on INTENB0 register). Stage transitions are carried out even if setting the DVST bit to "1" is inhibited by these bits. Figure 3.16 Device state transitions Rev1.00 2004.10.01 page 68 of 125 M66592FP/WG 3.2.6 Control transfer stage transition interrupt Figure 3.17 shows a diagram of how the controller handles the control transfer stage transition. The controller controls the control transfer sequence and generates control transfer stage transition interrupts. Control transfer stage transition interrupts can be enabled or disabled individually, using the INTENB0 register. Also, the transfer stage that underwent a transition can be confirmed using the CTSQ bit of the INTSTS0 register. The control transfer sequence errors are noted below. If an error occurs, the PID bit of the DCPCTR register goes to "1X" (STALL). (1) During control read transfers (a) At the IN token of the data stage, an OUT or PING token is received when there have been no data transfers at all (b) An IN token is received at the status stage (c) A packet is received at the status stage for which the data packet is "DATAPID=DATA0" (2) During control write transfers (a) For the OUT token of the data stage, when there have been no ACK responses at all, the IN token is received (b) A packet is received at the data stage for which the first data packet is "DATAPID=DATA0" (c) At the status stage, an OUT or PING token is received (3) During no-data control transfers (a) At the status stage, an OUT or PING token is received At the control write transfer stage, if the number of received data elements exceeds the wLength value of the USB request, it cannot be recognized as a control transfer sequence error. Also, at the control read transfer status stage, packets other than Zero-Length packets are received by an ACK response being carried out, and the transfer ends normally. If a CTRT interrupt occurs in response to a sequence error ("SERR=1"), the "CTSQ=110" value is held until "CTRT=0" is written from the user system (the interrupt status is cleared). Because of this, while "CTSQ=110" is being held, the CTRT interrupt that ends the setup stage will not be generated even if a new USB request is received. (The controller holds the setup stage end, and after the interrupt status has been cleared bysoftware, a setup stage end interrupt is generated.) Setup token received 5 Error detected Setup token received Setup token received "CTSQ=000" Setup stage ACK sent "CTSQ=110" Control transfer sequence error If errors are detected at all stages in the box, IN token reception is valid. "CTSQ=001" 1 Control read data stage "CTSQ=011" 1 Control write data stage OUT token "CTSQ=010" ACK sent 2 Control read status stage "CTSQ=100" ACK received 3 Control write status stage "CTSQ=101" Control write no1 data status stage 4 "CTSQ=000" Idle stage 4 ACK sent IN token ACK sent ACK received CTRT interrupts Setup stage completed Control read transfer status stage transition Control write transfer status stage transition Control transfer completed Control transfer sequence error Figure 3.17 Control transfer stage transitions Rev1.00 2004.10.01 page 69 of 125 M66592FP/WG 3.2.7 Frame refresh interrupt Figure 3.18 shows an example of the SOFR interrupt output timing of the controller. When the frame number is refreshed, or a damaged SOF packet is detected, the SOFR interrupt is generated. The interrupt operation should be specified using the SOFRM bit of the FRMNUM register. (1) When "SOFRM=0" is selected The SOFR interrupt is generated at the timing at which the frame number is refreshed (intervals of approximately 1 ms). Interrupts are generated by the internal interpolation function even if an SOF packet is damaged or missing. During Hi-Speed communication as well, interrupts are generated at the timing at which the frame number is refreshed (intervals of approximately 1 ms). (2) When "SOFRM=1" is selected The SOFR interrupt is generated when SOF packets are damaged and when they are missing. During Hi-Speed communication, the interrupt is generated only if the first packet of a uSOF packet with the same frame number is damaged or missing. (Corrupted and missing SOFs are recognized by the SOF interpolation function. For detailed information, please refer to Chapter 3.10, SOF interpolation function.) If the controller detects a new SOF packet during Full-Speed operation, it refreshes the frame number and generates an SOFR interrupt. However, if the system does not enter the SOF lock state during Hi-Speed operation, the frame number is not refreshed, and no SOFR interrupt is generated. Also, the SOF interpolation function is not activated. The SOF lock state is the state in which uSOF packets with different frame numbers are received twice in succession without an error occurring. The conditions under which SOF lock monitoring begins, and under which SOF lock monitoring stops, are as noted below. (1) Conditions under which SOF lock monitoring begins "USBE=1" and the internal clock (SCKE) is being supplied (2) Conditions under which SOF lock monitoring stops "USBE=0 (S/W reset)" or a USB bus reset is received, or a suspended state is detected Peripheral Device USOF packet USOF number Frame number SOFR interrupt (SOFRM=0) (SOFRM=1) 6 7 3 0 1 2 3 4 5 6 7 0 4 1 2 3 4 5 6 7 0 1 6 SOF interpolation SOF interpolation function SOF missing uSOF Lock USOF packet USOF number USOF lock SOFR interrupt Not locked Not locked SOF interpolation, missing 7 0 SOF interpolation 1 6 7 SOF interpolation 0 7 0 1 7 0 1 2 7 0 1 Figure 3.18 Example of SOFR interrupt output timing 3.2.8 VBUS interrupt If there has been a change in the VBUS pin, the VBUS interrupt is generated. The level of the VBUS pin can be detected using the VBSTS bit of the INTSTS0 register. Confirmation can be made of whether the host controller is connected or disconnected using the VBUS interrupt. However, if the user system is booted with the host controller connected, the first VBUS interrupt is not generated, because there is no change in the VBUS pin. 3.2.9 Resume interrupt The RESM interrupt is generated if the device state is the suspended state, and the USB bus state has changed (from the J-State to the K-State, or from the J-State to SE0). Recovery from the suspended state is detected by means of the Resume interrupt. Rev1.00 2004.10.01 page 70 of 125 M66592FP/WG Rev1.00 2004.10.01 page 71 of 125 M66592FP/WG 3.3 Pipe control Table 3.11 shows the pipe setting items of the controller. With USB data transfers, data communication has to be carried out using the logic pipe called the end point. This controller has eight pipes that are used for data transfers. Settings should be entered for each of the pipes in conjunction with the specifications of the user system. Table 3.11 Pipe setting items Register name DCPCFG PIPECFG Bit name TYPE BFRE DBLB CNTMD Setting contents Specifies the transfer type Selects the BRDY interrupt mode Selects a single or double buffer Selects continuous transfer or non-continuous transfer Note Please refer to 3.3.1. PIPE1-5: Can be set Please refer to 3.4.3.5 and 3.4.3.6. PIPE1-5: Can be set Please refer to 3.4.1.5. DCP: Can be set PIPE1-2: Can be set (can be set only when bulk transfer has been selected) PIPE3-5: Can be set With continuous transmission and reception, the buffer size should be set to an integer multiple of the payload. Please refer to 3.4.1.6. IN or OUT can be set. Please refer to 3.4.2.1 (DCP is controlled by ISEL). Please refer to 3.3.2. PIPE1-2: Can be set (can be set only when bulk transfer has been selected) PIPE3-5: Can be set Please refer to 3.3.7. DCP: Cannot be set (fixed at 256 bytes) PIPE1-5: Can be set (can be specified up to a maximum of 2 KB in 64-byte units) PIPR6-7: Cannot be set (fixed at 64 bytes) Please refer to 3.4.1. DCP: Cannot be set (areas fixed at 0-3) PIPE1-5: Can be set (can be specified in areas 6-4F) PIPE6-7: Cannot be set (areas fixed at 4-5) Please refer to 3.4.1. Please refer to Chapter 3.3.3. PIPE1-2: Can be set (only when isochronous transfer has been selected) PIPE3-7: Cannot be set Please refer to 3.9.5. PIPE1-2: Can be set (only when isochronous transfer has been selected) PIPE3-7: Cannot be set Please refer to 3.9.3. Please refer to 3.4.1.1 (also related to DIR / ISEU) Please refer to 3.4.1.1 (also related to DIR / ISEU) Enabled / disabled setting can be set when buffer memory reading is set. Please refer to 3.4.1.4. Clears the data toggle bit. Please refer to 3.3.6. Sets the data toggle bit. Please refer to 3.3.6. Confirms the data toggle bit. Please refer to 3.3.6. Please refer to 3.3.4. DIR EPNUM SHTNAK Selects transfer direction (reading or writing) End point number Selects disabled state for pipe when transfer ends Buffer memory size PIPEBUF BUFSIZE BUFNMB Buffer memory number DCPMAXP PIPEMAXP PIPEPERI MXPS IFIS Maximum packet size Buffer Flush IITV Interval Counter DCPCTR PIPExCTR BSTS INBUFM ACLRM SQCLR SQSET SQMON PID Buffer Status IN Buffer Monitor Auto Buffer Clear Sequence Clear Sequence Set Sequence Confirm Response PID Rev1.00 2004.10.01 page 72 of 125 M66592FP/WG 3.3.1 Transfer types The TYPE bit of the PIPEPCFG register is used to specify the type of transfer for the various pipes. The types of transfer that can be set for the pipes are noted below. (1) DCP: No setting is necessary (fixed at control transfer). (2) PIPE1-2: These should be set to bulk transfer or isochronous transfer. (3) PIPE3-5: These should be set to bulk transfer. (4) PIPE6-7: These should be set to interrupt transfer. 3.3.2 End point number The EPNUM bit of the PIPEPCFG register is used to set the end point numbers for the various pipes. DCP is fixed at end point 0. The other pipes can be set from end point 1 to end point 15. (1) DCP: No setting is necessary (fixed at end point 0). (2) PIPE1-7: "1" to "15" should be selected and set. However, these should be set so that the combination of the DIR bit and the EPNUM bit is a unique combination. 3.3.3 Maximum packet size setting The MXPS bit of the DCPMAXP register and the PIPEMAXP register is used to set the maximum packet size for the various pipes. DCP and PIPE1-5 can be set to any of the maximum pipe sizes defined by USB specification. For PIPE6-7, 64 bytes is the upper limit for the maximum packet size. The maximum packet size should be set before beginning the transfer ("PID=BUF"). (1) DCP: "64" should be set when using Hi-Speed operation. (2) DCP: Select and set "8", "16", "32" or "64" when using Full-Speed operation. (3) PIPE1-5: "0" or "512" should be set when using Hi-Speed bulk transfer. (4) PIPE1-5: Select and set "0", "8", "16", "32" or "64" when using Full-Speed bulk transfer. (5) PIPE1-2: Set a value between "1" and "1024" when using Hi-Speed isochronous transfer. (6) PIPE1-2: Set a value between "1" and "1023" when using Full-Speed isochronous transfer. (7) PIPE6-7: Set a value between "1" and "64". The High-Bandwidth transfers used with interrupt transfers and isochronous transfers are not supported. Also, setting "MXPS=0" for pipes when bulk transfer is being used results in the following operations. (1) Bulk IN: Data cannot be written to the buffer memory. When "PID=BUF" is set, a Zero-Length packet is sent in response to an IN token. The BRDY, NRDY, and BEMP interrupts are not generated. (2) Bulk OUT: The data in the received data packets cannot be stored in the buffer memory. When "PID=BUF" is set, the NAK response is sent in response to an OUT token. In this case, NRDY interrupts are generated, but BRDY and BEMP interrupts are not. Rev1.00 2004.10.01 page 73 of 125 M66592FP/WG 3.3.4 Response PID The PID bit of the DCPCTR register and PIPExCTR register is used to set the response PID for the various pipes. Operation with the various settings (1) NAK setting: The "NAK response" is always returned in response to the generated transaction. (2) BUF setting: Responses are made to transactions based on the status of the buffer memory. (3) STALL setting: The "STALL" response is always returned in response to the generated transaction. Also, for setup transactions, an "ACK response" is always returned, regardless of the PID setting, and the USB request is stored in the register. The controller may carry out writing to the PID bit, depending on the results of the transaction. If writing to the PID bit is generated by the controller (1) NAK setting: (a) When the SETUP token is received normally (DCP only) (b) When the transaction counter has ended or a short packet is received, if the SHTNAK bit of the PIPECFG register has been set to "1" for bulk transfers (2) BUF setting: There is no BUF writing by the controller. (3) STALL setting: (a) When an error has been detected in a received data packet indicating that the data size exceeds the maximum packet size (b) When a control transfer stage transition error has been detected 3.3.5 Registers that should not be set in the USB communication enabled ("PID=BUF") state ISEL bit of the CFIFOSEL register (applies only when DCP is selected) TGL and SCLR bits of the CFIFOSIE register DCLRM, TRENB, TRCLR, and DEZPM bits of the DxFIFOSEL register TRNCNT bit of the DxFIFOTRN register The various bits of the DCPCFG and DCPMAXP registers The various bits of the DCPCTR register (except for the CCPL bit) The various bits of the PIPECFG, PIPEBUF, and PIPEMAXP registers The various bits of the PIPEPERI and PIPExCTR registers 3.3.6 Data PID sequence bit The controller toggles the data PID sequence bit when data is transferred normally. Next, the sequence bit of the data PID that was sent can be used to confirm the SQMON bit of the DCPCTR register and the PIPExCTR register. When data is sent, the sequence bit switches at the timing at which the ACK handshake is received, and when data is received, the sequence bit switches at the timing at which the ACK handshake is sent. Also, the SQCLR bit and the SQSET bit of the DCPCTR register and the PIPExCTR register can be used to change the data PID sequence bit. With pipes for which isochronous transfer has been set, sequence bit operation cannot be carried out using the SQSET bit. 3.3.7 Response PID=NAK function The controller has a function that disables pipe operation ("Response PID=NAK") at the timing at which the final data packet of a transaction is received (the controller automatically distinguishes this based on reception of a short packet or the transaction counter) by setting the SHTNAK bit of the PIPECFG register to "1". When a double buffer is being used for the buffer memory, using this function enables reception of data packets in transfer units. Also, if pipe operation has been disabled, the pipe has to be set to the enabled state again ("Response PID=BUF") usingsoftware. This function can be used for operation only when using bulk transfers. Rev1.00 2004.10.01 page 74 of 125 M66592FP/WG 3.4 Buffer memory 3.4.1 Buffer memory allocation Figure 3.19 shows an example of a buffer memory map for the controller. The buffer memory is an area shared by the user system control CPU and the controller. In the buffer memory status, there are times when the access right to the buffer memory is allocated to the user system (CPU side), and times when it is allocated to the controller (SIE side). The buffer memory sets independent areas for each pipe. In the memory areas, 64 bytes comprise one block, and the memory areas are set using the first block number of the number of blocks (specified using the BUFNMB and BUFSIZE bits of the PIPEBUF register). Moreover, three FIFO ports are used for access to the buffer memory (reading and writing data). A pipe is assigned to the FIFO port by specifying the pipe number using the CURPIPE bit of the C/DxFIFOSEL register. The buffer statuses of the various pipes can be confirmed using the BSTS bit of the DCPCTR register and PIPExCTR register. Also, the access right of the FIFO port can be confirmed using the FRDY bit of the C/DxFIFOCTR register. FIFO Port CFIFO Port Buffer memory PIPE0 PIPEBUF reg BUFNMB=0, BUFSIZE=3 CURPIPE=6 PIPE6 PIPE7 PIPE5 BUFNMB=4, BUFSIZE=0 BUFNMB=5, BUFSIZE=0 BUFNMB=6, BUFSIZE=3 D0FIFO Port CURPIPE=1 PIPE1 D1FIFO Port BUFNMB=10, BUFSIZE=7 CURPIPE=3 PIPE2 PIPE3 BUFNMB=18, BUFSIZE=3 BUFNMB=22, BUFSIZE=7 PIPE4 BUFNMB=28, BUFSIZE=2 Figure 3.19 Example of buffer memory map Rev1.00 2004.10.01 page 75 of 125 M66592FP/WG 3.4.1.1 Buffer status Table 3.12 shows the buffer status. The buffer memory status can be confirmed using the BSTS bit and the INBUFM bit. The access direction for the buffer memory can be specified using either the DIR bit of the PIPExCFG register or the ISEL bit of the CFIFOSEL register (when DCP is selected). the INBUFM bit is valid for IN direction pipe ("DIR=1") For a IN pipe uses double buffer, software can refer the BSTS bit to monitor the buffer memory status of CPU side and the INBUFM bit to monitor the buffer memory status of SID side. In the case like the BEMP interrupt may not show bufer empty status because the CPU (DMAC) writes data slowly, software can use the INBUFM bit to tell the end of sending. Table 3.12 Buffer statuses and the BSTS bit ISEL or DIR 0 (receiving direction) 0 (receiving direction) BSTS 0 1 Buffer memory state There is no received data, or data is being received. Reading from the CPU is inhibited. There is received data, or a Zero-Length packet has been received. Reading from the CPU is allowed. However, because reading is not possible when a Zero-Length packet is received, the buffer must be cleared. The transmission has not been finished. Writing to the CPU is inhibited. Writing to the CPU is allowed. (1) "DBLB=0"(Single buffer) ; The transmission has been finished. (2) "DBLB=1"(Double buffer) ; The transmission for one side of the buffer has been finished. 1 (sending direction) 1 (sending direction) 0 1 Table 3.13 Buffer statuses and the INBUFM bit I DIR 0 (receiving direction) 1 (sending direction) 1 (sending direction) INBUFM invaild 0 1 Buffer memory state invaild The transmission has not been finished. There is no waiting data to be sent. There is data to be sent, because CPU(DMAC) has written data to the buffer. 3.4.1.2 Buffer clearing Table 3.14 shows the clearing of the buffer memory by the controller. The buffer memory can be cleared using the four bits indicated below. Table 3.14 Buffer clearing Bit name Register Function BCLR CFIFOCTR register DxFIFOCTR register Clears the buffer memory on the CPU side SCLR CFIFOSIE register Clears the buffer memory on the SIE side DCLRM DxFIFOSEL register In this mode, after the data of the specified pipe has been read, the buffer memory is cleared automatically. See 3.4.3.5. "1": Mode valid "0": Mode invalid ACLRM PIPExCTR register This is the Auto Buffer Clear mode, in which all of the received packets are destroyed. See 3.4.1.4. "1": Mode valid "0": Mode invalid Clearing method Cleared by writing "1" Cleared by writing "1" Rev1.00 2004.10.01 page 76 of 125 M66592FP/WG 3.4.1.3 Buffer areas Table 3.15 shows the FIFO buffer memory map of the controller. The buffer memory has special fixed areas to which pipes are assigned in advance, and user areas that can be set by the user. The buffer for the DCP is a special fixed area that is used both for control read transfers and control write transfers. The PIPE6-7 area is assigned in advance, but the area for pipes that are not being used can be assigned to PIPE1-5 as a user area. The settings should ensure that the areas of the various pipes do not overlap. Also, the buffer size should not be specified using a value that is less than the maximum packet size. Table 3.15 Buffer memory map Buffer memory no. 0-3 4 5 6 - 4F Buffer size 256 bytes 64 bytes 64 bytes 4736 bytes Pipe setting DCP special fixed area Fixed area for PIPE6 Fixed area for PIPE7 PIPE1-5 user area Note Single buffer, continuous transfers enabled Single buffer Single buffer Double buffer can be set, continuous transfers enabled 3.4.1.4 Auto Buffer Clear mode function With this controller, all of the received data packets are discarded if the ACLRM bit of the PIPExCTR register is set to "1". If a normal data packet has been received, however, the ACK response is returned to the host controller. This function can be set only in the buffer memory reading direction. Also, if the ACLRM bit is set to "1" and then to "0", the buffer memory of the pertinent pipe can be cleared regardless of the access direction. An access cycle of at least 100 ns is required between "ACLRM=1" and "ACLRM=0". Rev1.00 2004.10.01 page 77 of 125 M66592FP/WG 3.4.1.5 Buffer memory specifications (single / double setting) Either a single or double buffer can be selected for PIPE1-5, using the DBLB bit of the PIPExCFG register. The double buffer is a function that assigns two memory areas specified with the BUFSIZE bit of the PIPEBUF register to the same pipe. Figure 3.20 shows an example of buffer memory settings for the controller. Buffer memory 64 Byte 64 Byte 64 Byte 128 Byte PIPEBUF reg BUFSIZE=0, DBLB=0 BUFIZE=0, DBLB=1 BUFSIZE=1, DBLB=0 Figure 3.20 Example of buffer memory settings 3.4.1.6 Buffer memory operation (continuous transfer setting) Either the continuous transfer mode or the non-continuous transfer mode can be selected, using the CNTMD bit of the DCPCFG register and the PIPExCFG register. This selection is valid for pipes 0-5. The continuous transfer mode function is a function that sends and receives multiple transactions in succession. When the continuous transfer mode is set, data can be transferred without interrupts being issued to the CPU, up to the buffer sizes assigned for each of the pipes. In the continuous sending mode, the data being written is divided into packets of the maximum packet size and sent. If the data being sent is less than the buffer size (short packet, or the integer multiple of the maximum packet size is less than the buffer size), "BVAL=1" must be set after the data being sent has been written. In the continuous reception mode, interrupts are not issued during reception of packets up to the buffer size, until the transaction counter has ended, or until a short packet is received. Figure 3.21 shows an example of buffer memory operation for the controller. CNTMD=0 When packet is received CNTMD=1 When packet is received Max Packet Size Not used area Max Packet Size Max Packet Size Interrupt issued CNTMD=0 When packet is sent CNTMD=1 When packet is sent Interrupt issued Max Packet Size Not used area Max Packet Size Max Packet Size Sending enabled Sending enabled Figure 3.21 Example of buffer memory operation Rev1.00 2004.10.01 page 78 of 125 M66592FP/WG 3.4.2 FIFO port functions Table 3.16 shows the settings for the FIFO port functions of the controller. When data writing is being accessed, writing data until the buffer is full (or the maximum packet size for non-continuous transfers) automatically enables sending of the data. To enable sending of data before the buffer is full (or before the maximum packet size for non-continuous transfers), the BVAL bit of the C/DxFIFOCTR register (or the DEND signal when using DMA transfers) must be set to end the writing. Also, to send a Zero-Length packet, the BCLR bit of the same register must be used to clear the buffer and then the BVAL bit set in order to end the writing. When accessing reading, reception of new packets is automatically enabled if all of the data has been read. However, data cannot be read when a Zero-Length packet is being received (DTLN=0), so the BCLR bit of the register must be used to release the buffer. The length of the data being received can be confirmed using the DTLN bit of the C/DxFIFOCTR register. Table 3.16 FIFO port function settings Register name C/DxFIFOSEL Bit name REW DCLRM Function Buffer memory rewind (re-read, re-write) Automatically clears data received for a specified pipe after the data has been read Asserts DREQ signal FIFO port access bit width Enables transaction counter operation Clears the current number of transactions Zero-Length packet addition mode FIFO port access direction Ends writing to the buffer memory Clears the buffer memory on the CPU side Confirms the length of received data Sets the received transaction count CPU / SIE buffer toggle Clears the buffer memory on the SIE side Ends writing to the buffer memory Reference Note For DxFIFO only DMA transfer assumed For DxFIFO only For DxFIFO only For DxFIFO only For DMA only For DCP only DREQE MBW TRENB TRCLR DEZPM ISEL BVAL BCLR DTLN TRNCNT TGL SCLR DEND 3.4.2.2 3.4.1.2 3.4.3.4 3.4.4 3.4.3 3.4.2.1 3.4.2.5 3.4.2.5 3.4.3.3 3.4.2.1 3.4.2 3.4.1.2 3.4.2 3.4.2.5 3.4.2.3 3.4.2.4 3.4.3.4 C/DxFIFOCTR DxFIFOTRN CFIFOSIE (excluding DCP) External pin For DxFIFO only For CFIFO only For CFIFO only For DMA transfer only 3.4.2.1 FIFO port selection Table 3.17 shows the pipes that can be selected with the various FIFO ports. The pipe to be accessed is selected using the CURPIPE bit of the C/DxFIFOSEL register. After the pipe has been selected, "FRDY=1" should be confirmed before accessing the FIFO port. Also, the bus width to be accessed should be selected using the MBW bit. The buffer memory access direction conforms to the DIR bit of the PIPExCFG register. However, the ISEL bit determines this only for the DCP. Table 3.17 FIFO port access categorized by pipe Pipe DCP PIPE1~PIPE7 Access method CPU access CPU access DMA access Port that can be used CFIFO port register CFIFO port register DxFIFO port register DxFIFO port register 3.4.2.2 REW bit It is possible to temporarily stop access to the pipe currently being accessed, access a different pipe, and then continue processing using the current pipe once again. The REW bit of the C/DxFIFOSEL register is used for this. If a pipe is selected when the REW bit is set to "1" and at the same time the CURPIPE bit of the C/DxFIFOSEL register is set, the pointer used for reading from and writing to the buffer memory is reset, and reading or writing can be carried out from the first byte. Also, if a pipe is selected with "0" set for the REW bit, data can be read and written in continuation of the previous selection, without the pointer used for reading from and writing to the buffer memory being reset. To access the FIFO port, "FRDY=1" must be confirmed after selecting a pipe. Rev1.00 2004.10.01 page 79 of 125 M66592FP/WG 3.4.2.3 Reading the buffer memory on the SIE side (CFIFO port reading direction) Even in the "FRDY=0" state, when data cannot be read from the buffer memory, confirming the SBUSY bit in the CFIFOSIE register and setting "1" for the TGL bit makes it possible for the controller to read and access data on the SIE side. "PID=NAK" should be set and "SBUSY=0" confirmed, and then "TGL=1" written. The controller is then able to read data from the CFIFO register. This function can be used only in the buffer memory reading direction. Also, the BRDY interrupt is generated by operation of the TGL bit. "1" should not be written for the TGL bit in the following circumstances. (1) When DCP is selected (2) While the buffer memory is being read (3) Pipes in the buffer memory writing direction 3.4.2.4 Clearing the buffer memory on the SIE side (CFIFO port writing direction) The controller can cancel data that is waiting to be sent, by confirming the SBUSY bit of the CFIFOSIE register and setting "1" for the SCLR bit. "PID=NAK" should be set and "SBUSY=0" confirmed, and then "SCLR=1" written. The controller is then able to write new data from the CFIFO register. This function can be used only in the buffer memory writing direction. Also, the BRDY interrupt is generated by operation of the SCLR bit. "1" should not be written for the SCLR bit in the following circumstances. (1) When DCP is selected (2) While data is being written to the buffer memory (3) Pipes in the buffer memory reading direction 3.4.2.5 Transaction counter (DxFIFO port reading direction) When the specified number of transactions have been completed in the data packet receiving direction, the controller is able to recognize that the transfer has ended. The transaction counter is a function that operates when the pipe selected by means of the DxFIFO port has been set in the direction of reading data from the buffer memory. The transaction counter has a TRNCNT register that specifies the number of transactions and a current counter that counts the transactions internally. When the current counter matches the number of transactions specified in the TRNCNT register, reading is enabled for the buffer memory. The current counter of the transaction counter function is initialized by the TRCLR bit, so that the transactions can be counted again starting from the beginning. The information read by the TRNCNT register differs depending on the setting of the TRENB bit. TRENB=0: The set transaction counter value can be read. TRENB=1: The value of the current counter that counts the transactions internally can be read. The conditions for changing the CURPIPE bit are as noted below. (1) The CURPIPE bit should not be changed until the transaction for the specified pipe has ended. (2) The CURPIPE bit cannot be changed if the current counter has not been cleared. The operation conditions for the TRCLR bit are as noted below. (1) If the transactions are being counted and "PID=BUF", the current counter cannot be cleared. (2) If there is any data left in the buffer, the current counter cannot be cleared. Rev1.00 2004.10.01 page 80 of 125 M66592FP/WG 3.4.3 DMA transfers (DxFIFO port) 3.4.3.1 An overview of DMA transfers For pipes 1 to 7, the FIFO port can be accessed using the DMAC. For DMA transfers, there are two modes that can be selected. One is the cycle steal transfer mode, in which the DREQ signal is asserted each time a data element (8 or 16 bits) is transferred. The other is the burst transfer mode, in which the DREQ signal continues to be asserted until all of the data in the buffer memory has been transferred. For information regarding the timing, please refer to Chapter4, Electrical characteristics. The unit of transfer to the FIFO port (8 or 16 bits) should be selected using the MBW bit of the DxFIFOSEL register, and the pipe targeted for the DMA transfer should be selected using the CURPIPE bit. The selected pipe should not be changed during the DMA transfer. 3.4.3.2 Selecting the DMA control signal The DFORM bit of the DMAxCFG register should be used to select the pin to be used in the DMA transfer. Table 3.18 shows the DMA control pins of the controller. Table 3.18 DMA control pins ADDR Note +CS DREQE DFORM DATA BUS DREQ DACK RD/WR DSTB CPU bus 0 0 0 0 0 CPU v v CPU access CPU bus 1 1 0 0 0 CPU v v v DMA with CPU bus CPU bus 2 1 0 1 0 CPU v v v DMA with CPU bus *2) CPU bus 3 1 0 1 1 CPU v v DMA with CPU bus *2) SPLIT bus 1 1 1 1 0 SPLIT v v v Split bus *1) SPLIT bus 2 1 1 0 0 SPLIT v v Split bus *1) This access method can be set only in relation to the D0FIFO port. Also, if using the D0FIFO port with this setting and also using the D1FIFO port, the D1FIFO port should be used with the setting "DFROM=000". *2) When this access method is set CS_N pin shoul be held inactive (should be held in the high state) while the DMAC accsesses to the DxFIFO port. Access method Register Pin DMA transfer on CPU bus 1 DREQ DACK RD/WR CS ADDR D15-0 DEND DMA transfer on split bus 1 DREQ DACK DSTB SD7-0 DEND DMA transfer on CPU bus 2 DMA transfer on split bus 2 Figure 3.22 DMA control pins operation by FIFO port accessing methods Rev1.00 2004.10.01 page 81 of 125 M66592FP/WG 3.4.3.3 Zero-Length packet addition mode (DxFIFO port writing direction) With this controller, it is possible to add and send one Zero-Length packet after all of the data has been sent, under the conditions noted below, by setting "1" for the DEZPM bit of the DxFIFOSEL register. This function can be set only if the buffer memory writing direction has been set (a pipe in the sending direction has been set for the CURPIPE bit). (1) If the number of data bytes written to the buffer memory is a multiple of the integer for the maximum packet size when the DEND signal is received 3.4.3.4 DEND pin The controller is able to terminate DMA transfers that used the DEND pin. The DEND pin has separate input and output functions, depending on the USB data transfer direction. (1) Buffer memory reading direction The DEND pin becomes an output pin, making it possible to notify the external DMA controller of the final data transfer. The conditions under which the DEND signal is asserted can be set using the PKTM bit of DMAxCFG register. Table 3.19 shows the DEND pin assertion conditions for the controller. Table 3.19 DEND pin assertions BRDY Reception of short Reception of Reception of generated upon packet other than Zero-Length Zero-Length packet reception of Zero-Length packet packet when buffer when buffer is PKTM packet is not empty empty *1) 0 Asserted Not asserted Asserted Asserted Asserted 1 Asserted Asserted Asserted Asserted Not asserted *1) With reception of a Zero-Length packet when the buffer is empty, the DREQ signal is not asserted. (1) Buffer memory writing direction The DEND pin becomes the input pin, and data can be sent from the buffer memory (the same situation as when "BVAL=1" is set). Event Transaction count ended 3.4.3.5 DxFIFO auto clear mode (DxFIFO port reading direction) If "1" is set for the DCLRM bit of the DxFIFOSEL register, the controller automatically clears the buffer memory of the pertinent pipe when reading of the data from the buffer memory has been completed. Table 3.20 shows the packet reception and buffer memory clearing processing for each of the various settings. Using the DCLRM bit eliminates the need for the buffer to be cleared by software even if a situation occurs that necessitates clearing of the buffer. This makes it possible to carry out DMA transfers without involvingsoftware. This function can be set only in the buffer memory reading direction. Table 3.20 Packet reception and buffer memory clearing processing Register setting Buffer status when packet is received Buffer full Zero-Length packet reception Normal short packet reception Transaction count ended DCLRM = "0" BFRE=0 BFRE=1 Doesn't need to Doesn't need to be cleared be cleared Needs to be Needs to be cleared cleared Doesn't need to Needs to be be cleared cleared Doesn't need to Needs to be be cleared cleared DCLRM = "1" BFRE=0 BFRE=1 Doesn't need to Doesn't need to be cleared be cleared Doesn't need to Doesn't need to be cleared be cleared Doesn't need to Doesn't need to be cleared be cleared Doesn't need to Doesn't need to be cleared be cleared Rev1.00 2004.10.01 page 82 of 125 M66592FP/WG 3.4.3.6 BRDY interrupt timing selection function By setting the BFRE bit of the PIPECFG register, it is possible to keep the BRDY interrupt from being generated when a data packet consisting of the maximum packet size is received. When using DMA transfers, this function can be used to generate an interrupt only when the last data item has been received. The "last data item" refers to the reception of a short packet, or the ending of the transaction counter. When a short packet has been received, the BRDY interrupt is generated after the received data has been read. When the BRDY interrupt is generated, the length of the data received in the last data packet to have been received can be confirmed. Table 3.21 shows the timing at which the BRDY interrupts are generated by the controller. Table 3.21 Timing at which BRDY interrupts are generated BFRE = "0" BFRE = "1" When packet is Buffer full Not generated received When packet is Zero-Length packet received When packet is received received When packet is When reading of the received data from the Normal packet received received buffer memory has been completed When packet is When reading of the received data from the Transaction counter ended received buffer memory has been completed *1) This function is valid only in the direction of reading from the buffer memory. In the writing direction, the BFRE bit should be fixed at "0". Buffer state when packet is received Register setting Rev1.00 2004.10.01 page 83 of 125 M66592FP/WG 3.4.4 Timing at which the FIFO port can be accessed 3.4.4.1 Timing at which the FIFO port can be accessed when switching pipes Figure 3.23 shows a diagram of the timing up to the point where the FRDY bit and DTLN bit are determined when the pipe specified by the FIFO port has been switched (the CURPIPE bit of the C/DxFIFOSEL register has been changed). If the CURPIPE bit has been changed, access to the FIFO port should be carried out after waiting 450 ns after writing to the C/DxFIFOSEL register. The same timing applies with respect to the CFIFO port, when the ISEL bit is changed. Writing of the CURPIPE bit WR_N CURPIPE FRDY DTLN PIPE-A PIPE-A PIPE-A Indefinite Indefinite max 450ns PIPE-B PIPE-B PIPE-B max 100ns min 20ns Figure 3.23 Timing at which the FRDY and DTLN bits are determined after changing a pipe 3.4.4.2 Timing at which the FIFO port can be accessed after reading/writing has been completed when using a double buffer Figure 3.24 shows the timing at which, when using a pipe with a double buffer, the other buffer can be accessed after reading from or writing to one buffer has been completed. When using a double buffer, access to the FIFO port should be carried out after waiting 300 ns after the access made just prior to toggling. The same timing applies when a short packet is being sent based on the "BVAL=1" setting using the IN direction pipe. Access just prior to buffer toggling WR_N / RD_N CURPIPE FRDY DTLN Buffer-A Buffer-A Indefinite max 300ns min 20ns PIPE-A Buffer-B Buffer-B Figure 3.24. Timing at which the FRDY and DTLN bits are determined after reading from or writing to a double buffer has been completed Rev1.00 2004.10.01 page 84 of 125 M66592FP/WG 3.5 Data setup timing This section describes the OBUS bit used to select the timing of split bus. With this controller, the timing of the SD0-7 and DEND pin can be changed as shown in Table 3.22 , using the OBUS bit of the DMAxCFG register The OBUS bit is a function that is valid only for DMA transfers using a split bus. When using the CPU bus for DMA transfers, the setting of the OBUS bit is ignored. Table 3.22 Differences in operation based on the value set for the OBUS bit Direction Reading OBUS bit setting 0 Operation The SD0-7 and DEND signals are output on an ongoing basis, regardless of the control signal*1). The next data is output when the control signal is negated. This assures data setup time for the DMAC and enables high-performance DMA transfers. 1 The SD0-7 and DEND signals are output after the control signal has been asserted. The SD0-7 and DEND signals go to the Hi-Z state when the control signal is negated. Writing 0 The SD0-7 and DEND signals can be input on an ongoing basis, regardless of the DACKx_N signal. The DMAC can output the next data before the DACKx_N signal is asserted. This assures data setup time for the controller and enables high-performance DMA transfers. 1 The SD0-7 and DEND signals can be input only if the DACKx_N signal is asserted. The SD0-7 and DEND signals are ignored if the DACKx_N signal is negated. *1) *1 "Control signal" refers to the DACKx_N signal if the DFORM[9-7] of the DMAxCFG register is "100". If the DFORM[9-7] is "110", it refers to both DACK0_N and DSTRB0_N. In this case, "assertion of the control signal" means the state in which either DACK0_N or DSTRB0_N is asserted. If "OBUS=0" is set in the reading direction, the SD0-7 and DEND signals are output on an ongoing basis, so please be aware that sharing the bus with another device can cause the signals to collide. If "OBUS=0" is set in the writing direction, the SD0-7 and DEND signals can be input on an ongoing basis, so the user should make sure that the signals are not set to an intermediate potential. Figure 3.25 shows a schematic diagram of the data setup timing based on the OBUS bit. OBUS=1: Normal mode DREQ DACK SD7-0 DEND OBUS=0: High-speed mode Figure 3.25 Schematic diagram of data setup timing Rev1.00 2004.10.01 page 85 of 125 M66592FP/WG 3.6 Control transfers (DCP) Data transfers of the data stage of control transfers are done using the default control pipe (DCP). The DCP buffer memory is a 256-byte single buffer, and is a fixed area that is shared for both control reading and control writing. The buffer memory can be accessed through the CFIFO port. 3.6.1 Setup stage The controller always sends an ACK response in response to a setup packet that is normal with respect to the controller. The operation of the contoller in the setup stage is noted below. (1) When a new USB request is received, the controller set following registers: (a) Set the VALID bit of the INTSTS0 register to "1". (b) Set the PID bit of the DCPCTR register to "NAK". (c) Set the CCPL bit of the DCPCTR register to "0". (2) When a data packet is received right after the SETUP packet, the USB request parameters are stored in the USBREQ, USBVAL, USBINDX and USBLENG registers. Response processing with respect to the controller should always be carried out after first setting "VALID=0". In the "VALID=1" state, "PID=BUF" cannot be set, and the data stage cannot be terminated. Using the function of the VALID bit, the controller is able to interrupt the processing of a request currently being processed if a new USB request is received during a control transfer, and can send a response in response to the newest request. Also, the controller automatically judges the direction bit (bit 8 of the bmRequestType) and the request data length (wLength) of the USB request that was received, and then distinguishes between control read transfers, control write transfers, and no-data control transfers, and controls the stage transition. For a wrong sequence, the sequence error of the control transfer stage transition interrupt is generated, and the control program is notified. For information on the stage control of the controller, please refer to Figure 3.17, Control transfer stage transitions. 3.6.2 Data stage Data transfers corresponding to USB requests that have been received should be done using the DCP. Before accessing the DCP buffer memory, the access direction should be specified using the ISEL bit of the CFIFOSEL register. If the data being transferred is larger than the size of the DCP buffer memory, the data transfer should be carried out using the BRDY interrupt for control write transfers and the BEMP interrupt for control read transfers. With control write transfers during Hi-Speed operation, the NYET handshake response is carried out based on the state of the buffer memory. For information on the NYET handshake, please refer to 3.7.1 NYET handshake control. 3.6.3 Status stage Control transfers are terminated by setting the CCPL bit to "1" with the PID bit of the DCPCTR register set to "PID=BUF". After the above settings have been entered, the controller automatically executes the status stage in accordance with the data transfer direction determined at the setup stage. The specific procedure is as follows. (1) For control read transfers: The Zero-Length packet is received from the USB host, and the controller sends an ACK response. (2) For control write transfers and no-data control transfers: The controller sends a Zero-Length packet and receives the ACK response from the USB host. Rev1.00 2004.10.01 page 86 of 125 M66592FP/WG 3.6.4 Control transfer auto response function The controller automatically responds to a normal SET_ADDRESS request. If any of the following errors occur in the SET_ADDRESS request, a response from the S/W is necessary. "0x00" (1) Any transfer other than a control read transfer: bmRequestType "0x00" (2) If a request error occurs: wIndex "0x00" (3) For any transfer other than a no-data control transfer: wLength > "0x7F" (4) If a request error occurs: wValue = "011(Configured)" (5) Control transfer of a device state error: DVSQ For all requests other than the SET_ADDRESS request, a response is required from the correspondingsoftware. Rev1.00 2004.10.01 page 87 of 125 M66592FP/WG 3.7 Bulk transfers (PIPE1-5) The user can select the buffer memory specifications for bulk transfers (single / double buffer setting, or continuous / non-continuous transfer mode setting). The maximum size that can be set for the buffer memory is 2 KB. The buffer memory state is controlled by the controller, with a response sent automatically for a PING packet / NYET handshake. If "MXPS=0" has been set, the interrupt specifications are different from those of the other pipes. For detailed information, please refer to 3.3.3 Maximum packet size setting. 3.7.1 NYET handshake control Table 3.23 shows the NYET handshake responses of the controller. The NYET response of the controller is made in conformance with the conditions noted below. When a short packet is received, however, the response will be an ACK response rather than a NYET packet response. The same applies to data stages of control write transfers. Table 3.23 NYET handshake responses Value set for PID bit NAK/STALL BUF Buffer memory state *1) RCV-BRDY*1 RCV-BRDY*2 Token SETUP IN/OUT/PING SETUP OUT/PING OUT Response ACK NAK/STALL ACK ACK NYET Note If an OUT token is received, a data packet is received. Notification of whether a data packet is received or cannot be received Notification of whether a data packet is received or cannot be received Notification that reception is not possible Notification that reception is not possible Data packet transmission TRN-NRDY RCV-BRDY*2 OUT (Short) ACK RCV-BRDY*2 PING ACK RCV-NRDY OUT / PING NAK TRN-BRDY IN DATA0 / 1 TRN-NRDY IN NAK *1) Buffer memory is state is as following; RCV-BRDY*1: When an OUT/PING token is received, there is space in the buffer memory for two or more packets. RCV-BRDY*2: When an OUT token is received, there is only enough space in the buffer memory for one packet. RCV-NRDY: When a PING token is received, there is no space in the buffer memory. TRN-BRDY: When an IN token is received, there is data to be sent in the buffer memory. TRN-NRDY: When an IN token is received, there is no data to be sent in the buffer memory. 3.8 Interrupt transfers(PIPE6-7) The controller carries out interrupt transfers in accordance with the timing controlled by the host controller. For interrupt transfers, PING packets are ignored (no response is sent), and the ACK, NAK and STALL responses are carried out without an NYET handshake response being made. The controller does not support High-Bandwidth transfers of interrupt transfers. Rev1.00 2004.10.01 page 88 of 125 M66592FP/WG 3.9 Isochronous transfers(PIPE1-2) The controller is equipped with the following functions pertaining to isochronous transfers. (1) Notification of isochronous transfer error information (2) Interval counter (specified by the IITV bit) (3) Isochronous IN transfer data setup control (IDLY function) (4) Isochronous IN transfer buffer flush function (specified by the IFIS bit) (5) SOF pulse output function The controller does not support the High-Bandwidth transfers of isochronous transfers. 3.9.1 Error detection with isochronous transfers The controller has a function for detecting the error information noted below, so that when errors occur in isochronous transfers, software can control them. Table 3.24 and Table 3.25 show the order in which errors are confirmed, and the interrupts that are generated. (1) PID errors If the PID is illegal (2) CRC errors and bit stuffing errors If an error occurs in the CRC of the packet being received, or the bit stuffing is illegal (3) Maximum packet size exceeded The maximum packet size exceeded the set value. (4) Overrun and underrun errors When using isochronous IN transfers, the data transmission was not in time for the IN token. When using isochronous OUT transfers, the OUT token was received, but the buffer memory was not empty. (5) Interval errors During an isochronous IN transfer, the token could not be received during the interval frame. Table 3.24 Error detection when a token is received Detection priority order 1 2 3 4 Error PID errors CRC error and bit stuffing errors Overrun and underrun errors Interval errors Generated interrupt and status No interrupt generated (ignored) No interrupt generated (ignored) NRDY interrupt OVRN bit set NRDY interrupt Table 3.25 Error detection when a data packet is received Detection priority order 1 2 3 Error PID errors CRC error and bit stuffing errors Maximum packet size exceeded error Generated interrupt and status No interrupt generated (ignored) NRDY interrupt generated CRCE bit set BEMP interrupt PID set to "STALL" Rev1.00 2004.10.01 page 89 of 125 M66592FP/WG 3.9.2 DATA-PID Because High-Bandwidth transfers are not supported, the DATA-PID added with the USB 2.0 standard is supported as indicated below. (1) IN direction: (a) DATA0: Sent as data packet PID (b) DATA1: Not sent (c) DATA2: Not sent (d) mDATA: Not sent (2) OUT direction(when using Full-Speed operation): (a) DATA0: Received normally as data packet PID (b) DATA1: Received normally as data packet PID (c) DATA2: Packet is ignored (d) mDATA: Packet is ignored (3) OUT direction(when using Hi-Speed operation): (a) DATA0: Received normally as data packet PID (b) DATA1: Received normally as data packet PID (c) DATA2: Received normally as data packet PID (d) mDATA: Received normally as data packet PID 3.9.3 Interval counter 3.9.3.1 An overview of operation The isochronous interval can be set using the IITV bit of the PIPEPERI register. The interval counter enables the functions noted below. Table 3.26 Function of the interval counter Transfer Direction IN OUT Function IN buffer flush function Notification of a token not being received Conditions for detecition When a token cannot be normally received in the interval frame during an isochronous IN transfer When a token cannot be normally received in the interval frame during an isochronous OUT transfer The interval count is carried out when an SOF is received or for interpolated SOFs, so the isochronism can be maintained even if an SOF is damaged. The frame interval that can be set is 2IITV (u)frames. 3.9.3.2 Counter initialization The controller initializes the interval counter under the following conditions. (1) H/W reset The IITV bit is initialized. (2) S/W reset The IITV bit is initialized. (3) USB bus reset (the count is stopped, and is then begun once again after USB bus reset.) The IITV bit is initialized. (4) Buffer memory initialization using the ACLRM bit The IITV bit is not initialized but count value. The count is begun once again when the software set the ACLRM bit to "0") After the interval counter has been initialized, the counter is started under the following confitions (1) or (2) , when a packet has been transferred normally. (1) An SOF is received following transmission of data in response to an IN token, in the "PID-BUF" state (2) An SOF is received after data following an OUT token is received in the "PID=BUF" state The interval counter is not initialized under the conditions noted below. (1) The pipe is disabled (the "PID=NAK/STALL" setting temporarily stops the count, and the count resumes upon "PID=BUF") (2) The USB bus reset or the USB is suspended The count stops temporarily and then continues when operation is resumed Rev1.00 2004.10.01 page 90 of 125 M66592FP/WG Rev1.00 2004.10.01 page 91 of 125 M66592FP/WG 3.9.4 Setup of data to be transmitted using isochronous transfer With isochronous data transmission using this controller, after data has been written to the buffer memory, a data packet can be sent with the next frame in which an SOF packet is detected. This function is called the isochronous transfer transmission data setup function, and it makes it possible to designate the frame from which transmission began. If a double buffer is being used for the buffer memory, transmission will be enabled for only one of the two buffers even after the writing of data to both buffers has been completed, that buffer memory being the one to which the data writing was completed first. For this reason, even if multiple IN tokens are received, the only buffer memory that can be sent is one packet's worth of data. When an IN token is received, if the buffer memory is in the transmission enabled state, the controller transmits the data . If the buffer memory is not in the transmission enabled state, however, a Zero-Length packet is sent and an underrun error occurs. Figure 3.26 shows an example of transmission using the isochronous transfer transmission data setup function with the controller, when "IITV=0 (every frame)" has been set. Sending of a Zero-Length packet is displayed in the illustration as "Null", in a shaded box. Received token IN Empty state Writing in progress IN Writing completed Empty state IN Transmission enabled state Buffer A Buffer B Sent packet Empty state Null Null Data-A SOF packet Buffer A Buffer B Empty state Writing in progress Writing completed Writing in progress Transmission enabled state Transmission enabled state Empty state Received token IN Empty state Writing in progress Writing completed Writing in progress Transmission enabled state IN Empty state Writing in progress IN Writing completed Empty state Data-B Buffer A Buffer B Send packet Empty state Writing completed Data-A Transmission enabled state Null Received token IN Empty state Writing in progress Writing completed Writing in progress Transmission enabled state IN IN Empty state Writing in progress IN Writing completed Empty state Data-B Buffer A Buffer B Send packet Empty state Writing completed Data-A Null Transmission enabled state Null Figure 3.26 Example of data setup function operation Rev1.00 2004.10.01 page 92 of 125 M66592FP/WG 3.9.5 Isochronous transfer transmission buffer flush If a (u) SOF packet is received without an IN token having been received in the interval frame during isochronous data transmission, the controller operates as a IN token had been corrupted, and clears the buffer for which transmission is enabled, putting that buffer in the writing enabled state. If a double buffer is being used at that time and writing has been finished to both buffers, the buffer memory that was cleared is seen as the data having been sent at the same interval frame, and transmission is enabled for the other buffer memory. The timing at which the operation of the buffer flush function begins varies depending on the value set for the IITV bit. (1) If IITV=0 The buffer flush operation starts from the next frame after the pipe becomes valid. (2) In any case other than IITV=0 The buffer flush operation is carried out subsequent to the first normal transaction. Figure 3.27 shows an example of the buffer flush function of the controller. When an unanticipated token prior to the interval frame is received, the controller sends the written data or a Zero-Length packet accordance with buffer state. Buffer A Buffer B Empty state Writing in progress Writing completed Writing in progress Transmission enabled state Writing completed Empty state Writing in progress Writing completed Empty state Transmission enabled state Figure 3.27 Example of buffer flush function operation Figure 3.28 shows an example of the controller generating an interval error. There are five types of interval errors, as noted below. The interval error is generated at the timing indicated by in the illustration, and the IN buffer flush function is activated. If the interval error occurs during an IN transfer, the buffer flush function is activated, and if it occurs during an OUT transfer an NRDY interrupt is generated. The OVRN bit should be used to distinguish between NRDY interrupts such as received packet errors and overrun errors. In response to tokens that are shaded in the illustration, responses occur based on the buffer memory status. (1) IN direction: (a) If the buffer is in the transmission enabled state, the data is transferred as a normal response. (b) If the buffer is in the transmission disabled state, a Zero-Length packet is sent and an underrun error occurs. (2) OUT direction: (a) If the buffer is in the reception enabled state, the data is received as a normal response. (b) If the buffer is in the reception disabled state, the data is decarded and an overrun error occurs. SOF Normal transfer Token Token Token Token Token Token Token corrupted Token Packet inserted Frame misaligned Frame misaligned 1 Token Token Token Token Token Token Token Token 1 Token Token Token 1 1 Token Token Token Token 1 1 Token delayed 1 Token Figure 3.28 Example of interval error being generated when "IITV=1" Rev1.00 2004.10.01 page 93 of 125 M66592FP/WG Rev1.00 2004.10.01 page 94 of 125 M66592FP/WG 3.10 SOF interpolation function If data could not be received at intervals of 1 ms (when using Full-Speed operation) or 125 s (when using Hi-Speed operation) because an SOF packet was corrupted or missing, the controller interpolates the SOF. The SOF interpolation operation begins when "USBE=1", "SCKE=1" and an SOF packet is received. The interpolation function is initialized under the following conditions. (1) H/W reset (2) S/W reset (3) USB bus reset (4) Suspend state detected Also, the SOF interpolation operates under the following specifications. (1) 125 s/1 ms conforms to the results of the reset handshake protocol. (2) The interpolation function is not activated until an SOF packet is received. (3) After the first SOF packet is received, either 125 s or 1 ms is counted at an internal clock of 48 MHz, and interpolation is carried out. (4) After the second and subsequent SOF packets are received, interpolation is carried out at the previous reception interval. (5) Interpolation is not carried out in the suspended state or while a USB bus reset is being received. (With suspended transitions during Hi-Speed operation, interpolation continues for 3 ms after the last packet is received. The contorller supports the following functions based on the SOF detection. Those functions also operate normally with SOF interpolation, if the SOF packet was corrupted. (1) Refreshing of the frame number and micro-frame number (2) SOFR interrupt timing and uSOF lock (3) SOF pulse output (4) Isochronous transfer interval count If an SOF packet is missing when Full-Speed operation is being used, the FRNM bit of the FRMNUM0 register is not refreshed. If a SOF packet is missing during Hi-Speed operation, the UFRNM bit of the FRMNUM1 register is refreshed. However, if a SOF packet for which "FRNM=000" is missing, the FRNM bit is not refreshed. If this happens, the FRNM bit is not refreshed even if successive SOF packets other than "FRNM=000" are received normally. 3.10.1 SOF pulse output When SOF output is enabled, the controller is able to output SOF signals at the timing at which the SOFs are received. When the value of the SOFM bit of the SOFCFG register is "01" (1 ms SOF) or "10" (125s SOF), pulses are output from the SOF_N pin in the "L" active state. These are called "SOF signals". For information on pulse timing, please see Figure 3.29. The controller outputs SOF output based on SOF packet reception events or SOF interpolation events at uniform intervals. 1ms(Full-Speed) / 125us(High-Speed) SOF packet USB Bus SOF SYNC PID FRAME CRC5 minimun 640ns Figure 3.29 SOF output timing Rev1.00 2004.10.01 page 95 of 125 M66592FP/WG 4 Electrical characteristics 4.1 Absolute maximum ratings Symbol VDD VIF AFEA33V AFED33V AFEA15V AFED15V VBUS VI (IO) VO (IO) Pd Tstg Item Core power supply voltage IO power supply voltage USB transceiver analog 3.3V supply voltage USB transceiver digital 3.3V supply voltage USB transceiver analog 1.5V supply voltage USB transceiver digital 1.5V supply voltage VBUS input voltage System interface input voltage System interface output voltage Power consumption Storage M66592FP (LQFP) temperature M66592WG (FBGA) Rated value -0.3~+2.4 -0.3~+4.0 -0.3~+4.0 -0.3~+4.0 -0.3~+2.4 -0.3~+2.4 -0.3~+5.5 -0.3 ~VIF+0.3 -0.3~VIF+0.3 400 -55~+150 -55~+125 Unit V V V V V V V V V mW C C 4.2 Recommended operating conditions Symbol VDD VIF AFEA33V AFED33V AFEA15V AFED15V AFEA33G AFED33G AFEA15G AFED15G DGND VI (IO) VI (VBUS) VO (IO) Topr tr, tf Item Core power supply voltage IO power supply voltage 1.8V supported 3.3V supported USB transceiver analog 3.3V supply voltage USB transceiver digital 3.3V supply voltage USB transceiver 1.5V analog supply voltage USB transceiver digital 1.5V supply voltage USB transceiver analog supply GND USB transceiver digital supply GND USB transceiver analog supply GND USB transceiver digital supply GND Power supply GND System interface input voltage Input voltage (VBUS input only) System interface output voltage Ambient operating temperature Input rise, fall times Normal input Schmitt trigger input 0 0 0 -20 Min. 1.35 1.6 2.7 3.0 3.0 1.35 1.35 Rated value Typ. 1.5 1.8 3.3 3.3 3.3 1.5 1.5 0 0 0 0 0 VIF 5.25 VIF +85 500 5 Max. 1.65 2.0 3.6 3.6 3.6 1.65 1.65 Unit V V V V V V V V V V V V V V V C ns ms +25 Rev1.00 2004.10.01 page 96 of 125 M66592FP/WG 4.3 Electrical characteristics(ratings for VIF = 2.7~3.6V, VDD = 1.35~1.65V) Symbol VIH VIL VIH VIL VT+ VTVTH VOH VOL VOH VOL VOH VOL VT+ VTIIH IIL IOZH IOZL Rdv Rdt Icc (A) Item High input voltage Low input voltage High input voltage Low input voltage Threshold voltage in positive direction Threshold voltage in negative direction Hysteresis voltage High output voltage Low output voltage High output voltage Low output voltage High output voltage Low output voltage Forward direction threshold voltage Reverse direction threshold voltage High input current Low input current High output current in off status Low output current in off status Pull-down resistance Pull-down resistance Average supply current at Hi-Speed operation Average supply current at Full-Speed operation Supply current in static mode Pin capacitance (input) Pin capacitance (input / output) Pin capacitance (D+, D-) Xin Note 1 Note 2 AFEA33V = 3.0V VIF = 2.7V IOH = -50 uA IOL = 50 uA IOH = -2 mA IOL = 2 mA VIF = 2.7V IOH = -4 mA IOL = 4 mA AFED33V = 3.3V Measurement conditions AFEA33V = 3.6V AFEA33V = 3.0V VIF = 3.6V VIF = 2.7V VIF = 3.3V Min. 2.52 0 0.7VIF 0 1.4 0.5 0.8 Xout Note 3 Note 4 Note 5 2.6 0.4 VIF-0.4 0.4 VIF-0.4 1.4 0.5 VIF = 3.6V Note 4 Note 5 Note 6 Note 7 Note 7 Note 7 VIF = 3.6V VI = VIF VI = GND VO = VIF VO = GND 500 50 f(Xin) = 48 MHz VDD = 1.65V, VIF = 3.6V, AFEA33V, AFED33V = 3.6V, AFEA15V, AFED15V = 1.65V f(Xin) = 48 MHz VDD = 1.65V, VIF = 3.6V, AFEA33V, AFED33V = 3.6V, AFEA15V, AFED15V = 1.65V USB suspend state VIF = 3.6V USB cable detached VIF = 3.6V 40 0.4 2.4 1.65 10 -10 10 -10 Rated value Typ. Max. 3.6 0.9 3.6 0.3VIF 2.4 1.65 Unit V V V V V V V V V V V V V V V uA uA uA uA k k mA Icc (A) 18 mA Icc (S) 0.27 0.07 7 7 15 mA mA pF pF pF CIN COUT COUT Note 8 Note 1: A6/ALE, A5-1, TEST, MPBUS input pin, and D15-7, D6/AD6-D1/AD1, D0, SD7-0, DEND0-1_N input / output pins Note 2: CS_N, RD_N, WR0-1_N, DACK0_N, DACK1_N/DSTB0_N, RST_N input pins Note 3: INT_N, SOF_N, DREQ0-1_N output pins, and DEND0-1_N input / output pin Note 4: D15-7, D6/AD6-D1/AD1, D0, SD7-SD0 input / output pins Note 5: VBUS input pin Note 6: TEST input pin Note 7: The supply current is the total of the VDD, VIF, AFEA33V, AFED33V, AFEA15V, and AFED15V currents Note 8: Except D+ and D- Rev1.00 2004.10.01 page 97 of 125 M66592FP/WG 4.4 Electrical characteristics (ratings for VIF = 1.6~2.0V, VDD = 1.35~1.65V) Symbol VIH VIL VIH VIL VT+ VTVTH VOH VOL VOH VOL VOH VOL VT+ VTIIH IIL IOZH IOZL Rdv Rdt Icc(A) Item High input voltage Low input voltage High input voltage Low input voltage Threshold voltage in positive direction Threshold voltage in negative direction Hysteresis voltage High output voltage Low output voltage High output voltage Low output voltage High output voltage Low output voltage Forward direction threshold voltage Reverse direction threshold voltage High input current Low input current High output current in off status Low output current in off status Pull-down resistance Pull-down resistance Average supply current at Hi-Speed operation Average supply current at Full-Speed operation Supply current in static mode Xin Note 1 Note 2 Measurement conditions AFEA33V = 3.6V AFEA33V = 3.0V VIF = 2.0V VIF = 1.6V VIF = 1.8V Min. 2.52 0 0.7VIF 0 0.7 0.2 0.5 Xout Note 3 Note 4 Note 5 AFEA33V = 3.0V VIF = 1.6V IOH = -50 uA IOL = 50 uA IOH = -2 mA IOL = 2 mA VIF = 1.6V IOH = -4 mA IOL = 4 mA AFED33V=3.3V 2.6 0.4 VIF-0.4 0.4 VIF-0.4 1.4 0.5 VIF = 2.0V Note 4 Note 5 Note 6 Note 7 Note 7 Note 7 VIF = 2.0V VI= VIF VI = GND Vo = VIF Vo = GND 500 50 f(Xin) = 48 MHz VDD = 1.65V, VIF = 2.0V, AFEA33V, AFED33V = 3.6V, AFEA15V, AFED15V = 1.65V f(Xin) = 48 MHz VDD = 1.65V, VIF = 2.0V, AFEA33V, AFED33V = 3.6V, AFEA15V, AFED15V = 1.65V USB suspend state VIF = 2.0V USB cable detached VIF = 2.0V 40 0.4 2.4 1.65 10 -10 10 -10 Rated value Stand ard Max. 3.6 0.9 2.0 0.3VIF 1.4 0.8 Unit V V V V V V V V V V V V V V V uA uA uA uA k k mA Icc(A) 18 mA Icc(S) 0.27 0.07 mA mA Pin capacitance (input) 7 pF Pin capacitance (input / Note 7 pF output) 8 COUT Pin capacitance (D+, D-) 15 pF Note 1: A6/ALE, A5-1, TEST, MPBUS input pins, and D15-7, D6/AD6-D1/AD1, D0, SD7-0, DEND0-1_N input / output pins Note 2: CS_N, RD_N, WR0-1_N, DACK0_N, DACK1_N/DSTB0_N, RST_N input pins Note 3: INT_N, SOF_N, DREQ0-1_N output pin, and DEND0-1_N input / output pin Note 4: D15-7, D6/AD6-D1/AD1, D0, SD7-SD0 input / output pins Note 5: VBUS input pin Note 6: TEST input pin Note 7: The supply current is the total of the VDD, VIF, AFEA33V, AFED33V, AFEA15V, AFED15V currents. Note 8: Except D+ and D- CIN COUT Rev1.00 2004.10.01 page 98 of 125 M66592FP/WG 4.5 Measurement circuit 4.5.1 Pins except for USB buffer block VDD input VDD RL=1k SW1 item tdis(CTRL(LZ)) SW1 closed open closed open SW2 open closed open closed P.G. 50 Elements to be measured CL D15-0, tdis(CTRL(HZ)) SD7-0, ta(CTRL(ZL)) DEND0_N, ta(CTRL(ZH)) SW2 DEND1_N RL=1k CL GND (1) Input pulse level : 0 ~ 3.3V, 0 ~ 1.8V Input pulse rise/fall time : tr,tf=3ns Input timing standard voltage : VIF/2 Output timing judge voltage : VIF/2 other output (The tdis (LZ) is judged by 10% of the output amplitude and the tdis (HZ) by 90% of the output amplitude.) (2)The electrostatic capacity CL includes the stray capacitance of the wire connection and the input capacitance of the probe. 4.5.2 USB buffer block (Full-Speed) (1) The tr and tf are judged by the transition time of the 10% amplitude point and 90% amplitude point respectively. (2) The electrostatic capacity CL includes the stray capacitance of the wire connection and the input capacitance of the probe. VDD D+ DP Elements to be measured RL=15K DRL=15K CL DM CL GND 4.5.3 USB buffer block (Hi-Speed) (1) The tr and tf are judged by the transition time of the 10% amplitude point and 90% amplitude point respectively. (2) The electrostatic capacity CL includes the stray capacitance of the wire connection and the input capacitance of the probe. CL VDD D+ Elements to be measured DP RL=45 DRL=45 CL DM GND Rev1.00 2004.10.01 page 99 of 125 M66592FP/WG 4.6 Electrical characteristics (D+/D-) 4.6.1 DC characteristics Symbol RREF Ro Item Reference resistance FS driver output impedance Measurement conditions Min. 5.544 40.5 28 0.9 1.425 2.0 0.8 0.2 0.8 2.5 Rated value Typ. Max. 5.6 5.656 45 49.5 36 44 1.575 3.09 Unit k k k V V V V HS operation FS operation Rpu D+ pull-up resistance Idle status Transmitting and receiving status Input characteristics for Full-Speed operation VIH High input voltage VIL Low input voltage VDI Differential input sensitivity (D+)-(D-) VCM Differential common mode range Output characteristics for Full-Speed operation AFEAVDD = VOL Low output voltage From 1.5K RL 3.0V 3.6V VOH High output voltage From 15K RL GND Single-ended receiver VSE threshold voltage 0.3 2.8 0.8 1.3 3.6 2.0 2.0 V V V V Output signal crossover voltage Input characteristics for Hi-Speed operation VHSSQ Squelch detection threshold voltage (differential) VHSCM Common mode range Output characteristics for Hi-Speed operation VHSOI Idle state VHSOH High output voltage VHSOL Low output voltage VCHIRPJ Chirp J output voltage (differential) VCHIRPK Chirp K output voltage (differential) VORS CL=50 pF 100 -50 -10.0 360 -10.0 700 -900 150 500 10 440 10 1100 -500 mV mV mV mV mV mV mV 4.6.2 AC characteristics (Full-Speed) Item Rise time Fall time Rise / fall time ratio Measurement conditions Data signal: 10% 90% of amplitude Data signal: 90% 10% of amplitude tr/tf CL=50 pF CL=50 pF Min. 4 4 90 Rated value Standa Max. rd 20 20 111.11 Unit ns ns % Symbol Tr Tf TRFM Rev1.00 2004.10.01 page 100 of 125 M66592FP/WG 4.7 Switching characteristics (VIF = 2.7~3.6V, or 1.6~2.0V) Symbol ta (A) tv (A) ta (CTRL - D) tv (CTRL - D) ten (CTRL - D) tdis (CTRL - D) ta (CTRL - DV) tv (CTRL - DV) ta (CTRL - DendV) tv (CTRL - DendV) ta (CTRL - Dend) Item Address access time Time that data is valid after address Time that data can be accessed after control Time that data is valid after control Time that data output is enabled after control Time that data output is disabled after control Time that data can be accessed after control when split bus (DMA Interface) Obus=0 Time that data can is valid after control when split bus (DMA Interface) Obus=0 Time that DEND output can be accessed after control when split bus (DMA Interface) Obus=0 Time that DEND output is valid after control when CPU bus and split bus (DMA Interface) Obus=0 Time that DEND output can be accessed after control when split bus (DMA Interface) Obus=1 Time that DEND output is valid after control when CPU bus and split bus (DMA Interface) Obus=1 Time that DEND output is enabled after control when CPU bus and split bus (DMA Interface) Obus=1 Time that DEND output is disabled after control when CPU bus and split bus (DMA Interface) Obus=1 Time that DREQ is disabled after control Time that DREQ is disabled after control Time that DREQ is enabled after control DREQ output "H" pulse width INT output negated delay time INT output "H" pulse width 650 30 20 50 250 Measurement conditions / other CL=50 pF CL=10 pF CL=50 pF CL=10 pF 2 2 CL=50 pF CL=30 pF CL=10 pF CL=30 pF CL=10 pF CL=30 pF 2 30 2 30 ns ns ns ns 30 30 2 30 Min. Rated value Typ. Max. 40 Unit ns ns ns ns ns ns ns Ref. no. 1 2 3 4 5 6 9 10 11 12 13 tv (CTRL - Dend) ten (CTRL - Dend) tdis (CTRL-Dend) tdis (CTRL - Dreq) tdis (CTRLH -Dreq) ten (CTRL - Dreq) twh (Dreq) td (CTRL - INT) twh (INT) td (DREQ - DV) CL=10 pF 2 2 ns ns 30 70 70 ns ns ns ns ns ns ns 14 15 16 17 18 19 20 21 22 CL=30 pF 0 ns Data access after DREQ begins to be 23 asserted when split bus (DMA Interface) Obus=0 td (DREQ - DendV) Time that DEND can be accessed after 0 ns 24 DREQ begins to be asserted when split bus (DMA Interface) Obus=0 Key ta: Access time, tv: Valid time, ten: Output enabled time, tdis: Output disabled time, td: propagation delay (A): Address, (D): Data, (Dend): DEND, (CTRL): Control, (V): Obus=0 Rev1.00 2004.10.01 page 101 of 125 M66592FP/WG 4.8 Required timing conditions (VIF = 2.7~3.6V, or 1.6~2.0V) Symbol tsuw (A) tsur (A) tsu (A - ALE) thw (A) thr (A) th (A - ALE) tw (ALE) tdwr (ALE - CTRL) trec (ALE) tw (CTRL) trec (CTRL) trecr (CTRL) twr (CTRL) tsu (D) th (D) tsu (Dend) th (Dend) Item Address write setup time Address read setup time Address setup time when using multiplex bus Address write hold time Address read hold time Address setup hold time when using multiplex bus ALE pulse width when using multiplex bus Write / read delay time when using multiplex bus ALE recovery time when using multiplex bus Control pulse width (write) Control recovery time (FIFO) Control recovery time (REG) Control pulse width (read) Data setup time Data hold time DEND input setup time DEND input hold time FIFO access cycle time Measurement conditions / other CL=50 pF Min. 30 0 10 0 30 0 10 7 0 30 30 12 30 20 0 30 0 30 50 84 12 30 30 12 15 0 100 500 Rated value Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Ref. no. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 tw (cycle) tw (CTRL_B) 8-bit FIFO access 16-bit FIFO access 8- / a6-bit FIFO access when using multiplex bus When using split bus, and Obus=0 When using split bus, and Obus=1 *1) When using DMA transfers with CPU bus Control pulse width when using burst transfers 48 trec (CTRL_B) tsud (A) thd (A) tw (RST) tst (RST) Key Control recovery time for burst transfers DMA address write setup time DMA address write hold time Reset pulse width time Control starts time after reset 49 50 51 52 53 tsuw: Write setup time, tsur: Read setup time, tsu: Setup time thw: Write hold time, thr: Read hold time, th: Hold time, tw: Pulse width, twr: Read pulse width tdwr: Read / write delay time, trec: Recovery time, trecr: Register recovery time tsud: DMA setup time, thd: DMA hold time, tst: Start time (A): Address, (D): Data, (CTRL): Control, (CTRL_B): Burst control, (ALE): ALE *1) Only for data writing, when the DACK0_N signal is assuring an active period of at least 30 ns, the DSTB0_N signal can be accessed at a minimum of 12 ns. Rev1.00 2004.10.01 page 102 of 125 M66592FP/WG 4.9 Timing diagrams Table 4.1 Index for register access timing diagram Bus specification Separate bus Separate bus Multiplex bus Multiplex bus access CPU CPU CPU CPU R/W WRITE READ WRITE READ INDEX 4.9.1.1 4.9.1.2 4.9.2.1 4.9.2.2 Note CPU bus 0 CPU bus 0 CPU bus 0 CPU bus 0 Table 4.2 Index for FIFO port access Bus I/F I/F specifications when DFORM OBUS R/W Note INDEX specifications *2) operating CPU CPU bus 0 Separate bus WRITE 4.9.1.1 CPU CPU bus 0 Separate bus READ 4.9.1.2 CPU CPU bus 0 Multiplex bus WRITE 4.9.2.1 CPU CPU bus 0 Multiplex bus READ 4.9.2.2 DMA CPU bus 2 ACK+RD/WR 010 WRITE Cycle steal transfer 4.9.3.1*1) DMA CPU bus 2 ACK+RD/WR 010 READ Cycle steal transfer 4.9.3.2*1) DMA SPLIT bus 1 ACK+STB 110 1 WRITE Cycle steal transfer 4.9.3.3*1) DMA SPLIT bus 1 ACK+STB 110 1 READ Cycle steal transfer 4.9.3.4 *1) DMA SPLIT bus 1 ACK+STB 110 0 WRITE Cycle steal transfer 4.9.3.3 *1) DMA SPLIT bus 1 ACK+STB 110 0 READ Cycle steal transfer 4.9.3.5 *1) DMA CPU bus 1 Separate bus 000 WRITE Cycle steal transfer 4.9.3.6 DMA CPU bus 1 Separate bus 000 READ Cycle steal transfer 4.9.3.7 DMA SPLIT bus 2 ACK only 100 1 WRITE Cycle steal transfer 4.9.3.8 *1) DMA SPLIT bus 2 ACK only 100 1 READ Cycle steal transfer 4.9.3.9*1) DMA SPLIT bus 2 ACK only 100 0 WRITE Cycle steal transfer 4.9.3.8*1) DMA SPLIT bus 2 ACK only 100 0 READ Cycle steal transfer 4.9.3.10*1) DMA CPU bus 3 ACK only 011 WRITE Cycle steal transfer 4.9.3.11*1) DMA CPU bus 3 ACK only 011 READ Cycle steal transfer 4.9.3.12*1) DMA CPU bus 1 Multiplex bus 000 WRITE Cycle steal transfer 4.9.4.1 DMA CPU bus 1 Multiplex bus 000 READ Cycle steal transfer 4.9.4.2 DMA CPU bus 2 ACK+RD/WR 010 WRITE Burst transfer 4.9.5.1*1) DMA CPU bus 2 ACK+RD/WR 010 READ Burst transfer 4.9.5.2*1) DMA SPLIT bus 1 ACK+STB 110 1 WRITE Burst transfer 4.9.5.3*1) DMA SPLIT bus 1 ACK+STB 110 1 READ Burst transfer 4.9.5.4*1) DMA SPLIT bus 1 ACK+STB 110 0 WRITE Burst transfer 4.9.5.3*1) DMA SPLIT bus 1 ACK+STB 110 0 READ Burst transfer 4.9.5.5*1) DMA CPU bus 1 Separate bus 000 WRITE Burst transfer 4.9.5.6 DMA CPU bus 1 Separate bus 000 READ Burst transfer 4.9.5.7 DMA SPLIT bus 2 ACK only 100 1 WRITE Burst transfer 4.9.5.8*1) DMA SPLIT bus 2 ACK only 100 1 READ Burst transfer 4.9.5.9*1) DMA SPLIT bus 2 ACK only 100 0 WRITE Burst transfer 4.9.5.8*1) DMA SPLIT bus 2 ACK only 100 0 READ Burst transfer 4.9.5.10*1) DMA CPU bus 3 ACK only 011 WRITE Burst transfer 4.9.5.11*1) DMA CPU bus 3 ACK only 011 READ Burst transfer 4.9.5.12*1) DMA CPU bus 1 Multiplex bus 000 WRITE Burst transfer 4.9.6.1 DMA CPU bus 1 Multiplex bus 000 READ Burst transfer 4.9.6.2 *1) Because the address signal is not used, the timing will be the same for the separate bus and multiplex bus. *2) For the bus I/F specifications, please refer to 3.4.4.2, DMA control signal selection. The reading and writing timing are carried out using control signal. If the control signal is configured of a combination of multiple signals, the ratings from the falling edge will be valid starting from when the active delay signal changes. The ratings from the rising edge will be valid starting from the change in signals that become inactive more quickly. Rev1.00 2004.10.01 page 103 of 125 Access M66592FP/WG Rev1.00 2004.10.01 page 104 of 125 M66592FP/WG 4.9.1 CPU access timing(when a separate bus is set) 4.9.1.1 CPU access write timing (when a separate bus is set) 30 33 tsuw(A) A6-A1 CS_N thw(A) Address determination Note 1-4 47 39 tw(CTRL) tw(cycle) Note 1-1 41 trec(CTRL), 40 trecr(CTRL) WR1_N, WR0_N Note 1-2 43 44 tsu(D) D15-D0 th(D) Data determination 4.9.1.2 CPU access read timing (when a separate bus is set) 1 ta(A) 31 tsur(A) 34 thr(A) Address determination CS_N Note 1-4 42 47 tw(cycle)Note 1-1 twr(CTRL) RD_N Note 1-3 5 Note 1-1 trec(CTRL), trecr(CTRL) 4 40 41 tv(A) 2 6 ta(CTRL-D) ten(CTRL-D) 3 tv(CTRL-D) tdis(CTRL-D) D15-D0 Data determination Note 1-1: tw (cycle) and trec (CTRL) are necessary when accessing the FIFO. Note 1-2: The control signal when writing data is a combination of CS_N, WR1_N, and WR0_N. Note 1-3: The control signal when reading data is a combination of CS_N and RD_N. Note 1-4: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N should not be timed to fall at the same timing that WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10 ns must be left open. Rev1.00 2004.10.01 page 105 of 125 M66592FP/WG 4.9.2 CPU access timing (when a multiplex bus is set) 4.9.2.1 CPU access write timing (when a multiplex bus is set) 47 tw (cycle) Note 2-1 32 tsu (A - ALE) 35 th (A - ALE) 43 44 tsu (D) th (D) Address determinatio AD6-AD1 / D15-D0 36 Address determination Data determination trec (ALE) 38 tw (ALE) ALE CS_N Note 2-4 WR1_N, WR0_N 37 tdwr (ALE - CTRL) 39 tw (CTRL) Note 2-2 4.9.2.2 CPU access read timing (when a multiplex bus is set) 47 32 35 tw (cycle) Note 2-1 tdis (CTRL - D) tv (CTRL - D) 4 Address determination 6 tsu (A - ALE) Address determination th (A - ALE) AD6-AD1 / D15-D0 36 Data determination ten (CTRL - D) 5 ta (CTRL - D) 3 trec (ALE) 38 tw (ALE) ALE CS_N Note 2-4 37 tdwr (ALE - CTRL) twr (CTRL) 42 RD_N Note 2-3 Note 2-1: tw (cycle) and trec (CTRL) are necessary when accessing the FIFO. Note 2-2: The control signal when writing data is a combination of CS_N, WR1_N, and WR0_N. Note 2-3: The control signal when reading data is a combination of CS_N and RD_N. Note 2-4: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N should not be timed to fall at the same timing that RD_N, WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10 ns must be left open. Rev1.00 2004.10.01 page 106 of 125 M66592FP/WG 4.9.3 DMA access timing(when a cycle steal transfer and separate bus are set) 4.9.3.1 DMA cycle steal transfer write timing (when a CPU bus address is not used: DFORM=010) 17 20 tdis (CTRL - Dreq) DREQi_N (i=0,1) twh (Dreq) Note 3-1 19 ten (CTRL - Dreq) DACKi_N (i=0,1) WR1_N, WR0_N Note 3-8 tw (CTRL) Note 3-2 39 43 44 tsu (D) D15-D0 th (D) Data determination tsu (Dend) 45 th (Dend) 46 DENDi_N (i=0,1) DENDi determination 4.9.3.2 DMA cycle steal transfer read timing(when a CPU bus address is not used: DFORM=010) 17 tdis (CTRL - Dreq) 20 twh (Dreq) DREQi_ N (i=0,1) Note 3-1 19 ten (CTRL - Dreq) DACKi_N (i=0,1) Note 3-8 twr (CTRL) 42 RD_N Note 3-3 5 ta (CTRL - D) 3 tv (CTRL - D) 4 6 ten (CTRL - D) D15-D0 ta (CTRL - DendV) 11 tdis (CTRL - D) Data determination tv (CTRL - DendV) 12 DENDi_N (i=0,1) Note 3-9 DENDi_N determination Rev1.00 2004.10.01 page 107 of 125 M66592FP/WG 4.9.3.3 DMA cycle steal transfer write timing for strobe use (split bus : DFORM=110, OBUS=1/0) 17 20 tdis (CTRL - Dreq) DREQ0_N Note 3-1 DACK0_N tw (CTRL) 39 STRB0_N Note 3-4 43 twh (Dreq) 19 ten (CTRL - Dreq) tsu (D) SD7-SD0 th (D) 44 Data determination tsu (Dend) 45 th (Dend) 46 DEND0_N DEND0_N determination 4.9.3.4 DMA cycle steal transfer read timing for strobe use(split bus : DFORM=110, OBUS=1) 17 tdis (CTRL - Dreq) twh (Dreq) 20 DREQ0_N Note 3-1 DACK0_N twr (CTRL) STRB0_N Note 3-4 5 42 19 ten (CTRL - Dreq) ta (CTRL - D) 3 ten (CTRL - D) SD7-SD0 15 tv (CTRL - D) 4 6 tdis (CTRL - D) Data_N determination ta (CTRL - Dend) 13 ten (CTRL - Dend) 16 tv (CTRL - Dend) tdis (CTRL - Dend) 14 DEND0_N DEND0_N determination Rev1.00 2004.10.01 page 108 of 125 M66592FP/WG 4.9.3.5 DMA cycle steal transfer read timing (split bus : DFORM=110,OBUS=0) DMA transfer begins 17 tdis (CTRL - Dreq) twh (Dreq) 20 DREQ0_N Note 3-1 DACK0_N 42 19 ten (CTRL - Dreq) twr (CTRL) STRB0_N Note 3-4 23 td (DREQ - DV) ta (CTRL - DV) 9 tv (CTRL - DV) 10 SD7-SD0 11 24 td (DREQ - DendV) ta (CTRL - DendV) Data determination tv (CTRL - DendV) 12 DEND0_N DEND0_N determination Rev1.00 2004.10.01 page 109 of 125 M66592FP/WG 4.9.3.6 DMA cycle steal transfer write timing (CPU separate bus setting: DFORM=000) 18 tdis (CTRLH - Dreq) twh (Dreq) 20 ten (CTRL - Dreq) 19 DREQi_N (i=0,1) Note 3-1 50 tsud (A) thd (A) 51 A6-A1 CS_N Note 3-7 Address determination tw (CTRL) 39 WR0_N, WR1_N Note 3-5 tsu (D) 43 D15-D0 45 th (D) 44 Data determination tsu (DEND) th (DEND) 46 DENDi _N (i=0,1) DENDi_N determination 4.9.3.7 DMA cycle steal transfer read timing (CPU separate bus setting: DFORM=000) tdis (CTRL - Dreq) DREQi_N (i=0,1) Note 3-1 31 17 twh (Dreq) 20 ta (A) 1 19 ten (CTRL - Dreq) tsur (A) A6-A1 CS_N Note 3-7 thr (A) 34 Address determination twr (CTRL) RD_N Note 3-6 5 ten (CTRL - D) ta (CTRL - D) 42 tv (A) 3 4 tv (CTRL - D) 2 6 tdis (CTRL - D) D15-D0 ta (CTRL - DendV) 11 Data determination tv (CTRL - DendV) 12 DENDi _N (i=0,1) Note 3-9 DENDi_N determination Rev1.00 2004.10.01 page 110 of 125 M66592FP/WG 4.9.3.8 DMA cycle steal transfer write timing for strobe use (split bus : DFORM=100, OBUS=1/0) tdis (CTRL - Dreq) DREQi_N (i=0, 1) Note 3-1 tw (CTRL) 39 DACKi_N (i=0,1) 43 17 twh (Dreq) 19 20 ten (CTRL - Dreq) tsu (D) th (D) 44 SD7-SD0 45 Data determination tsu (Dend) th (Dend) 46 DENDi_N (i=0,1) DENDi determination 4.9.3.9 DMA cycle steal transfer read timing for strobe use (split bus : DFORM=100, OBUS=1) 17 tdis (CTRL - Dreq) twh (Dreq) 20 DREQi_N (i=0, 1) Note 3-1 twr (CTRL) DACKi_N (i=0,1) 5 19 ten (CTRL - Dreq) 42 ta (CTRL - D) 3 tv (CTRL - D) 4 6 ten (CTRL - D) SD7-SD0 15 tdis (CTRL - D) Data determination ta (CTRL - Dend) 13 tv (CTRL - Dend) 14 16 ten (CTRL - Dend) DENDi_N (i=0, 1) DENDi_N determination tdis (CTRL - Dend) Rev1.00 2004.10.01 page 111 of 125 M66592FP/WG 4.9.3.10 DMA cycle steal transfer read timing when strobe is not used(split bus : DFORM=100, OBUS=0) DMA transfer begins 17 tdis (CTRL - Dreq) twh (Dreq) 20 DREQi_N (i=0, 1) Note 3-1 twr (CTRL) DACKi_N (i=0, 1) 23 42 19 ten (CTRL - Dreq) td (DREQ - DV) ta (CTRL - DV) 9 tv (CTRL - DV) 10 SD7-SD0 11 24 td (DREQ - DendV) ta (CTRL - DendV) Data determination tv (CTRL - DendV) 12 DENDi_N (i=0, 1) Note 3-9 DENDi_N determination Rev1.00 2004.10.01 page 112 of 125 M66592FP/WG 4.9.3.11 DMA cycle steal transfer write timing(CPU bus address not used: DFORM=011) 17 20 tdis (CTRL - Dreq) DREQi_N (i=0,1) Note 3-1 tw (CTRL) Note 3-8 39 twh (Dreq) 19 ten (CTRL - Dreq) DACKi_N (i=0,1) 43 44 tsu (D) D15-D0 th (D) Data determination tsu (Dend) 45 th (Dend) 46 DENDi_N (i=0,1) DENDi determination 4.9.3.12 DMA cycle steal transfer read timing(CPU bus address not used: DFORM=011) 17 tdis (CTRL - Dreq) 20 twh (Dreq) DREQi_N (i=0,1) Note 3-1 twr (CTRL) 42 DACKi_N (i=0,1) Note 3-8 5 ta (CTRL - D) 3 19 ten (CTRL - Dreq) tv (CTRL - D) 4 6 ten (CTRL - D) D15-D0 tdis (CTRL - D) Data determination 11 12 ta (CTRL - DendV) tv (CTRL - DendV) DENDi_N (i=0,1) DENDi_N determination Rev1.00 2004.10.01 page 113 of 125 M66592FP/WG Note 3-1: The inactive condition for DREQi_N (i=0, 1) is the control signal. If there is a next DMA transfer, the delay ratings for twh (Dreq) and ten (CTRL-Dreq) will be valid for the time until DREQi_N becomes active is twh (Dreq). Note 3-2: The control signal when writing data is a combination of DACKi_N, WR1_N, and WR0_N. Note 3-3: The control signal when reading data is a combination of DACKi_N and RD_N. Note 3-4: The control signal when writing data is a combination of DACK0 and DSTRB0_N. Note 3-5: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N. Note 3-6: The control signal when reading data is a combination of CS_N and RD_N. Note 3-7: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N should not be timed to fall at the same timing that RD_N or WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10 ns must be left open. Note 3-8: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that DACKi_N is rising (or falling). Similarly, DACK should not be timed to fall (or rise) at the same timing that RD_N or WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10 ns must be left open. Note 3-9: When the receipt data is one byte, the data determined time is "(23)td(DREQ-DV)" and the DEND determined time is "(24)td(DREQ-DendV)". Rev1.00 2004.10.01 page 114 of 125 M66592FP/WG 4.9.4 DMA access timing(cycle steal transfer, when a multiplex bus is set) 4.9.4.1 DMA cycle steal transfer write timing (CPU multiplex bus setting: DFORM=000) 18 tdis (CTRLH Dreq) twh (Dreq) 20 ten (CTRL - Dreq) 19 DREQi_N (i=0,1) 32 tsu (A - ALE) th (A - ALE) Address determination 35 tsu (D) 43 th (D) 44 Address determination AD6-AD1 / D15-D0 Data determination 38 tw (ALE) 36 trec (ALE) ALE CS_N Note 4-3 37 tdwr (ALE - CTRL) tw (CTRL) 39 WR1_N, WR0_N Note 4-1 45 tsu (DEND) th (DEND) 46 DENDi_N (i=0,1) DENDi_N determination 4.9.4.2 DMA cycle steal transfer read timing (CPU multiplex bus setting: DFORM=000) 17 tdis (CTRL - Dreq) twh (Dreq) 20 19 ten (CTRL - Dreq) DREQi_N (i=0,1) 32 tsu (A - ALE) th (A - ALE) Address determination 35 tdis (CTRL - D) 6 tv (CTRL - D) 4 A6-A1 / D15-A0 36 Data determination ten (CTRL - D) 5 ta (CTRL - D) 3 Address determination tw (ALE) ALE CS_N Note 4-3 37 tdwr (ALE - CTRL) trec (ALE) 38 twr (CTRL) 42 RD_N Note 4-2 DENDi _N (i=0,1) Note 4-4 ta (CTRL - DendV) 11 tv (CTRL - DendV) 12 DENDi_N determination Note 4-1: The control signal when writing data is a combination of CS_N, WR0_N, and WR1_N. Note 4-2: The control signal when reading data is a combination of CS_N and RD_N. Note 4-3: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N should not be timed to fall (or rise) at the same timing that RD_N or WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10 ns must be left open. Note 4-4: When the receipt data is one byte, the DEND determined time is "(24)td(DREQ-DendV)". Rev1.00 2004.10.01 page 115 of 125 M66592FP/WG 4.9.5 DMA access timing (when burst transfer and separate bus are set) 4.9.5.1 DMA burst transfer write timing (CPU bus address not used: DFORM=010) 17 tdis (CTRL - Dreq) 18 tdis (CTRLH - Dreq) DREQi_N (i=0,1) DACKi_N (i=0,1) Note 5-8 48 tw (cycle) 47 WR1_N, WR0_N Note 5-1 tw (CTRL_B) trec (CTRL_B) 49 43 tsu (D) th (D) 44 D15-D0 D0 D1 D2 Dn 45 tsu (Dend) th (Dend) 46 DENDi_N (i=0,1) 4.9.5.2 DMA burst transfer read timing (CPU bus address not used: DFORM=010) 17 tdis (CTRL - Dreq) DREQi_N (i=0,1) DACKi_N (i=0,1) Note 5-8 48 tw (cycle) 47 tw (CTRL_B) trec (CTRL_B) 49 3 RD_N Note 5-2 D15-D0 ta (CTRL - D) tv (CTRL - D) 4 D0 D1 11 Dn-1 ta (CTRL - DendV) Dn 12 tv (CTRL - DendV) DENDi _N (i=0,1) Note 5-6 Rev1.00 2004.10.01 page 116 of 125 M66592FP/WG 4.9.5.3 DMA burst transfer write timing for strobe use(split bus : DFORM=110, OBUS=1/0) 17 tdis (CTRL - Dreq) 18 tdis (CTRLH - Dreq) DREQ0_N DACK0_N 48 tw (cycle) 47 tw (CTRL_B) trec (CTRL_B) 49 DSTRB0_N Note 5-3 43 tsu (D) th (D) 44 SD7-SD0 D0 D1 D2 45 Dn 46 tsu (Dend) th (Dend) DEND0_N 4.9.5.4 DMA burst transfer read timing for strobe use(split bus : DFORM=110, OBUS=1) 17 tdis (CTRL - Dreq) DREQ0_N DACK0_N 48 tw (cycle) 47 tw (CTRL_B) trec (CTRL_B) 49 STRB0_N Note 5-3 3 ta (CTRL - D) SD7-SD0 tv (CTRL - D) 4 D0 D1 13 Dn-1 ta (CTRL - Dend) Dn tv (CTRL - Dend) 14 DEND0_N Rev1.00 2004.10.01 page 117 of 125 M66592FP/WG 4.9.5.5 DMA burst transfer read timing for strobe use (split bus : DFORM=110, OBUS=0) 17 tdis (CTRL - Dreq) DREQ0_N DACK0_N 48 tw (cycle) 47 tw (CTRL_B) trec (CTRL_B) 49 STRB0_N Note 5-3 23 9 td (DREQ - DV) SD7-SD0 Note 5-6 ta (CTRL - DV) tv (CTRL - DV) 10 D0 24 td (DREQ - DendV) D1 11 Dn-1 ta (CTRL - DendV) Dn 12 tv (CTRL - DendV) DEND0_N Note 5-6 Rev1.00 2004.10.01 page 118 of 125 M66592FP/WG 4.9.5.6 DMA burst transfer write timing (separate bus setting: DFORM=000) 17 tdis (CTRL - Dreq) 18 tdis (CTRLH - Dreq) DREQi _N (i=0,1) 50 tsud (A) thd (A) 51 Address determination Address determination Address determination A6-1 CS_N Note 5-7 48 Address determination tw (cycle) 47 tw (CTRL_B) trec (CTRL_B) 49 WR0_N, WR1_N Note 5-4 D15-D0 43 tsu (D) th (D) 44 D0 D1 D2 Dn 46 45 tsu (DEND) th (DEND) DENDi _N (i=0,1) 4.9.5.7 DMA burst transfer read timing(separate bus setting: DFORM=000) tdis (CTRL - Dreq) 17 DREQi_N (i=0,1) 31 tsur (A) thr (A) 34 Address determination Address determination Address determination A6-A1 CS_N Note 5-7 48 Address determination tw (cycle) 47 tw (CTRL_B) trec (CTRL_B) 49 RD_N Note 5-5 3 ta (A) 1 ta (CTRL-D) tv (A) 2 tv (CTRL-D) 4 D15-D0 D0 D1 11 Dn-1 ta (CTRL - DendV) Dn 12 tv (CTRL - DendV) DENDi_N (i=0,1) Note 5-6 Rev1.00 2004.10.01 page 119 of 125 M66592FP/WG 4.9.5.8 DMA burst transfer write timing when no strobe is used (split bus: DFORM=100, OBUS=1/0) 17 tdis (CTRL - Dreq) 18 tdis (CTRLH - Dreq) DREQi_N (i=0, 1) 48 tw (cycle) 47 tw (CTRL_B) trec (CTRL_B) 49 DACKi_N (i=0, 1) 43 tsu (D) th (D) 44 SD7-SD0 D0 D1 D2 Dn 46 45 tsu (Dend) th (Dend) DENDi_N (i=0, 1) 4.9.5.9 DMA burst transfer read timing when no strobe is used (split bus: DFORM=100, OBUS=1) 17 tdis (CTRL - Dreq) DREQi_N (i=0, 1) 48 tw (cycle) 47 tw (CTRL_B) trec (CTRL_B) 49 DACKi_N (i=0, 1) 3 ta (CTRL - D) SD7-SD0 tv (CTRL - D) 4 D0 D1 13 Dn-1 ta (CTRL - Dend) Dn 14 tv (CTRL - DendV) DENDi_N (i=0, 1) Rev1.00 2004.10.01 page 120 of 125 M66592FP/WG 4.9.5.10 DMA burst transfer read timing when no strobe is used (split bus: DFORM=100, OBUS=0) 17 tdis (CTRL - Dreq) DREQi_N (i=0, 1) 48 tw (cycle) 47 tw (CTRL_B) trec (CTRL_B) 49 DACKi_N (i=0, 1) 23 td (DREQ - DV) 9 ta (CTRL - DV) tv (CTRL - DV) 10 SD7-SD0 Note 5-6 DENDi_N (i=0, 1) Note 5-6 D0 24 td (DREQ - DendV) D1 Dn-1 11 ta (CTRL - DendV) Dn 12 tv (CTRL - DendV) Rev1.00 2004.10.01 page 121 of 125 M66592FP/WG 4.9.5.11 DMA Burst transfer write timing (CPU bus address not used: DFORM=011) 17 tdis (CTRL - Dreq) DREQi_N (i=0,1) tw (cycle) 47 18 tdis (CTRLH - Dreq) 48 DACKi_N (i=0,1) tw (CTRL_B) trec (CTRL_B) 49 43 tsu (D) th (D) 44 D15-D0 D0 D1 D2 Dn 45 tsu (Dend) th (Dend) 46 DENDi_N (i=0,1) 4.9.5.12 DMA burst transfer read timing (CPU bus address not used: DFORM=011) 17 tdis (CTRL - Dreq) DREQi_N (i=0,1) 48 tw (cycle) 47 tw (CTRL_B) trec (CTRL_B) 49 DACKi_N (i=0,1) 3 ta (CTRL - D) tv (CTRL - D) 4 D15-D0 D0 D1 11 Dn-1 Dn 12 tv (CTRL - DendV) ta (CTRL - DendV) DENDi _N (i=0,1) Note 5-6 Note 5-1: The control signal when writing data is a combination of DACKi_N(i=0, 1), WR0_N and WR1_N. Note 5-2: The control signal when reading data is a combination of DACKi_N and RD_N. Note 5-3: The control signal when writing data is a combination of DACK0 and DSTRB0_N. Note 5-4: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N. Note 5-5: The control signal when reading data is a combination of CS_N and RD_N. Note 5-6: When the receipt data is one byte, the data determined time is "(23)td(DREQ-DV)" and the DEND determined time is "(24)td(DREQ-DendV)". Note 5-7: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N should not be timed to fall at the same timing that RD_N, WR0_N and WR1_N are rising. In the instances noted above, an interval must be needed at least 10ns. Note 5-8:. RD_N, WR0_N and WR1_N should not be timed to fall at the same time that DACKi_N is rising. Similarly, DACKi_N should not be timed to fall at the same timing that RD_N, WR0_N and WR1_N are rising. In the instances noted above, an interval must be needed at least 10ns. Rev1.00 2004.10.01 page 122 of 125 M66592FP/WG 4.9.6 DMA access timing(burst transfer, when a multiplex bus is set) 4.9.6.1 DMA burst transfer write timing (CPU multiplex bus setting: DFORM=000) 17 tdis (CTRL - Dreq) 18 tdis (CTRLH - Dreq) DREQi_N (i=0, 1) tsu (A - ALE) AD6-AD1 / D15-D0 ALE 32 thw (A - ALE) 35 43 tsu (D) th (D) 44 Address Address D0 tw (cycle) D1 Address Dn tw (ALE) 36 47 CS_N Note 6-3 48 tdwr (ALE_CTRL) 37 trec (CTRL_B) 49 46 45 tsu (DEND) th (DEND) tw (CTRL_B) WR0_N, WR1_N Note 6-1 DENDi_N (i=0, 1) 4.9.6.2 DMA burst transfer read timing(CPU multiplex bus setting: DFORM=000) 17 tdis (CTRL - Dreq) DREQi_N (i=0, 1) tsu (A - ALE) th (A - ALE) 35 AD6-AD1 / D15-D0 32 Address 3 ta (CTRL-D) Address tv (CTRL-D) 4 Address D0 tw (cycle) 47 D1 Dn tw (ALE) ALE 36 CS_N Note 6-3 tdwr (ALE_CTRL) 37 trec (CTRL_B) 49 tw (CTRL_B) 48 RD_N Note 6-2 11 ta (CTRL - DendV) tv (CTRL - DendV) 12 DENDi_N (i=0, 1) Note 6-4 Rev1.00 2004.10.01 page 123 of 125 M66592FP/WG Note 6-1: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N. Note 6-2: The control signal when reading data is a combination of CS_N and RD_N. Note 6-3: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N should not be timed to fall at the same timing that RD_N or WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10 ns must be left open. Note 6-4: When the receipt data is one byte, the DEND determined time is "(24)td(DREQ-DendV)". Rev1.00 2004.10.01 page 124 of 125 M66592FP/WG 4.10 Interrupt timing 22 twh (INT) INT_N 21 td (CTRL - INT) CS_N, WR0_N, WR1_N Note 7-1 Note 7-1: Writing using the combination of CS_N, WR0_N and WR1_N takes place during the active ("L") overlap period. The ratings from the rising edge are valid starting from the earliest change in the inactive signal. 4.11 Reset timing 52 tw (RST) RST_N 53 tst (RST) CS_N, WR0_N, WR1_N Note 8-1 Note 8-1: Writing using the combination of CS_N, WR0_N and WR1_N takes place during the active ("L") overlap period. The ratings from the rising edge are valid starting from the earliest change in the inactive signal. Rev1.00 2004.10.01 page 125 of 125 REVISION HISTORY Rev. 0.80 1.00 M66592 Data Sheet Description Summary Date Jul 12, 2004 Oct 1, 2004 Page 11 (1.7.5) 16-17 (Table2.2) 20 (2.4) 26 (2.4) 31 (2.7) 47 (2.14) 47 (2.14) 50 (3.1.6.1) 51 (3.1.6.2) 53 (3.1.6.5) 55 (3.1.7.3) 57 (3.1.7.4) 57 (3.1.7.5) 59 (3.1.7.6) (3.1.7) 64 (Table 3.7) 64 (Table 3.9) 72 (Table 3.11) 76 (Table 3.13) 77 (3.4.1.4) 81 (Table3.18) 86 (3.6.3) 97,98 Preliminary edition issued First edition issued Deleted: description; " It is also possible to output pulses only when an SOF packet is damaged." Added: the BRDYM bit and the PCSE bit of the INTENB1 register the INBUFM bit of the PIPEnCTR (n=1,2,...,5) Added: note *2) of the DVSTCTR register Deleted: note *3) for the DREQE bit Added: the BRDYM bit and the PCSE bit of the INTENB1 register Added: the INBUFM bit of the PIPEnCTR (n=1,2,...,5) Added and modified: notes of the PIPEnCTR (n=1,2,...,5) Corrected: 2nd row, 1st column of the Table 3.3 ; DPRPU=0 DPRPU=x Added: 3.1.6.2 "Overview of Clock stop state" Added: 3.1.6.5 "Recovering from the clock stop state" Modified: 3.1.7.3 (1) Added: 3.1.7.4 "Stopping the internal clock supply (from the normal operating state to the clock stop state)" Added: 3.1.7.5 "Starting the internal clock supply (from the clock stop state to the normal operating state : with "ATCKM=1")" Added: 3.1.7.6 "Starting the internal clock supply (from the clock stop state to the normal operating state : with "ATCKM=0")" Deleted: 3.1.7.4(previous) "Starting the internal clock supply (from the low-power sleep state to the normal operating state: Auto clock supply function disabled) Added: Description of SORF interrupt Added: Description was added to "Conditions under which a BRDY interrupt is generated" Added: the SHTNAK bit and the INBUFM bit Added: Table 3.13 "Buffer statuses and the INBUFM bit" Added: description; "An access cycle of at least 100 ns is required between "ACLRM=1" and "ACLRM=0"." Added: Note *2) Corrected: Description of (a) and (b) Corrected: Average supply current at Hi-Speed operation: 60mA 40mA Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 http://www.renesas.com (c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .1.0 |
Price & Availability of M66592WG
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |