 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset 74F114 DESCRIPTION The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and complementary outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table regardless of the level at the other inputs. A High level on the clock (CP) input enables the J and K inputs and data will be accepted. The logic levels and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CP. TYPICAL SUPPLY CURRENT (TOTAL) 15mA PIN CONFIGURATION RD K0 J0 SD0 Q0 Q0 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC CP K1 J1 SD1 Q1 Q1 SF00110 ORDERING INFORMATION DESCRIPTION 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F114N N74F114D PKG. DWG. # SOT27-1 SOT108-1 TYPE 74F114 TYPICAL fMAX 100MHz INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS J0, J1 K0, K1 SD0, SD1 RD CP Q0, Q0; Q1, Q1 J inputs K inputs Set inputs (active Low) Reset input (active Low) Clock Pulse input (active falling edge) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/5.0 1.0/10.0 1.0/8.0 50/33 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/3.0mA 20A/6.0mA 20A/4.8mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state. LOGIC SYMBOL 3 11 2 12 IEC/IEEE SYMBOL 1 13 J0 13 4 1 10 CP SD0 RD0 SD1 Q0 Q0 Q1 Q1 10 11 12 5 VCC = Pin 14 GND = Pin 7 6 9 8 J1 K0 K1 4 3 2 R C1 S 1K 1J 5 6 9 8 SF00111 SF00112 1996 Mar 14 1 853-0340 16572 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset 74F114 LOGIC DIAGRAM Q Q SD RD K J CP TO OTHER FLIP-FLOP SF00113 FUNCTION TABLE INPUTS SD L H L H H H H RD H L L H H H H CP X X X J X X X h l h l K X X X l h l l OUTPUTS OPERATING MODE Q H L H* q L H q Q L H H* q H L q Asynchronous Set Asynchronous Reset Undetermined * Toggle Load "0" (Reset) Load "1" (Set) Hold "no change" H = High voltage level h = High voltage level one setup time prior to High-to-Low clock transition L = Low voltage level l = Low voltage level one setup time prior to High-to-Low clock transition q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition X = Don't care = High-to-Low clock transition Asynchronous inputs: Low input to SD sets Q to High level, Low input to RD sets Q to Low level Set and Reset are independent of clock Simultaneous Low on both SD and RD makes both Q and Q High. * = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously. ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 -65 to +150 UNIT V V mA V mA C C 1996 Mar 14 2 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset 74F114 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 -18 -1 20 +70 NOM 5.0 MAX 5.5 V V V mA mA mA C UNIT DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Jn, Kn CP IIL Low-level input current L l li SDn RD IOS ICC Short-circuit output current3 VCC = MAX VCC = MAX -60 15 VCC = MAX, VI = 0 5V MAX 0.5V VCC = MIN, VIL = MAX VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V 10%VCC 5%VCC 10%VCC 5%VCC LIMITS MIN 2.5 V 2.7 3.4 0.35 0.35 -0.73 0.50 V 0.50 -1.2 100 20 -0.6 -4.8 -3.0 -6.0 -150 21 V A A mA mA mA mA mA mA TYP2 MAX UNIT VOH High-level output voltage VOL VIK II IIH Supply current (total)4 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC with the clock input grounded and all outputs open, with the Q and Q outputs High in turn. 1996 Mar 14 3 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset 74F114 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CP to Qn or Qn Propagation delay SDn, RD to Qn or Qn Waveform 1 Waveform 1 Waveform 2,3 85 2.0 2.0 2.0 2.0 TYP 100 5.0 5.5 4.5 4.5 6.5 7.5 6.5 6.5 MAX VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN 80 2.0 2.0 2.0 2.0 7.5 8.5 7.5 7.5 MAX MHz ns ns UNIT AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF, RL = 500 MIN tS(H) tS(L) th(H) th(L) tW(H) tW(L) tW(L) tREC Setup time, High or Low Jn, Kn to CP Hold time, High or Low Jn, Kn to CP CP Pulse width High or Low SDn, RD Pulse width Low Recovery time SDn, RD to CP Waveform 1 Waveform 1 Waveform 1 Waveform 2,3 Waveform 2,3 4.0 3.5 0.0 0.0 4.5 4.5 4.5 4.5 TYP MAX VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN 5.0 4.0 0.0 0.0 5.0 5.0 5.0 5.0 MAX ns ns ns ns ns UNIT AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. Kn Jn, Kn VM ts(L) VM th(L) fmax CP VM tw(L) VM tw(H) tPHL Qn VM tPLH Qn VM VM tPLH VM tPHL VM VM ts(H) Jn VM th(H) Jn Kn SF00114 Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width 1996 Mar 14 4 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset 74F114 Jn, Kn SDn VM tw(L) VM tREC CP VM tPLH Qn VM tPHL Qn VM SF00115 Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock Jn, Kn RD VM tw(L) VM tREC CP tPHL Qn VM tPLH Qn VM VM SF00116 Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width, and Recovery Time for Reset to Clock 1996 Mar 14 5 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset 74F114 TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V) tTLH (tr ) 90% POSITIVE PULSE VM 10% tw tTHL (tf ) AMP (V) 90% VM 10% 0V Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns SF00006 1996 Mar 14 6 |
Price & Availability of N74F114D
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |