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| CY26049-22 FailSafeTM PacketClockTM Global Communications Clock Generator Features * Fully integrated phase-locked loop (PLL) * FailSafe output * PLL driven by a crystal oscillator that is phase aligned with external reference * 100-MHz output from 10-MHz input * Low-jitter, high-accuracy outputs * 3.3V 5% operation * 16-lead TSSOP Benefits * Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external loop filter components * When reference is off, DCXO maintains clock outputs and SAFE pin indicates FailSafe conditions * DCXO maintains continuous operation should the input reference clock fail * Glitch-free transition simplifies system design * Works with commonly available, low-cost 10-MHz crystal * Zero-ppm error for all output frequencies * Compatible across industry standard design platforms * Industry standard package with 6.4 x 5.0 mm2 footprint and a height profile of just 1.1 mm Logic Block Diagram e xte rn a l p u lla b le c rysta l (1 0 M H z ) X IN in p u t re fe re n ce (1 0 M H z ) IC L K F A IL S A F E TM CONTROL D IG IT A L C O N TR O LLE D CRYSTAL O S C IL L A T O R PHASE LO C K E D LO O P CLKA 100M H z XOUT OUTPUT D IV ID E R SAFE IC L K d e te cte d Cypress Semiconductor Corporation Document #: 38-07730 Rev. ** * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised January 12, 2005 CY26049-22 Pin Configuration 16-pin TSSOP Top View ICLK 1 NC 2 NC 3 NC 4 VDD 5 VSS 6 NC 7 XIN 8 16 NC 15 CLKA 14 NC 13 NC 12 VDD 11 VSS 10 SAFE 9 XOUT Pin Description Pin Number Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ICLK NC NC NC VDD VSS NC XIN XOUT SAFE VSS VDD NC NC CLKA NC Reference Input Clock; 10 MHz. No Connect. No Connect. No Connect. Voltage Supply; 3.3V. Ground. No Connect Pullable Crystal Input; 10 MHz. Pullable Crystal Output; 10 MHz. High = reference ICLK within range, Low = reference ICLK out of range. Ground. Voltage Supply; 3.3V. No Connect. No Connect. Clock Output. 100 MHz No Connect. Pin Description Selector Guide Part Number CY26049ZXC-22 Input Frequency Range Reference Input Clock: 10 MHz Crystal: 10-MHz pullable Crystal per Cypress Specification Outputs 1 Output Frequencies 100 MHz Description CY26049-22 is a FailSafe frequency synthesizer with a reference clock input and 100-MHz output. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The continuous, glitch-free operation is achieved by using a DCXO, which serves as a primary clock source. The FailSafe control circuit synchronizes the DCXO oscillator with the reference as long as the reference is within the pull range of the crystal. In the event of a reference clock failure the DCXO maintains the last frequency of the reference clock. The unique feature of the CY26049-22 is that the DCXO is, in fact, the primary clocking source. When the reference clock is restored, the DCXO automatically resynchronizes to the reference. The status of the reference clock input, as detected by the CY26049-22, is reported by the SAFE pin. Document #: 38-07730 Rev. ** Page 2 of 6 CY26049-22 Absolute Maximum Conditions Supply Voltage (VDD) ........................................-0.5 to +7.0V DC Input Voltage...................................... -0.5V to VDD + 0.5 Storage Temperature (Non-Condensing) .... -55C to +125C Junction Temperature ................................ -40C to +125C Data Retention @ Tj = 125C................................ >10 Years Package Power Dissipation...................................... 350 mW ESD (Human Body Model) MIL-STD-883.................... 2000V (Above which the useful life may be impaired. For user guidelines, not tested.) Recommended Pullable Crystal Specifications Parameter FNOM CLNOM R1 R3/R1 DL F3SEPLI F3SEPLO C0 C0/C1 C1 Name Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Ratio of third overtone mode ESR to fundamental mode ESR Crystal drive level Fundamental mode Ratio used because typical R1 values are much less than the maximum spec No external series resistor assumed Comments Parallel resonance, fundamental mode, AT cut Min. - - - 3 - 400 - - 180 14.4 Typ. 10 14 - - 0.5 - - - - 18 Max. - - 25 - 2 - -200 7 250 21.6 fF mW ppm ppm pF Unit MHz pF Third overtone separation from 3*FNOM High side Third overtone separation from 3*FNOM Low side Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance Recommended Operating Conditions Parameter VDD TAC CLOAD tpu Operating Voltage Ambient Temperature (Commercial Temperature) Max Output Load Capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.15 0 - 0.05 Typ. 3.3 - - - Max. 3.45 70 15 500 Unit V C pF ms DC Electrical Specifications (Commercial Temp: 0to 70C) Parameter IOH IOL VIH VIL IIH IIL CIN IDD Description Output High Current Output Low Current Input High Voltage Input High Voltage Input High Current Input Low Current Input Capacitance Supply Current CLOAD = 15 pF, VDD = 3.45V Test Conditions VOH = VDD - 0.5, VDD = 3.3V (source) VOL = 0.5, VDD = 3.3V (sink) CMOS Levels CMOS Levels VIH=VDD VIL=0V Min. 12 12 0.7 - - - - - Typ. 24 24 - - 5 5 - - Max. - - - 0.3 10 10 7 45 Unit mA mA VDD VDD A A pF mA AC Electrical Specifications (Commercial Temp: 0 to 70C) Parameter fICLK-E LR DC = t2/t1 TPJIT1 Description Frequency, Input Clock FailSafe Lock Range Output Duty Cycle Clock Jitter [1] Test Conditions Input Clock Frequency, External Mode Range of reference ICLK for Safe = High Duty Cycle defined in Figure 1, measured at 50% of VDD Period Jitter, Peak to Peak, 10,000 periods RMS Period Jitter Min. - -250 45 - - Typ. 10 - 50 - - Max. Unit - 55 250 50 MHz % ps ps +250 ppm Note: 1. Dependent on crystals chosen and crystal specs. Document #: 38-07730 Rev. ** Page 3 of 6 CY26049-22 AC Electrical Specifications (Commercial Temp: 0 to 70C) (continued) Parameter t6 tfs_lock ferror ER EF Description PLL Lock Time FailSafe Lock Time Frequency Synthesis Error Rising Edge Rate Falling Edge Rate Test Conditions Time for PLL to lock within 150 ppm of target frequency Time for PLL to lock to ICLK (outputs phase aligned with ICLK and Safe = High) Actual mean frequency error vs. target Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Min. - - - 0.8 0.8 Typ. - - 0 1.4 1.4 Max. Unit 3 7 - 2 2 ms s ppm V/ns V/ns Voltage and Timing Definitions t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definition; DC = t2/t1 t3 80% CLK 20% t4 Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4 Test Circuit ICLK 1 2 3 4 16 15 14 13 12 11 10 9 CLKA CLOAD VDD 0.1uF 5 6 7 8 VDD 0.1uF 10MHz Ordering Information Ordering Code Lead-Free CY26049ZXC-22 CY26049ZXC-22T 16-lead TSSOP 16-lead TSSOP--Tape and Reel Commercial 0 to 70C Commercial 0 to 70C Package Type Operating Temperature Range Document #: 38-07730 Rev. ** Page 4 of 6 CY26049-22 Package Drawing and Dimensions 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] PACKAGE WEIGHT 0.05gms 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0-8 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A FailSafe and PacketClock are trademarks of Cypress Semiconductor. Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07730 Rev. ** Page 5 of 6 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY26049-22 Document History Page Document Title: CY26049-22 FailSafeTM PacketClockTM Global Communications Clock Generator Document Number: 38-07730 REV. ** ECN No. 308456 Issue Date See ECN Orig. of Change RGL New Data Sheet Description of Change Document #: 38-07730 Rev. ** Page 6 of 6 |
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