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19-0547; Rev 3; 11/07
KIT ATION EVALU LE B AVAILA
High-Precision Clock Generators with Integrated VCXO
General Description Features
Integrated VCXO Provides a Cost-Effective Solution for High-Precision Clocks 8kHz to 500MHz Input Frequency Range 15MHz to 160MHz Output Frequency Range I2C or SPI Programming for the Input and Output Frequency Selection PLL Lock Range > 60ppm Two Differential Outputs with Three Types of Signaling: LVPECL, LVDS, or HSTL Input Clock Monitor with Hitless Switch Internal Holdover Function within 20ppm of the Nominal Frequency Low Output CLK Jitter: < 0.8ps RMS in the 12kHz to 20MHz Band Low Phase Noise > -130dBc at 100kHz, > -140dBc at 1MHz
MAX9450/MAX9451/MAX9452
The MAX9450/MAX9451/MAX9452 clock generators provide high-precision clocks for timing in SONET/SDH systems or Gigabit Ethernet systems. The MAX9450/ MAX9451/MAX9452 can also provide clocks for the highspeed and high-resolution ADCs and DACs in 3G base stations. Additionally, the devices can also be used as a jitter attenuator for generating high-precision CLK signals. The MAX9450/MAX9451/MAX9452 feature an integrated VCXO. This configuration eliminates the use of an external VCXO and provides a cost-effective solution for generating high-precision clocks. The MAX9450/MAX9451/ MAX9452 feature two differential inputs and clock outputs. The inputs accept LVPECL, LVDS, differential signals, and LVCMOS. The input reference clocks range from 8kHz to 500MHz. The MAX9450/MAX9451/MAX9452 offer LVPECL, HSTL, and LVDS outputs, respectively. The output range is up to 160MHz, depending on the selection of crystal. The input and output frequency selection is implemented through the I 2 C or SPITM interface. The MAX9450/ MAX9451/MAX9452 feature clock output jitter less than 0.8ps RMS (in a 12kHz to 20MHz band) and phasenoise attenuation greater than -130dBc/Hz at 100kHz. The phase-locked loop (PLL) filter can be set externally, and the filter bandwidth can vary from 1Hz to 20kHz. The MAX9450/MAX9451/MAX9452 feature an input clock monitor with a hitless switch. When a failure is detected at the selected reference clock, the device can switch to the other reference clock. The reaction to the recovery of the failed reference clock can be revertive or nonrevertive. If both reference clocks fail, the PLL retains its nominal frequency within a range of 20ppm at +25C. The MAX9450/MAX9451/MAX9452 operate from 2.4V to 3.6V supply and are available in 32-pin TQFP packages with exposed pads.
Ordering Information
PART MAX9450EHJ MAX9451EHJ MAX9452EHJ PIN-PACKAGE 32 TQFP-EP* 32 TQFP-EP* 32 TQFP-EP* OUTPUT LVPECL HSTL LVDS PKG CODE H32E-6 H32E-6 H32E-6
Note: All devices are specified over the -40C to +85C temperature range. For lead-free packages, contact factory. *EP = Exposed paddle.
Pin Configuration
CLK1+ CLK0+ CLK1VDDQ VDDQ 18 GND
TOP VIEW
CLK0-
24
23
22
21
20
19
17
VDD 25 X1 26 X2 27 VDDA 28 LP1 29 LP2 30 GNDA 31 RJ 32
OE 16 CMON 15 AD1 14 AD0 13 SDA 12 SCL 11 GND/CS 10 MR 9 INT 8 IN1-
Applications
SONET/SDH Systems 10 Gigabit Network Routers and Switches 3G Cellular Phone Base Stations General Jitter Attenuation
MAX9450 MAX9451 MAX9452
EXPOSED PAD (GND)
1 LOCK
2 SEL0
3 SEL1
4 IN0+
5 IN0-
6 VDD
7 IN1+
SPI is a trademark of Motorola, Inc.
TQFP (5mm x 5mm)
1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
High-Precision Clock Generators with Integrated VCXO MAX9450/MAX9451/MAX9452
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +4.0V VDDA to GNDA ......................................................-0.3V to +4.0V All Other Pins to GND ...................................-0.3V to VDD + 0.3V Short-Circuit Duration (all pins) ..................................Continuous Continuous Power Dissipation (TA = +85C) 32-Pin TQFP (derate 27.8mW/C above +70C)........2222mW Storage Temperature Range .............................-65C to +165C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) .................................+300C ESD Protection Human Body Model (RD = 1.5k, CS = 100pF) ..............2kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VDDA = VDD = VDDQ = 2.4V to 3.6V, and VDDQ = 1.4V to 1.6V for MAX9451, TA = -40C to +85C. Typical values at VDDA = VDD = VDDQ = 3.3V, and VDDQ = 1.5V for MAX9451, TA = +25C, unless otherwise noted.)
PARAMETER Input High Level Input Low Level Input Current LVCMOS OUTPUT (INT, LOCK) Output High Level Output Low Level THREE-LEVEL INPUT (AD0, AD1) Input High Level Input Low Level Input Open Level Input Current DIFFERENTIAL INPUTS (IN0, IN1) Differential Input High Threshold Differential Input Low Threshold Common-Mode Input-Voltage Range Input Current VIDH VIDL VCOM IIN+, IINVID = VIN+ - VINVID = VIN+ - VINVID = VIN+ - VIN-50 |VID / 2| -1 VDDQ - 1.42 VDDQ - 2.15 VDDQ - 0.4V 2.4 - |VID / 2| +1 VDDQ - 1.00 VDDQ - 1.70 50 mV mV V A VIH2 VIL2 VIO2 IIL2, IIH2 Measured at the opened inputs VIL2 = 0V or VIH2 = VDD 1.05 -15 1.8 0.8 1.35 +15 V V V A VOH1 VOL1 IOH1 = -4mA IOL1 = 4mA VDD - 0.4 0.4 V V SYMBOL VIH1 VIL1 IIN1 VIN = 0V to VDD CONDITIONS MIN 2.0 0 -50 TYP MAX VDD 0.8 +50 UNITS V V A
LVCMOS INPUT (SEL_, CMON, OE, MR)
MAX9450 OUTPUTS (CLK0, CLK1) (LVPECL) Output High Voltage Output Low Voltage VOH2 VOL2 50 load connected to VDDQ - 2.0V 50 load connected to VDDQ - 2.0V V V
MAX9451 OUTPUTS (CLK0, CLK1) (differential HSTL) Output High-Level Voltage Output Low-Level Voltage Differential Output Voltage Change in VOD Between Complementary Output States VOH3 VOL3 VOD VOD With 50 load resistor to GND, Figure 1 With 50 to GND and 16mA sink current With a total 100 load, Figure 1 300 370 10 VDDQ 0.4 450 35 V V mV mV
MAX9452 OUTPUTS (CLK0, CLK1) (LVDS)
2
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High-Precision Clock Generators with Integrated VCXO
DC ELECTRICAL CHARACTERISTICS (continued)
(VDDA = VDD = VDDQ = 2.4V to 3.6V, and VDDQ = 1.4V to 1.6V for MAX9451, TA = -40C to +85C. Typical values at VDDA = VDD = VDDQ = 3.3V, and VDDQ = 1.5V for MAX9451, TA = +25C, unless otherwise noted.)
PARAMETER Output Offset Voltage Change in VOS Between Complementary Output States Output Short-Circuit Current SYMBOL VOS VOS IOS Two output pins connected to GND 0.7 x VDD 0.3 x VDD -1 3mA sink current 10 Output clock frequency = 155MHz Output clock frequency = 155MHz (MAX9450) MAX9450 MAX9451 MAX9452 MAX9450 MAX9451 MAX9452 55 70 65 55 65 14 85 94 88 80 80 25 +1 0.4 CONDITIONS MIN 1.05 TYP 1.2 10 -7.5 MAX 1.35 35 -15 UNITS V mV mA
MAX9450/MAX9451/MAX9452
SERIAL INTERFACE INPUT, OUTPUT (SCL, SDA, CS) Input High Level Input Low Level Input Leakage Current Output Low Level Input Capacitance POWER CONSUMPTION VDD and VDDA Supply Current ICC1 mA VIH VIL IIL VOL CI V V A V pF
VDDQ Supply Current
ICC2
mA
AC ELECTRICAL CHARACTERISTICS
(VDDA = VDD = VDDQ = 2.4V to 3.6V, and VDDQ = 1.4V to 1.6V for MAX9451, TA = -40C to +85C. |VID| = 200mV, VCOM = |VID / 2| to 2.4 - |VID / 2|. Typical values at VDDA = VDD = VDDQ = 3.3V and VDDQ = 1.5V for MAX9451, TA = +25C. CL = 10pF, clock output = 155.5MHz and clock input = 19.44MHz, unless otherwise noted.) (Note 1)
PARAMETER CLK OUTPUTS (CLK0, CLK1) Reference Input Frequency Output Frequency VCXO Pulling Range Output-to-Output Skew Rise Time Fall Time Duty Cycle Period Jitter (RMS) TJ Measured at the band 12kHz to 20MHz 1kHz offset Phase Noise 10kHz offset 100kHz offset 1MHz offset tSKO tR tF fIN fOUT Measured at IN0 or IN1 Measured at CLK0 or CLK1 CL = 8pF (Note 2) Skew between CLK0 and CLK1 (MAX9450 and MAX9452) Skew between CLK0 and CLK1 (MAX9451) 20% to 80% of output swing 80% to 20% of output swing 43 0.8 -70 -110 -130 -140 dBc 50 55 0.4 0.4 0.008 15 500 160 60 90 106 0.590 0.590 56 ns ns % ps MHz MHz ppm ps SYMBOL CONDITIONS MIN TYP MAX UNITS
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High-Precision Clock Generators with Integrated VCXO MAX9450/MAX9451/MAX9452
SERIAL I2C-COMPATIBLE INTERFACE TIMING CHARACTERISTICS
(VDD = 2.4V to 3.6V, TA = -40C to +85C. See Figure 4 for the timing parameters definition.)
PARAMETER Serial Clock Bus Free Time Between STOP and START Conditions Repeated Hold Time START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Clock-Low Period SCL Clock-High Period Maximum Receive SCL/SDA Rise Time Minimum Receive SCL/SDA Rise Time Maximum Receive SCL/SDA Fall Time Minimum Receive SCL/SDA Fall Time Fall Time of SDA, Transmitting Pulse Width of Suppressed Spike Capacitive Load for Each Bus Line SYMBOL fSCL tBUF tHD,STA tSU,STA tSU,STO tHD,DAT tSU,DAT tLOW tHIGH tR tR tF tF tF,TX tSP CB (Note 4) (Note 4) (Note 5) (Note 4) 20 + 0.1Cb 0 (Note 4) (Note 3) 1.3 0.6 0.6 0.6 100 100 1.3 0.7 300 20 + 0.1 x Cb 300 20 + 0.1 x Cb 250 50 400 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s ns ns s s ns ns ns ns ns ns pF
SERIAL SPI INTERFACE TIMING CHARACTERISTICS
(VDD = 2.4V to 3.6V, TA = -40C to +85C. See Figure 7 for the timing parameters definition.)
PARAMETER Serial-Clock Frequency CS Fall to CLK Rise Setup Time DIN Setup Time DIN Hold Time CLK High to CS High CS Pulse-High Time SYMBOL fSCL tCSS tDS tDH tCSH tCSW 12.5 12.5 0 0 20 CONDITIONS MIN TYP MAX 2 UNITS MHz ns ns ns ns ns
Note 1: All timing AC electrical characteristics and timing specifications are guaranteed by design and not production tested. Note 2: The VCXO tracks the input clock frequency by 60ppm. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined regions of SCL's falling edge. Note 4: CB = total capacitance of one bus line in pF. Tested with CB = 400pF. Note 5: Input filters on SDA and SCL suppress noise spikes less than 50ns.
4
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High-Precision Clock Generators with Integrated VCXO
Typical Operating Characteristics
(VDD = VDDA = VDDQ = 3.3V. TA = +25C, unless otherwise noted.)
VDD AND VDDA SUPPLY CURRENT vs. VOLTAGE (MAX9450)
MAX9450 toc01
MAX9450/MAX9451/MAX9452
VDDQ SUPPLY CURRENT vs. VOLTAGE (MAX9450)
MAX9450 toc02
OUTPUT RMS JITTER vs. TEMPERATURE
MAX9450 toc03
80
80
10
72 TA = +25C IDD + IDDA (mA) TA = -40C
72 TA = -40C IDDQ (mA) 64 TA = +25C
8 RMS JITTER (ps)
64
6
56 TA = +85C
56 TA = +85C
4
48
48
2
40 2.4 2.6 2.8 3.0 VOLTAGE (V) 3.2 3.4 3.6
40 2.4 2.6 2.8 3.0 VOLTAGE (V) 3.2 3.4 3.6
0 -40
-15
10
35
60
85
TEMPERATURE (C)
OUTPUT FREQUENCY CHANGE vs. TEMPERATURE
MAX9450 toc04
PHASE NOISE vs. FREQUENCY
0 -20 -40 PHASE NOISE (dBc) -60 -80 -100 -120 -140
MAX9450 toc05
OUTPUT CLOCK SYNCHRONIZED TO INPUT REFERENCE
MAX9450 toc06
40 OUTPUT FREQUENCY CHANGE (ppm)
INPUT REFERENCE = 38.88 MHz OUTPUT CLOCK = 155.52 MHz 153.13mV/div 100mV/div
INPUT REFERENCE = 19.44MHz OUTPUT CLOCK = 155.52 MHz
20
0
-20
-40 -40 -15 10 35 60 85 TEMPERATURE (C)
-160 1k 10k 100k 1M FREQUENCY (Hz) 10M
10ns/div
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High-Precision Clock Generators with Integrated VCXO MAX9450/MAX9451/MAX9452
Pin Description
PIN 1 2, 3 4, 5 6, 25 7, 8 9 10 11 12 13 14, 15 16 17 NAME LOCK FUNCTION Lock Indicator. LOCK goes low when the PLL locks. LOCK is high when the PLL is not locked.
INO_ and IN1_ Select Inputs. Drive SEL0 high to activate IN0; drive SEL1 high to activate IN1. Driving SEL0 SEL0, SEL1 and SEL1 low disables the corresponding input. A 165k pullup resistor pulls SEL0 and SEL1 up to VDD. IN0+, IN0- Differential Reference Input Pair. IN0+ and IN0- accept LVPECL, LVDS, and LVCMOS signals. VDD Digital Power Supply. Connect a 2.4V to 3.6V power supply to VDD. Bypass VDD to GND with a 0.1F capacitor. Reference Input Condition Indicator. A high indicates a failed reference. Master Reset. Drive MR high to reset all I2C registers to their default state and INT to zero. Ground and Chip-Select Input. Connect to GND in I2C mode. This is the chip-select input in SPI mode. Clock Input. SCL is the clock input in I2C bus mode and SPI bus mode. Data Input. SDA is the data input in I2C bus mode and SPI bus mode. I2C Address Selection. Drive AD0 and AD1 high to convert the serial interface from I2C to SPI. GND/CS becomes CS. See Table 3 for the unique addresses list. Clock Monitor. Drive CMON low to enable the clock monitor. Drive CMON high to disable the clock monitor. Output Enable Input. Drive OE low to enable the clock outputs. Driving OE high disables the clock outputs, and the outputs go high impedance. An internal 165k pullup resistor pulls OE up to VDD. Clock-Output Power Supply. Connect a 2.4V to 3.6V power supply to VDDQ for the MAX9450 and MAX9452. Connect a 1.5V power supply to VDDQ for the MAX9451. Connect a 0.1F bypass capacitor from VDDQ to GND. Differential Clock Output 0. The MAX9450 features LVPECL outputs. The MAX9451 features HSTL outputs and the MAX9452 features LVDS outputs. Digital GND Differential Clock Output 1. The MAX9450 features LVPECL outputs. The MAX9451 features HSTL outputs, and the MAX9452 features LVDS outputs. Reference Crystal Input. Connect the reference crystal from X1 to X2. Analog Power Supply. Connect a 2.4V to 3.6V power supply to VDDA. Bypass VDDA to GNDA with a 0.1F capacitor. External Loop Filter. Connect an RC circuit between LP1 and LP2. See the External Loop Filter section. Analog Ground Charge-Pump Set Current. Connect an external resistor to GND to set the charge-pump current. See Table 11. Exposed Paddle. Connect to ground.
IN1+, IN1- Differential Reference Input Pair. IN1+ and IN1- accept LVPECL, LVDS, and LVCMOS signals. INT MR GND/CS SCL SDA AD0, AD1 CMON OE
18, 24
VDDQ CLK0-, CLK0+ GND CLK1-, CLK1+ X1, X2 VDDA LP1, LP2 GNDA RJ EP
19, 20 21 22, 23 26, 27 28 29, 30 31 32 EP
6
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High-Precision Clock Generators with Integrated VCXO
Functional Diagram
6nF 12k TO 200k 60nF 10k CRYSTAL 15MHz TO 160MHz FUNDAMENTAL MODE AND AT CUT
MAX9450/MAX9451/MAX9452
RJ
LP2
LP1
X1
X2
LOCK IN0+ IN00 IN1+ 1 1/P
LOCK DET DIV0 1/N0 PFD/CP LOOP FILTER VCXO DIV1 1/N1 CLK1+ MUX CLK1CLK0+ CLK0-
IN1CMON INT SEL0 SEL1 SCL SDA AD0 AD1 CLK MONITOR
1/M
LUT FOR P
LUT FOR M
OE LUT FOR N1, N2
I2C PORT
CONTROL REGISTERS
GND/CS
SPI PORT
MAX9450 MAX9451 MAX9452
MR
VDDA
GNDA
VDD
GND
Detailed Description
The MAX9450/MAX9451/MAX9452 clock generators provide high-precision clocks for timing in SONET/SDH systems or Gigabit Ethernet systems. The MAX9450/ MAX9451/MAX9452 can also provide clocks for the high-speed and high-resolution ADCs and DACs in 3G base stations. Additionally, the MAX9450/MAX9451/ MAX9452 can be used as a jitter attenuator for generating high-precision clock signals. The MAX9450/MAX9451/MAX9452 feature two differential inputs and two differential clock outputs. The inputs accept LVPECL, LVDS, and LVCMOS signals. The
input reference clock ranges from 8kHz to 500MHz and the output clock ranges from 15MHz to 160MHz. The internal clock monitor observes the condition of the input reference clocks and provides a hitless switch when an input failure is detected. The MAX9450/ MAX9451/MAX9452 also provide holdover in case no input clock is supplied.
Control and Status Registers
The MAX9450/MAX9451/MAX9452 contain eight 8-bit control registers named CR0 to CR7. The registers are accessible through the I2C/SPI interface. CR0 is for the frequency-dividing factor, P. CR1 and CR2 hold the values of the divider, M. CR3 and CR4 are for dividers
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High-Precision Clock Generators with Integrated VCXO MAX9450/MAX9451/MAX9452
N1 and N2, respectively. CR5 and CR6 are the control function registers for output enabling, reference clock selection, and activation of the clock monitor and the holdover function. CR7 contains the status of clock monitor, holdover, and PLL locking. The addresses of the eight registers are shown in Table 4. Tables 5 through 10 show the register maps.
3.3V
LVPECL OUTPUT
127
Z = 50
127
LVPECL INPUT
Output Buffers
Three different output formats (LVPECL, HSTL, and LVDS) are available. Each output contains its own frequency divider. All the output clocks align to their coincident rising edges. After changing the dividing ratio, the output clocks complete the current cycle and stay logic-low until the rising edges of the newly divided clock. When CR5[7] is high, the MAX9450/MAX9451/ MAX9452 set all the outputs to logic-low. Setting the bits CR5[6] and CR5[5] properly enables and disables the outputs individually; see Table 8. A disabled output is always in high impedance. At the receiver end, the two cables or PCB traces can be terminated as shown in Figure 1. The VCXO output is divided down before driving the output buffers. Program the dividing factor through the serial interface. The MAX9450/MAX9451/MAX9452 feature two output dividers DIV0 and DIV1 (see the Functional Diagram). DIV0 drives OUT0 and either DIV0 or DIV1 can drive OUT1. CR6[2] sets which divider output drives OUT1. This function allows for programming OUT1 and OUT0 to different frequencies.
83 83
(A) LVPECL DC-COUPLING
LVDS OUTPUT
Z = 50
LVDS INPUT
100
(B) LVDS COUPLING
HSTL OUTPUT
Z = 50
HSTL INPUT
Reference Clock Inputs
The MAX9450/MAX9451/MAX9452 feature two "anything" differential clock inputs. "Anything" means that the inputs take any differential signals, such as CML, LVDS, LVPECL, or HSTL. The inputs can also take a single-ended input. For example, with LVCMOS reference inputs, connect the inputs to the positive pins INn+ and connect the negative pins INn- to a reference voltage of VDD - 1.32V. See Figure 2. Setting CR5[4] and CR6[3] selects the input reference. Failure detection and revert function apply only to IN0 and IN1. Also, SEL0 and SEL1 or CR5[3:2] can disable the corresponding inputs. See Table 2.
50
50
(C) HSTL DC-COUPLING
Figure 1. DC LVPECL, LVDS, and HSTL Termination
LVCMOS CLK OUTPUT
ANYTHING INPUT
Frequency Selection and Programming
The output frequency at CLKn, (n = 0, 1) is determined by the reference clock and the dividing factors M, Ni (i = 0, 1), and P, shown in the following equation: fCLKn = fREF x M Ni x P
VREF = VDD - 1.32V
Figure 2. Connecting LVCMOS Output to LVPECL Input
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High-Precision Clock Generators with Integrated VCXO
where fCLKn is the frequency at the CLKn output, fREF is the frequency of the reference clock, M (1 to 32,768) is the dividing factor in the feedback loop, Ni (1, 2, 3, 4, 5, 6, 8, 16) are the dividing factors of the outputs, and P (1 to 256) is the dividing factor to the input reference clock. It is possible to set various frequencies at the two differential CLK_ outputs with this configuration. For example, in 10 Gigabit Ethernet or SONET applications, set the dividing factors to generate the required frequencies, as shown in Table 1. Failure-Detection Monitor Reset Reset the fault by toggling CMON from low to high, toggling MR or CR6[4] from low to high, or by toggling the bit CR5[0] from low to high. In revert mode, when the monitor is reset, INT and CR7[5:6] reset to zero and the default input is the one indicated by CR5[4]. Holdover Function The holdover function locks the output frequency to its nominal value within 20ppm. Activate this function by setting CR6[7] to 1. The MAX9450/MAX9451/MAX9452 enter holdover when the devices detect a failure from both input references. Setting CR6[6] to 1 forces the device into the holdover state, while resetting CR6[6] exits holdover. Use a reset holdover. If the revert function is activated once an input is recovered from the failure, the device also exits holdover and switches to the recovered input reference. If both inputs recover simultaneously, the device switches to the default input. VCXO frequency during holdover is the value of the frequency right before the failure of inputs. When CR6[5] goes from 0 to 1, the value of the VCXO frequency is acquired and stored. The VCXO can be switched to this acquired frequency by setting CR6[1] to 1. Such a transition can happen in both the normal mode of operation and the holdover mode.
MAX9450/MAX9451/MAX9452
Input Clock Monitor
Failure Detection The MAX9450/MAX9451/MAX9452 clock-failure-detection function monitors the two reference inputs simultaneously. If a reference input clock signal (IN_) does not transition for two or more VCO cycles, the device reports a failure by setting INT high and bit CR7[6] or CR7[5] to 1. See Table 9. After a reference clock failure, the monitor switches to the other valid input reference. At the same time, the clock monitor loads CR7 with the status of the reference clocks and which input is selected. The mapping of CR7 is given in Table 9. If one of the inputs is disabled according to the bits in CR5[3:2], then the monitor is disabled. Revert Function The response of the MAX9450/MAX9451/MAX9452 to a detected input failure depends on the setting of the revert function. If the failed input recovers from the failure, INT and CR7[5:6] resets to zero if revert is activated. If the recovered input is selected by CR5[4] as the default input reference, the MAX9450/MAX9451/ MAX9452 reselect this input. If the revert function is not activated, once an input failure is detected, the monitor remains in the failure state with INT = 1 and CR7[5:6] = 1, until the MAX9450/MAX9451/MAX9452 are reset. Activate the revert function using the bit CR5[1].
PLL Lock Detect
The MAX9450/MAX9451/MAX9452 also feature PLL lock detection. The MAX9450/MAX9451/MAX9452 compare the frequency of the phase-detector input with the output frequency of the loop frequency divider. When these two frequencies deviate more than 20ppm, the LOCK output goes high. At power-up, LOCK is high. LOCK goes low when the PLL locks. PLL lock time also depends on the loop filter bandwidth.
Table 1. Output Frequency Selection and Register Content Values
10 GIGABIT ETHERNET INPUT CLK: 50MHz CRYSTAL FREQUENCY (MHz) 50 125 125 -- P 2 2 2 -- M 2 5 5 -- Ni 1 2 1 -- OUTPUT FREQUENCY (MHz) 50 62.5 125 -- CRYSTAL FREQUENCY (MHz) 51.84 77.76 155.52 155.52 SONET INPUT CLK: 19.44MHz P 1 1 1 1 M 8 4 8 4 Ni 1 1 1 2 OUTPUT FREQUENCY (MHz) 51.84 77.76 155.52 77.76
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High-Precision Clock Generators with Integrated VCXO MAX9450/MAX9451/MAX9452
External Loop Filter
When the device switches from one input reference to the other or reverts to an input reference from holdover, the output phase changes smoothly during the transition due to the narrowband external PLL filter. The narrower the filter bandwidth is, the smoother the phase transition. However, if bandwidth is too narrow, it can cause some degradation on output jitter performance. Charge-Pump Current Setting The MAX9450/MAX9451/MAX9452 allow external setting of the charge-pump current in the PLL. Connect a resistor from RJ to GNDA to set the PLL charge-pump current: charge-pump current (A) = 2.48 x 1000 / (RSET (k) + 0.375) where RSET is in k and the value of the charge-pump current is in A. Use RSET to adjust the loop response to meet individual application requirements. The charge-pump current and the external filter components change the PLL bandwidth. Table 11 shows the charge-pump current vs. the resistor's value. The loop response equation is defined as: unity-gain bandwidth = (ICP x RFILT x 12kHz) / M where ICP is the charge-pump current set by REXT, RFILT is the external filter resistance, and M is the feedback divider.
I2C Interface
The control interface of the MAX9450/MAX9451/MAX9452 is an I2C or SPI depending on the states of AD0 and AD1. Drive both AD0 and AD1 high to active SPI mode. Otherwise, I2C is activated. The device operates as a slave that sends and receives data through the clock line, SCL, and data line, SDA, to achieve bidirectional communication with the masters. A master (typically a microcontroller) initiates all data transfers to and from slaves, and generates the SCL clock that synchronizes the data transfer. Figure 4 shows the timing of SCL and SDA. The SDA line operates as both an input and an open-drain output. SDA requires a pullup resistor, typically 4.7k. The SCL line operates only as an input. A pullup resistor, typically 4.7k, is required on SCL if there are multiple masters on the 2-wire bus, or if the master in a single-master system has an open-drain SCL output.
I2C Device Address
Every I2C port has a 7-bit device address. This 7-bit address is the slave (MAX9450/MAX9451/MAX9452) ID for the master to write and read. In the MAX9450/ MAX9451/MAX9452, the first 4 bits (1101) of the address are hard coded into the device at the factory. See Table 3. The last 3 bits of the address are input programmable by the three-level AD0 and AD1. This configuration provides eight selectable addresses for the MAX9450/MAX9451/MAX9452, allowing eight devices to be connected to one master.
Input Disable
The two inputs can be disabled separately by SEL0 and SEL1 or the 2 bits in CR5[3:2]. Table 2 shows the state map.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not busy. The active master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 3). The interval between a START and a STOP is called a session.
Power-Up and Master Reset
Upon power-up, default frequency divider rates and the states of the monitor, inputs, and outputs are set according to Table 10. Setting MR high or CR6[4] to 1 also resets the device. When the device resets, INT and CR7[5:6] go low and all the registers revert to their default values.
Table 2. Input Activation by SEL0, SEL1, or CR5[3:2]
SEL1 0 0 1 1 X X X SEL0 0 1 0 1 X X X CR5[3:2] 00 00 00 00 01 10 11 IN1 Disabled Disabled Enabled Enabled Disabled Enabled Enabled IN0 Disabled Enabled Disabled Enabled Enabled Disabled Enabled
SDA
SCL S START CONDITION P STOP CONDITION
Figure 3. START and STOP Conditions
10
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High-Precision Clock Generators with Integrated VCXO
Data Transfer and Acknowledge
Following the START condition, each SCL clock pulse transfers 1 bit. Between a START and a STOP, multiple bytes can be transferred on the 2-wire bus. The first 7 bits (B0-B6) are for the device address. The eighth bit (B7) indicates the writing (low) or reading (high) operation (W/R). The ninth bit (B8) is the ACK for the address and operation type. A low ACK bit indicates a successful transfer; otherwise, a high ACK bit indicates an unsuccessful transfer. The next 8 bits (register address), B9-B16, form the address byte for the control register to be written (Figure 4). The next bit, bit 17, is the ACK for the register address byte. The following byte (Data1)
Write Byte Format S -- ADDRESS 7 bits WR -- ACK -- COMMAND 8 bits ACK -- DATA 8 bits ACK -- P 1
is the content to be written into the addressed register of the slave. After this, the address counter of I2C is increased by 1 (Rgst Addr + 1) and the next byte (Data2) writes into a new register. To read the contents in the MAX9450/MAX9451/MAX9452s' control registers, the master sends the register address to be read to the slave by a writing operation. Then it sends the byte of device address + R to the slave. The slave (MAX9450/ MAX9451/MAX9452) responds with the content bytes from the registers, starting from the pointed register to the last register, CR8, consecutively back to the master (Figures 5 and 6).
MAX9450/MAX9451/MAX9452
Slave address: equivalent to chip-select line of a 3-wire interface Read Byte Format S -- ADDRESS 7 bits WR -- ACK -- COMMAND 8 bits
Command byte: selects to which register you are writing
Data byte: data goes into the register set by the command byte (to set thresholds, configuration masks, and sampling rate) RD -- ACK -- DATA 8 bits /// -- P --
ACK --
S --
ADDRESS 7 bits
Slave address: equivalent to chip-select line Send Byte Format S -- ADDRESS 7 bits WR -- ACK --
Command byte: selects from which register you are reading
Slave address: repeated due to change in dataflow direction Receive Byte Format
Data byte: reads from the register set by the command byte
COMMAND 8 bits
ACK --
P --
S --
ADDRESS 7 bits
RD --
ACK --
DATA 8 bits
/// --
P --
S = Start condition P = Stop condition
Command byte: sends command with no data, usually used for one-shot command Shaded = Slave transmission /// = Not acknowledged
Data byte: reads data from the register commanded by the last read byte or write byte transmission; also used for SMBus alert response return address
Figure 4. I2C Interface Data Structure
A tLOW SMBCLK B tHIGH C D E F G H I J K L M
SMBDATA tSU:STA tHD:STA tSU:DAT A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE tSU:STO E = SLAVE PULLS SMBDATA LINE LOW F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO SLAVE I = MASTER PULLS DATA LINE LOW J = ACKNOWLEDGE CLOCKED INTO SLAVE K = ACKNOWLEDGE CLOCK PULSE L = STOP CONDITION M = NEW START CONDITION tBUF
Figure 5. SMBus Write Timing Diagram ______________________________________________________________________________________ 11
High-Precision Clock Generators with Integrated VCXO MAX9450/MAX9451/MAX9452
A tLOW B tHIGH C D E F G H I J K L M
SMBCLK
SMBDATA tSU:STA tHD:STA tSU:DAT tHD:DAT F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO MASTER H = LSB OF DATA CLOCKED INTO MASTER I = MASTER PULLS DATA LINE LOW
tSU:STO tBUF J = ACKNOWLEDGE CLOCKED INTO SLAVE K = ACKNOWLEDGE CLOCK PULSE L = STOP CONDITION M = NEW START CONDITION
A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE E = SLAVE PULLS SMBDATA LINE LOW
Figure 6. SMBus Read Timing Diagram
SPI Interface
The SPI interface is activated when AD0 = AD1 = high. The SPI port is a write-only interface, and it uses the three inputs: CS, SCL, and SDA. Bit D15 is always zero, indicating the write-only mode, as shown in Figure 5. D14-D8 are the register address bits and D7-D0 are the data bits. In Table 4, the register address mapping is still valid, except the first address bit on the left is not used. D14 is the MSB of the address, and D7 is the MSB of the data. D15-D0 are sent with MSB (D15) first. The maximum SCL frequency is 2MHz.
To perform a write, set D15 = 0, drive CS low, toggle SCL to latch SDA data on the rising edge, then drive CS high after 16 SCL cycles for two SCL cycles to signal the boundary of a 16-bit word (Figure 5). SCL must be low when CS falls at the start of a transmission. Switching of SCL and SDA is ignored unless CS is low. Figure 7 shows the SPI write operation timing diagram and Figure 8 shows SPI register address and data configuration function setting tables.
CS tCSH tCSS SCLK tDS tDS DIN D15 D14 D1 D0 fSCL
tCSW
Figure 7. SPI Write Operation Timing Diagram
CS
SLK D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA
REGISTER ADDRESS
REGISTER DATA
Figure 8. SPI Register Address and Data Configuration Function Setting Tables 12 ______________________________________________________________________________________
High-Precision Clock Generators with Integrated VCXO
Table 3. I2C Address Setting by AD0 and AD1
AD0 Low Low Low Open Open Open High High High AD1 Low Open High Low Open High Low Open High ADDRESS 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 Convert to SPI
MAX9450/MAX9451/MAX9452
Table 6. Dividing Rate Setting for M Divider
CR1 0000-0000 0000-0000 -- 1111-1111 1111-1111 1111-1111 CR2[7:1]* 0000-000 0000-001 -- 0011-110 0011-111 1111-111 DIVIDING VALUE OF M 1 2 -- 8191 8192 32,768
*CR2[0], the last LSB, is reserved.
Table 7. Dividing Rate Setting for N0 and N1 Divider
CR3* 000XXXXX 001XXXXX 010XXXXX 011XXXXX 100XXXXX 101XXXXX 110XXXXX 111XXXXX DIVIDING VALUE OF N0 1 2 3 4 5 6 8 16 CR4* 000XXXXX 001XXXXX 010XXXXX 011XXXXX 100XXXXX 101XXXXX 110XXXXX 111XXXXX DIVIDING VALUE OF N1 1 2 3 4 5 6 8 16
Table 4. I2C and SPI Register Address*
REGISTER NAME CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 REGISTER ADDRESS 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 FUNCTION P divider M divider byte 1 M divider byte 2 N1 divider N2 divider Control Control Status Reserved
*The last 5 LSBs of CR3[4:0] and CR4[4:0] are reserved.
*When the SPI port is activated, the first address bit on the left is omitted and the remaining 7 bits are used. The LSB is the first bit on the right.
Table 5. Dividing Rate Setting for P Divider
CR0 0000-0000 0000-0001 -- 1111-1110 1111-1111 DIVIDING RATE FOR P 1 2 -- 255 256
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High-Precision Clock Generators with Integrated VCXO MAX9450/MAX9451/MAX9452
Table 8. Control Registers and Control Functions
CR5, CR6 CR5[7] CR5[6] CR5[5] CR5[4] FUNCTION Output disable CLK0 enabling CLK1 enabling Default input setting 0: Outputs are enabled 1: Outputs disabled to logic-low 0: CLK0 is disabled to high impedance (overrides CR5[7] = 1 setting) 1: CLK0 is enabled 0: CLK1 is disabled to high impedance (overrides CR5[7] = 1 setting) 1: CLK1 is enabled 0: IN0 is the default input 1: IN1 is the default input 00: The selection is controlled by SEL0, SEL1 (see Table 2) 01: Enable IN0, disable IN1 10: Enable IN1, disable IN0 11: Enable both IN0 and IN1 0: The function is not activated 1: The function is activated 0: Holdover function is disabled 1: Holdover function is enabled 0: Holdover is in normal mode 1: Holdover is forced to be activated As the bit goes from 0 to 1, the current VCXO frequency is taken as the nominal value STATE
CR5[3:2]
Input enabling
CR5[1] CR5[0] CR6[7]
Revert function
CLK monitor reset CLK monitor is reset in revert mode: INT = 0 and CR7[7] = 0, and the PLL switches to the default input Holdover function enabling Forced holdover
CR6[6]
CR6[5] CR6[4] CR6[3] CR6[2] CR6[1] CR6[0]
Acquiring nominal As this bit is toggling from 0 to 1, the current VCXO frequency is taking as the nominal holdover VCXO frequency value Master reset REF ODIV select Acquire select Reserved The bit acts at the same as the input MR; CR6[4] = 1, the chip is reset This bit is always set to zero CR6[2] = 0: DIV0 output drives CLK2 CR6[2] = 1: DIV1 output drives CLK2 CR6[1] = 0 PLL controls the Xtal frequency CR6[1] = 1 Xtal frequency is controlled by the acquired value (acquired at rising edge of CR6[5]) --
Table 9. Mapping for the Input Monitor Status
CR7 CR7[6] CR7[5] CR7[4] CR7[3] CR7[2] CR7[1:0] FUNCTION Status of IN0 Status of IN1 Input clock selection indicator LOCK indicator Holdover status Reserved STATE 0: Normal 1: Failure detected 0: IN0 is currently used 1: IN1 is currently used 1: PLL not locked 0: PLL locked 1: Device is in holdover state 0: Device is in normal state --
Table 10. Register Default Values at Power-Up
REGISTER CR0 CR1 CR2 CR3 CR4 P=1 M=1 M=1 N0 = 1 N1 = 1 1. Outputs enable 2. IN0 is the default input 3. Both inputs are enabled by SEL0 and SEL1 4. Monitor is nonrevertive 5. Holdover is disabled Status Reserved ACTION DEFAULT 00000000 00000000 00000000 00000000 00000000
CR5, CR6
CR5: 01100000 CR6: 00000000
CR7 CR8
00000000 00000000
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High-Precision Clock Generators with Integrated VCXO
Table 11. Resistor Value vs. Charge-Pump Current
RESISTOR (k) 12 20 50 100 150 200 CURRENT (A) 200.5 121.88 49.41 24.86 16.61 12.48
Power-Supply Bypassing
Bypass VDDA, VDD, and VDDQ to ground with high-frequency, surface-mount ceramic 0.1F and 0.01F capacitors. Place the capacitors as close as possible to the device with the 0.01F capacitor closest to the device pins.
MAX9450/MAX9451/MAX9452
Board Layout
Circuit-board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50 (100 for LVDS outputs) characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or vias. Ensure the two traces are parallel and close to each other to increase common-mode noise immunity and reduce EMI. Matching the electrical length of the differential traces further reduces signal skew.
Applications Information
Crystal Selection
The MAX9450/MAX9451/MAX9452 internal VCXO circuitry requires an external crystal. The frequency of the crystal ranges from 15MHz to 160MHz, depending on the application. It is important to use a quartz crystal that prevents reduction of the frequency pulling range, temperature stability, or excessive output phase jitter. Choose an AT-cut crystal that oscillates at the required frequency on its fundamental mode with a variation of 25ppm, including frequency accuracy and operating temperature range. Select a crystal with a load capacitance of 8pF and a motional capacitance of at least 7fF to achieve the specified pulling range. Crystals from manufacturers KDS (www.kdsj.co.jp) and 4Timing (www.4timing.com) are recommended.
Output Termination
Terminate the MAX9450 outputs with 50 to VCC - 2V or use an equivalent thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. The MAX9452 outputs are specified for a 100 load, but can drive 90 to 132 to accommodate various types of interconnects. The termination resistor at the driven receiver should match the differential characteristic impedance of the interconnect and be located close to the receiver input. Use a 1% surface-mount termination resistor.
LVDS Cables and Connectors
The interconnect for LVDS typically has a 100 differential impedance. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic-field-canceling effects.
Chip Information
PROCESS: CMOS
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15
High-Precision Clock Generators with Integrated VCXO MAX9450/MAX9451/MAX9452
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm, EP OPTION
21-0079
F
1 2
16
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32L,TQFP.EPS
High-Precision Clock Generators with Integrated VCXO
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX9450/MAX9451/MAX9452
PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm, EP OPTION
21-0079
F
2 2
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17
High-Precision Clock Generators with Integrated VCXO MAX9450/MAX9451/MAX9452
Revision History
REVISION NUMBER 0 1 2 3 REVISION DATE -- -- 9/06 11/07 Initial release Various changes Various changes Fixed typo in crystal frequency range (Functional Diagram) REVISION DESCRIPTION PAGES CHANGED -- -- 1-4, 7-10, 12, 15, 16 7
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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