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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16520,16520A
VERTICAL DRIVER FOR CCD SENSORS
DESCRIPTION
The PD16520 and PD16520A are vertical drivers for CCD image sensors that have a level conversion circuit and a 3-level output function. Since it incorporates a CCD vertical register driver equivalent to the PD16510 (10
channels, consisting of six 3-level channels and four 2-level channels) and a VOD shutter driver (1 channel), it is ideal as a vertical driver for multiple-electrode high-pixel CCD transfer type area image sensors employed in digital still cameras. The PD16520 and PD16520A use a CMOS process to achieve optimum transmission delay characteristics for vertical driving of CCD image sensors, as well as output on-state resistance characteristics. The PD16520 and
PD16520A also support low-voltage logic (logic power supply voltage: 2.0 to 5.5 V).
FEATURES
* CCD vertical register driver: 10 channels (3-level: 6 channels, 2-level: 4 channels) * VOD shutter driver: 1 channel * High withstanding voltage: 33 V MAX. * Low-output on-state resistance: 30 TYP. * Low-voltage input supported (Logic power supply voltage: 2.0 to 5.5 V) * Latch-up free * Same drive capacity as PD16510 * Small package: 38-pin plastic SSOP (7.62 mm (300) ) * Super small package: 42-pin wafer level CSP
APPLICATIONS
Digital still cameras, digital video cameras, etc.
ORDERING INFORMATION
Part Number Package 38-pin plastic SSOP (7.62 mm (300) ) 42-pin wafer level CSP
PD16520GS-BGG PD16520AFH-2Q1
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S14201EJ3V0DS00 (3rd edition) Date Published February 2005 NS CP(K) Printed in Japan
The mark
shows major revised points.
1999, 2003
PD16520,16520A
1. PIN CONFIGURATION
(1) 38-pin plastic SSOP (7.62 mm (300) )
PD16520GS-BGG (Top view)
GND VCC TI1 TI2 TI3 TI4 TI5 TI6 PG1 PG2 PG3 PG4 PG5 PG6 BI1 BI2 BI3 BI4 SUBI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 VSS VDD1 TO1 VDD2a TO2 TO3 VDD2a TO4 TO5 VDD2A TO6 BO1 BO2 VDD2b BO3 BO4 SUBO Vsb VSS
2
Data Sheet S14201EJ3V0DS
PD16520,16520A
(2) 42-pin wafer level CSP
PD16520AFH-2Q1 (Bottom view)
13 12 11 10 9 8 7 6 5
14 33 32 31 30 29 28 27 4
15 34 42
16 35 36 37 38 39
17 18 19 20 21 22 23 24 1
41 26 3
40 25 2
Index Mark
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin Name BO4 Vsb VSS BI4 BI2 BI1 PG6 PG4 PG3 PG1 TI5 TI3 TI2 TI1
Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin Name VSS VDD1 VDD2a TO2 TO3 TO4 TO5 TO6 BO2 BO3 BO4 SUBO BI3 BI2
Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Pin Name PG5 PG2 TI6 TI4 TI2 GND TO1 VDD2a VDD2a VDD2a BO1 VDD2b SUBI VCC
Data Sheet S14201EJ3V0DS
3
PD16520,16520A
2. BLOCK DIAGRAM
(1) PD16520GS-BGG
GND
1
38 VSS 37 VDD1
VCC TI1 TI2 TI3 TI4 TI5 TI6 PG1
2 3 4 5 6 7 8 9
+ - + - + - + - + - + - + - + - + - + - + - + - + -
3-level
36 TO1 35 VDD2a
3-level
34 TO2
3-level
33 TO3 32 VDD2a
3-level
31 TO4
PG2 10 PG3 11 PG4 12 PG5 13 PG6 14 BI1 15
3-level
30 TO5 29 VDD2a
3-level
28 TO6
2-level
27 BO1
BI2 16
+ -
2-level
26 BO2 25 VDD2b
BI3 17
+ -
2-level
24 BO3
BI4 18
+ -
2-level
23 BO4
SUBI 19
+ -
2-level
22 SUBO 21 Vsb 20 VSS
4
Data Sheet S14201EJ3V0DS
PD16520,16520A
(2) PD16520AFH-2Q1
GND 34
15 VSS 16 VDD1
VCC 42 TI1 14 TI2 13 TI2 33 TI3 12 TI4 32 TI5 11 TI6 31 PG1 10 PG2 30 PG3 PG4 9 8
+ - + - + - + - + - + - + - + - + - + - + - + - + -
3-level
35 TO1 17 VDD2a 36 VDD2a
3-level
18 TO2
3-level
19 TO3 37 VDD2a
3-level
20 TO4
3-level
21 TO5 38 VDD2a
PG5 29 PG6 BI1 7 6
3-level
22 TO6
2-level
39 BO1
BI2
5
+ -
2-level
23 BO2 40 VDD2b
BI2 28
BI3 27
+ -
2-level
24 BO3
BI4
4
+ -
2-level
1
BO4
25 BO4
SUBI 41
+ -
2-level
26 SUBO 2 3 Vsb VSS
Data Sheet S14201EJ3V0DS
5
PD16520,16520A
3. PIN FUNCTIONS
(1) PD16520GS-BGG
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Pin Name GND VCC TI1 TI2 TI3 TI4 TI5 TI6 PG1 PG2 PG3 PG4 PG5 PG6 BI1 BI2 BI3 BI4 SUBI VSS Vsb SUBO BO4 BO3 VDD2b BO2 BO1 TO6 VDD2a TO5 TO4 VDD2a TO3 TO2 VDD2a TO1 VDD1 VSS I/O - - Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input - - Output Output Output - Output Output Output - Output Output - Output Output - Output - - VMa power supply (for 3-level driver) 3-level pulse output VH power supply VL power supply VMa power supply (for 3-level driver) 3-level pulse output 3-level pulse output VMa power supply (for 3-level driver) 3-level pulse output VMb power supply (for 2-level driver) 2-level pulse output VOD shutter drive pulse input VL power supply VHH power supply (for SUB drive) VOD shutter drive pulse output 2-level pulse output 2-level driver input (for charge transfer) (Refer to 4. FUNCTION TABLES.) 3-level driver input (for charge read) (Refer to 4. FUNCTION TABLES.) Ground Logic power supply 3-level driver input (for charge transfer) (Refer to 4. FUNCTION TABLES.) Function
6
Data Sheet S14201EJ3V0DS
PD16520,16520A
(2) PD16520AFH-2Q1
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 BO4 Vsb VSS BI4 BI2 BI1 PG6 PG4 PG3 PG1 TI5 TI3 TI2 TI1 VSS VDD1 VDD2a TO2 TO3 TO4 TO5 TO6 BO2 BO3 BO4 SUBO BI3 BI2 PG5 PG2 TI6 TI4 TI2 GND TO1 VDD2a VDD2a VDD2a BO1 VDD2b SUBI VCC Pin Name I/O Output - - Input Input Input Input Input Input Input Input Input Input Input - - - Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input - Output - - - Output - Input - 2-level pulse output VMb power supply (for 2-level driver) VOD shutter drive pulse input Logic power supply Ground 3-level pulse output VMa power supply (for 3-level driver) VOD shutter drive pulse output 2-level driver input (for charge transfer) (Refer to 4. FUNCTION TABLES.) 3-level driver input (for charge read) (Refer to 4. FUNCTION TABLES.) 3-level driver input (for charge transfer) (Refer to 4. FUNCTION TABLES.) 2-level pulse output VL power supply VH power supply VMa power supply (for 3-level driver) 3-level pulse output 3-level driver input (for charge transfer) (Refer to 4. FUNCTION TABLES.) 3-level driver input (for charge read) (Refer to 4. FUNCTION TABLES.) 2-level pulse output VHH power supply (for SUB drive) VL power supply 2-level driver input (for charge transfer) (Refer to 4. FUNCTION TABLES.) Function
Data Sheet S14201EJ3V0DS
7
PD16520,16520A
4. FUNCTION TABLE (VL = VSS, VMa = VDD2a, VMb = VDD2b, VH = VDD1, VHH = Vsb)
Pins TO1 to TO6
Input Pin Name Pin No. 3 14 4 13, 33 L L H H L H L H VH VMa VL 5 12 6 32 7 11 8 31 9 10 10 30 11 9 12 8 13 29 14 7 36 35 34 18 33 19 31 20 30 21 28 22 TI1 TI2 TI3 TI4 TI5 TI6 PG1 PG2 PG3 PG4 PG5 PG6 TO1 TO2 Output TO3 TO4 TO5 TO6
Remark Pin No. upper row: PD16520GS-BGG, lower row: PD16520AFH-2Q1
Pins BO1 to BO4
Input Pin Name Pin No. 15 6 16 5, 28 L H VMa VL 17 27 28 4 27 39 26 23 24 24 23 1, 25 BI1 BI2 BI3 BI4 BO1 Output BO2 BO3 BO4
Remark Pin No. upper row: PD16520GS-BGG, lower row: PD16520AFH-2Q1
Pin SUBO
Input Pin Name Pin No. 19 41 L H 22 26 VHH VL SUBI Output SUBO
Remark Pin No. upper row: PD16520GS-BGG, lower row: PD16520AFH-2Q1
8
Data Sheet S14201EJ3V0DS
PD16520,16520A
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, GND = 0 V)
Parameter Power supply voltage Symbol VSS VCC VDD1 VDD2 Vsb Input pin voltage Operating ambient temperature Storage temperature Allowable dissipation VI TA Tstg Pd Condition Rating 0 to -10 VSS - 0.3 to VSS + 20.0 VSS - 0.3 to VSS + 33.0 VSS - 0.3 to VSS + 33.0 VSS - 0.3 to VSS + 33.0 VSS - 0.3 to VCC + 0.3 -25 to +85 -40 to +125 Unit V V V V V V C C mW mW
PD16520GS-BGG PD16520AFH-2Q1
500 600
Note
Note Mounted on 8-layer glass epoxy board of 30 mm x 30 mm x 1.6 mm
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions (TA = 25C, GND = 0 V)
Parameter Power supply voltage Symbol VCC VDD1 VDD1-VSS VDD2a VDD2b VSS Vsb-VSS High level input voltage Low level input voltage Operating ambient temperature VIH VIL TA Note 0.8 VCC 0 -20 Note Note Condition MIN. 2.0 10.5 16.5 -1.0 -1.0 -10.0 15.0 TYP. MAX. 5.5 21.0 31.0 +4.0 +4.0 -6.0 31.0 VCC 0.3 VCC +70 Unit V V V V V V V V V C
Note Set VDD1 and VSS to values that satisfy VDD1-VSS rating.
Data Sheet S14201EJ3V0DS
9
PD16520,16520A
Electrical Characteristics (Unless otherwise specified, TA = 25C, VDD1 = +15 V, VDD2a = 0 V, VDD2b = +1.0 V, Vsb = 21.5 V, VCC = +2.5 V, VSS = -7.0 V, GND = 0 V)
Parameter High level output voltage Middle level output voltage Symbol VH VMa VMb Low level output voltage SUB high level output voltage SUB low level output voltage Output on-state resistance VL VsubH VsubL RL RM RH Rsub Transmission delay time 1 Transmission delay time 2 Transmission delay time 3 Rise/fall time 1 Rise/fall time 2 Rise/fall time 3 TD1 TD2 TD3 TP1 TP2 TP3 Refer to Figure 5-1. Output Load Equivalence Circuit and Figure 5-2. Timing Chart. No load, Refer to Figure 5-2. Timing Chart. IO = -20 A IO = -20 A IO = 20 A IO = 20 A IO = -20 A IO = 20 A IO = 10 mA IO = 10 mA IO = -10 mA Condition MIN. VDD1 - 0.1 VDD2a - 0.1 VDD2b VSS Vsb - 0.1 VSS 20 30 30 30 TYP. MAX. VDD1 VDD2a VDD2b + 0.1 VSS + 0.1 Vsb VSS + 0.1 30 45 40 40 200 200 200 500 500 200 Unit V V V V V V ns ns ns ns ns ns
10
Data Sheet S14201EJ3V0DS
PD16520,16520A
Figure 5-1. Output Load Equivalence Circuit
(a) Between output pins
BO4 R10 BO3 R9 BO3' TO2' BO2' R8 BO1' TO4' R7 BO1 TO6' R6 TO6 TO5' R5 TO5 R4 TO3' R3 TO3 BO2 BO4' R1 TO2 TO1' R2 BO3 TO1
(b) Between output pin and GND
BO4 TO1
R10 BO4' R9 BO3' C10 C9
R1 TO1' C1 C2 C3 TO3' R3 TO3 TO2' R2 TO2
BO2
R8 BO2' C8 C4 C7 BO1' R7 C6 TO6' R6 RGND TO5 C5 TO5' R5 TO4 TO4' R4
TO4
BO1
TO6
SUBO C11
Output Load Capacitance Symbol
TO1' TO1' TO2' TO3' TO4' TO5' TO6' BO1' BO2' BO3' BO4' SUBO - C_33 C_33 C_33 C_33 C_33 C_32 C_23 C_32 C_23 - TO2' C_33 - C_33 C_33 C_33 C_33 C_23 C_32 C_23 C_32 - TO3' C_33 C_33 - C_33 C_33 C_33 C_32 C_23 C_32 C_23 - TO4' C_33 C_33 C_33 - C_33 C_33 C_23 C_32 C_23 C_32 - TO5' C_33 C_33 C_33 C_33 - C_33 C_32 C_23 C_32 C_23 - TO6' C_33 C_33 C_33 C_33 C_33 - C_23 C_32 C_23 C_32 - BO1' C_32 C_23 C_32 C_23 C_32 C_23 - C_22 C_22 C_22 - BO2' C_23 C_32 C_23 C_32 C_23 C_32 C_22 - C_22 C_22 - BO3' C_32 C_23 C_32 C_23 C_32 C_23 C_22 C_22 - C_22 - BO4' C_23 C_32 C_23 C_32 C_23 C_32 C_22 C_22 C_22 - - GND C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11
Data Sheet S14201EJ3V0DS
11
PD16520,16520A
Output Load Equivalence Circuit Constants Parameter Vertical register serial resistor Vertical register ground resistor Capacitance 1 between vertical register clocks (3-level - 3-level) Capacitance 2 between vertical register clocks (2-level - 2-level) Capacitance 3 between vertical register clocks (3-level - 2-level) Capacitance 4 between vertical register clocks (2-level - 3-level) Vertical register ground capacitance 1 (3-level) Vertical register ground capacitance 2 (2-level) Substrate ground capacitance Symbol R1 to R10 PGND C_33 C_22 C_32 C_23 C1 to C6 C7 to C10 C11 Constant 0 0 0 pF 0 pF 1000 pF 500 pF 3000 pF 1500 pF 1600 pF
Figure 5-2. Timing Chart
BI1 to BI4 TI1 to TI6 TD1 TD1 VMb VMa BO1 to BO4 TO1 to TO6 VL TP1 TP1
PG1 to PG6
TD2
TD2 VH
TO1 to TO6 VMa TP2 TP2
SUBI
TD3
TD3 VHH
SUBO VL TP3 TP3
12
Data Sheet S14201EJ3V0DS
PD16520,16520A
6. NOTE ON USE
6.1 Power ON/OFF Sequence In the PD16520 and PD16520A, a PN junction (diode) exists between VDD2 VDD1, input pin (TI1 to TI6, PG1 to PG6, BI1 to BI4, and SUBI) VCC, so that in the case of voltage conditions: VDD2 > VDD1, input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, and SUBI) > VCC, an abnormal current flows. Therefore, when turning the power ON/OFF, make sure that the following voltage conditions are satisfied: VDD2 VDD1, input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, and SUBI) VCC. Also, to minimize the negative potential applied to the SUB pin of the CCD image sensor, following the power ON/OFF sequence described below.
(1) Power ON <1> Powering ON VCC Make sure that input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, and SUBI) VCC. Also, when Vsb = 2 V, make sure that VCC reaches the rated voltage. <2> Powering ON Vsb, VDD1, VDD2a, VDD2b and VSS At this time, make SUBI high level (0.8VCC or higher) .
Vsb VDD1
2V
VCC VDD2a, VDD2b 0V <2>
<1>
VSS Time
Data Sheet S14201EJ3V0DS
13
PD16520,16520A
(2) Power OFF <1> Powering OFF Vsb, VDD1, VDD2a, VDD2b and VSS Until VCC power OFF, keep SUBI high level (0.8VCC or higher) . <2> Powering OFF VCC Power OFF VCC when Vsb becomes 2 V or lower. At this time, make sure that the input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, and SUBI) VCC.
<1> Vsb VDD1
<2> VCC VDD2a, VDD2b 2V 0V
VSS Time
6.2 Recommended Connection of Unused Pins Handle input pins and output pins that are not used as follows.
Input pin: High level (connect to VCC) Output pin: Leave open
14
Data Sheet S14201EJ3V0DS
7. APPLICATION CIRCUIT EXAMPLE
VCC
VSS
VDD1
Vsb
VDD2b
VSUB (Substrate voltage)
TG/SSG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
PD16520GS-BGG
GND VCC TI1 TI2 TI3 TI4 TI5 TI6 PG1 PG2 PG3 PG4 PG5 PG6 BI1 BI2 BI3 BI4 SUBI VSS VDD1 TO1 VDD2a
CCD 38 37 36
35 34 TO2 33 TO3 32 VDD2a 31 TO4 30 TO5 29 VDD2a 28 TO6 27 BO1 26 BO2 25 VDD2b 24 BO3 23 BO4 22 SUBO 21 Vsb 20 VSS
Data Sheet S14201EJ3V0DS
0.1 F
+
1 F
PD16520,16520A
1 M
0.1 F 0.1 F 0.1 F 0.1 F
0.1 F
15
PD16520,16520A
8. PACKAGE DRAWINGS
38-PIN PLASTIC SSOP (7.62 mm (300))
38 20 detail of lead end F G
1 A
19 E
P
L
H I S J
C D M
M
N
S
B K
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 12.70.3 0.65 MAX. 0.65 (T.P.) 0.37 +0.05 -0.1 0.1250.075 1.6750.125 1.55 7.70.2 5.60.2 1.050.2 0.2 +0.1 -0.05 0.60.2 0.10 0.10 3 +7 -3 P38GS-65-BGG-1
16
Data Sheet S14201EJ3V0DS
PD16520,16520A
42-PIN WAFER LEVEL CSP (Unit: mm)
wSA
wSB
D
ZD
Pitch 0.5 x (5 - 1) = 2.0
9 8
Pitch 0.5 x (9 - 1) = 4.0
7 6 5 4
INDEX 0.25 loaded yet.
E
3 Solder ball is not 2 1
ZE
INDEX MARK tSAB
E
42 - b
D
C
B
A
xM S A B
C Block
// y1 S
yS
C Block Details
Parameter MIN. D 2.98 E 4.99 ZD - ZE - e t A 0.66 A1 0.18 A2 0.48 b 0.25 y - x - w - y1 -
Standard TYP. MAX. 3.03 3.08 5.04 5.09 0.515 - 0.520 - 0.5 0.15 0.73 0.8 0.23 0.28 0.50 0.52 0.30 0.35 - 0.08 - 0.05 - 0.20 - 0.20
A
A1
A2
Data Sheet S14201EJ3V0DS
17
PD16520,16520A
9. RECOMMENDED SOLDERING CONDITIONS
The PD16520 and PD16520A should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Surface Mount Device
PD16520GS-BGG: 38-pin plastic SSOP (7.62 mm (300) )
Process Infrared reflow Conditions Peak temperature: 235C or below (package surface temperature) , Reflow time: 30 seconds or less (at 210C or higher) , Maximum number of reflow processes: 3 times or less. Vapor phase soldering Peak temperature: 215C or below (package surface temperature) , Reflow time: 40 seconds or less (at 200C or higher) , Maximum number of reflow processes: 3 times or less. Wave soldering Solder temperature: 260C or below, Flow time: 10 seconds or less, Maximum number of flow processes: 1 time, Pre-heating temperature: 120 or below (package surface temperature) . Partial heating method Pin temperature: 300C or below, Heat time: 3 seconds or less (per each side of the device) . - WS60-00-1 VP15-00-3 Symbol IR35-00-3
PD16520AFH-2Q1: 42-pin wafer level CSP
Process Infrared reflow Conditions Peak temperature: 260C or below (package surface temperature) , Reflow time: 60 seconds or less (at 220C or higher) , Maximum number of reflow processes: 3 times or less. Symbol IR60-00-3
Caution Do not use different soldering methods together (except for partial heating) .
REFERENCE DOCUMENTS
NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades on NEC Semiconductor Devices (C11531E)
18
Data Sheet S14201EJ3V0DS
PD16520,16520A
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Data Sheet S14201EJ3V0DS
19

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