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(Preliminary)PL611
s-28
1.8V-3.3V PicoPLL TM , World's Smallest Programmable Clock
FEATURES
* Designed for Very Low-Power applications * Offered in Tiny GREEN/RoHS compliant packages o 6-pin DFN (2.0mmx1.3mmx0.6mm) o 6-pin SC70 (2.3mmx2.25mmx1.0mm) o 6-pin SOT23 (3.0mmx3.0mmx1.35mm) * Input Frequency: o Fundamental Crystal: 10MHz to 50MHz o Reference Input: 1MHz to 200MHz * Accepts >0.1V reference signal input voltage * Output Frequency: o <65MHz @ 1.8V operation o <90MHz @ 2.5V operation o <125MHz @ 3.3V operation * Disabled outputs programmable as HiZ or Active Low. * Low current consumption: o <1.2mA @ 27MHz o < 5 A when PDB is activated * Single 1.8V, 2.5V, or 3.3V 10% power supply * Operating temperature range from -40C to 85C
DESCRIPTION
The PL611s-28 consumes very low-power while producing high performance clock outputs of up to 55MHz. Designed for low-power applications with very stringent space requirement, PL611s-28 consumes about 1.2mA, while producing 2 distinct outputs of 27MHz and 13.5MHz. Designed to fit in a small SOT, SC70, or SOT23 package for high performance applications, the PL611s-28 offers excellent phase noise and jitter performance. The power down feature of PL611s-28, when activated, allows the IC to consume less than 5 A of power, while its programming flexibility allows generating any output, using a low-cost crystal or reference input. In addition, one programmable I/O pin can be configured as Output Enable (OE), Frequency switching (FSEL), Power Down (PDB) input, or CLK1 (FOUT, FREF, FREF/2) output.
PACKAGE PIN CONFIGURATION
GND
XIN/FIN OE, PDB, FSEL, CLK1 GND
1 2 3
6 5 4
CLK0 VDD XOUT
OE, PDB, FSEL, CLK1 GND XIN/FIN
1 2 3
6 5 4
CLK0 VDD XOUT
PL611s-28 PL611s-28 PL611s-28 PL611s-28
PL611s-28 PL611s-28 PL611s-28 PL611s-28
1 2 3
6 5 4
XOUT VDD CLK0
OE, PDB, FSEL, CLK1 XIN/FIN
DFNDFN-6L (2.0mmx1.3mmx0.6mm) mmx1 mmx0 mm)
BLOCK DIAGRAM
XIN/FIN XOUT XTAL F ref R-counter (8-Bit) OSC
M-counter (11-Bit)
Programmable CLoad
Programmable Function
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 1
PL611s-28
SC70 70SC70-6L (2.3mmx2.25mmx1.0mm) mmx2 25mmx1 mm) mmx
SOT23 23SOT23-6L (3.0mmx3.0mmx1.35mm) mmx3 mmx1 35mm) mm
Phase Detector
Charge Pump
Loop Filter
Fvco= Fref * (2 * M / R)
VCO
Fout= Fvco / (2 * P)
P-counter (5-Bit)
CLK0
Programming Logic
OE, FSEL, PDB, CLK1
(Preliminary)PL611
s-28
1.8V-3.3V PicoPLL TM , World's Smallest Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK[0:1] Output Frequency FOUT = FREF * M / (R * P) Where M = 11 bit R = 8 bit P = 5 bit CLK0 = FOUT, FREF or FREF / (2*P) CLK1 = FREF, FREF/2, CLK0 or CLK0/2 Output Drive Strength Three optional drive strengths to choose from: * Low: 4mA * Std: 8mA (default) * High: 16mA Programmable Input/Output One output pin can be configured as: * * * * OE - input PDB - input FSEL - input
HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name Pin Assignment SOT SC70 DFN Pin # Pin# Pin# Type Description
This programmable I/O pin can be configured as an Output Enable (OE) input, Power Down (PDB) input, On-the-Fly Frequency Switching Selector (FSEL)input or CLK1 clock output. This pin has an internal 60K pull up resistor (OE, PDB & FSEL Only). OE, PDB, FSEL, CLK1 1 2 2 I/O The OE and PDB features can be programmed to allow the output to float (Hi Z), or to operate in the `Active low' mode. State 0 1 (default) GND XIN, FIN XOUT VDD CLK0 2 3 4 5 6 1 3 4 5 6 3 1 6 5 4 P I O P O GND connection Crystal or Reference input pin Crystal Output pin Do Not Connect (DNC ) when FIN is present VDD connection Programmable Clock Output OE Disable CLK Normal mode PDB Power Down Mode Normal mode FSEL Frequency `2' Frequency `1'
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 2
(Preliminary)PL611
s-28
1.8V-3.3V PicoPLL TM , World's Smallest Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-28 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-28 accepts a fundamental input crystal of 10MHz to 50MHz or reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 125MHz. This flexible design allows the PL611s-28 to deliver any PLL generated frequency, FREF (Crystal or Ref Clk) frequency or FREF /(2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-28 are mentioned below: PLL Programming The PLL in the PL611s-28 is fully programmable. The PLL is equipped with an 8-bit input frequency divider (R-Counter), and an 11-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 5-bit post VCO divider (PCounter). The output frequency is determined by the following formula [FOUT = FREF * M / (R * P) ]. Clock Output (CLK0) CLK0 is the main clock output. The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), FREF (Crystal or Ref Clk Frequency) output, or FREF/(2*P) output. Clock Output (CLK1) The CLK1 feature allows the PL611s-28 to have an additional clock output. This output can be programmed to one of the following: FREF - Reference (Crystal or Ref Clk) Frequency FREF / 2 CLK0 CLK0 / 2 The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA) for each clock independently. The maximum output frequency is 125MHz. Output Enable (OE) The Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin incorporates a 60k pull up resistor giving a default condition of logic "1". The OE feature can be programmed to allow the output to float (Hi Z), or to operate in the `Active low' mode. Power-Down Control (PDB) The Power Down (PDB) feature allows the user to put the PL611s-28 into "Sleep Mode". When activated (logic `0'), PDB `Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes <10 A of power. The PDB pin incorporates a 60k pull up resistor giving a default condition of logic "1". The PDB feature can be programmed to allow the output to float (Hi Z), or to operate in the `Active low' mode. Frequency Select (FSEL) The Frequency Select (FSEL) feature allows the PL611s-28 to switch between two pre-programmed outputs allowing the device "On the Fly" frequency switching. The FSEL pin incorporates a 60k pull up resistor giving a default condition of logic "1".
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 3
(Preliminary)PL611
s-28
1.8V-3.3V PicoPLL TM , World's Smallest Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature (Green package) Data Retention @ 85C Storage Temperature Ambient Operating Temperature* TS 10 -65 -40 150 85
SYMBOL
VDD VI VO
MIN.
MAX.
7 VDD+0.5 VDD+0.5 260
UNITS
V V V C Year C C
-0.5 -0.5 -0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency (XIN)
CONDITIONS
Fundamental Crystal @ VDD =3.3V
MIN.
10
TYP.
MAX.
50 200 166 133
UNITS
MHz
Input (FIN) Frequency
@ VDD =2.5V @ VDD =1.8V
MHz
Input (FIN) Signal Amplitude Input (FIN) Signal Amplitude
Internally AC coupled (High Frequency) Internally AC coupled (Low Frequency) 3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz @ VDD =3.3V @ VDD =2.5V @ VDD =1.8V
0.9 0.1
VDD VDD 125 90 65 2 10 2
Vpp Vpp MHz MHz MHz ms ns ms ppm ns ns % ps
Output Frequency
Settling Time Output Enable Time VDD Sensitivity Output Rise Time Output Fall Time Duty Cycle
At power-up (after VDD increases over 1.62V) OE Function; Ta=25 C, 15pF Load PDB Function; Ta=25 C, 15pF Load Frequency vs. VDD +/-10% 15pF Load, 10/90% VDD, High Drive, 3.3V 15pF Load, 90/10% VDD, High Drive, 3.3V VDD /2 45 -2 1.2 1.2 50 70
2 1.7 1.7 55
Period Jitter,Pk-to-Pk* With capacitive decoupling between VDD and (measured from 10,000 samples) GND. * Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 4
(Preliminary)PL611
s-28
1.8V-3.3V PicoPLL TM , World's Smallest Programmable Clock
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic with Loaded CMOS Outputs PLL Off: Supply Current, Dynamic, with Loaded CMOS Output PLL Off: Supply Current, Dynamic, with Loaded CMOS Output PLL Off: Supply Current, Dynamic with Loaded CMOS Output Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output Low Voltage Output High Voltage Output Current, Low Drive Output Current, Standard Drive Output Current, High Drive
SYMBOL
IDD IDD IDD IDD IDD IDD IDD VDD VOL VOH IOSD IOSD IOHD
CONDITIONS
@ VDD =3.3V, load=15pF @ VDD =2.5V, load=10pF @ VDD =1.8V, load=5pF @ VDD =3.3V, load=15pF @ VDD =2.5V, load=10pF @ VDD =1.8V, load=5pF When PDB=0 27MHz, 27MHz, 27MHz, 27MHz, 27MHz, 27MHz,
MIN.
TYP.
4.0 2.7 1.2 2.0 1.3 0.8
MAX.
UNITS
mA mA mA mA mA mA
5 1.62 3.63 0.4 VDD - 0.4 4 8 16
A V V V mA mA mA
IOL = +4mA Standard Drive IOH = -4mA Standard Drive VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V
* Note: Please contact PhaseLink, if super-low-power is required.
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency Crystal Loading Rating (The IC can be programmed for any value in this range.) Maximum Sustainable Drive Level Operating Drive Level Metal Can Crystal Shunt Capacitance ESR Max Small SMD Crystal Shunt Capacitance ESR Max C0 ESR C0 ESR 30 5.5 50 2.5 80 pF
SYMBOL
FXIN CL (xtal)
MIN.
10 8
TYP.
MAX.
50 12 100
UNITS
MHz pF W W pF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 5
(Preliminary)PL611
s-28
1.8V-3.3V PicoPLL TM , World's Smallest Programmable Clock
LAYOUT RECOMMENDATIONS
DFN-6L Evaluation Board The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short! - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces as "striplines" or "microstrips" with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth.
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Multiple VDD pins should be decoupled separately for best performance. - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1F for designs using crystals < 50MHz and 0.01F for designs using crystals > 50MHz.
Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer
( Typical buffer impedance 20 50 line
To CMOS Input
Series Resistor
Use value to match output buffer impedance to 50 trace. Typical value 30
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 6
(Preliminary)PL611
s-28
1.8V-3.3V PicoPLL TM , World's Smallest Programmable Clock
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 7
(Preliminary)PL611
s-28
1.8V-3.3V PicoPLL TM , World's Smallest Programmable Clock
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6L Symbol A A1 A2 b c D E H L e SC70-6L Symbol A A1 A2 b c D E H L e DFN-6L
D1
Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.00 0.35 0.55 0.95 BSC
Pin1 Dot
E
H
D
A2 A A1 e b C L
Dimension in MM Min. Max. 0.80 1.00 0.00 0.09 0.80 0.91 0.15 0.30 0.08 0.25 1.85 2.25 1.15 1.35 2.00 2.30 0.21 0.41 0.65BSC
Pin1 Dot
E
H
D
A2 A A1 e b C L
Symbol A A1 A3 b e D E D1 E1 L
Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30
b
e Pin 6 ID Chamfer E1 E
D
L Pin1 Dot A A1
A3
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 8
(Preliminary)PL611
s-28
1.8V-3.3V PicoPLL TM , World's Smallest Programmable Clock
ORDERING INFORMATION (GREEN PACKAGE)
For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range
PL611s-28-XXX X X X
PART NUMBER
3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE G=DFN-6L U=SC70-6L T=SOT23-6L Part/Order Number PL611s-28-XXXGC-R PL611s-28-XXXUC-R PL611s-28-XXXTC-R
NONE= TUBE R=TAPE and REEL TEMPERATURE C=COMMERCIAL I = INDUSTRIAL Marking XXX XXX 28XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SC70 (Tape and Reel) 6-Pin SOT23 (Tape and Reel)
Note: `XXX' designates marking identifier that, at times, could be independent of the part number. Please consult your PhaseLink sales for marking information.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 9

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