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DG508A
Data Sheet September 13, 2004 FN3137.5
CMOS Analog Multiplexers [ /Title (DG50 6A, DG507 A, DG508 A, DG509 A) /Subject CMO Anaog ultilexrs) /Autho () /Keyords Interil orpoation, emionuctor, ultilexer, ux, hanel, atched ideo) /Cretor ()
The DG508A is a CMOS Monolithic 8-Channel Analog Multiplexer, which can also be used as a demultiplexer. An enable input is provided. When the enable input is high, a channel is selected by the address inputs, and when low, all channels are off. A channel in the ON state conducts current equally well in both directions. In the OFF state each channel blocks voltages up to the supply rails. The address inputs and the enable input are TTL and CMOS compatible over the full specified operating temperature range. The DG508A is pinout compatible with the industry standard devices.
Features
* Low Power Consumption * TTL and CMOS-Compatible Address and Enable Inputs * 44V Maximum Power Supply Rating * High Latch-Up Immunity * Break-Before-Make Switching * Alternate Source * Pb-free Available
Applications
* Data Acquisition Systems * Communication Systems * Signal Multiplexing/Demultiplexing * Audio Signal Multiplexing
Ordering Information
PART NUMBER DG508AAK DG508ABK DG508ACJ DG508ACJZ (See Note) TEMP. RANGE (oC) -55 to 125 -25 to 85 0 to 70 0 to 70 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld PDIP (Pb-free) PKG. DWG. # F16.3 F16.3 E16.3 E16.3 A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1
Truth Table
DG508A A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 ON SWITCH None 1 2 3 4 5 6 7 8
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
Pinout
DG508A (PDIP, CERDIP) TOP VIEW
A0 1 16 A1 15 A2 14 GND 13 V+ 12 S5 11 S6 10 S7 9 S8
A0 , A1 , A2 , EN Logic "1" = VAH 2.4V, Logic "0" = VAL 0.8V
EN 2 V- 3 S1 S2 S3 S4 4 5 6 7
D8
1
1-888-INTERSIL or 321-724-7143
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Intersil and Design is a trademark of Intersil Americas Inc. | Copyright (c) Intersil Americas Inc. 2001, 2004
DG508A Functional Diagram
DG508A
S1 S2 S3 S4 S5 S6 S7 S8 A0 A1 A2 EN (ENABLE INPUT) D ADDRESS DECODER 1 OF 8
3 Line Binary Address Inputs (1 0 1) and EN = 1 Above example shows channel 6 turned ON.
Schematic Diagram
V+ V+ SX
LOGIC TRIP POINT REF GND LOGIC AX INPUT OR EN VLOGIC INTERFACE AND LEVEL SHIFTER
DECODER +
-
AX
DX
TYPICAL SWITCH
2
DG508A
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Digital Inputs, VS, VD (Note 1) . . . . . . . . . . . . . .(V- -2V) To (V+ +2V) Continuous Current, (Any Terminal Except S or D) . . . . . . . . . 30mA Continuous Current, (S or D) . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 40mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) 16 Ld CERDIP Package. . . . . . . . . . . . 75 20 16 Ld PDIP Package . . . . . . . . . . . . . . 90 N/A Maximum Junction Temperature CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature "A" and "B" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to 150oC "C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to 125oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Range "A" Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC "B" Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC "C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Signals on SX , D, EN, or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified "A" SUFFIX "B" AND "C" SUFFIX
PARAMETER DYNAMIC CHARACTERISTICS Switching Time of Multiplexer, tTRANSITION Break-Before-Make Interval, tOPEN Enable Turn-ON Time, tON(EN) Enable Turn-OFF Time, tOFF(EN) OFF Isolation, OIRR Source OFF Capacitance, CS(OFF) Drain OFF Capacitance, CD(OFF) Charge Injection, Q
TEST CONDITIONS
(NOTE 4) (NOTE 3) (NOTE 4) (NOTE 4) (NOTE 3) (NOTE 4) MIN TYP MAX MIN TYP MAX UNITS s s s s dB pF pF pC A A A A
See Figure 1 See Figure 3 See Figure 2 See Figure 2 VEN = 0V, RL = 1k, CL = 15pF, VS = 7VRMS , f = 500kHz (Note 5) VS = 0V, VEN = 0V, f = 140kHz VD = 0V, VEN = 0V, f = 140kHz See Figure 4
-
0.6 0.2 1 0.4 68 5 25 4
1 1.5 1.0 -
-
0.6 0.2 1 0.4 68 5 25 4
-
DIGITAL INPUT CHARACTERISTICS Address Input Current, Input Voltage High, IAH VA = 2.4V VA = 15V VA = 0V -10 -10 -10 -0.002 0.006 -0.002 -0.002 10 -10 -10 -10 -0.002 0.006 -0.002 -0.0002 10 -
Address Input Current Input VEN = 2.4V Voltage Low, IAL VEN = 0V ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) (Note 7)
-15 -
270 230
+15 400 400
-15 -
270 230
+15 450 450
V
Sequence Each IS = -200A, VD = +10V Switch ON IS = -200A, VD = -10V VAL = 0.8V, VAH = 2.4V -10V VS +10V r DS(ON)MAX - r DS ( ON )MIN r DS ( ON ) = ----------------------------------------------------------------------r DS ( ON )AVG
rDS(ON) Matching Between Channels
-
6
-
-
6
-
%
3
DG508A
Electrical Specifications
TA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified (Continued) "A" SUFFIX PARAMETER Source OFF Leakage Current, IS(OFF) Drain OFF Leakage Current, ID(OFF) Drain ON Leakage Current, ID(ON) VEN = 0V VEN = 0V TEST CONDITIONS VS = +10V, VD = -10V VS = -10V, VD = +10V VS = -10V, VD = +10V VS = +10V, VD = -10V (Note 6) VD = VS(ALL) = +10V Sequence Each V = V D S(ALL) = -10V Switch ON VAL = 0.8V, VAH = 2.4V "B" AND "C" SUFFIX
(NOTE 4) (NOTE 3) (NOTE 4) (NOTE 4) (NOTE 3) (NOTE 4) MIN TYP MAX MIN TYP MAX UNITS -1 -1 -10 -10 0.002 -0.005 0.01 -0.015 0.015 -0.03 1 1 10 10 -5 -5 -20 -20 0.002 -0.005 0.01 -0.015 0.015 -0.03 5 5 20 20 nA nA nA nA nA nA
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ VEN = 5.0V (Enabled) or Negative Supply Current, I- VEN = 0V (Standby), VA = 0V -1.5 1.3 -0.7 2.4 -1.5 1.3 -0.7 2.4 mA mA
Electrical Specifications
TA = Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified "A" SUFFIX
PARAMETER DIGITAL INPUT CHARACTERISTICS Address Input Current, Input Voltage High, IAH Address Input Current Input Voltage Low, IAL VA = 2.4V VA = 15V VEN = 2.4V VEN = 0V (Note 7)
TEST CONDITIONS
MIN
(NOTE 3) TYP
MAX
UNITS A A A A
-30 VA = 0V -30 -30
-
30 -
ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) Source OFF Leakage Current, IS(OFF) Drain OFF Leakage Current, ID(OFF) Drain ON Leakage Current, ID(ON) POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, IPositive Standby Supply Current, I+ Negative Standby Supply Current, INOTES: 3. Typical values are for design aid only, not guaranteed and not subject to production testing. 4. The algebraic convention whereby the most negative value is a minimum, and the most positive value is a maximum, is used in this data sheet. 5. Off isolation = 20Log |VS |/|VD |, where VS = input to Off switch, and VD = output due to VS . 6. ID(ON) is leakage from driver into "ON" switch. 7. Parameter not tested. Parameter guaranteed by design or characterization. VEN = 0V, VA = 0V VEN = 5.0V, VA = 0V -3.2 -3.2 -3.2 -3.2 4.5 4.5 4.5 4.5 mA mA mA mA -15 IS = -200A, VD = +10V IS = -200A, VD = -10V VS = +10V, VD = -10V VS = -10V, VD = +10V VEN = 0V VS = -10V, VD = +10V VS = +10V, VD = -10V (Note 6) Sequence Each Switch ON VD = VS(ALL) = +10V VAL = 0.8V, VAH = 2.4V VD = VS(ALL) = -10V -50 -200 -200 +15 500 500 50 200 200 V nA nA nA nA nA nA
Sequence Each Switch ON VAL = 0.8V, VAH = 2.4V VEN = 0V
4
DG508A Test Circuits and Waveforms
+2.4V +15V V+ EN DG508A S1 +10V LOGIC INPUT 3V 50% 0 VS1 S1 ON 0.8VS1 SWITCH OUTPUT VO SWITCH OUTPUT VO 1M -15V 35pF TRANSITION TIME tr < 20ns tf < 20ns
S2 THRU S7 A2 A1 LOGIC INPUT 50 A0 GND S8 -10V
0
D V-
0.8VS8 VS8 S8 ON TRANSITION TIME
FIGURE 1A. TEST CIRCUIT FIGURE 1. SWITCHING TIME
+15V V+ EN DG508A S2 THRU S8 A2 A1 A0 EN 50 GND V-15V D 1k SWITCH OUTPUT VO 35pF SWITCH OUTPUT VO S1 -5V EN
FIGURE 1B. MEASUREMENT POINTS
3V 50% 0V tON (EN) 0V
tr < 20ns tf < 20ns 50% tOFF (EN)
0.1VO
VO
0.9VO
FIGURE 2A. TEST CIRCUIT FIGURE 2. ENABLE TIMES
+2.4V V+ EN S1 THRU S8 DG508A +5V (VS) LOGIC INPUT +15V
FIGURE 2B. MEASUREMENT POINTS
3V
tr < 20ns tf < 20ns
A0 A1
0V
VS A2 D GND 50 -15V V1k 35pF SWITCH OUTPUT VO SWITCH OUTPUT VO 0V tOPEN 50% 50%
LOGIC INPUT
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
5
DG508A Test Circuits and Waveforms
+15V V+ EN DG508A S1 A2 A1 VO A0 LOGIC INPUT GND V1000pF -15V D VO EN 0 3V
(Continued)
VO
VO is the measured voltage error due to charge injection. The charge transfer error in Coulombs is Q = CL x VO . FIGURE 4B. CHARGE INJECTION WAVEFORMS
FIGURE 4A. TEST CIRCUIT
FIGURE 4. CHARGE INJECTION
Typical Performance Curves
550 V+ = +15V, V- = -15V V+ = +10V, V- = -10V 450 V+ = +12V, V- = -12V V+ = +7.5V, V- = -7.5V 400 500 rDS(ON) () rDS(ON) () 350 300 250 200 150 100 50 0 -15 -10 -5 0 5 10 15 0 -55 -25 0 20 45 70 100 125 100 400 V+ = +15V V- = -15V VEN = 2.4V IO = -200A 300 -10V SIGNALS 200 +10V SIGNALS
ANALOG SIGNAL VOLTAGE (V)
TEMPERATURE (oC)
FIGURE 5. rDS(ON) vs ANALOG SIGNAL VOLTAGE vs SUPPLY VOLTAGE
FIGURE 6. TYPICAL rDS(ON) VARIATION WITH TEMPERATURE
6
DG508A Die Characteristics
DIE DIMENSIONS: 3100m x 2083m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kA 1.4kA Nitride: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG508A
EN A0 A1 A2
GND
VV+
S1
S5
S2
S6
S3 S4 D S8
S7
7
DG508A Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150
2.54 BSC 7.62 BSC 2.93 16 10.92 3.81
8
DG508A Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 9

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