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| SI4724CY Vishay Siliconix N-Channel Synchronous MOSFETs with Break-Before-Make FEATURES D D D D D 0- to 30-V Operation Driver Impedance--3 W Undervoltage Lockout Fast Switching Times 30-V MOSFETs D D D D High Side: 0.0375 W @ VDD = 4.5 V Low Side: 0.029 W @ VDD = 4.5 V Switching Frequency: 250 kHz to 1 MHz Integrated Schottky DESCRIPTION The SI4724CY n-channel synchronous MOSFET with break-before-make (BBM) is a high speed driver designed to operate in high frequency dc-dc switchmode power supplies. It's purpose is to simplify the use of n-channel MOSFETs in high frequency buck regulators. This device is designed to be used with any single output PWM IC or ASIC to produce a highly efficient low cost synchronous rectifier converter. A synchronous enable pin (disable = low, enable = high) controls the synchronous function for light load conditions. The SI4724CY is packaged in Vishay Siliconix's high performance LITTLE FOOTR SO-16 package. FUNCTIONAL BLOCK DIAGRAM VDD BOOT D1 Level Shift Undervoltage Lockout VDD IN SYNC EN Q1 S1 D2 Q2 + GND S2 VREF Document Number: 71863 S-03922--Rev. D, 19-May-03 www.vishay.com 1 SI4724CY Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED) Parameter Logic Supply Logic Inputs Drain Voltage Bootstrap Voltage Synchronous Pin Voltage TA = 25_C Continuous Drain Current TA =70_C TA = 25_C TA =70_C Maximum Power Dissipationa Driver Operating Junction and Storage Temperature Range MOSFETs Tj, Tstg Symbol VDD VIN VD1 VBOOT VSYNC ID1 ID2 PD Steady State 7 - 0.7 to VDD + 0.3 30 VS1 + 7 - 0.7 to VDD +0.3 5.1 4.09 6.5 5.2 1.2 - 65 to 125 - 65 to 150 Unit V A W _C Notes a. Surface mounted on 1" x1" FR4 board, full copper two sides. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Drain Voltage Logic Supply Input Logic High Voltage Input Logic Low Voltage Bootstrap Capacitor Ambient Temperature Symbol VD1 VDD VIH VIL CBOOT TA Steady State 0 to 30 4.5 to 5.5 0.7 VDD to VDD VDD Unit V - 0.3 to 0.3 100 n to 1 m - 40 to 85 F _C THERMAL RESISTANCE RATINGS Parameter Highside Junction-to-Ambienta Lowside Junction-to-Ambienta Highside Junction-to-Foot (Drain)b Steady State Symbol RthJA1 RthJA2 RthJF1 RthJF2 Typical 85 68 28 19 Maximum 105 85 35 24 Unit _C/W Lowside Junction-to-Foot (Drain)b Notes a. Surface Mounted on 1" x 1" FR4 Board. b. Junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJF + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of a heat carrying (drain) lead is known. www.vishay.com 2 Document Number: 71863 S-03922--Rev. D, 19-May-03 SI4724CY Vishay Siliconix SPECIFICATIONS Test Conditions Unless Specified p Parameter Power Supplies Logic Voltage Logic Current VDD IDD(EN) IDD(DIS) VDD = 4.5 V, VIN = 4.5 V VDD = 4.5 V, VIN = 0 V 4.5 280 220 5.5 500 500 V mA Limits Min Typ Max Unit Symbol TA = 25_C 4.5 V < VDD < 5.5 V, 4.5 V < VD1 < 30 V Logic Input High Logic Input Voltage (VIN) Low VIH VIL VDD = 4.5 V - 40_C TA 85_C 3.15 - 0.3 2.3 2.25 0.8 V Protection Break-Before-Make Reference Undervoltage Lockout Undervoltage Lockout Hysteresis VBBM VUVLO VH VDD = 5.5 V SYNC = 4.5 V 3.75 2.4 4 0.4 4.25 V MOSFET Drivers Driver Impedance RDR1 RDR2 Driver 1 VDD = 4 5 V 4.5 Driver 2 3 2 W MOSFETs Drain-Source Voltage Drain-Source On-State Drain Source On State Resistancea Diode Forward Voltagea VDS rDS(on)1 rDS(on)2 VSD1 VSD2 ID = 250 mA VDD = 4.5 V, ID = 5 A TA = 25_C IS = 2 A VGS = 0 V A, Q1 Q2 Q1 Q2 30 30 24 0.7 0.7 37.5 29 1.1 1.1 V mW V Dynamicb (Unless Specified--Fs = 250 kHz, VIN = 12 V. VDD = 5 V, I = 5 A, Refer to Switching Test Setup) Turn-Off Turn Off Delay Dt Source-Drain Reverse Recovery Time--Q2 td(off)1 td(off)2 Dt1-2 Dt2-1 tfrr See Timing Diagram VIN to G1 VIN to G2 G1 to G2 G2 to G1 IF 2.7 A, di/dt = 100 A/ms 28 17 16 38 50 56 40 32 80 80 ns Notes a. Pulse test: pulse width v300 ms; duty cycle v 2%. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. SCHOTTKY SPECIFICATIONS (TJ = 25_C UNLESS OTHERWISE NOTED) Parameter Forward Voltage Drop Symbol VF Test Condition IF = 1.0 A IF = 1.0 A, TJ = 125_C Vr = 30 V Vr = 30 V, TJ = 100_C Vr = - 30 V, TJ = 125_C Vr = 10 V Min Typ 0.47 0.36 0.004 0.7 3.0 50 Max 0.50 0.42 0.100 10 20 Unit V Maximum Reverse Leakage Current g Irm mA Junction Capacitance CT pF Document Number: 71863 S-03922--Rev. D, 19-May-03 www.vishay.com 3 SI4724CY Vishay Siliconix APPLICATION CIRCUIT 0 V to 30 V 5V VDD Si4724 CBOOT D1 Q1 MOSFET Drive Circuitry with Break-BeforeMake S1 D2 CBOOT VOUT + SYNC EN DC-DC Controller IN GND Q2 S2 GND GND Power Up Sequence: Ensure VDD is within spec before allowing IN or SYNC EN to be set high. Power Down Sequence: Ensure IN and SYNC EN are low before turning VDD off. FIGURE 1. PIN CONFIGURATION TRUTH TABLE Sync EN SO-16 D1 D1 GND IN SYNC EN S2 S2 S2 1 2 3 4 5 6 7 8 Top View Order Number: SI4724CY 16 15 14 13 12 11 10 9 S1 S1 CBOOT VDD D2 D2 D2 D2 H H L L IN H L H L Q1 ON OFF ON OFF Q2 OFF ON OFF OFF PIN DESCRIPTION Pin Number 1, 2 3 4 5 6, 7, 8 9, 10, 11, 12 13 14 15, 16 Symbol D1 GND IN SYNC EN S2 D2 VDD CBOOT S1 Ground Description Highside MOSFET Drain Input Logic Signal Synchronous Enable Lowside MOSFET Source Lowside MOSFET Drain Logic Supply, decoupling to GND with a cap is strongly recommended. Bootstrap Capacitor For Upper MOSFET Highside MOSFET Source Document Number: 71863 S-03922--Rev. D, 19-May-03 www.vishay.com 4 SI4724CY Vishay Siliconix TIMING DIAGRAM IN IN G1 G2 G2 G1 td(off) output (S1/D2, not to scale) Dt1-2 td(off) Dt2-1 output (S1/D2, not to scale) FIGURE 2. Dt1-2 FIGURE 3. Dt2-1 SWITCHING TEST SETUP 12 V C VDD 5V D1 C G1 CBOOT MOSFET Drive Circuitry with Break-BeforeMake S1 G2 D2 S1/D2 CL S2 GND + RL L CBOOT SYNC EN IN Signal Input GND GND FIGURE 4. Document Number: 71863 S-03922--Rev. D, 19-May-03 www.vishay.com 5 SI4724CY Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) On-Resistance vs. Gate-to-Source Voltage (Q1) 80 Output Capacitance vs. Drain Voltage (Q1 and Q2) 800 700 r DS(on) - On-Resistance (M W ) 60 C oss (pF) 600 500 400 300 ID = 5 A 40 20 200 100 0 0 2 4 6 8 10 VGS - Gate-to-Source Voltage (V) 0 0 6 12 18 24 30 VDS - Drain-to-Source Voltage (V) On-Resistance vs. Ambient Temperature 1.6 ID = 5 A VGS = 4.5 V 16 14 12 1.2 10 1.0 I CC (mA) 8 6 4 0.6 2 0.4 - 50 0 - 25 0 25 50 75 100 125 150 0 200 ICC vs. Frequency VIN = 12 V VDD = 5 V DC = 25% BOOT = 0.1 mF ILOAD = 1 A r DS(on) - On-Resistance (W) (Normalized) 1.4 0.8 400 600 800 1000 TA - Ambient Temperature (_C) Frequency (kHz) Input Current vs. Junction Temperature 350 10 Source-Drain Diode Forward Voltage 300 ( mA) IDDQ @ IN = H 250 I S - Source Current (A) I DDQ 200 IDDQ @ IN = L 150 TJ = 150_C TJ = 25_C 100 - 50 - 25 0 25 50 75 100 125 150 1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 TJ - Junction Temperature (_C) VSD - Source-to-Drain Voltage (V) www.vishay.com 6 Document Number: 71863 S-03922--Rev. D, 19-May-03 SI4724CY Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Single Pulse Power, Junction-to-Foot (Q1) 50 50 Single Pulse Power, Junction-to-Ambient (Q1) 40 40 Power (W) 20 Power (W) 30 30 20 10 10 0 0.01 0.1 1 Pulse (S) 10 100 1000 0 0.01 0.1 1 10 100 1000 Time (sec) Single Pulse Power, Junction-to-Foot (Q2) 50 50 Single Pulse Power, Junction-to-Ambient (Q2) 40 40 Power (W) 20 Power (W) 30 30 20 10 10 0 0.01 0.1 1 Pulse (S) 10 100 1000 0 0.01 0.1 1 10 100 1000 Time (sec) Normalized Thermal Transient Impedance, Junction-to-Ambient (Q1) 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 0.05 t1 PDM 0.02 t2 1. Duty Cycle, D = 2. Per Unit Base = RthJA = 85_C/W t1 t2 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 Square Wave Pulse Duration (sec) 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 10 100 600 Document Number: 71863 S-03922--Rev. D, 19-May-03 www.vishay.com 7 SI4724CY Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 Normalized Thermal Transient Impedance, Junction-to-Foot (Q1) 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 10 100 1000 Square Wave Pulse Duration (sec) 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 Normalized Thermal Transient Impedance, Junction-to-Ambient (Q2) 0.2 Notes: 0.1 0.1 0.05 t1 PDM 0.02 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 68_C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 Square Wave Pulse Duration (sec) 10 100 600 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 Normalized Thermal Transient Impedance, Junction-to-Foot (Q2) 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 10 100 1000 Square Wave Pulse Duration (sec) www.vishay.com 8 Document Number: 71863 S-03922--Rev. D, 19-May-03 |
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