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LXT905
Universal 10BASE-T Transceiver with 3.3V Support
Datasheet
The LXT905 Universal 10BASE-T Transceiver is designed for IEEE 802.3 physical layer applications. It provides, in a single CMOS device, all the active circuitry for interfacing most standard 802.3 controllers to 10BASE- T media. LXT905 functions include Manchester encoding/decoding, receiver squelch and transmit pulse shaping, jabber, link integrity testing, and reversed polarity detection/correction. The LXT905 drives the 10BASE-T twisted-pair cable with only a simple isolation transformer using a single 3.3V or 5V power supply. Integrated filters simplify the design work required for FCCcompliant EMI performance.
Applications
s s
Cable Modems Hub/Switched Dedicated LANs for 10BASE-T
s s
Desktop 10BASE-T LAN adapter boards USB to Ethernet Converters
Product Features
s s s s s s s
Transparent 3.3 V or 5 V operation Integrated filters - Simplifies FCC compliance Integrated Manchester encoder/decoder 10BASE-T compliant transceiver Automatic polarity correction SQE enable/disable Four LED drivers
s s s s s
Full duplex capability Power-down mode with tristate Available in 28-pin PLCC and 32-pin LQFP packages Commercial Temperature Range ( 0 to +70C) Extended Temperature Range (-40 to +85C)
As of January 15, 2001, this document replaces the Level One document LXT905 Universal 10BASE-T Transceiver with 3.3V Support Datasheet.
Order Number: 249271-001 January 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT905 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners.
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
Contents
1.0 2.0 Pin Assignments and Signal Descriptions......................................................8 Functional Description...........................................................................................10
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Introduction..........................................................................................................10 Controller Compatibility Modes ...........................................................................10 Transmit Function................................................................................................10 Jabber Control Function ......................................................................................12 SQE Function ......................................................................................................13 Receive Function.................................................................................................13 Polarity Reverse Function ...................................................................................14 Collision Detection Function................................................................................14 Loopback Functions ............................................................................................15 2.9.1 Internal Loopback...................................................................................15 2.9.2 External Loopback/Full Duplex...............................................................15 Link Integrity Test Function .................................................................................15 Introduction..........................................................................................................17 3.1.1 Termination Circuitry ..............................................................................17 3.1.2 Twisted-Pair Interface ............................................................................17 3.1.3 RBIAS Pin ..............................................................................................17 3.1.4 Crystal Information .................................................................................17 3.1.5 Magnetic Information..............................................................................17 Typical 10BASE-T Application ............................................................................18 Dual Network Support - 10BASE-T and Token Ring...........................................19 Simple 10BASE-T Connection ............................................................................21 Timing Diagrams for Mode 1(MD1 = Low, MD0 = Low) ......................................25 Timing Diagrams for Mode 2 (MD1=Low, MD0=High) ........................................27 Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low) ....................................29 Timing Diagrams for Mode 4 (MD1 = High, MD0 = High) ...................................31
2.10
3.0
Application Information.........................................................................................17
3.1
3.2 3.3 3.4
4.0
Test Specifications ..................................................................................................22
4.1 4.2 4.3 4.4
5.0
Mechanical Specifications....................................................................................34
Datasheet
3
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 LXT905 Block Diagram ......................................................................................... 7 LXT905 Pin Assignments...................................................................................... 8 LXT905 TPO Output Waveform .......................................................................... 10 Jabber Control Function...................................................................................... 12 SQE Function...................................................................................................... 13 Collision Detection Function................................................................................ 14 Link Integrity Test Function ................................................................................. 16 Intel Controller Application (Mode 2)................................................................... 18 LXT905/380C26 Interface for Dual 10BASE-T and Token Ring Support (Mode 4).............................................................................................................. 20 LXT905/MC68EN360 Interface for Full Duplex 10BASE-T (Mode 1) ................. 21 Mode 1 RCLK/Start-of-Frame Timing ................................................................ 25 Mode 1 RCLK/End-of-Frame Timing .................................................................. 26 Mode 1 Transmit Timing .................................................................................... 26 Mode 1 COL Output Timing ............................................................................... 27 Mode 2 RCLK/Start-of-Frame ............................................................................ 27 Mode 2 RCLK/End-of-Frame Timing .................................................................. 28 Mode 2 Transmit Timing .................................................................................... 28 Mode 2 COL Output Timing ............................................................................... 29 Mode 3 RCLK/Start-of-Frame Timing ................................................................ 29 Mode 3 RCLK/End-of-Frame Timing................................................................... 30 Mode 3 Transmit Timing .................................................................................... 30 Mode 3 COL Output Timing ............................................................................... 31 Mode 4 RCLK/Start-of-Frame Timing ................................................................ 31 Mode 4 RCLK/End-of-Frame Timing .................................................................. 32 Mode 4 Transmit Timing .................................................................................... 32 Mode 4 COL Output Timing ............................................................................... 33 LXT905PC Package Specifications ................................................................... 34 LXT905LC Package Specifications .................................................................... 35
4
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LXT905 Signal Descriptions .................................................................................. 8 Controller Compatibility Mode Options................................................................11 Loopback Modes .................................................................................................15 Suitable Crystals .................................................................................................17 Absolute Maximum Values..................................................................................22 Recommended Operating Conditions .................................................................22 I/O Electrical Characteristics ...............................................................................22 TP Electrical Characteristics ...............................................................................23 Switching Characteristics ....................................................................................23 RCLK/Start-of-Frame Timing...............................................................................23 RCLK/End-of-Frame Timing................................................................................24 Transmit Timing...................................................................................................24 Miscellaneous Timing..........................................................................................24 PLASTIC LEADED CHIP CARRIER ...................................................................34 QUAD FLAT PACKAGE......................................................................................35
Datasheet
5
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
Revision History
Revision 2.7 Date 10/00 Description Change resistor values for Figures 7, 8, and 9.
6
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
Figure 1. LXT905 Block Diagram
Mode Select Logic Controller Compatibility / Loopback / Link Test XTAL OSC Manchester Encoder Watch-Dog Timer
D
LI TCLK CLKI CLKO TEN TXD CD LEDL RCLK RXD
MD0 MD1
RC
Pulse Shaper & Filter
RC
CMO S TX
TPOP TPON
Loopback Control Squelch/ Link Detect Manchester Decoder Collision Logic Collision/ Polarity Detect/ Correct
RX Slicer
TPIP TPIN
COL LEDR
LEDT/PDN
LEDC/FDE
DSQE
LBK
Datasheet
7
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
1.0
Pin Assignments and Signal Descriptions
Figure 2. LXT905 Pin Assignments
GND4 CLKO CLKI VCC5 VCC4 VCC3 TPIN TPIP
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
Table 1.
LQFP Pin # 13 20 27 28 29 30 31 11 12 21 32 1 2 3
LXT905 Signal Descriptions
Symbol VCC1 VCC2 VCC3 VCC4 VCC5 CLKI CLKO GND1 GND2 GND3 GND4 LBK TEN TCLK I/O - - - - - I O - - - - I I O Loopback. When High, forces internal loopback. Disables collision and the transmission of both data and link pulses. Pulled Low internally1. Transmit Enable. Enables data transmission and starts the Watch-Dog Timer (WDT). Synchronous to TCLK. Pulled Low internally1. Transmit Clock. A 10 MHz clock output. This clock signal should be directly connected to the transmit clock input of the controller. Transmit Data. Input signal containing NRZ data to be transmitted on the network. TXD should be connected directly to the transmit data output of the controller. Pulled Low internally1. Collision Signal. Output that drives the collision detect input of the controller. Ground. Crystal Oscillator. A 20 MHz crystal must be connected across these pins, or a 20 MHz clock applied at CLKI with CLKO left open. Power Inputs 1 thru 5. Power supply inputs of 3.3V or 5V. Description
PLCC Pin # 1 22 - - - 2 3 15 23 4 - 5 6 7
4 5
8 9
1. Externally pull-up or pull-down each pin separately using a 10k , 1% termination resistor or tie directly to VCC or ground. 2. Do not allow this pin to float. If unused, tie High.
8
LEDL CD GND1 GND2 VCC1 RCLK RXD LI
TXD COL
I O
LEDR LEDL CD GND1 RCLK RXD LI
12 13 14 15 16 17 18
LBK TEN TCLK TXD COL LEDC/FDE LEDT/PDN LEDR
1 2 3 4 5 6 7 8
LQFP
Rev #
Part # LXT905LC/LE XX LOT # XXXXXX FPO # XXXXXXXX
24 23 22 21 20 19 18 17
MD1 MD0 TPON GND3 VCC2 TPOP DSQE RBIAS
LBK TEN TCLK TXD COL LEDC/FDE LEDT/PDN
4 3 2 1 28 27 26
GND3 CLKO CLKI VCC1 TPIN TPIP MD1 5 6 Rev # 7 PLCC 8 Part # LXT905PC/PE XX 9 LOT # XXXXXX FPO # XXXXXXXX 10 11 25 24 23 22 21 20 19 MD0 TPON GND2 VCC2 TPOP DSQE RBIAS
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
Table 1.
LQFP Pin #
LXT905 Signal Descriptions (Continued)
Symbol I/O Description LED Collision or Full Duplex Enable.
PLCC Pin #
6
10
LEDC/ FDE
O I
LEDC is an open drain driver for the collision indicator pulls Low during collision. LED "on" (which is Low output) time is extended by approximately 100 ms. FDE enables full duplex mode (external loopback) if tied Low externally. Pulled High internally1. LED Transmit or Power Down. LEDT is an open drain driver for the transmit indicator. LED "on" (which is Low output) time is extended by approximately 100 ms. Output is pulled Low during transmit.2 If externally tied Low, the LXT905 goes to power down state (PDN). In powerdown mode, all logic inputs and outputs are tristated.
7
11
LEDT/ PDN
O I
8
12
LEDR
O
LED Receive. Open drain driver for the receive indicator LED. LED "on" (i.e., Low output) time is extended by approximately 100 ms. Output is pulled Low during receive. Pulled High internally1. LED Link. Open drain driver for link integrity indicator. Output is pulled Low during link test pass. Pulled High internally1. Carrier Detect. An output for notifying the controller that activity exists on the network. Receive Clock. A recovered 10 MHz clock that is synchronous to the received data and connected to the controller receive clock input. Receive Data. Output signal connected directly to the receive data input of the controller. Link Enable. Controls link integrity test; enabled when LI is High, disabled when LI is Low. Bias Circuitry. A 7.5 k 1% resistor to ground at this pin controls operating circuit bias. SQE Disable. When DSQE is High, the SQE function is disabled. When DSQE is Low, the SQE function is enabled. SQE should be disabled for normal operation in Hub/Switch/Repeater applications. Pulled Low internally1. Twisted-Pair Outputs. Differential outputs to the twisted-pair cable. The outputs are pre-equalized. Mode Select 0 and 1. Mode select pins determine controller compatibility mode in accordance with Table 2. Pulled Low internally1. Twisted-Pair Inputs. A differential input pair from the twisted-pair cable. Receive filter is integrated on-chip. No external filters are required.
9 10 14 15 16 17
13 14 16 17 18 19
LEDL CD RCLK RXD LI RBIAS
O O O O I I
18 19 22 23 24 25 26
20 21 24 25 26 27 28
DSQE TPOP TPON MDO MDI TPIP TPIN
I O O I I I I
1. Externally pull-up or pull-down each pin separately using a 10k , 1% termination resistor or tie directly to VCC or ground. 2. Do not allow this pin to float. If unused, tie High.
Datasheet
9
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
2.0
2.1
Functional Description
Introduction
The LXT905 Universal 10BASE-T Transceiver performs the physical layer signaling (PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification. It functions as an integrated PLS/MAU for use with 10BASE-T twisted-pair networks. The LXT905 interfaces a back-end controller to a twisted-pair (TP) cable. The controller interface includes transmit and receive clock and NRZ data channels, as well as mode control logic and signaling. The twisted-pair interface comprises two circuits: Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). In addition to the two basic interfaces, the LXT905 contains an internal crystal oscillator and four LED drivers for visual status reporting. Functions are defined from the back-end controller side of the interface. The LXT905 Transmit function refers to data transmitted by the back end to the twisted-pair network. The LXT905 Receive function refers to data received by the back end from the twisted-pair network. The LXT905 performs all required functions defined by the IEEE 802.3 10BASE-T MAU specification such as collision detection, link integrity testing, signal quality error messaging, jabber control, and loopback.
Figure 3. LXT905 TPO Output Waveform
2.2
Controller Compatibility Modes
The LXT905 is compatible with most industry standard controllers including devices produced by Advanced Micro Devices (AMD), Intel, Fujitsu, National Semiconductor, Seeq, Motorola and Texas Instruments. Four different control signal timing and polarity schemes (Modes 1 through 4) are required to achieve this compatibility. Mode select pins MD0 and MD1 determine controller compatibility modes as listed in Table 2. Refer to the Test Specifications section for timing diagrams and parameters.
2.3
Transmit Function
The LXT905 receives NRZ data from the controller at the TXD input as shown in the block diagram, and passes it through a Manchester encoder. The encoded data is then transferred to the twisted-pair network (the TPO circuit). The advanced integrated pulse shaping and filtering network produces the output signal on TPON and TPOP, shown in Figure 3. The TPO output is pre-distorted and prefiltered to meet the 10BASE-T jitter template. An internal continuous resistorcapacitor filter is used to remove any high-frequency clocking noise from the pulse shaping
10
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
circuitry. Integrated filters simplify the design work required for FCC compliant EMI performance. During idle periods, the LXT905 transmits link integrity test pulses on the TPO circuit (if LI is enabled and LBK is disabled). Table 2. Controller Compatibility Mode Options
Controller Mode Mode 1 - For Motorola MC68EN360 or compatible controllers (AMD AM7990) Mode 2 - For Intel 82596 or compatible controllers1 Mode 3 - For Fujitsu MB86950, MB86960 or compatible controllers (Seeq 8005)2 Mode 4 - For TI TMS380C26 or compatible controllers MD1 Low Low High High MD0 Low High Low High
1. Refer to Intel Application Note 51 (MAC Interface Design Guide for Intel Controllers) when designing with Intel controllers. 2. SEEQ controllers require inverters on CLKI, LBK, RCLK and COL.
Datasheet
11
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
2.4
Jabber Control Function
Figure 4 is a state diagram of the LXT905 jabber control function. The LXT905 on-chip WatchDog Timer (WDT) prevents the DTE from locking into a continuous transmit mode. When a transmission exceeds the time limit, the WDT disables the transmit and loopback functions and activates the COL pin. Once the LXT905 is in the jabber state, the TXD circuit must remain idle for a period of 0.25 to 0.75 seconds before it exits the jabber state.
Figure 4. Jabber Control Function
Power On No Output DO=Active Nonjabber Output
Start_XMIT_MAX_Timer
DO=Idle Jab
DO=Active XMIT_Max_Timer_Done
XMIT=Disable LPBK=Disable CI=SQE
DO=Idle Unjab Wait
Start_Unjab_Timer XMIT=Disable LPBK=Disable CI=SQE
Unjab_ Timer_Done
DO=Active Unjab_Timer_Not_Done
12
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
2.5
SQE Function
The LXT905 supports the Signal Quality Error (SQE) function as shown in Figure 5. After every successful transmission on the 10BASE-T network, the LXT905 transmits the SQE signal for 10 bit times (BT) 5BT on the COL pin of the device. The SQE can be disabled for repeater/switch applications. When DSQE is set High, the SQE function is disabled. When DSQE is Low, the SQE function is enabled.
Figure 5. SQE Function
Power On Output Idle DO=Active Output Detected DSQE=1 DO=Idle DSQE=0
SQE Wait Test
Start_SQE_Test__Wait_Timer
XMIT=Disable
SQE_Test__Wait_Timer_Done XMIT=Enable SQE Test
Start_SQE_Test_Timer CI=SQE
SQE_Test_Timer_Done
2.6
Receive Function
The LXT905 receive function acquires timing and data from the twisted-pair network (the TPI circuit). Valid received signals are passed through the on-chip filters and Manchester decoder then output as decoded NRZ data and receive timing on the RXD and RCLK pins, respectively. An internal RC filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. The receive function is activated only by valid data streams above the squelch level with proper timing. If the differential signal at the TPI circuit inputs falls below 85% of the threshold level (unsquelched) for 8 bit times (typical), the LXT905 receive function enters the idle state. The LXT905 automatically corrects reversed polarity on the TPI circuit.
Datasheet
13
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
2.7
Polarity Reverse Function
The LXT905 polarity reverse function uses both link pulses and end-of-frame data to determine polarity of the received signal. If Link Integrity testing is disabled, polarity detection is based only on received data. A reversed polarity condition is detected when eight consecutive opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. Reversed polarity is also detected if four consecutive frames are received with a reversed start-of-idle. Whenever a correct polarity frame or a correct link pulse is received, these two counters are reset to zero. If the LXT905 enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. Polarity correction is always enabled.
2.8
Collision Detection Function
A collision is defined as the simultaneous presence of valid signals on both the TPI circuit and the TPO circuit. The LXT905 reports collisions to the back-end via the COL pin. If the TPI circuit becomes active while there is activity on the TPO circuit, the TPI data is passed to the back-end over the RXD circuit, disabling normal loopback. Figure 6 is a state diagram of the LXT905 collision detection function.
Figure 6. Collision Detection Function
A TEN=Active TPI=Idle XMIT=Enable Power On
Idle TPI=Active
Output TPO=TXD RXD=TXD TEN=Active TPI=Active XMIT=Enable
Input RXD=TPI
TEN=Active TPI=Active XMIT=Enable
Collision A TEN=Idle + XMIT=Disable TPO=TXD RXD=TPI COL=ACTIVE A TPI=Idle
TEN=Active TPI=Idle
TEN=Idle
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Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
2.9
2.9.1
Loopback Functions
Internal Loopback
The LXT905 provides standard loopback mode as specified in the IEEE specification for the twisted-pair port, as well as a forced internal loopback mode. Loopback mode operates in conjunction with the transmit function. Data transmitted by the MAC is internally looped back within the LXT905 from the TXD pin through the Manchester encoder/decoder to the RXD pin and returned to the MAC. Standard loopback mode is disabled when a data collision occurs, clearing the RXD circuit for the TPI data. Standard loopback is also disabled during link fail, jabber, and full-duplex states. Loopback is always enabled during forced internal loopback mode.
2.9.2
External Loopback/Full Duplex
The LXT905 also provides an external loopback test mode for system-level testing. When both LEDC/FDE and LBK are Low, the LXT905 enables external loopback and full-duplex mode. Internal loopback circuits, SQE, and collision detection are disabled. Refer to Table 3 for a summary of loopback and duplex modes.
Table 3.
Loopback Modes
Pin Settings LBK LEDC/ FDE Low Disable internal loopback. Enable external loopback test mode and full-duplex mode. Standard loopback mode (default). Low High Data transmitted by the MAC is internally looped back and returned to the MAC except during collision. Standard loopback is disabled when a data collision occurs, clearing RXD for data on the twisted-pair port. High High Low High Not Used. Forced internal loopback. Transmit data is looped back on the receive data bus and the twisted-pair port is ignored. Mode Description
Low
2.10
Link Integrity Test Function
Figure 7 is a state diagram of the LXT905 Link Integrity test function. The link integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity testing is enabled when LI is tied High. When enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic. If no serial data stream or link integrity pulses are detected within 50~150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. The LXT905 ignores any link integrity pulse with interval less than 2~7 ms. The LXT905 remains in the link fail state until it detects either a serial data packet or two or more link integrity pulses.
Datasheet
15
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
Figure 7. Link Integrity Test Function
Power On
Idle Test Start_Link_Loss_Timer Start_Link_Test_Min_Timer Link_Loss_Timer_Done TPI=Idle Link_Test_Rcvd=False TPI=Active + (Link_Test_Rcvd=True Link_Test_Min_Timer_Done)
Link Test Fail Reset Link_Count=0 XMIT=Disable RCVR=Disable LPBK=Disable TPI=Active Link_Test_Rcvd=False TPI=Idle Link Test Fail Wait XMIT=Disable RCVR=Disable LPBK=Disable Link_Count=Link_Count + 1 TPI=Active
Link_Test_Rcvd=Idle TPI=Idle
Link Test Fail Start_Link_Test_Min_Timer Start_Link_Test_Max_Timer XMIT=Disable RCVR=Disable LPBK=Disable TPI=Active + Link_Count=LC_Max Link_Test_Min_Timer_Done Link_Test_Rcvd=True Link Test Fail Extended XMIT=Disable RCVR=Disable LPBK=Disable TPI=Idle DO=Idle (TPI=Idle Link_Test_Max_Timer_Done) + (Link_Test_Min_Timer_Not_Done Link_Test_Rcvd=True)
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Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
3.0
3.1
Application Information
Introduction
Figures 7 through 9 show typical LXT905 applications. These diagrams group similar pins; they do not portray the actual chip pinout. The controller interface pins; Transmit Data (TXD), Transmit Clock (TCLK) Transmit Enable (TEN), Receive Data (RXD), Receive Clock (RCLK), Collision Signal (COL) and Carrier Detect (CD) pins are at the upper left. Power and ground pins are at the bottom of each diagram. VCC1 and VCC2 use a single power supply with decoupling capacitors installed between the power and ground busses. VCC may be powered by a 5V or 3.3V supply.
3.1.1
Termination Circuitry
Several I/O pins are internally pulled-up or pulled-down to keep the signals from floating. It is recommended to hard-wire these pins either High or Low. Externally pull-up pins (LEDT/PDN, LEDC/FDE, LEDR, LEDL) and pull-down pins (LBK, TEN, TXD, DSQE, MDO, MDI) separately using a 10k , 1% resistor or tie directly to VCC or ground.
3.1.2
Twisted-Pair Interface
The Twisted-Pair interface (TPOP/N and TPIP/N) is at the upper right. The I/O pairs have impedance-matching resistors for 100 UTP, but no external filters are required.
3.1.3
RBIAS Pin
The RBIAS pin sets the levels for the LXT905 output drivers. The LXT905 requires a 7.5k, 1% resistor directly connected between the RBIAS pin and ground. This resistor should be located as close to the device as possible. Keep the traces as short as possible and isolated from all other high speed signals.
3.1.4
Crystal Information
Based on limited evaluation, Table 4 lists some of the suitable crystals. Designers should test and validate all crystals before committing to a specific component.
Table 4.
Suitable Crystals
Manufacturer MTRON Part Number MP-1 MP-2
3.1.5
Magnetic Information
The LXT905 requires a 1:1 turns ratio for the receive transformer and a 1:2 turns ratio for the transmit transformer. Application Note 073 lists transformers suitable for the applications described in this data sheet. Designers are advised to test and validate all magnetics before committing to a specific component.
Datasheet
17
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
3.2
Typical 10BASE-T Application
Figure 8 is a typical LXT905 application. The DTE is connected to a 10BASE-T network through the twisted-pair RJ-45 connector. With MD0 tied high and MD1 grounded, the LXT905 logic and framing are set to Mode 2 (compatible with Intel 82596 controllers*). Connect 20 MHz system clock input at CLKI. (Leave CLKO open.) The LI pin externally controls the link test function. * Refer to Intel Application Note 51 (MAC Interface Design Guide for Intel Controllers) when designing with Intel controllers.
Figure 8. Intel Controller Application (Mode 2)
1 0.1 F Not Connected 20 MHz System Clock 82596 Back-End/ Controller Interface CLK TXD RTS TXC RXC RXD CRS CDT CLKO CLKI TXD TEN TCLK RCLK RXD TPIP TPON 11.8 1% 11.8 1% TPOP 100 pF 100 pF TPIN 50 1% 50 1% RJ-45 To 10 Base-T Twisted-Pair Network 6 5
1 1:1
16
3 6 1:2
14 11
4 3 2 1
LXT905
CD COL
Programming Options Link Test Enable Loopback Enable Line Status 10K 10K 10K +5V Power Down Full Duplex 0.1 F
8
9
MD0 MD1 DSQE LI LBK
LEDL LEDC/FDE LEDT/PDN VCC1 VCC2 RBIAS GND1 GND2
7.5 k 1%
1
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
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Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
3.3
Dual Network Support - 10BASE-T and Token Ring
Figure 9 shows the LXT905 with a Texas Instruments 380C26 CommProcessor. The 380C26 is compatible with Mode 4 (MD0 and MD1 both high). When used with the 380C26, both the LXT905 and a TMS38054 Token Ring transceiver can be tied to a single RJ-45 allowing dual network support from a single connector.
Datasheet
19
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
Figure 9. LXT905/380C26 Interface for Dual 10BASE-T and Token Ring Support (Mode 4)
To TI TMS38054 Token Ring Transceiver 20 pF CLKI TXD TXD TEN TCLK RCLK RXD CD COL LBK TPIP TPIN 50 1% 50 1% TXE TXC RXC RXD CRS COL LBK From TI TMS38054 Token Ring Transceiver 1 0.1 F 2 RJ-45 To 10 Base-T Twisted-Pair Network 6 5
20 MHz 20 pF CLKO
1 1:1
16
380C26
3 6 1:2
14 11
4 3 2 1
Line Status
MD0 MD1 LI 300
LXT905
TPON
11.8 1% 11.8 1%
TPOP 100 pF
8
9
300
300
300
100 pF
Green Red
Red
Red
LEDR LEDC/FDE LEDT/PDN LEDL VCC1 VCC2 GND1 GND2 GND3 0.1 F 7.5 k 1% RBIAS
+5V
1 2
Optional: Centertap capacitor may improve EMC depending on board layout and system design. Additional magnetics and switching logic (not shown) are required to implement the dual network solution.
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Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
3.4
Simple 10BASE-T Connection
Figure 10 shows a simple 10BASE-T application using an LXT905 transceiver and a Motorola MC68EN360. The MC68EN360 is compatible with Mode 1 (MD0 and MD1 both Low).
Figure 10. LXT905/MC68EN360 Interface for Full Duplex 10BASE-T (Mode 1)
20 MHz System Clock
MC68EN360
CLK1-4 CLK1-4 TXD
CLKI
CLKO
Not Connected RJ-45 To 10 Base-T Twisted-Pair Network 6 5
RCLK TCLK TXD TPIN 100
1 1:1
16
SCC1
LXT905
RXD RTS CD CTS
RXD TEN CD COL LBK DSQE
TPIP TPON 11.8 1% 11.8 1% TPOP 100 pF
3 6 1:2
14 11
4 3 2 1
Parallel I/O
+5V 10 k
1 LEDC/FDE
8
9
+5V 300 Green
MD0 MD1
100 pF
LEDL +5V VCC1 VCC2 LI 0.1 F RBIAS 7.5 k 1%
GND1 GND2 GND3
1
LEDC/FDE requires an open-collector driver.
Datasheet
21
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
4.0
Note:
Test Specifications
The minimum and maximum values in Table 5 through Table 13 and Figure 11 through Figure 26 represent the performance specifications of the LXT905 and are guaranteed by test, except where noted by design. Minimum and maximum values in Table 7 through Table 13 apply over the recommended operating conditions specified in Table 6. Absolute Maximum Values
Parameter Symbol VCC TOP TOP TST Min -0.3 0 -40 -65 Max +6 +70 +85 +150 Units V C C C
Table 5.
Supply voltage Ambient operating temperature (Commercial) Ambient operating temperature (Extended) Storage temperature
Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 6.
Recommended Operating Conditions
Parameter Symbol VCC TOP TOP Min 3.135 0 -40 Typ 5.0 - - Max 5.25 +70 +85 Units V C C
Recommended supply voltage1 Recommended operating temperature (Commercial) Recommended operating temperature (Extended) 1. Voltage is with respect to ground unless specified otherwise.
Table 7.
I/O Electrical Characteristics
Parameter Sym VIL VIH VOL VOL Min - 2.0 - - - 2.4 90 - - - - - Typ1 - - - - - - - 3 2 3 2 - Max 0.8 - 0.4 10 0.7 - - 15 15 15 15 10 Units V V V %VCC %VCC V %VCC ns ns ns ns ns CLOAD= 20 pF IOL = 1.6 mA IOL < 10 A IOLL = 10 mA IOH = 40 A IOH < 10 A CLOAD = 20 pF Test Conditions
Input low voltage2 Input high voltage2 Output low voltage
Output low voltage (Open drain LED driver) Output high voltage
VOLL VOH VOH
Output rise time TCLK & RCLK Output fall time TCLK & RCLK
CMOS TTL CMOS TTL
- - - - -
CLKI rise time (externally driven)
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Limited functional tests are performed at these input levels. The majority of functional tests are performed at levels of 0V and 3V. This applies to all inputs except TPIP and TPIN.
22
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
Table 7.
I/O Electrical Characteristics
Parameter Sym - ICC ICC ICC Min - - - - Typ1 50/50 40 70 0.01 Max 40/60 80 100 1 Units % mA mA A Idle Mode Transmitting on TP Test Conditions
CLKI duty cycle (externally driven) Supply current Normal Mode Power Down Mode
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Limited functional tests are performed at these input levels. The majority of functional tests are performed at levels of 0V and 3V. This applies to all inputs except TPIP and TPIN.
Table 8.
TP Electrical Characteristics
Symbol ZOUT
2
Parameter Transmit output impedance Transmit timing jitter addition
Min - - - - 300
Typ1 5 6.4 3.5 24 420
Max - 10 5.5 - 585
Units
Test Conditions
ns ns k mV 0 line length for internal MAU After line model specified by IEEE 802.3 for 10BASE-T internal MAU Between TPIP/TPIN 5 MHz square wave input
- - ZIN VDS
Transmit timing jitter added by the MAU and PLS sections2, 3 Receive input impedance Differential squelch threshold
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. 3. IEEE 802.3 specifies maximum jitter additions at 0.5 ns from the encoder, and 3.5 ns from the MAU.
Table 9.
Switching Characteristics
Parameter Maximum transmit time Symbol - - - - - - Minimum 20 250 50 2 50 8 Typical1 - - - - - 10 Maximum 150 750 150 7 150 24 Units ms ms ms ms ms ms
Jabber Timing Unjab time Time link loss receive Link Integrity Timing Link min receive Link max receive Link transmit period
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Table 10. RCLK/Start-of-Frame Timing
Parameter Decoder acquisition time CD turn-on delay Mode 1 Receive data setup from RCLK Modes 2, 3, and 4 tRDS 30 45 - ns 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Symbol tDATA tCD tRDS Min - - 60 Typ1 1300 400 70 Max 1500 550 - Units ns ns ns
Datasheet
23
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
Table 10. RCLK/Start-of-Frame Timing
Parameter Mode 1 Receive data hold from RCLK Modes 2, 3, and 4 RCLK shut off delay from CD assert (Mode 3) tRDH tsws 30 - 45 100 - - ns ns Symbol tRDH Min 10 Typ1 20 Max - Units ns
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Table 11. RCLK/End-of-Frame Timing
Parameter RCLK after CD off Rcv data through-put delay CD turn-off delay
2
Type Min Max Max Typical1 Typical1
Sym tRC tRD tCDOFF tIFG tswe
Mode 1 5 400 500 5 -
Mode 2 1 375 475 50 -
Mode 3 - 375 475 - 120 (80)
Mode 4 5 375 475 - -
Units BT ns ns BT ns
Receive block out after TEN off 3 RCLK switching delay after CD off
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CD Turnoff delay measured from middle of last bit: timing specification is unaffected by the value of the last bit. 3. Blocking of Carrier Detect is disabled during full duplex operation.
Table 12. Transmit Timing
Parameter TEN setup from TCLK TXD setup from TCLK TEN hold after TCLK TXD hold after TCLK Transmit start-up delay Transmit through-put delay Symbol tEHCH tDSCH tCHEL tCHDU tSTUD tTPD Minimum 22 22 5 5 - - Typical1 - - - - 350 338 Maximum - - - - 450 350 Units ns ns ns ns ns ns
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Table 13. Miscellaneous Timing
Parameter COL (SQE) Delay after TEN off COL (SQE) Pulse Duration Power Down recovery time
2 2
Symbol tSQED tSQEP tPDR
Minimum 0.65 500 -
Typical1 - - 25
Maximum 1.6 1500 -
Units
s
ns ms
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. When SQE is enabled (DSQE is Low).
24
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
4.1
Timing Diagrams for Mode 1(MD1 = Low, MD0 = Low)
(Figure 11 through Figure 14)
Figure 11. Mode 1 RCLK/Start-of-Frame Timing
1 TPIP/TPIN 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0
tCD
CD
RCLK
tRDS tRDH tDATA
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
Datasheet
25
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
Figure 12. Mode 1 RCLK/End-of-Frame Timing
1 TPIP/TPIN 0 1 0 1 0 1 0 0
tCDOFF
CD
tRD tRC
RCLK
RXD 1 0 1 0 1 0 1 0 0
Figure 13. Mode 1 Transmit Timing
TEN
tEHCH
tCHEL
TCLK tDSCH tCHDU TXD tSTUD TPO tTPD
26
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
Figure 14. Mode 1 COL Output Timing
TEN tSQED COL
tSQEP
4.2
Timing Diagrams for Mode 2 (MD1=Low, MD0=High)
(Figure 15 through Figure 18)
Figure 15. Mode 2 RCLK/Start-of-Frame
1 TPIP/TPIN 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0
CD RCLK
tCD
tRDS tDATA
RXD 1 0 1 0 1 0 1 0 1 1 1 0 1
tRDH
NOTE: 1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Datasheet
27
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
Figure 16. Mode 2 RCLK/End-of-Frame Timing
1 TPIP/TPIN 0 1 0 1 0 1 0 0
CD
tCDOFF tRD
RCLK
RXD 1 0 1 0 1 0 1 0 0
NOTE: 1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 17. Mode 2 Transmit Timing
TEN tEHCH TCLK tDSCH tCHDU TXD tSTUD TPO tTPD tCHEL
28
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
Figure 18. Mode 2 COL Output Timing
TEN tSQED COL
tIFG
tSQEP
NOTE: 1. CD output is disabled for a maximum of 55 bit times after TEN turns off.
4.3
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
(Figure 19 through Figure 22)
Figure 19. Mode 3 RCLK/Start-of-Frame Timing
1 TPIP/TPIN 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1
tCD
CD
tSWS
RCLK Generated from TCLK RXD
Recovered from Input Data Stream
tRDS
tRDH
tDATA
1 0 1 0 1 0 1 0 1 1 1 0 1
NOTE: 1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Datasheet
29
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
Figure 20. Mode 3 RCLK/End-of-Frame Timing
1 TPIP/TPIN 0 1 0 1 0 1 0 0
tCDOFF
CD
tRD tSWE
Recovered Clock Generated from TCLK
RCLK
RXD 1 0 1 0 1 0 1 0 0
NOTE: 1. RSD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 21. Mode 3 Transmit Timing
TEN tEHCH TCLK tDSCH TXD tSTUD TPO tTPD tCHDU tCHEL
30
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
Figure 22. Mode 3 COL Output Timing
TEN tSQED COL
4.4 Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)
(Figure 23 through Figure 26)
Figure 23. Mode 4 RCLK/Start-of-Frame Timing
1 TPIP/TPIN 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1
tSQEP
tCD
CRS RCLK
tRDS tDATA
RXD 1 0 1 0 1 0 1 0 1 1 1 0 1
tRDH
NOTE: 1. RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.
Datasheet
31
LXT905 -- Universal 10BASE-T Transceiver with 3.3V Support
Figure 24. Mode 4 RCLK/End-of-Frame Timing
1 TPIP/TPIN 0 1 0 1 0 1 0 0
tCDOFF
CD
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE: 1. RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.
Figure 25. Mode 4 Transmit Timing
TEN tEHCH TCLK tDSCH tCHDU tCHEL
TXD tTPD tSTUD TPO
32
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
Figure 26. Mode 4 COL Output Timing
TEN tSQED COL
tSQEP
Datasheet
33
5.0
Mechanical Specifications
Figure 27. LXT905PC Package Specifications
28-Pin PLCC
* Part Number LXT905PC (Commercial Temperature Range) * Part Number LXT905PE (Extended Temperature Range)
C L
Table 14. PLASTIC LEADED CHIP CARRIER
Inches Dim Millimeters Min 4.191 2.286 1.575 1.270 0.660 12.319 11.430 0.330 Max 4.572 3.048 2.108 - 0.813 12.573 11.582 0.533
C
A A1
Min 0.165 0.090 0.062 0.050 0.026 0.485 0.450 0.013
Max 0.180 0.120 0.083 - 0.032 0.495 0.456 0.021
B
A2 B C D D1 F
D1 D D A2 A1 F A
Universal 10BASE-T Transceiver with 3.3V Support -- LXT905
Figure 28. LXT905LC Package Specifications
32-Pin LQFP
* Part Number LXT905LC (Commercial Temperature Range) * Part Number LXT905LE (Extended Temperature Range)
D D1
e
E1 E
e/ 2
11/13 8 PLACES 0 MIN. A A2
-C-Ho
o
0.08/0.20 R. 0-7
o
A1
b
M 0.08 R. MIN.
L 0.20 MIN. 1.00 REF.
All Dimensions in millimeters
Table 15. QUAD FLAT PACKAGE
All Dimensions in millimeters Dim. Min. A A1 A2 D D1 E E1 L M b e 0.45 0.15 0.30 --0.05 1.35 Typ. --0.10 1.40 9.00 BSC. 7.00 BSC. 9.00 BSC 7.00 BSC 0.60 --0.37 0.80 BSC. 0.75 --0.45 9 Max. 1.60 0.15 1.4 5 6, 7, 8 5 6, 7, 8 Notes
NOTES: 1. All dimensions are in millimeters. 2. This package conforms to JEDEC publication 95 registration MO-136, variation BC. 3. Datum plane -H- located at mold parting line and is coincident with leads where leads exit plastic body at bottom of parting line. 4. Measured at seating plane -C-. 5. Measured at datum plane -H-. 6. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 mm. 7. Package top dimensions are smaller than bottom dimensions. Top of package will not overhang bottom of package. 8. Dimension b does not include dambar protrusion. Allowable dambar protrusion is no more than 0.08 mm.
Datasheet
35

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