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19-0626; Rev 0; 1/07
KIT ATION EVALU BLE AVAILA
6-Channel High-Speed Logic-Level Translators
General Description
The MAX13030E-MAX13035E 6-channel, bidirectional level translators provide the level shifting necessary for 100Mbps data transfer in multivoltage systems. The MAX13030E-MAX13035E are ideally suited for memory-card level translation, as well as generic level translation in systems with six channels. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as a higher voltage logic signal on the V CC side of the device and vice versa. The MAX13035E features a CLK_RET output that returns the same clock signal applied to the CLK_VL input. The MAX13030E-MAX13035E operate at full speed with external drivers that source as little as 4mA output current. Each I/O channel is pulled up to VCC or VL by an internal 30A current source, allowing the MAX13030E-MAX13035E to be driven by either pushpull or open-drain drivers. The MAX13030E-MAX13034E feature an enable (EN) input that places the device into a low-power shutdown mode when driven low. The MAX13030E-MAX13035E features an automatic shutdown mode that disables the part when VCC is less than VL. The state of I/O VCC_ and I/O VL_ during shutdown is chosen by selecting the appropriate part version (see Ordering Information/ Selector Guide). The MAX13030E-MAX13035E accept V CC voltages from +2.2V to +3.6V and VL voltages from +1.62V to +3.2V, making them ideal for data transfer between low-voltage ASIC/PLDs and higher voltage systems. The MAX13030E-MAX13035E are available in 16-bump UCSP (2mm x 2mm) and 16-pin TQFN (4mm x 4mm) packages, and operate over the extended -40C to +85C temperature range. o 100Mbps Guaranteed Data Rate o Six Bidirectional Channels o Clock Return Output (MAX13035E) o Enable Input (MAX13030E-MAX13034E) o 15kV ESD Protection on I/O VCC Lines o +1.62V VL +3.2V and +2.2V VCC +3.6V Supply Voltage Range o Lead-Free, 16-Bump UCSP (2mm x 2mm) and 16-pin TQFN (4mm x 4mm) Packages
Features
o Compatible with 4mA Input Drivers or Larger
MAX13030E-MAX13035E
Typical Operating Circuits
+1.8V +3.3V
0.1F
0.1F
1F
VL +1.8V SYSTEM CONTROLLER DAT3 DAT2 DAT1 DAT0 CMD CLOCK CLOCK_IN GND
VCC +3.3V SD CARD
MAX13035E
I/O VL_ I/O VL_ I/O VL_ I/O VL_ I/O VL_ CLK_VL CLK_RET I/O VCC_ I/O VCC_ I/O VCC_ I/O VCC_ I/O VCC_ CLK_VCC
DAT3 DAT2 DAT1 DAT0 CMD CLOCK
GND
GND
Applications
SD Card Level Translation MiniSD Card Level Translation MMC Level Translation Transflash Level Translation Memory Stick Card Level Translation
Typical Operating Circuits continued at end of data sheet. Functional Diagram and Pin Configurations appear at end of data sheet.
Ordering Information/Selector Guide
I/O VL_ STATE DURING SHUTDOWN High impedance High impedance I/O VCC_ STATE DURING SHUTDOWN High impedance High impedance PKG CODE B16-1 T1644-4
PART MAX13030EEBE+ MAX13030EETE+
PIN-PACKAGE 16 UCSP 16 TQFN-EP**
Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes a lead-free package. **EP = Exposed paddle.
Ordering Information/Selector guide continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
6-Channel High-Speed Logic-Level Translators MAX13030E-MAX13035E
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) VCC, VL .....................................................................-0.3V to +4V I/O VCC_, CLK_VCC ....................................-0.3V to (VCC + 0.3V) I/O VL_, CLK_VL, CLK_RET ..........................-0.3V to (VL + 0.3V) EN.............................................................................-0.3V to +4V Short-Circuit Duration I/O VL_, I/O VCC_, CLK_VCC, CLK_VL, CLK_RET to GND.......................Continuous Continuous Power Dissipation (TA = +70C) 16-Bump UCSP (derate 8.2mW/C) ..............................660mW 16-Pin TQFN (derate 25.0mW/C)...............................2000mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Bump Temperature (soldering)........................................+235C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V and TA = +25C.) (Notes 1, 2)
PARAMETER POWER SUPPLIES VL Supply Range VCC Supply Range Supply Current from VCC Supply Current from VL VL VCC IQVCC IQVL I/O VCC_ = VCC, I/O VL_ = VL I/O VCC_ = VCC, I/O VL_ = VL TA = +25C, EN = GND or VL > VCC + 0.7V, MAX13030E-MAX13034E VCC Shutdown Supply Current ISHDN-VCC TA = +25C, VL > VCC + 0.7V, MAX13035E, TA = +25C, EN = GND or VL > VCC + 0.7V, MAX13030E-MAX13034E TA = +25C, VL > VCC + 0.7V, MAX13035E I/O VCC_, I/O VL_, CLK_VCC Tri-State Leakage Current EN Input Leakage Current VL - VCC Shutdown Threshold High VL - VCC Shutdown Threshold Low I/O VCC_ Pulldown Resistance During Shutdown I/O VCC_ Pullup Resistance During Shutdown I/O VL_ Pulldown Resistance During Shutdown ILEAK ILEAK_EN VTH_H VTH_L TA = +25C, EN = GND or VL > VCC + 0.7V TA = +25C, MAX13030E-MAX13034E VCC rising VCC falling -0.2 -0.2 10 10 10 0.05VL 0.1VL 16.5 16.5 16.5 (Note 2) 1.62 2.2 16 6 2 2 0.1 0.1 0.1 3.20 3.6 25 10 4 A 4 4 4 2 1 0.7 0.7 23 23 23 A A V V k k k V V A A SYMBOL CONDITIONS MIN TYP MAX UNITS
VL Shutdown Supply Current
ISHDN-VL
A
RVCC_PD_SD EN = GND, MAX13032E/MAX13034E RVCC_PU_SD EN = GND, MAX13031E RVL_PD_SD EN = GND, MAX13033E/MAX13034E
2
_______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = 1.8V and TA = +25C.) (Notes 1, 2)
PARAMETER I/O VL_, CLK_VL, CLK_RET Pullup Resistance During Shutdown I/O VL_, CLK_VL, CLK_RET Pullup Current I/O VCC_, CLK_VCC Pullup Current I/O VL to I/O VCC DC Resistance ESD PROTECTION (Note 3) Human Body Model, CVCC = 1.0F I/O VCC_, CLK_VCC IEC 61000-4-2 Air-Gap Discharge, CVCC = 1.0F IEC 61000-4-2 Contact Discharge, CVCC = 1.0F LOGIC-LEVEL THRESHOLDS I/O VL_, CLK_VL Input-Voltage High Threshold I/O VL_, CLK_VL Input-Voltage Low Threshold I/O VCC_, CLK_VCC InputVoltage High Threshold I/O VCC_, CLK_VCC InputVoltage Low Threshold EN Input-Voltage High Threshold EN Input-Voltage Low I/O VL_, CLK_VL, CLK_RET Output-Voltage High I/O VL_, CLK_VL, CLK_RET Output-Voltage Low I/O VCC_, CLK_VCC OutputVoltage High VIHL VILL VIHC VILC VIH VIL VOHL VOLL VOHC (Note 4) (Note 4) (Note 4) (Note 4) MAX13030E-MAX13034E MAX13030E-MAX13034E I/O VL_, CLK_VL, CLK_RET source current = 20A, I/O VCC_ VCC - 0.4V I/O VL_, CLK_VL, CLK_RET sink current = 20A, I/O VCC_ 0.2V I/O VCC_, CLK_VCC source current = 20A, I/O VL_ VL - 0.2V 2/3 VCC 0.4 2/3 VL 1/3 VL 0.2 VL 0.4 0.15 VCC 0.4 VL 0.2 V V V V V V V V V 15 12 8 kV SYMBOL RVL_PU_SD CONDITIONS (VL > VCC + 0.7V), MAX13035E MIN 45 TYP 75 MAX 105 UNITS k
MAX13030E-MAX13035E
RVL_PU RVCC_PU
EN = VCC or VL, I/O VL_ = GND EN = VCC or VL, I/O VCC_ = GND
20 20 3
A A k
RIOVL_IOVCC (Note 3)
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3
6-Channel High-Speed Logic-Level Translators MAX13030E-MAX13035E
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = 1.8V and TA = +25C.) (Notes 1, 2)
PARAMETER I/O VCC_, CLK_VCC OutputVoltage Low SYMBOL VOLC CONDITIONS I/O VCC_, CLK_VCC sink current = 20A, I/O VL_ 0.15V On falling edge On rising edge VL = 1.62V VL = 3.2V VCC = 2.2V VCC = 3.6V VL = 1.62V VL = 3.2V VCC = 2.2V VCC = 3.6V 3 3 11 6 9 8 9 8 10 9 MIN TYP MAX 1/3 VCC UNITS V
RISE/FALL TIME ACCELERATOR STAGE (Note 3) Accelerator Pulse Duration VL-Output-Accelerator Source Impedance VCC-Output-Accelerator Source Impedance VL-Output-Accelerator Sink Impedance VCC-Output-Accelerator Sink Impedance ns
TIMING CHARACTERISTICS
(VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, CI/OVL 15pF, CI/OVCC 15pF, RSOURCE = 150, EN = VL, I/O VL_ to I/O VCC_ rise/fall time = 3ns, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = 1.8V and TA = +25C.) (Note 1)
PARAMETER I/O VCC_, CLK_VCC Rise Time I/O VCC_, CLK_VCC Fall Time I/O VL_, CLK_VL Rise Time I/O VL_, CLK_VL Fall Time Propagation Delay (Driving I/O VL_, CLK_VL) Propagation Delay (Driving I/O VCC_, CLK_VCC) Channel-to-Channel Skew Propagation Delay from I/O VL_ to I/O VCC_ after EN SYMBOL tRVCC tFVCC tRVL tFVL tPVL-VCC tPVCC-VL tSKEW tEN-VCC CONDITIONS RS = 150, CI/OVCC = 10pF, CCLK_VCC = 10pF, push-pull drivers (Figure 1) RS = 150, CI/OVCC = 10pF, CCLK_VCC = 10pF (Figures 1, 2) RS = 150, CI/OVL = 15pF, CCLK_VL = 15pF, push-pull drivers (Figure 3) RS = 150, CI/OVL = 15pF, CCLK_VL = 15pF (Figures 3, 4) RS = 150, CI/OVCC = 10pF, CCLK_VCC = 10pF, push-pull drivers (Figure 1) RS = 150, CI/OVL = 15pF, CCLK_VL = 15pF, push-pull drivers (Figure 3) RS = 150, CI/OVCC = 10pF, CI/OVL = 15pF RLOAD = 1M, CI/OVCC = 10pF (Figure 5) (MAX13030E-MAX13034E) 5 MIN TYP MAX 2.5 2.5 2.5 2.5 6.5 6.5 0.8 UNITS ns ns ns ns ns ns ns s
4
_______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
TIMING CHARACTERISTICS (continued)
(VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, CI/OVL 15pF, CI/OVCC 15pF, RSOURCE = 150, EN = VL, I/O VL_ to I/O VCC_ rise/fall time = 3ns, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = 1.8V and TA = +25C.) (Note 1)
PARAMETER Propagation Delay from I/O VCC_ to I/O VL_ after EN Maximum Data Rate SYMBOL tEN-VL CONDITIONS RLOAD = 1M, CI/OVL = 15pF (Figure 5) (MAX13030E-MAX13034E) Push-pull operation, RSOURCE = 150_, CI/OVCC_ = 10pF, CI/OVL_ = 15pF, CCLK_VCC = 10pF, CCLK_VL = 15pF 100 MIN TYP 5 MAX UNITS s
MAX13030E-MAX13035E
Mbps
Note 1: All units are 100% production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design and not production tested. Note 2: VL must be less than or equal to VCC - 0.2V during normal operation. However, VL can be greater than VCC during startup and shutdown conditions and the part will not latch-up or be damaged. Note 3: Guaranteed by design. Note 4: Input thresholds are referenced to the boost circuit.
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5
6-Channel High-Speed Logic-Level Translators MAX13030E-MAX13035E
Typical Operating Characteristics
(VCC = 3.3V, VL = 1.8V, CL = 15pF, RSOURCE = 150, data rate = 100Mbps, push-pull driver, TA = +25C, unless otherwise noted.)
VL SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE (DRIVING I/O VL_, VL = 1.8V)
MAX13030E toc01
VL SUPPLY CURRENT vs. VL SUPPLY VOLTAGE (DRIVING I/O VCC_, VCC = 3.6V)
9 VL SUPPLY CURRENT (mA) 8 7 6 5 4 3 2 1 0 DRIVING ONE I/O VCC
MAX13030E toc02
VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE (DRIVING I/O VL_, VL = 1.8V)
22.5 VCC SUPPLY CURRENT (mA) 20.0 17.5 15.0 12.5 10.0 7.5 5.0 DRIVING ONE I/O VL
MAX13030E toc03
850 840 VL SUPPLY CURRENT (A) 830 820 810 800 790 780 770 760 750 2.2 2.4 2.6 2.8 3.0 3.2 3.4 DRIVING ONE I/O VL
10
25.0
3.6
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC SUPPLY VOLTAGE (V)
VL SUPPLY VOLTAGE (V)
VCC SUPPLY VOLTAGE (V)
VCC SUPPLY CURRENT vs. VL SUPPLY VOLTAGE (DRIVING I/O VCC_, VCC = 3.6V)
MAX13030E toc04
19.5 VCC SUPPLY CURRENT (mA) 19.0 18.5 18.0 17.5 17.0 16.5 16.0 15.5 15.0
DRIVING ONE I/O VCC
MAX13030E toc05
16 SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 0
DRIVING ONE I/O VCC
18 16 SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 0
DRIVING ONE I/O VL ICC
ICC
IL
IL
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
-40
-15
10
35
60
85
-40
-15
10
35
60
85
VL SUPPLY VOLTAGE (V)
TEMPERATURE (C)
TEMPERATURE (C)
VL SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING I/O VCC_)
MAX13030E toc07
VCC SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING I/O VL_)
DRIVING ONE I/O VL 19.5 VCC SUPPLY CURRENT (mA) 19.0 18.5 18.0 17.5 17.0 16.5 16.0 10 15 20 25 30 35 40
MAX13030E toc08
RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING I/O VL_)
1400 1300 RISE/FALL TIME (ps) 1200 1100 1000 900 800 700 600 500 10 15 20 25 30 35 40 tRVCC tFVCC
MAX13030E toc09
5.0 DRIVING ONE I/O VCC 4.5 VL SUPPLY CURRENT (mA) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 10 15 20 25 30 35
20.0
1500
40
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
6
_______________________________________________________________________________________
MAX13030E toc06
20.0
SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/O VCC_)
18
SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/O VL_)
20
6-Channel High-Speed Logic-Level Translators
Typical Operating Characteristics (continued)
(VCC = 3.3V, VL = 1.8V, CL = 15pF, RSOURCE = 150, data rate = 100Mbps, push-pull driver, TA = +25C, unless otherwise noted.)
RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING I/O VCC_)
MAX13030E toc10
MAX13030E-MAX13035E
PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING I/O VL_)
MAX13030E toc11
3000 2750 2500 RISE/FALL TIME (ps) 2250 2000 1750 1500 1250 1000 750 500 10 15 20 25 30 35 tFVL tRVL
5.0 4.5 PROPAGATION DELAY (ns) 4.0 3.5 tPHL 3.0 2.5 2.0
tPLH
40
10
15
20
25
30
35
40
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING I/O VCC_)
4.5 PROPAGATION DELAY (ns) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 10 15 20 25 30 35 40 tPLH tPHL
MAX13030E toc12
TYPICAL I/O VL_ DRIVING (FREQUENCY = 26MHz, CIOVCC = 40pF)
5.0
MAX13030E toc13
I/O VL_ 1V/div
I/O VCC_ 2V/div
10ns/div
CAPACITIVE LOAD (pF)
TYPICAL I/O VCC_ DRIVING (FREQUENCY = 26MHz, CIOVL = 15pF)
MAX13030E toc14
TYPICAL CLK_ VL DRIVING (FREQUENCY = 26MHz, CCLK_VCC = 40pF)
MAX13030E toc15
I/O VCC_ 2V/div
CLK_ VL 1V/div
CLK_ VCC 2V/div I/O VL_ 1V/div
CLK_RET 1V/div 10ns/div
10ns/div
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7
6-Channel High-Speed Logic-Level Translators MAX13030E-MAX13035E
Pin Description
PIN MAX13030E-MAX13034E UCSP A1 A2 A3 A4 B1 B2 B3 B4 C1 TQFN 4 6 7 9 3 5 8 10 2 MAX13035E UCSP A1 A2 A3 A4 B1 B2 B3 B4 C1 TQFN 4 6 7 9 3 5 8 10 2 I/O VL3 I/O VCC3 I/O VCC4 I/O VL4 I/O VL2 I/O VCC2 I/O VCC5 I/O VL5 VL Input/Output 3. Referenced to VL. Input/Output 3. Referenced to VCC. Input/Output 4. Referenced to VCC. Input/Output 4. Referenced to VL. Input/Output 2. Referenced to VL. Input/Output 2. Referenced to VCC. Input/Output 5. Referenced to VCC. Input/Output 5. Referenced to VL. Logic-Supply Voltage, +1.62V to +3.2V. Bypass VL to GND with a 0.1F capacitor placed as close as possible to the device. Power-Supply Voltage, +2.2V to +3.6V. Bypass VCC to GND with a 0.1F ceramic capacitor. For full ESD protection, connect a 1F ceramic capacitor from VCC to GND as close as possible to the VCC input. Ground Enable Input. Drive EN to GND for shutdown mode, or drive EN to VL or VCC for normal operation. Input/Output 1. Referenced to VL. Input/Output 1. Referenced to VCC. Input/Output 6. Referenced to VCC. Input/Output 6. Referenced to VL. Clock Return Output. CLK_RET is the returned signal of a clock applied to CLK_VL. CLK_RET is referenced to VL. Translator Channel for a Clock Applied to VCC Translator Channel for a Clock Applied to VL Exposed Paddle. Connect exposed paddle to GND. NAME FUNCTION
C2
16
C2
16
VCC
C3 C4 D1 D2 D3 D4 -- -- -- --
13 11 1 15 14 12 -- -- -- EP
C3 -- D1 D2 -- -- C4 D3 D4 --
13 -- 1 15 -- -- 11 14 12 EP
GND EN I/O VL1 I/O VCC1 I/O VCC6 I/O VL6 CLK_RET CLK_VCC CLK_VL EP
8
_______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
Test Circuits/Timing Diagrams
VL VL EN** VCC I/O VL VCC 50% I/O VL_ (CLK_VL*) 150 I/O VCC_ (CLK_VCC*) I/O VCC CIOVCC (CCLK_VCC*) 10% 10% 50% 50% 50% VCC tRVCC tFVCC
MAX13030E-MAX13035E
90%
90%
MAX13030E- MAX13035E
VL
*MAX13035E ONLY
**MAX13030E-MAX13034E ONLY
tPLH tPVL-VCC = tPLH OR tPHL
tPHL
Figure 1. Push-Pull Driving I/O VL_ Test Circuit and Timing
VL VL EN** VCC
VCC
tRVCC I/O VCC 90%
tFVCC
90%
MAX13030E- MAX13035E
VL VCC
VGATE 50% 50% 50% 50%
I/O VL_ (CLK_VL*)
I/O VCC_ (CLK_VCC*) 10% 10%
VGATE
CIOVCC (CCLK_VCC*)
tPLH tPVL-VCC = tPHL *MAX13035E ONLY **MAX13030E-MAX13034E ONLY
tPHL
Figure 2. Open-Drain Driving I/O VL_ Test Circuit and Timing
_______________________________________________________________________________________
9
6-Channel High-Speed Logic-Level Translators MAX13030E-MAX13035E
Test Circuits/Timing Diagrams (continued)
VL VL EN** VCC VCC tRVL tFVL
I/O VCC
MAX13030E- MAX13035E
VL VCC 50% I/O VL_ (CLK_VL*) I/O VCC_ (CLK_VCC*) 150 CIOVL (CCLK_VL*) *MAX13035E ONLY **MAX13030E-MAX13034E ONLY tPLH tPVCC-VL = tPLH OR tPHL tPHL 10% 90% 50% 50% 50% 10% I/O VL 90%
Figure 3. Push-Pull Driving I/O VCC_ Test Circuit and Timing
VL VL EN** VCC
VCC
tRVL
tFVL
(CCLK_VL*)
MAX13030E- MAX13035E
VL VCC
I/O VL 50% 90% 90% 50% 50% 10%
50% I/O VL_ (CLK_VL*) I/O VCC_ (CLK_VCC*) 10%
CIOVL (CCLK_VL*) *MAX13035E ONLY **MAX13030E-MAX13034E ONLY
VGATE
tPLH tPVCC-VL = tPHL
tPHL
Figure 4. Open-Drain Driving I/O VCC_ Test Circuit and Timing
10
______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
Test Circuits/Timing Diagrams (continued)
MAX13030E-MAX13035E
EN VL MAX13030E- VCC I/O VCC_ I/O VL_ EN
VL
MAX13034E
SOURCE I/O VL_
t'EN-VCC
0 VL 0
RLOAD VL VCC EN VL MAX13030E- SOURCE I/O VL_ I/O VCC_ VCC RLOAD
CIOVCC I/O VCC_ VCC / 2
VCC 0
VL EN t"EN-VCC 0 VL 0 I/O VCC_ CIOVCC VCC / 2 VCC 0
MAX13034E
I/O VL_
tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
EN VL SOURCE I/O VCC_ I/O VL_ RLOAD CIOVL I/O VCC_ VCC
VL
MAX13030E- VCC MAX13034E
EN
t'EN-VL
0 VCC 0 VL
I/O VL_
VL / 2
0
VL EN VL EN t"EN-VL 0 VCC 0 I/O VCC_ I/O VL_ CIOVL I/O VL_ VL / 2 VL 0
VL SOURCE RLOAD
MAX13030E- VCC MAX13034E
I/O VCC_
tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
Figure 5. Enable Test Circuit and Timing
______________________________________________________________________________________
11
6-Channel High-Speed Logic-Level Translators MAX13030E-MAX13035E
Detailed Description
The MAX13030E-MAX13035E 6-channel, bidirectional level translators provide the level shifting necessary for 100Mbps data transfer in multivoltage systems. The MAX13030E-MAX13035E are ideally suited for memory card level translation, as well as generic level translation in systems with six channels. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as a higher voltage logic signal on the VCC side of the device, and vice versa. The MAX13035E features a CLK_RET output that returns the same clock signal applied to the CLK_VL input. The MAX13030E-MAX13035E operate at full speed with external drivers that source as little as 4mA output current. Each I/O channel is pulled up to VCC or VL by an internal 30A current source, allowing the MAX13030E-MAX13035E to be driven by either pushpull or open-drain drivers. The MAX13030E-MAX13034E feature an enable (EN) input that places the device into a low-power shutdown mode when driven low. The MAX13030E-MAX13035E features an automatic shutdown mode that disables the part when VCC is less than VL. The state of I/O VCC_ and I/O VL_ during shutdown is chosen by selecting the appropriate part version (see Ordering Information/ Selector Guide). The MAX13030E-MAX13035E accept VCC voltages from +2.2V to +3.6V and VL voltages from +1.62V to +3.2V.
VL ENABLE ENABLE ENABLE VCC
30A I/O VL_
30A I/O VCC_
VL BOOST CIRCUIT VL BOOST CIRCUIT
VCC
VCC
NOTES: 1) THE MAX13030E-MAX13034E ARE ENABLED WHEN VL < VCC - 0.2V AND EN = VL. 2) THE MAX13035E IS ENABLED WHEN VL < VCC - 0.2V.
Figure 6. Simplified Functional Diagram for One I/O Line
active during the one-shot pulse. This can lead to some current feeding into the external source that is driving the translator. However, this behavior helps to speed up the transition on the driven side. The MAX13030E-MAX13035E have internal current sources capable of sourcing 30A to pullup the I/O lines. These internal pullup current sources allow the inputs to be driven with open-drain drivers, as well as push-pull drivers. It is not recommended to use external pullup resistors on the I/O lines. The architecture of the MAX13030E-MAX13035E permit either side to be driven with a minimum of 4mA drivers or larger.
Level Translation
For proper operation, ensure that +2.2V VCC +3.6V, and +1.62V VL VCC - 0.2V. When power is supplied to V L while V CC is either missing or less than V L , the MAX13030E-MAX13035E automatically enters a low- power mode. In addition, the MAX13030E- MAX13034E enters a low-power mode if EN = 0V. This allows VCC to be disconnected and still have a known state on I/O VL_. The maximum data rate depends heavily on the load capacitance (see the Typical Operating Characteristics Rise/Fall Times), output impedance of the driver, and the operating voltage range.
Output Load Requirements
The MAX13030E-MAX13035E I/O are designed to drive CMOS inputs. Do not load the I/O lines with a resistive load less than 25k and do not place an RC circuit at the input of these devices to slow down the edges. If a slower rise/fall time is required, refer to the MAX3000E/ MAX3001E logic-level translator datasheet. For I 2C level translation, refer to the MAX3372E-MAX3379E/ MAX3390E-MAX3393E datasheet.
Input Driver Requirements
The MAX13030E-MAX13035E architecture is based on an nMOS pass gate and output accelerator stages (see Figure 6). Output accelerator stages are always in tristate mode except when there is a transition on any of the translators on the input side, either I/O VL_, CLK_VL, I/O VCC_, or CLK_VCC. A short pulse is then generated during which the output accelerator stages become active and charge/discharge the capacitances at the I/Os. Due to its architecture, both input stages become
12
Shutdown Mode
The MAX13030E-MAX13034E feature an enable (EN) input that places the device into a low-power shutdown mode when driven low. The MAX13030E-MAX13035E features an automatic shutdown mode that disables the part when VCC is missing or less than VL.
______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
Clock Return (CLK_RET)
The MAX13035E features a CLK_RET output that returns the clock signal applied to CLK_V L . CLK_V L and CLK_VCC are identical to the other I/O channels, the only difference being that CLK_VCC is internally tied to the VCC side of CLK_RET (see the Functional Diagram).
Open-Drain Signaling
The MAX13030E-MAX13035E are designed to pass open-drain as well as CMOS push-pull signals. When used with open-drain signaling, the rise time is dominated by the interaction of the internal pullup current source and the parasitic load capacitance. The MAX13030E-MAX13035E include internal rise time accelerators to speed up transitions, eliminating any need for external pullup resistors.
MAX13030E-MAX13035E
Application Information
Layout Recommendations
Use standard high-speed layout practices when laying out a board with the MAX13030E-MAX13035E. For example, to minimize line coupling, place all other signal lines not connected to the MAX13030E-MAX13035E at least 1x the substrate height of the PCB away from the input and output lines of the MAX13030E-MAX13035E.
SD Card Detection
SD, MiniSD, MMC and similar types of cards provide detection of a card through a pullup resistor on one of the DAT lines, or by use of a mechanical switch. This pullup resistor is internal to the memory card itself. The MAX13030E-MAX13035E only support detection of a memory card through a mechanical switch, and it is recommended that the internal resistor for card detection be switched off by the command interface. For example, when using SD cards, the command SET_CLR_CARD_DETECT (ACMD42) disables this resistor.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data errors, bypass VL and VCC to ground with 0.1F ceramic capacitors. Place all capacitors as close as possible to the power-supply inputs. For full ESD protection, bypass VCC with a 1F ceramic capacitor located as close as possible to the VCC input.
UCSP Applications Information
For the latest application details on UCSP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profiles, as well as the latest information on reliability testing results, go to Maxim's web site at www.maxim-ic.com/ucsp to find the Application Note: UCSP - A Wafer-Level Chip-Scale Package.
Unidirectional vs. Bidirectional Level Translator
The MAX13030E-MAX13035E bidirectional level translators can operate as a unidirectional device to translate signals without inversion. These devices provide the smallest solution (UCSP package) for unidirectional level translation without inversion.
Use with External Pullup/Pulldown Resistors
Due to the architecture of the MAX13030E- MAX13035E, it is not recommended to use external pullup or pulldown resistors on the bus. In certain applications, the use of external pullup or pulldown resistors is desired to have a known bus state when there is no active driver on the bus. For example, this may happen when interfacing to a memory card slot with no memory card inserted. The MAX13030E-MAX13035E include internal pullup current sources that set the bus state when the device is enabled. In shutdown mode, the state of I/O V CC_ and I/O V L_ is dependent on the selected part version (see Ordering Information/ Selector Guide for further information). Process: BiCMOS
Chip Information
______________________________________________________________________________________
13
6-Channel High-Speed Logic-Level Translators MAX13030E-MAX13035E
Functional Diagram
VL VCC VL VCC
MAX13030E- MAX13034E
MAX13035E
I/O VL1
I/O VCC1
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
I/O VL2
I/O VCC2
I/O VL3
I/O VCC3
I/O VL3
I/O VCC3
I/O VL4
I/O VCC4
I/O VL4
I/O VCC4
I/O VL5
I/O VCC5
I/O VL5
I/O VCC5
I/O VL6 EN GND
I/O VCC6
CLK_ VL
CLK_ VCC
CLK_RET GND
14
______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
Pin Configurations
TOP VIEW I/O VL6 I/O VL5 I/O VL4 TOP VIEW (BUMPS ON BOTTOM) 1 + 8 7 I/O VCC5 I/O VCC4 I/O VCC3 I/O VCC2 C + 1 I/O VL1 2 VL 3 I/O VL2 4 I/O VL3 D I/O VL1 I/O VCC1 I/O VCC6 I/O VL6 VL VCC GND EN B I/O VL2 5 I/O VCC2 I/O VCC5 I/O VL5 A I/O VL3 I/O VCC3 I/O VCC4 I/O VL4 2 3 4
MAX13030E-MAX13035E
12
11
EN
10
9
MAX13030E-MAX13034E
GND 13
I/O VCC6 14 I/O VCC1 15 VCC 16 *EP
MAX13030E- MAX13034E
6
16 TQFN (4mm x 4mm)
*CONNECT EXPOSED PADDLE TO GROUND
16 UCSP (2mm x 2mm)
TOP VIEW CLK_RET CLK_VL I/O VL5 I/O VL4 TOP VIEW (BUMPS ON BOTTOM) 1 + 8 7 I/O VCC5 I/O VCC4 I/O VCC3 I/O VCC2 C + 1 I/O VL1 2 VL 3 I/O VL2 4 I/O VL3 D I/O VL1 I/O VCC1 CLK_VCC CLK_VL VL VCC GND CLK_RET B I/O VL2 5 I/O VCC2 I/O VCC5 I/O VL5 A I/O VL3 I/O VCC3 I/O VCC4 I/O VL4 2 3 4
12
11
10
9
MAX13035E
GND 13
CLK_VCC 14
MAX13035E
I/O VCC1 15 VCC 16 *EP 6
16 TQFN (4mm x 4mm)
*CONNECT EXPOSED PADDLE TO GROUND
16 UCSP (2mm x 2mm)
______________________________________________________________________________________
15
6-Channel High-Speed Logic-Level Translators MAX13030E-MAX13035E
Typical Operating Circuits (continued)
+1.8V
+3.3V
0.1F
0.1F
1F
VL +1.8V SYSTEM CONTROLLER EN DATA 6 GND
VCC +3.3V SYSTEM
MAX13030E- MAX13034E
EN I/O VL_
I/O VCC_ 6 GND
DATA GND
Ordering Information/Selector Guide (continued)
PART MAX13031EEBE+* MAX13031EETE+* MAX13032EEBE+ MAX13032EETE+ MAX13033EEBE+* MAX13033EETE+* MAX13034EEBE+* MAX13034EETE+* MAX13035EEBE+ MAX13035EETE+ PIN-PACKAGE 16 UCSP 16 TQFN-EP** 16 UCSP 16 TQFN-EP** 16 UCSP 16 TQFN-EP** 16 UCSP 16 TQFN-EP** 16 UCSP 16 TQFN-EP** I/O VL_ STATE DURING SHUTDOWN High impedance High impedance High impedance High impedance 16.5k to GND 16.5k to GND 16.5k to GND 16.5k to GND 75k to VL 75k to VL I/O VCC_ STATE DURING SHUTDOWN 16.5k to VCC 16.5k to VCC 16.5k to GND 16.5k to GND High impedance High impedance 16.5k to GND 16.5k to GND High impedance High impedance PKG CODE B16-1 T1644-4 B16-1 T1644-4 B16-1 T1644-4 B16-1 T1644-4 B16-1 T1644-4
Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes a lead-free package. **EP = Exposed paddle.
16
______________________________________________________________________________________
6-Channel High-Speed Logic-Level Translators
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX13030E-MAX13035E
PACKAGE OUTLINE, 4x4 UCSP 21-0101 H
1 1
______________________________________________________________________________________
16L,UCSP.EPS
17
6-Channel High-Speed Logic-Level Translators MAX13030E-MAX13035E
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
1
2
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
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