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HV4937 64-Channel Serial To Parallel Converter With P-Channel Open Drain Outputs
Ordering Information
Package Options Device HV4937 80-Lead Quad Plastic Gullwing HV4937PG Die HV4937X
Features
s HVCMOS(R) Technology s Output voltages up to -375V s Source current minimum 0.25mA s Shift register speed 6 MHz s Latched outputs s CMOS compatible inputs s Forward and reverse shifting options
General Description
Not recommended for new designs. The HV49 is a low voltage serial to high voltage parallel converter with open drain outputs. It has been designed especially for use as a driver for electrostatic printers. This device consists of a 64-bit shift register, 64 latches, a latch enable (LE), and an output enable (OE). Data is shifted through the shift register on the high to low transition of the clock. When the DIR pin is set high, the HV49 shifts in the counterclockwise direction when viewed from the top of the package. When the DIR pin is set low, the HV49 shifts in the clockwise direction. A serial data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE or the OE inputs. Transfer of data from the shift register to the latch occurs when the LE input is high. The data in the latch is stored when LE is low.
12
Absolute Maximum Ratings1
Supply voltage, VDD Supply voltage, VPP Logic input levels Ground current Continuous total power dissipation2 Operating temperature range Storage temperature range +0.5V to -9V +0.5V to -400V +0.5V to VDD -0.5V 0.75A 1200mW -40C to +85C -65C to +150C
Notes: 1. All voltages are referenced to VSS. 2. For operation above 25C ambient derate linearly by 20mW/C up to 85C.
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HV4937
Electrical Characteristics (over recommended operating conditions unless noted)
DC Characteristics
Symbol IDD IDDQ IO(OFF) IIH IIL VOH VOL VOC CHVO Parameter VDD Supply Current Quiescent VDD Supply Current Off State Output Current at 25C, per Switch High-Level Logic Input Current Low-Level Logic Input Current High-Level Data Out Low-Level Output HVOUT Data Out HVOUT Clamp Voltage Output Capacitance per Channel -10 -1 -3.0 3 Min Typ Max -15 Units mA A nA A A V V V V pF Conditions fCLK = 6MHz, fDATA = 3MHz LE = LOW -250 -100 -10 +10 VDD +1 All VIN = 0V Output high, and at -375V VIH = VDD VI = 0V IDOUT = -100A IHVOUT = -0.25mA IDOUT = 100A IOL = 1mA VDS = 100V
AC Characteristics
Symbol fCLK tW tSU tH tWLE tDLE tSLE tDHL tDLH
(For VDD = -5V, TA = 25C)
Parameter Clock Frequency Clock Width High or Low Data Setup Time Before Clock Falls Data Hold Time After Clock Falls Width of Latch Enable Pulse LE Delay Time After Falling Edge of Clock LE Setup Time Before Falling Edge of Clock Clock Delay Time Data High to Low Clock Delay Time Data Low to High
Min
Typ
Max 6
Units MHz ns ns ns ns ns ns
Conditions
83 35 15 83 35 40 160 160
ns ns
Recommended Operating Conditions
Symbol VDD HVOUT VIH VIL TA Logic supply voltage High voltage output High-level input voltage Low-level input voltage Operating free-air temperature Parameter Min -4.5 +0.3 -3.5 0 -40 Typ -5.0 Max -5.5 -375 VDD -0.8 +85 Units V V V V C
Notes: All voltages are referenced to VSS. Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. Power-down sequence should be the reverse of the above.
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HV4937
Input and Output Equivalent Circuit
VSS VSS
VSS
Input
Data Out
HVIN
HVOUT
VDD Logic Inputs
VDD Logic Data Output High Voltage Output
Switching Waveforms
VIH Data In Data Valid 1 tSU Clock VIL Data Out tWH tWL tH VIH Data Valid 2 VIL
VOL tDHL VOH Data Out tDLH VIH VIL tDLE tWLE tSLE
Latch Enable
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HV4937
Functional Block Diagram
VSS Output Enable Latch Enable Data Input HVOUT1 Clock HVOUT2 64 bit Static Shift Register 64 Latches * * * 60 Additional Outputs * * * HVOUT63
DIR
HVOUT64 Data Out
Function Table
Inputs Function All off Load S/R Data X H or L H or L Load Latch Output Enable Transparent Latch Mode H or L X H L CLK X H or L LE X L L H H H H OE L L L L H H H DIR X H L X X X X Shift Reg 1 2 ... 64 *...* H or L...Qn Qn+1 H or L...Qn Qn-1 H or L...* H or L...* H...* L ...* Outputs Latch HVOUT 1 2 ... 64 1 2 ... 64 *...* *...* *...* H or L...* H or L...* H...* L...* H...H H...H H...H H...H L or H...* L ...* H...* DOUT * * * * * * *
Notes: X = Don't care * = Dependent on previous stage's state before the last CLK : High to low transition. = -5V to VSS transition H = VDD L = VSS
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HV4937
Pin Configurations
PG Package HV49 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function VSS N/C HVOUT 59/6 HVOUT 60/5 HVOUT 61/4 HVOUT 62/3 HVOUT 63/2 HVOUT 64/1 DIR Data Out CLK VSS VDD LE Data In OE HVOUT 1/64 HVOUT 2/63 HVOUT 3/62 HVOUT 4/61 HVOUT 5/60 HVOUT 6/59 N/C VSS HVOUT 7/58 HVOUT 8/57 HVOUT 9/56 HVOUT 10/55 HVOUT 11/54 HVOUT 12/53 HVOUT 13/52 HVOUT 14/51 HVOUT 15/50 HVOUT 16/49 HVOUT 17/48 HVOUT 18/47 HVOUT 19/46 HVOUT 20/45 HVOUT 21/44 HVOUT 22/43 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function N/C N/C HVOUT 23/42 HVOUT 24/41 HVOUT 25/40 HVOUT 26/39 HVOUT 27/38 HVOUT 28/37 HVOUT 29/36 HVOUT 30/35 HVOUT 31/34 HVOUT 32/33 HVOUT 33/32 HVOUT 34/31 HVOUT 35/30 HVOUT 36/29 HVOUT 37/28 HVOUT 38/27 HVOUT 39/26 HVOUT 40/25 HVOUT 41/24 HVOUT 42/23 N/C N/C HVOUT 43/22 HVOUT 44/21 HVOUT 45/20 HVOUT 46/19 HVOUT 47/18 HVOUT 48/17 HVOUT 49/16 HVOUT 50/15 HVOUT 51/14 HVOUT 52/13 HVOUT 53/12 HVOUT 54/11 HVOUT 55/10 HVOUT 56/9 HVOUT 57/8 HVOUT 58/7
Package Outline
64 65 41 40
Index 80 1 top view 80-pin Gullwing Package 24 25
Note: Pin designation DIR = H or L Example: For DIR = H, Pin 3 is HVOUT 59 For DIR = L, Pin 3 is HVOUT 6
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