View ISL45042IR-T_719456.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL45042
Data Sheet June 21, 2005 FN6072.3
LCD Module Calibrator
The VCOM voltage of an LCD panel needs to be adjusted to remove flicker. This part provides a digital interface to control the sink-current output that attaches to an external voltage divider. The increase in output sink current lowers the voltage on the external divider, which is applied to an external VCOM buffer amplifier. Once the desired VCOM setting is obtained, the settings can be stored in the nonvolatile memory, which would then be automatically recalled during every power-up. The VCOM adjustment and non-volatile memory programming is through a single interface pin. An additional pin is used to prevent programming. An external resistor attaches to the SET pin, and sets the full-scale sink current that determines the lowest voltage of the external voltage divider. The ISL45042 is available in an 8-pin 3mm x 3mm Thin DFN package with a maximum thickness of 0.8mm for ultra thin LCD panel design.
Features
* 128-Step Adjustable Sink Current Output * 2.6V to 3.6V Logic Supply Voltage Operating Range * 4.5V to 20V Analog Supply Voltage Range * Rewritable EEPROM for storing the optimum VCOM value * Output Adjustment Enable/Disable Control * Output Guaranteed Monotonic Over Temperature * Two Pin Adjustment, Programming and Enable * Ultra Thin 8-Pin 3mm x 3mm DFN (0.8mm max) * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* LCD Panels
Ordering Information
PART NO. ISL45042IR TEMP. RANGE (C) -40 to 85 -40 to 85 PACKAGE 8 Ld 3x3 Thin DFN 8 Ld 3x3 Thin DFN Tape and Reel 8 Ld 3x3 Thin DFN (Pb-free) 8 Ld 3x3 Thin DFN Tape and Reel (Pb-free) PKG. DWG. # L8.3x3A L8.3x3A
Pinout
ISL45042 (THIN DFN) TOP VIEW
OUT 1 AVDD 2 N/C 3 GND 4 8 7 6 5 SET CE CTL VDD
ISL45042IR-T
ISL45042IRZ (Note) ISL45042IRZ-T (Note)
-40 to 85
L8.3x3A
-40 to 85
L8.3x3A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL45042 Pin Descriptions
PIN OUT FUNCTION Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 128. See SET pin function description for the maxim adjustable sink current setting. High-Voltage Analog Supply. Bypass to GND with 0.1F capacitor. No Connect. Not internally connected. Ground connection. System power supply input. Bypass to GND with 0.1F capacitor. Internal Counter Up/Down Control and Internal EEPROM Programming Control Input. If CE is high, a mid-to-low transition increments the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage at OUT. Applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-bit counter. See EEPROM Programming section for details. Counter Enable Pin. Connect CE to VDD to enable counting of the internal counter. Connect CE to GND to inhibit counting. Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET.
AVDD N/C GND VDD CTL
CE SET
Block Diagram
ISL45042 CE AVDD
IBIAS UP CTL DWN DIGITAL INTERFACE WITH THRESHOLD SENSORS PWRUP POR PRGM UP/DOWN COUNTER WITH PRESET LATCHES ANALOG DCP AND CURRENT OUTPUT BLOCK SET IOUT
READ POR EEPROM OR NVL MEMORY
PRGM MEMORY
PRGM
GND
VDD
2
FN6072.3 June 21, 2005
ISL45042
Absolute Maximum Ratings
VDD to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4V Input Voltages to GND SET, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V CTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V Output Voltages to GND OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V ESD Rating HBM for Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75kV HBM for CTL to GND (no EEPROM Content Disruption). . . . .8kV
Thermal Information
Thermal Resistance (Typical, Note 1)
JA
8 Ld Thin DFN Package. . . . . . . . . . . . . . . . . . . . . . 90(C/W) Moisture Sensitivity (see Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Junction Temperature (Plastic Package) . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (Lead Tips Only) Erase/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10,000 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 years @ 85C
Operating Conditions
Temperature Range ISL45042IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9k; Unless Otherwise Specified. Typicals are at TA = 25C SYMBOL TEST CONDITIONS TEMP (C) MIN TYP MAX UNITS
PARAMETER DC CHARACTERISTICS VDD Supply Range
VDD
For Programming For Operation
0 to 85 Full Full Full 0 to 85 Full Full
3 2.6 4.5 0.7*VDD 0.2*VDD 20 20 1.6 1 4.9
10 -
3.6 3.6 50 20 23 3 20 20 0.8*VDD 0.3*VDD 200 200 10 10 10 0.4 15.75
V V A A mA mA V A V V s s s s s A A pF V V ms V
VDD Supply Current
IDD
CE = VDD CE = GND Program (Charge Pump Current) (Note 5) Read (Note 5)
AVDD Supply Range AVDD Supply Current CTL High Voltage CTL Low Voltage CTL High Rejected Pulse Width CTL Low Rejected Pulse Width CTL High Minimum Pulse Width CTL Low Minimum Pulse Width CTL Minimum Time Between Counts CTL Input Current
AVDD IAVDD CTLIH CTLIL CTLIHRPW CTLILRPW CTLIHMPW CTLILMPW CTLMTC ICTL CTL = GND CTL = VDD (Note 3) 2.6V < VDD < 3.6V 2.6V < VDD < 3.6V
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
CTL Input Capacitance CE Input Low Voltage CE Input High Voltage CE Minimum Start Up Time CTL EEPROM Program Voltage
CTLCAP CEIL CEIH CEST CTLPROM
(Note 5) 2.6V < VDD < 3.6V 2.6V < VDD < 3.6V (Note 5) 2.6V < VDD < 3.6V, (Note 2)
3
FN6072.3 June 21, 2005
ISL45042
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9k; Unless Otherwise Specified. Typicals are at TA = 25C (Continued) SYMBOL CTLPT PT EEWC SETVR SETDN SETZSE SETFSE ISET SETER Through RSET (Note 5) To GND, AVDD = 20V (Note 5) To GND, AVDD = 4.5V (Note 5) AVDD to SET Voltage Attenuation OUT Settling Time OUT Voltage Range OUT Voltage Drift NOTES: 2. CTL signal only needs to be greater than 4.9V to program EEPROM. 3. Tested at AVDD = 20V. 4. The Counter value is set to mid-scale 4 LSB's in the Production. 5. Simulated and Determined via Design and NOT Directly Tested. AVDD to SET OUTST VOUT OUTVD to 0.5 LSB Error Band (Note 5) (Note 5) (Note 5) Guaranteed by Design (Note 4) Monotonic Over Temperature >4.9V TEST CONDITIONS TEMP (C) Full Full 25 Full Full Full Full Full Full Full Full Full Full 25 to 55 1000 7 10 2.25 VSET + 0.5V 1:20 20 MIN 200 TYP MAX 100 1 2 8 120 200 45 13 10 UNITS s ms Cycles Bits LSB LSB LSB A k k V/V s V mV
PARAMETER CTL EEPROM Programming Signal Time Programming Time EE Write Cycles SET Voltage Resolution SET Differential Nonlinearity SET Zero-Scale Error SET Full-Scale Error SET Current SET External Resistance
Application Information
This device provides the ability to reduce the flicker of an LCD panel by adjustment of the VCOM voltage during production test and alignment. A 128-step resolution is provided under digital control, which adjusts the sink current of the output. The output is connected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing the output sink current.
AVDD ISL45042 SET
RSET
AVDD R1
The adjustment of the output and the programming of the non-volatile memory are provided on one pin, while the counter enable (CE) is provided on a separate pin. The output is adjusted via the CTL pin either by counting up with a mid to low transition, or by counting down with a mid to high transition. Once the minimum or maximum value is reached on the 128-steps, the device will not overflow or underflow beyond that minimum or maximum value. An increment of the counter will increase the output sink current, which will lower the voltage on the external voltage divider. A decrement of the counter will decrease the output sink current, which will raise the voltage on the external voltage divider. Once the desired output level is obtained, the part can store its setting using the non-volatile memory in the device. (See the Non-volatile programming section for detailed information.) The output adjustment can also be prevented from changing by pulling down the counter enable pin.
OUT R2
+
FIGURE 1. OUTPUT CONNECTION CIRCUIT EXAMPLE
4
FN6072.3 June 21, 2005
ISL45042
AVDD Ra VCOM Rb + ISL45042 OUT R2 RSET AVDD
AVDD R1 + VCOM
SET Rc
R1 = Ra R2 = Rb + Rc RSET = (Ra(Rb + Rc)) / 20Rb
FIGURE 2. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE ISL45042
Adjustable Sink Current Output
The device provides an output sink current which lowers the voltage on the external voltage divider. The equations that control the output are given below. See Figure 1.
Setting AVDD IOUT = -------------------- X ---------------------------128 20 ( RSET ) R2 Setting R1 VOUT = --------------------- VAVDD 1 - -------------------- X ---------------------------- R1 + R2 128 20 ( RSET )
To avoid unintentional adjustment, the ISL45042 guarantees to reject CTL pulses shorter than 20s. To avoid the possibility of a false pulse (since the internal comparators come up in an unknown state) the very first CTL pulse is ignored. See Figure 4 for the timing information.
.
1k 0.01F
ISL45042
CTL
NOTE: Where setting is an integer between 1 and 128.
Replacing Existing Mechanical Potentiometer Circuits
Figure 2 shows the common adjustment mechanical circuits and equivalent replacement with the ISL45042.
FIGURE 3. EXTERNAL ESD PROTECTION ON CTL PIN
TABLE 1. TRUTH TABLE INPUT CTL Mid to Hi Mid to Lo X >4.9V X CE Hi Hi Lo X X VDD VDD VDD VDD VDD 0 to VDD SET Decrement Increment No Change OUTPUT ICC Normal Normal Lower MEMORY X X X Program Read
7-Bit UP/DOWN Counter
The counter sets the level to the digital potentiometer and is connected to the non-volatile memory. When the part is programmed, the counter setting is loaded into the non-volatile memory. This value will be loaded from the non-volatile memory into the counter during power-on. The counter will not exceed its maximum level and will hold that value during subsequent increment requests on the CTL pin. The counter will not exceed its minimum level and will hold that value during subsequent decrement requests on the CTL pin.
No Change Increased Read Increased
CTL Pin
CTL should have a noise filter to reduce bouncing or noise on the input that could cause unwanted counting when the CE pin is high. The board should have an additional ESD protection circuit, with a series 1k resistor and a shunt 0.01F capacitor connected on the CTL pin. (See Figure 3) In order to increment the setting, pulse CTL low for more than 200s. The output sink current increases and lowers the VCOM lever by one least-significant bit (LSB). On the other hand, to decrement the setting, pulse CTL high for more than 200s. The output sink current will decrease, and the VCOM level will increase by one LSB.
NOTE: `CE' should be disabled (pulled low) before powering the device down to assure that the glitches and transients will not cause unwanted EEPROM overwriting. NOTE: In case where CE is tied to VDD, CTL pin should be tied to ground (pulled low) when the programming is finished (should not move the counter as the first pulse after programming is ignored), and before the power-down. This will assure that no glitches or transients on CTL input would cause unwanted counter movements.
5
FN6072.3 June 21, 2005
ISL45042
CEST CTLMTC CTLIHRPW
CTL HIGH CTL VDD/2 CTL LOW CTLIHMPW CTLILMPW CTLILRPW
CE
COUNTER OUTPUT
UNDEF.
78
79
7A
7B
7A
VCOM
FIGURE 4. VCOM ADJUSTMENT
Non-Volatile Memory (EEPROM) Programming
When the CTL pin exceeds 4.9V, the non-volatile programming cycle will be activated. The CTL signal needs to remain above 4.9V for more than 200s. The level and timing needed to program the non-volatile memory is given below. It then takes a maximum of 100ms for the programming to be completed inside the device (see PT specification in Electrical Specification Table).
CTL VOLTAGE >200s 4.9V
CTLPT
TIME
FIGURE 5. EEPROM PROGRAMMING
6
FN6072.3 June 21, 2005
ISL45042 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X A 0.15 C A D 2X 0.15 C B
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A3 b D D2 E E2 e
0.08 C
MIN 0.70 0.25 2.20 1.40 0.25 0.20
NOMINAL 0.75 0.02 0.20 REF 0.30 3.00 BSC 2.30 3.00 BSC 1.50 0.65 BSC 0.30 8 4
MAX 0.80 0.05 0.35 2.40 1.60 0.40
NOTES 5, 8 7, 8, 9 7, 8, 9 8 2 3 Rev. 3 11/04
E 6 INDEX AREA TOP VIEW B
// A C SEATING PLANE SIDE VIEW
0.10 C
k L N Nd
A3
D2 (DATUM B) 6 INDEX AREA (DATUM A) 1 2 D2/2
7
8
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals.
NX k E2 E2/2
3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-WEEC-2 except for the "L" min dimension.
L1 10 L
NX L N 8 N-1 e (Nd-1)Xe REF. BOTTOM VIEW (A1) C L NX b 5 0.10 M C A B
NX (b) 5 SECTION "C-C"
e TERMINAL TIP FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7
FN6072.3 June 21, 2005

▲Up To Search▲

Price & Availability of ISL45042IR-T

	To Download ISL45042IR-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .