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HIP1012A
Data Sheet March 2004 FN4419.6
Dual Power Distribution Controller
The HIP1012A is a HOT SWAP dual supply power distribution controller. Two external N-Channel MOSFETs are driven to distribute power while providing load fault isolation. At turn-on, the gate of each external N-Channel MOSFET is charged with a 10A current source. Capacitors on each gate (see the Typical Application Diagram), create a programmable ramp (soft turn-on) to control inrush currents. A built in charge pump supplies the gate drive for the 12V supply N-Channel MOSFET switch. Overcurrent protection is facilitated by two external current sense resistors. When the current through either resistor exceeds the user programmed value the controller enters the current regulation mode. The time-out capacitor, CTIM, starts charging as the controller enters the time out period. Once CTIM charges to a 2V threshold, the N-Channel MOSFETs are latched off. In the event of a fault at least three times the current limit level, the N-Channel MOSFET gates are pulled low immediately before entering time out period. The controller is reset by a rising edge on either PWRON pin. Choosing the voltage selection mode the HIP1012 controls either +12V/5V or +3.3V/+5V supplies.
Features
* HOT SWAP Dual Power Distribution Control for +5V and +12V or +5V and +3.3V * Provides Fault Isolation * Programmable Current Regulation Level * Programmable Time Out * Charge Pump Allows the Use of N-Channel MOSFETs * Power Good and Overcurrent Latch Indicators * Enhanced Overcurrent Sensitivity Available * Redundant Power On Controls * Adjustable Turn-On Ramp * Protection During Turn-On * Two Levels of Current Limit Detection Provide Fast Response to Varying Fault Conditions * Less Than 1s Response Time to Dead Short * 3s Response Time to 200% Current Overshoot * Pb-Free Package Option * Tape & Reel Packaging with `-T' Part Number Suffix
Ordering Information
PART NUMBER HIP1012ACB HIP1012ACBZA (Note) TEMP. RANGE (C) -0 to 70 -0 to 70 PACKAGE 14 Ld SOIC PKG. DWG. # M14.15
Applications
* Redundant Array of Independent Disks (RAID) System * Power Distribution Control * Hot Plug, Hot Swap Components
14 Ld SOIC( Pb-free) M14.15
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
HIP1012A (SOIC) TOP VIEW
3/12VS 3/12VG VDD MODE/ PWRON1 PWRON2 5VG 5VS 1 2 3 4 5 6 7 14 3/12VISEN 13 RILIM 12 GND 11 CPUMP 10 CTIM 9 8 PGOOD 5VISEN
Typical Application Diagram
CPUMP RSENSE 12V OPTIONAL VDD RFILTER CFILTER CGATE RGATE HIP1012A
3/12VS 3/12VG VDD M/PON1 PWRON2 5VG 5VS 3/12VISEN RILIM GND CPUMP CTIM PGOOD 5ISEN
RLOAD RILIM
POWER ON INPUTS 5V CGATE RGATE
CTIM 5V OR 3.3V
RSENSE
RLOAD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Simplified Block Diagram
12VIN
RSENSE
TO LOAD
12VS
OC
CLIM + -
R 100A 2R
12V
12ISEN
10A
2
12VG FALLING EDGE DELAY 18V CGATE 20 OPTIONAL VDD RFILTER CFILTER PWRON1 RISING EDGE RESET VDD R QN R Q S 20 CGATE 10A 5VG PWRON2 12V ENABLE FALLING EDGE DELAY 5VS 5VIN
+ 3X
RILIM RILIM
ENABLE
18V
POR
GND
ENABLE
QPUMP 12V 10A TO VDD CPUMP
HIP1012A
CPUMP
12V 3X + CLIM + OC R PGOOD 5ISEN HIP1012A OPTIONAL 2R + 2V CTIM CTIM + PGOOD OC LATCH
RSENSE
TO LOAD
HIP1012A Pin Descriptions
PIN # 1 2 SYMBOL 3V/12VS 3V/12VG FUNCTION 3.3 V/12V Source 3.3V/12V Gate DESCRIPTION Connect to source of associated external N-Channel MOSFET switch to sense output voltage. Connect to the gate of associated N-Channel MOSFET switch. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to 17.4V by a 10A current source when in 5v/12V mode of operation, otherwise capacitor will be charged to 11.4V. A small resistor (10 - 200) should be placed in series with the gate capacitor to ground to prevent current oscillations. Connect to 12V supply. This can be either connected directly to the +12V rail supplying the load voltage or to a dedicated VDD +12V supply. If the former is chosen special attention to VDD decoupling must be paid.
3
VDD
Chip Supply
4
MODE/ PWRON1 PWRON2
5
PWRON1 and PWRON2 are used to turn-on and reset the chip. Both outputs turn-on when Power ON/ Reset Invokes 3.3V operation either pin is driven low. After a current limit time out, the chip is reset by the rising edge of a when shorted to VDD, pin 3. reset signal applied to either PWRON pin. Each input has 100A pull up capability which is compatible with 3V and 5V open drain and standard logic. PWRON1 is also used to invoke Power ON/ Reset 3.3V control operation in preference to +12V control. By tying pin 4 to pin 3 the charge pump is disabled and the UV threshold also shifts to 2.8V. 5V Gate Connect to the gate of the external 5V N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to 11.4V by a 10A current source. A small resistor (10 - 200) should be placed in series with the gate capacitor to ground to prevent current oscillations. Connect to the source side of 5V external N-Channel MOSFET switch to sense output voltage. Connect to the load side of the 5V sense resistor to measure the voltage drop across this resistor between 5VS and 5VISEN pins. Indicates that all output voltages are within specification. PGOOD is driven by an open drain N-Channel MOSFET. It is pulled low when any output is not within specification. Connect a capacitor from this pin to ground. This capacitor controls the time between the onset of current limit and chip shutdown (current limit time-out). The duration of current limit time-out (in seconds) = 200k x CTIM (Farads). Connect a 0.1F capacitor between this pin and VDD (pin3). Directly connect this pin to VDD when in 3.3V control mode.
6
5VG
7 8 9 10
5VS 5VISEN PGOOD CTIM
5V Source 5V Current Sense Power Good indicator Current Limit Timing Capacitor Charge Pump Capacitor Chip Ground Current Limit Set Resistor
11 12 13
CPUMP GND RILIM
A resistor connected between this pin and ground determines the current level at which current limit is activated. This current is determined by the ratio of the RILIM resistor to the sense resistor (RSENSE). The current at current limit onset is equal to 10A x (RILIM/ RSENSE). Connect to the load side of sense resistor to measure the voltage drop across this resistor.
14
3V/12VISEN
3.3V/12V Current Sense
3
HIP1012A
Absolute Maximum Ratings TA = 25C
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +13.2V 3/12VG, CPUMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 18.5V 3/12VISEN, 3/12VS . . . . . . . . . . . . . . . . . . . . . . . -5V to VDD + 0.3V 5VISEN, 5VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 7.5V PGOOD, RILIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V MODE/PWRON1, PWRON2, CTIM, 5VG . . . . . -0.3V to VDD + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (Class 2)
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (SOIC - Lead Tips Only)
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . +10.5V to +13.2 Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER 12V CONTROL SECTION Current Limit Threshold Voltage (Voltage Across Sense Resistor)
VDD = 12V, CVG = 0.01F, CTIM = 0.1F, RSENSE = 0.1, CBULK = 220F, ESR = 0.5, TA = TJ = 0C to 70C, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VIL12V VIL12V 3XViL12V 3XVIL12V 20%iLrt 10%iLrt 1%iLrt RTSHORT tON12V ION12V 3XdisI 12VVUV V12VG
RILIM =10k RILIM = 5k RILIM =10k RILIM = 5k 200% Current Overload, RILIM = 10k, RSHORT = 6.0 200% Current Overload, RILIM = 10k, RSHORT = 6.0 200% Current Overload, RILIM = 10k, RSHORT = 6.0 C12VG = 0.01F C12VG = 0.01F C12VG = 0.01F 12VG = 18V
92 47 250 100 8 0.5 10.5
100 53 300 165 2 4 10 500 12 10 0.75 10.8 17.3
108 59 350 210 1000 12 11.0 17.9
mV mV mV mV s s s ns ms A A V V
3X Current Limit Threshold Voltage (Voltage Across Sense Resistor) 20% Current Limit Response Time (Current within 20% of Regulated Value) 10% Current Limit Response Time (Current within 10% of Regulated Value) 1% Current Limit Response Time (Current within 1% of Regulated Value) Response Time To Dead Short Gate Turn-On Time Gate Turn-On Current 3X Gate Discharge Current 12V Undervoltage Threshold Qpumped 12VG Voltage 3.3V/5V CONTROL SECTION Current Limit Threshold Voltage (Voltage Across Sense Resistor) 3X Current Limit Threshold Voltage (Voltage Across Sense Resistor) 20% Current Limit Response Time (Current within 20% of regulated value) 10% Current Limit Response Time (Current within 10% of Regulated Value) 1% Current Limit Response Time (Current within 1% of Regulated Value) Response Time To Dead Short Gate Turn-On Time
CPUMP = 0.1F
16.8
VIL5V 3XVIL5V
RILIM =10k RILIM = 5k RILIM =10k RILIM = 5k 200% Current Overload, RILIM = 10k, RSHORT = 2.5 200% Current Overload, RILIM = 10k, RSHORT = 2.5 200% Current Overload, RILIM = 10k, RSHORT = 2.5
92 47 250 100 -
100 53 300 155 2 4 10 500 5
108 59 350 210 -
mV mV mV mV s
s s 800 ns ms
RTSHORT tON5V
CVG = 0.01F CVG = 0.01F
4
HIP1012A
Electrical Specifications
PARAMETER Gate Turn-On Current 3X Gate Discharge Current 5V Undervoltage Threshold 3.3V Undervoltage Threshold 3.3/5VG High Voltage VDD = 12V, CVG = 0.01F, CTIM = 0.1F, RSENSE = 0.1, CBULK = 220F, ESR = 0.5, TA = TJ = 0C to 70C, Unless Otherwise Specified (Continued) SYMBOL ION5V 3XdisI 5VVUV 3.3VVUV 3/5VG TEST CONDITIONS CVG = 0.01F CVG = 0.01F, PWRON = Low MIN 8 0.5 4.35 2.65 11.2 TYP 10 0.75 4.5 2.8 11.9 MAX 12 4.65 2.95 UNITS A A V V V
SUPPLY CURRENT AND IO SPECIFICATIONS VDD Supply Current VDD POR Rising Threshold VDD POR Falling Threshold Current Limit Time-Out PWRON Pull-up Voltage PWRON Rising Threshold PWRON Hysteresis PWRON Pull-Up Current Current Limit Time-Out Threshold (CTIM) CTIM Charging Current CTIM Discharge Current CTIM Pull-Up Current RILIM Pin Current Source Output Charge Pump Output Current Charge Pump Output Voltage Charge Pump Output Voltage - Loaded Charge Pump POR Rising Threshold Charge Pump POR Falling Threshold TILIM PWRN_V PWR_Vth PWR_hys PWRN_I CTIM_Vth CTIM_I CTIM_disI CTIM_disI RILIM_Io Qpmp_Io Qpmp_Vo Qpmp_VIo Qpmp+Vth Qpmp-Vth CPUMP = 0.1F, CPUMP = 16V No load Load current = 100A VCTIM = 8V CTIM = 0.1F PWRON pin open IVDD 4 9.5 9.3 16 1.8 1.1 0.1 60 1.8 8 1.7 3.5 90 320 17.2 16.2 15.6 15.2 8 10.0 9.8 20 2.4 1.5 0.2 80 2 10 2.6 5 100 560 17.4 16.7 16 15.7 10 10.7 10.3 24 3.2 2 0.3 100 2.2 12 3.5 6.5 110 800 16.5 16.2 mA V V ms V V V A V A mA mA A A V V V V
HIP1012A Description and Operation
The HIP1012A is a multifeatured dual power supply distribution controller, including programmable current limiting regulation and time to latch off. Additionally the HIP1012A operates both as a +3.3V and 5V or a +5V and +12V power supply controller with each mode having appropriate UnderVoltage (UV) fault notification levels. Upon initial power up HIP1012A can either isolate the voltage supply from the load by holding the external N-Channel MOSFET switches off or apply the supply rail voltage directly to the load for true hot swap capability. In either case the HIP1012A turns on in a soft start mode protecting the supply rail from sudden current loading. If either PWRON pin is pulled low the HIP1012A will be in true hot swap mode. Both PWRON pins must be high to turn off the HIP1012A thus isolating the power supply from the load through the external FETs. At turn-on, the gate capacitor of each external N-Channel MOSFET is charged with a 10A current source. These capacitors create a programmable ramp (soft turn-on). A charge pump supplies the gate drive for the 12V supply switch driving that gate to 17V. The load currents pass through two external current sense resistors. When the voltage across either resistor exceeds the user programmed Overcurrent (OC) voltage threshold value, (see Table 1) the controller enters current regulation. At this time the time-out capacitor, CTIM, starts charging with a 10A current source and the controller enters the time out period. The length of the time out period is set by the single external capacitor (see Table 2) placed from the CTIM pin (pin 10) to ground and is characterized by a lowered gate drive voltage to the appropriate external N-Channel MOSFET. Once CTIM charges to 2V, an internal comparator is tripped resulting in both N-Channel MOSFETs being latched off.
5
HIP1012A
TABLE 1. RILIM RESISTOR 15k 10k 7.5k 4.99k NOTE: Nominal OC Vth = Rilim x 10A. NOMINAL OC VTH 150mV 100mV 75mV 50mV
and motor startup currents, choosing the current limiting level is crucial to provide both protection and still allow for this inrush current without latching off. Consider this in addition to the time out delay when choosing MOSFETs for your design. To these ends it is suggested that CR levels be programmed to 150% of nominal load. When using the HIP1012A in the 12V and 5V mode additional VDD decoupling may be necessary to prevent a power on reset due to a sag on VDD pin upon an OC latch off. The addition of a capacitor from VDD to GND may often be adequate but a small value isolation resistor may also be necessary (see the Simplified Block Diagram on page 2). Current loop stabilization is facilitated through a small value resistor in series with the gate timing capacitor. As the HIP1012A drives a highly inductive current load, instability characterized by the gate voltage repeatedly ramping up and down may appear. A simple method to enhance stability is provided by the substitution of a larger value gate resistor. Typically this situation can be avoided by eliminating long point to point wiring to the load. Random resets occur if the HIP1012A sense pins are pulled below ground when turning off a highly inductive load. Place a large load capacitor (10-50F) on the output or ISEN clamping diodes to ground to eliminate. During the Time Out delay period with the HIP1012A in current limit mode, the VGS of the external N-Channel MOSFETs is reduced driving the N-Channel MOSFET switch into a high rDS(ON) state. Thus avoid extended time out periods as the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET manufacturer's data sheet for SOA information. External Pull Down resistors from the xISEN pins to ground will prevent the voltage outputs from floating up due to leakage current through the external switch FET body diode when the FETs are disabled and the outputs are open. Physical layout of Rsense resistors is critical to avoid the possibility of false overcurrent occurrences. Ideally trace routing between the Rsense resistors and the HIP1012A is direct and as short as possible with zero current in the sense lines as shown below.
CORRECT INCORRECT
TABLE 2. CTIM CAPACITOR 0.022F 0.047F 0.1F NOMINAL TIME OUT PERIOD 4.4ms 9.4ms 20ms
NOTE: Nominal time-out period in seconds = CTIM x 200k.
The HIP1012A responds to a load short (defined as a current level 3X the OC set point) immediately, driving the relevant N-Channel MOSFET gate to 0V in less than 10s. The gate voltage is then slowly ramped up turning on the N-Channel MOSFET to the programmed current limit level; this is the start of the time out period. The programmed current level is held until either the OC event passes or the time out period expires. If the former is the case then the N-Channel MOSFET is fully enhanced and the CTIM charging current is diverted away from the capacitor. If the time out period expires prior to OC resolution then both gates are quickly pulled to 0V turning off both N-Channel MOSFETs simultaneously. Upon any UV condition the PGOOD signal will pull low when tied high through a resistor to the logic supply. This pin is a fault indicator but not the OC latch off indicator. For an OC latch off indication, monitor CTIM, pin 10. This pin will rise rapidly to 12V once the time out period expires. See Simplified Block Diagram on page 2 for OC latch off circuit suggestion. The HIP1012A is reset by a rising edge on either PWRON pin and is turned on by either PWRON pin being driven low. The HIP1012A can control either +12V/5V or +3.3V/+5V supplies. Tying the PWRON1 pin to VDD , invokes the +3.3V/+5V voltage mode. In this mode, the external charge pump capacitor is not needed and Cpump, pin 11 is tied directly to VDD .
HIP1012A Application Considerations
Current Regulation vs current trip often causes confusion when using this and other ICs with a Current Regulation (CR) feature. The CR level is the level at which the HIP1012 will hold an overcurrent load for the programmed duration. This level is programmable by the RLIM and RSENSE resistors values. As the current being monitored by the HIP1012A approaches a level >85% of the CR level the HIP1012A may trip-off due to variances in manufacturing and the design of the low gain high speed input comparators. In addition with the high levels of inrush current e.g., highly capacitive loads 6
TO ISEN AND RISET
CURRENT SENSE RESISTOR
FIGURE 1. SENSE RESISTOR PCB LAYOUT
HIP1012A Typical Performance Curves
8.4 8.2 SUPPLY CURRENT(mA) 105
7.8 7.6 7.4 7.2 -40
CURRENT (A)
8.0
104
103
-30
-20 -10
0
10
20
30
40
50
60
70
80
102 -40
-30
-20
-10
0
10
20
30
40
50
60
70
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 2. SUPPLY CURRENT
FIGURE 3. RILIM SOURCE CURRENT
10.7 CTIM OC VOLTAGE THRESHOLD (V) -30 -20 -10 0 10 20 30 40 50 60 70 80 CTIM CURRENT SOURCE (A)
2.04
10.6
2.02
2.00
10.5
1.98
10.4
1.96
10.3 -40
1.94 -40
-30 -20 -10
0
10
20
30
40
50
60
70
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 4. CTIM CURRENT SOURCE
FIGURE 5. CTIM OC VOLTAGE THRESHOLD
11.00
4.615
2.888
12V UV THRESHOLD (V)
4.610
5V UV
2.886
10.98
4.605 3.3V UV 4.600
2.884
10.96
2.882
10.94 -40
-20
0
20
40
60
80
4.595 -40
-20
0
20
40
60
80
2.880
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 6. 12V UV THRESHOLD
FIGURE 7. 5V/3.3V UV THRESHOLD
7
3.3V UV THRESHOLD (V)
5V UV THRESHOLD (V)
HIP1012A Typical Performance Curves
17.36
(Continued)
11.935 11.930 3.3V, 5V GATE DRIVE (V) 17.6
17.34 12V GATE DRIVE (V) 12V VG 17.32
17.4 CHARGE PUMP VOLTAGE NO LOAD VOLTAGE (V) 17.2
11.925 11.920 11.915
17.30 3.3V, 5V VG 17.28
17.0 CHARGE PUMP VOLTAGE 100A LOAD
11.910 11.905 11.900 80
16.8
17.26
-40
-20
0
20
40
60
16.6 -40
-20
TEMPERATURE (C)
0 20 40 TEMPERATURE (C)
60
80
FIGURE 8. 12V, 3/5V GATE DRIVE
FIGURE 9. PUMP VOLTAGE
54.5 VOLTAGE THRESHOLD (mV) VOLTAGE THRESHOLD (mV)
102.5
54.0
12 OC Vth
102.0
12 OC VTth
53.5
101.5
5 OC Vth 53.0
101.0
5 OC Vth
52.5 -40
-20
0
20
40
60
80
100.5 -40
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 10. OC VOLTAGE THRESHOLD WITH RLIM = 5k
FIGURE 11. OC VOLTAGE THRESHOLD WITH RLIM = 10k
10.2 VDD LOW TO HIGH POWER ON RESET (V) 10.0
9.8
VDD HIGH TO LOW
9.6 -40
-30 -20 -10
0
10
20
30
40
50
60
70
80
TEMPERATURE (C)
FIGURE 12. POWER ON RESET VOLTAGE THRESHOLD
8
HIP1012A Exploring and Using the HIP1012EVAL1 Board (Figures 13 and 14)
The HIP1012EVAL1 is a flexible platform for a thorough evaluation of the HIP1012A dual power supply controller. This eval board comes in three separate parts allowing the evaluation of two principal configurations. To simulate a passive back plane implementation both the GENERIC and LOAD sections are first connected together and then the GENERIC board is connected onto the BUS board. For an active backplane or for the HIP1012A on an interposer board configuration, the BUS and GENERIC sections are first connected together and then the load board is connected onto the GENERIC board. The HIP1012EVAL1 board has many built in features besides the configuration flexibility described above. The BUS board is designed so that adding suitable connectors and/or power supply capacitive filtering is very easy to do through the numerous through holes for each rail voltage and ground. Passive backplane power sequencing can be simulated by simply shortening the finger lengths for the rail(s) that need to come up after initial ground connection is made. The GENERIC board, is a flexible evaluation platform with many designed in features for user customizing and evaluation. The circuit is shipped default configured in the 3.3V and 5V controller mode by jumpers for easy reconfiguration (see Table 3 for jumper settings). The default configuration is highlighted in Table 3. The default OC levels are 5A on the 3.3V and 1A on the 5V supplies. To operate the HIP1012 GENERIC board in its default configuration (3V and 5V) a dedicated +12V power supply must be provided for the HIP1012 through tie point, W1 on the generic board. To operate the board in the +12V and 5V mode, JP2 and JP3 need to be reconfigured (see Table 3) and a suitable current load needs to be provided. A programmable electronic current load is an excellent evaluation tool for this device. The load board is configured to sink about 3A 1A at 3.3V. For 12V operation, the load must be modified to sink less than 5A, otherwise, an OC failure upon power will occur. The GENERIC board is provided with a single pair of N-Channel MOSFETs, if currents > 6A are to be evaluated then an additional pair of MOSFETs can be installed in the provided space to reduce distribution losses. Additionally, for even higher current evaluations, space for TO-252AA, DPAK or D2PAK devices has been provided. Tie points on the output side of the GENERIC board are provided for direct access to a high current load. Performance customizing can easily be accomplished by substitution/addition of several SMD components to the existing layout or by utilizing the included bread board area. See Table 5 for the component listing and applicable formulae. The LOAD board, consists of four load switches, output resistive and capacitive loads and output on indicating
1
LED's. The resistive loads are configured so that either no current, a low or high current load relative to the OC trip point can be invoked for both supplies. An OC event can be emulated by switching both switches of any one output to the on position (see Table 4, OC conditions highlighted). Load connection sequencing can be done by shorting the desired finger lengths. As noted, the GENERIC board is default configured for 3V and 5V operation. For 12V evaluation replace RL3 and RL4 with a suitable load.
TABLE 3. JUMPER CONFIGURATION JP # 1 OPEN / SHORT CIRCUIT CONDITION
Short to GND PWRON2 shorted to ground. True HOT SWAP mode. PWRON1 only controls reset 2-3 with rising edge. Short to 5V 1-2 Open PWRON2 shorted to 5V. Reset and turn on controlled only by PWRON1. Single input control mode PWRON2 will be internally pulled high to ~2.5V, compatible with logic signal. The HIP1012A can not turn on until PWRON2 is driven low. HIP1012A must be powered from a dedicated +12V power supply. HIP1012A VDD pin connected to same 12V supply as load. See Decoupling Concerns in Critical Items section. C1 in circuit. Charge pump capacitor necessary for 5V and 12V operating mode to develop ~ 11.7V for 12VG voltage. Shorts across charge pump capacitor, C1. Capacitor not needed in 3V and 5V mode.
1
2 2
Open Short
3
Open
3 4
Short
Short to GND HIP1012A MODE/PWRON1 shorted to 1-2 ground. True HOT SWAP mode. PWRON2 rising edge only resets HIP1012A. Short to 5V 2-4 Short to VDD 2-3 Open MODE/PWRON1 shorted to 5V. PWRON2 only single mode control. HIP1012A MODE/PWRON1 connected to VDD pin. This along with JP3 installed invokes and configures HIP1012A for 3V and 5V operation. Controlled by PWRON2 HIP1012A MODE/PWRON1 will be internally pulled high to ~2.5V, compatible with logic. Redundant controller mode when each PWRON pin is driven by separate signals.
4 4
4
TABLE 4. LOAD CURRENT SW13 0 0 1 1 SW14 0 1 0 1 3.3V IOUT A 0 2 4 6 SW11 0 0 1 1 SW12 0 1 0 1 5.0V IOUT A 0 0.5 0.74 1.24
9
HIP1012A
CEC1 3 /12VIN GND GND 5VIN 1 JP2
CEC2 Q2 R4 20 R2 20m C1 0.1F JP1 1 2 U1 3/12VS 3/12VG HIP1012A JP3 3/12ISEN RILIM GND CPUMP CTIM PGOOD 5VISEN 14 13 12 11 10 9 8 C2 0.047F 10k R5 C4 GND 0.01F GND 5VOUT 3 / 12VOUT
VDD 0.1F C5
3 VDD JP4 4 MODE/ PWRON1 5 PWRON2 6 5VG 7 5VS
R3 20 C3 0.01F
R101 LED1
R1 Q1 100m
NOTE: Test point number equals HIP1012A pin number. GENERIC BOARD
CEF CEF 1,2,3 R102 LED2 CEF 4,5,6, 7,8,10 CEF 9,11, 12 SW11 R103 LED3 SW12 SW13 RL3 SW14 1.6 RL4 INPUT CEF RL1 7 RL2 10 GND BJ3 5VIN BJ4 1 GND BJ2 CEF 4,5,6 7,8,10 CEF 9,11,12 3.3/12VIN BJ1 CEF 1,2,3 0.8
LOAD BOARD FIGURE 13.
BUS BOARD
10
11
HIP1012A
FIGURE 14. HIP1012EVAL1 EVAL BOARD
HIP1012A
TABLE 5. HIP1012EVAL1 BOARD COMPONENT LISTING COMPONENT DESIGNATOR GENERIC BOARD U1 Q1, Q2 QxB and QxC R1 R2 R3, R4 R5 R* C3, C4 C1 C2 HIP1012CB or HIP1012ACB RF1K49156, Si4404DY NOT POPULATED 5V Sense Resistor 3.3V/12V Sense Resistor Loop compensation Resistors Current Limit Set Resistor Isolation resistor (not provided, see Decoupling Concerns in Critical Items section) Gate Timing Capacitors Charge Pump Capacitor Time-out Set Capacitor Intersil Corporation, Dual Power Controller N-Channel MOSFET in 8 SOIC or equivalent replacement Mounting areas for additional 8 SOIC, DPAK or D2PAK packaged COMPONENT NAME COMPONENT DESCRIPTION
MOSFETs
100m, 1%, Metal Strip current sensing resistor 20m, 1%, Metal Strip current sensing resistor 20, Resistor in series with gate capacitor. This RC may be necessary to provide current loop stability. Keep resistor < 50. 10k, Current limit = ~10A x (RILIM/ RSENSE). Add resistor (<50) to isolate VDD from load transients if necessary to eliminate random VDD low reset. Cut short to install. 0.01F, 10A charging I source provides slow ramp on of N-Channel MOSFETs 0.1F, Charge Pump Capacitor necessary for +12V and +5V operation. 0.047F, Provides ~9ms of time-out period prior to latch off during which IOC can be resolved. The duration of current limit time-out (in seconds) = 200k x CTIM (Farads). 0.1F, Provides VDD decoupling See Table 3 for jumper configuration descriptions
C5 JP1 JP2 JP3 JP4 LED1 W1 TP1 - TP14 P1 - P2 LOAD BOARD SW11 and RL1 SW12 and RL2 SW13 and RL3 SW14 and RL4 LED2, LED3 BUS BOARD
Vdd decoupling capacitor Jumper to configure PWRON2 Jumper to configure VDD Jumper to configure Charge Pump Cap Jumper to configure PWRON1 Pgood indicator NOT PROVIDED Test Points for HIP1012 pin 1 to pin 14 Edge connector fingers
Lit indicates a fault condition Tie point for dedicated +12V HIP1012 supply, use in default configuration
Modify edge connector finger lengths for power sequencing
5V high load (7) 5V low load (10) 3.3V high load (0.8) 3.3V low load (1.6) Load "HOT" indicators
Switch and load resistor pair to invoke high current load on 5V Switch and load resistor pair to invoke low current load on 5V Switch and load resistor pair to invoke high current load on 3.3V Switch and load resistor pair to invoke low current load on 3.3V Lit indicates N-Channel MOSFETs are on and loads are HOT
Bus interconnect board
12
HIP1012A HIP1012 Evaluation Circuit for Disk Drive Hot Swap HIP1012EVAL2
Introduction
The HIP1012EVAL2 is specifically designed to test and demonstrate hot swapping of disk drives onto passive 12V and 5V power buses using the HIP1012 Hot-Swap control IC. The small size of the board allows it to be included in a shuttle alongside the disk drive during evaluation. The outlined area on the board represents the actual area used for PCB implementation.
Control Connections, Fault Notification, and Test Points
HIP1012 EVAL2 is shipped with JP2 installed so that a connected disk drive is started simply by connecting 12V and 5V power supplies to J2. In this configuration, the ribbon cable is not necessary, since the HIP1012 can be reset by toggling the voltage on VDD. This configuration represents a disk drive that would be removed after any over-current trip and would start immediately upon insertion. Additional control is available using the ribbon cable and resetting the HIP1012 by applying a rising edge to PWRON1. If redundant control is desired, removing JP2 makes the second control signal PWRON2 available to start or reset the chip. An example of this control configuration would be to turn the chip on using PWRON1 and reset it using PWRON2. The PGOOD pin is an open drain logic output which can be tied high through a resistor for fault indication. Upon detection of either overcurrent or undervoltage fault conditions, PGOOD goes low and remains low until the fault condition is cleared. Also included on the ribbon cable are additional monitor points for 12VG, 5VG and CTIM. These are included for monitoring during evaluation and they are not necessary for operation.
Description
The HIP1012EVAL2 board is provided with a standard Molex four-terminal disk-drive power connector. The solder holes J2 allows the board to be connected to a power supply connector on the disk-drive shuttle. PGOOD, PWRON1, PWRON2, 5VG. 12VG, CTIM, VDD and GND are all accessible through a ribbon cable. With JP1 installed, the HIP1012 is powered from the same 12V power supply as the disk drive motor. JP2 connects the control signal PWRON2 to ground allowing the unit to be plugged directly into the power bus for automatic, controlled startup. In this configuration, PWRON1 is available to reset the HIP1012 in case of an over-current trip. Otherwise the HIP1012 can be reset by toggling the voltage on VDD. With JP2 removed, the circuit is controlled using one or both of the PWRON signal lines. The HIP1012EVAL2 is shipped with both jumpers installed. The HIP1012EVAl2 is configured with a 10k RILIM resistor (R5) setting the nominal current limit threshold to 100mV. The 12V current sense resistor (R2) is 20m and the 5V current sense resistor (R1) is 100m. These values set the nominal current limits to 5A and 1A respectively. The CTIM capacitor (C2) sets the time out period to approximately 9ms.
Data Line Considerations
The HIP1012A does not integrate data bus line switches, although control of the data bus can be assisted by the timeout feature of the HIP1012A. During the time-out period, the operating system software can determine whether to halt I/O activity to a disk drive which is undergoing an under-voltage or over-current fault as indicated by the status of PGOOD.
13
HIP1012A
R2 0.020 1% R4, 20 1% C5 0.1F JP2 1 2 C4, 0.01F 12VOUT GND GND U1 HIP1012 3/12VS 3/12ISEN 14 13 12 11 10 9 8 C2 0.047F R5 10k 1% 5VOUT
J2 12VIN GND GND 5VIN 1 J1 VDD 12VG CTIM PWRON1 PWRON2 PGOOD 5VG GND 1 R3, 20 1% C3 0.01F JP1 R6 10 1%
Q2 RF1K49157
C1, 0.1F
RILIM 3/12VG 3V DD GND 4 MODE/ CPUMP 5 PWRON1 CTIM PWRON2 6 PGOOD 5VG 7 5VISEN 5VS
R1 0.1 1%
RF1K49157 Q1
FIGURE 15. HIP1012 EVALUATION CIRCUIT SCHEMATIC AND PHOTO FOR DISK DRIVE HOT PLUG
14
HIP1012A Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574
A1 B C D E e
C
A1 0.10(0.004)
e
B 0.25(0.010) M C AM BS
0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27
H h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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