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| SI6924EDQ Vishay Siliconix N-Channel 2.5-V (G-S) Battery Switch, ESD Protection PRODUCT SUMMARY VDS (V) 28 rDS(on) (W) 0.033 @ VGS = 4.5 V 0.038 @ VGS = 3.0 V 0.042 @ VGS = 2.5 V ID (A) "4.6 "4.3 "4.1 ESD Protected 2000 V FEATURES D D D D Low rDS(on) VGS Max Rating: 14 V Exceeds 2-kV ESD Protection Low Profile TSSOP-8 Package D rDS(on) Rating at 2.5-V VGS D 28-V VDS Rated D Symetrical Voltage Blocking (Off Voltage) DESCRIPTION The SI6924EDQ is a dual n-channel MOSFET with ESD protection and gate over-voltage protection circuitry incorporated into the MOSFET. The device is designed for use in Lithium Ion battery pack circuits. The common-drain contsruction takes advantage of the typical battery pack topology, allowing a further reduction of the device's on-resistance. The 2-stage input protection circuit is a unique design, consisting of two stages of back-to-back zener diodes separated by a resistor. The first stage diode is designed to absorb most of the ESD energy. The second stage diode is designed to protect the gate from any remaining ESD energy and over-voltages above the gates inherent safe operating range. The series resistor used to limit the current through the second stage diode during over voltage conditions has a maximum value which limits the input current to v 10 mA @ 14 V and the maximum toff to 12 ms. The SI6924EDQ has been optimized as a battery or load switch in Lithium Ion applications with the advantage of both a 2.5-V rDS(on) rating and a safe 14-V gate-to-source maximum rating. APPLICATION CIRCUITS D ESD and Overvoltage Protection ESD and Overvoltage Protection R** G S **R typical value is 1.8 kW by design. Battery Protection Circuit See Typical Characteristics, Gate-Current vs. Gate-Source Voltage, Page 3. *Thermal connection to drain pins is required to achieve specific performance. FIGURE 1. Typical Use In a Lithium Ion Battery Pack Document Number: 70814 S-59522--Rev. C, 30-Nov-98 FIGURE 2. Input ESD and Overvoltage Protection Circuit. www.vishay.com 1 SI6924EDQ Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION *D *D TSSOP-8 D S1 S1 G1 1 2 3 4 Top View S1 N-Channel N-Channel S2 D 8D 7 S2 6 S2 5 G2 1.8 kW G1 G2 1.8 kW SI6924EDQ *Thermal connection to drain pins is required to achieve specific performance. FIGURE 3. FIGURE 4. ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED) Parameter Drain-Source Voltage, Source-Drain Voltage Gate-Source Voltage Continuous Drain-to-Source Current (TJ = 150_C)a, b _ Pulsed Drain-to-Source Current Pulsed Source Current (Diode Conduction)a, b Maximum Power Dissipationa, b Operating Junction and Storage Temperature Range TA = 25_C TA = 70_C TA = 25_C TA = 70_C Symbol VDS VGS ID IDM IS PD TJ, Tstg Limit - to + "14 "4.6 "3.7 "20 1.25 1.1 0.72 -55 to 150 Unit V A W _C THERMAL RESISTANCE RATINGS Parameter t v 10 sec Maximum Junction-to-Ambienta Steady-State RthJA 115 Symbol Typical Maximum 125 Unit _C/W Notes a. Surface Mounted on FR4 Board. b. t v 10 sec. www.vishay.com Document Number: 70814 S-59522--Rev. C, 30-Nov-98 2 SI6924EDQ Vishay Siliconix SPECIFICATIONS (TJ = 25_C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 mA VDS = 0 V, VGS = "4.5 V Gate-Body Leakage IGSS VDS = 0 V, VGS = "14 V VDS = 22.4 V, VGS = 0 V Zero Gate Voltage Drain Current On-State Drain Currentb IDSS ID(on) VDS = 22.4 V, VGS = 0 V, TJ = 55_C VDS w 5 V, VGS = 5 V VGS = 4.5 V, ID = 4.6 A Drain-Source On-State Resistanceb rDS(on) VGS = 3.0 V, ID = 4.3 A VGS = 2.5 V, ID = 4.1 A Forward Transconductanceb Diode Forward Voltageb gfs VSD VDS = 10 V, ID = 4.6 A IS = 1.25 A, VGS = 0 V 10 0.026 0.029 0.031 18 0.7 1.1 0.033 0.038 0.042 S V W 0.5 "1 "10 1 5 V mA mA mA m A Symbol Test Condition Min Typ Max Unit Dynamica Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf VDD = 10 V, RL = 10 W ID ^ 1 A, VGEN = 4.5 V, RG = 6 W VDS = 10 V, VGS = 4.5 V, ID = 4.6 A 14 2.1 4.2 0.55 2.0 7.0 4.5 1.0 4.0 12 8 ms m 20 nC Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width v 300 ms, duty cycle v 2%. TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Gate-Current vs. Gate-Source Voltage 8 10,000 1,000 I GSS - Gate Current (mA) 6 I GSS - Gate Current (mA) 100 10 1 0.1 TJ = 25_C 0.01 0 0 4 8 12 16 0.001 0 2 4 6 8 10 12 14 Gate Current vs. Gate-Source Voltage 4 TJ = 150_C 2 VGS - Gate-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Document Number: 70814 S-59522--Rev. C, 30-Nov-98 www.vishay.com 3 SI6924EDQ Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Output Characteristics 20 VGS = 5 thru 2,5 V 16 I D - Drain Current (A) 2V I D - Drain Current (A) 16 20 Transfer Characteristics 12 12 8 8 TC = 125_C 4 25_C -55 _C 4 1.5 V 1V 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.0 0.5 1.0 1.5 2.0 2.5 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) On-Resistance vs. Drain Current 0.05 1200 Capacitance r DS(on) - On-Resistance ( W ) VGS = 2.5 V 0.03 C - Capacitance (pF) 0.04 900 Ciss 600 Coss 300 Crss VGS = 3 V 0.02 VGS = 4.5 V 0.01 0 4 8 12 16 20 0 0 4 8 12 16 20 24 28 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) Gate Charge 4.5 V GS - Gate-to-Source Voltage (V) VDS = 10 V ID = 4.6 A 1.8 On-Resistance vs. Junction Temperature VGS = 4.5 V ID = 4.6 A r DS(on) - On-Resistance (W) (Normalized) 8 12 16 3.6 1.6 1.4 2.7 1.2 1.8 1.0 0.9 0.8 0.0 0 4 0.6 -50 -25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (_C) www.vishay.com 4 Document Number: 70814 S-59522--Rev. C, 30-Nov-98 SI6924EDQ Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Source-Drain Diode Forward Voltage 20 0.08 On-Resistance vs. Gate-to-Source Voltage I S - Source Current (A) 10 TJ = 150_C r DS(on) - On-Resistance ( W ) 0.06 ID = 4.6 A 0.04 TJ = 25_C 0.02 1 0 0.4 0.6 0.8 1.0 1.2 0.00 0 1 2 3 4 5 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Threshold Voltage 0.2 ID = 250 mA 30 25 Single Pulse Power 0.1 V GS(th) Variance (V) -0.0 Power (W) 20 -0.1 15 -0.2 10 -0.3 5 0 -25 0 25 50 75 100 125 150 0.01 0.1 1 Time (sec) 10 30 TJ - Temperature (_C) -0.4 -50 Normalized Thermal Transient Impedance, Junction-to-Ambient 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 0.05 PDM t1 t2 1. Duty Cycle, D = t1 t2 0.02 Single Pulse 0.01 10- 4 10- 3 10- 2 10- 1 1 2. Per Unit Base = RthJA = 115_C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 10 100 600 Square Wave Pulse Duration (sec) Document Number: 70814 S-59522--Rev. C, 30-Nov-98 www.vishay.com 5 |
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