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A S 11 2 0 46-Segment LCD Driver
D a ta S he e t
1 General Description
The AS1120 is an LCD direct-driver capable of driving up to 46 LCD segments with one non-multiplexed backplane. The device contains an integrated serial-to-parallel interface and generates the necessary signals to drive LCD panels. Internal synchronous backplane signal regeneration allows the device to mix different drivers with different LCDs for superior brightness stability over a wide temperature range. The device also supports external backplane signals. The AS1120 was specifically designed to easily interface with a variety of microprocessors and a wide range of LCD panel types. The AS1120 is available in a 64-pin PQFP package.
2 Key Features
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46-Segment LCD Driver Serial-to-Parallel Interface Integrated Oscillator w/ External R/C and Backplane Input Supports Alphanumeric and Bar-Graph Devices Two Data Transfer Configurations: - Cascade - Parallel Non-Multiplexed Backplane Very-Low Current Consumption Power Supply Range: 3.0 to +5.5V Operating Temperature Range: -40 to +85C 64-pin PQFP Package
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3 Applications
The device is ideal for industrial LCD systems, portablesystem displays, panel meters with wide temperature ranges, high-performance optical displays, or for any other space-limited A/D application with low power-consumption and single-supply requirements.
Figure 1. Application Diagram
+VDD
43 VDD
AS1120
XOR 46-bit LCD[0:45]
6 TEST 9 LOAD 13 RESETN 10 DATAIN 8 CLKIN 11 BPLIN 15 OSC OSC Shift Register 46-bit 7 DATAOUT 12 BPLOUT 42 VSS 14 VSSOSC Register 46-bit
REXT
Divide by 16
CEXT
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AS1120 Data Sheet
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4 Absolute Maximum Ratings
Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Section 5 Electrical Characteristics on page 3 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 1. Absolute Maximum Ratings Symbol VDD Parameter Positive Supply Voltage to Ground Min -0.3 0 -200 -65 Max +7.0 VDD +200 +150 +150 760 1000 5 85 Unit V V mA C C mW V % The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C "Moisture/Reflow Sensitivity Classification for non-hermetic Solid State Surface Mount Devices" Package related HBM Mil-Std883E 3015.7 methods Norm: JEDEC 17 Comments
VIN, VOUT Digital Input and Output Voltage to Ground ISCR TJMAX TSTRG Pt ESD Input Current (Latchup Immunity) Maximum Junction Temperature Storage Temperature Package Power Dissipation (TJMAX - TAMB)/RTH Electrostatic Discharge Humidity (Non-Condensing)
Package Body Temperature
+250
C
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AS1120 Data Sheet
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5 Electrical Characteristics
Table 2. Electrical Characteristics Symbol VDD TAMB IDD fOSC CSEG CBP Parameter Positive Supply Voltage Ambient Temperature Supply Current Oscillator Frequency Segment Capacitance Backplane Capacitance 0.7 x VDD 0.2 x VDD 1 10 Verify that the LCD is compatible with the desired temperature range fBPL =50Hz, output not connected, TAMB = 25C Bpfreq = fOSC/16 Conditions Min +3.0 -40 5 0.5 100 300 50 Max +5.5 85 Unit V C A kHz pF nF
CMOS Input Pin: TEST (VDD = 5V, TAMB = -40 to +85 C unless otherwise noted). VIH VIL ILEAK tT High Level Input Voltage Low Level Input Voltage Input Leakage Current Input Transition Time V V A ns
CMOS Input with Schmitt Trigger, Pin: CLKIN, LOAD, DATAIN, BPLIN, RESETN (VDD = 5V, TAMB = -40 to +85 C unless otherwise noted). VTH+ VTLILEAK Positive-Going Threshold Negative-Going Threshold Input Leakage Current VDD = 5V, IOH = -4mA VDD = 3.3V, IOH = -2.8mA VDD = 5V, IOL = 4mA VDD = 3.3V, IOL = 3.2mA VDD = 5V, IOH = -25A VDD = 3.3V, IOH = -16A VDD = 5V, IOL = 22A VDD = 3.3V, IOL = 17A 4.0 2.5 0.4 0.4 4.0 2.5 0.4 0.4 VDD = 4.5V VDD = 5.5V VDD = 4.5V VDD = 5.5V 2.8 3.4 1.1 1.4 3.2 3.9 1.6 1.9 1 V V A
CMOS Output Pins: BPLOUT, DATAOUT (VDD = 5V, TAMB = -40 to +85 C unless otherwise noted). VOH VOL High Level Input Voltage Low Level Input Voltage V V
CMOS Output Pin: LCDxx (VDD = 5V, TAMB = -40 to +85 C unless otherwise noted). VOH VOL High Level Input Voltage Low Level Input Voltage V V
Oscillator Pin: OSC (VDD = 5V, TAMB = -40 to +85 C unless otherwise noted). VOL REXT CEXT fOSC Low Level Output Voltage (open collector) External Resistance External Capacitance Frequency 1/fOSC = 0.69 x REXT x CEXT VDD = 5V, IOL = 4mA 47 0.3 0.5 1 100 0.4 V k nF kHz
Table 3. Timing Characteristics Symbol tCHP tCLP Parameter Time CLKIN high pulse Time CLKIN low pulse Min 50 50 Max Unit ns ns
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AS1120 Data Sheet
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Table 3. Timing Characteristics Symbol tSDC tHDC tSLC tHLC tRLP tSRC tDOUT Parameter Time setup DATAIN to CLKIN rising edge Time hold DATAIN from CLKIN rising edge Time setup LOAD to CLKIN rising edge (active low) Time hold LOAD to CLKIN rising edge (active low) Time RESETN low pulse (active low) Time setup RESETN to CLKIN rising edge Time from CLKIN falling edge to DATAOUT
1, 2
Min 30 30 30 30 20000 30
Max
Unit ns ns ns ns ns ns
1, 2
10
ns
1. LOAD must be high while RESETN is active (low). 2. LOAD can stay low for more than one CLKIN cycle. Figure 2. Signal Waveform Timing
tCHP CLKIN
tCLP
tSDC DATAIN
tHDC
tSLC LOAD tSRC tRLP RESETN
tHLC
DATAOUT
tDOUT
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AS1120 Data Sheet
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Shift Register
6 Detailed Description
The AS1120 can drive up to 46 LCD segments and multiple AS1120 devices can be cascaded (see Figure 7 on page 8) to increase the number of LCD segments. Note: Due to the accurate delay balance between the backplane input, backplane output, and the LCD segments, it is possible to mix segments of different display crystal types.
Shift Register
Data accesses are made serially via pins DATAIN and CLKIN. At each CLKIN rising edge the signal present at DATAIN pin is shifted in the first bit of the internal shift register and the other bits are shifted ahead of the first bit. To cascade multiple AS1120 devices (see Figure 7 on page 8), the last bit of the internal shift register is presented at pin DATAOUT at the falling edge of the same CLKIN pulse. The LSB is entered first while MSB is the last bit to be shifted into the shift register. Note: The shift register is cleared at when the AS1120 is reset.
Latch Register and Error
When a signal is applied at pin LOAD, data present in the shift register is latched into the internal latch register and presented to the LCD output segments (LCD[0:45]), also passing through an XOR gate with the backplane signal (BPLIN). The XOR function is necessary to generate the appropriate signals to drive the LCD segments. Note: At reset the latch register is cleared, thus no LCD segment will be active at power-on.
Synchronous Mode
Data is shifted into the internal shift register at the rising edge of the CLKIN signal. To load the shift register all 46 data bits are clocked into the register at the rising edge of CLKIN (see Figure 3). The LOAD signal has to be set high for 8 CLKIN periods before the end of the 46 bits. The display will be updated at the 8th CLKIN rising edge after LOAD goes high as is shown in Figure 3. Note: During synchronous mode, a clock on BPLIN must be applied to avoid the risk of damaging the LCD crystal. Figure 3. Synchronous Mode Timing Diagram
46 CLKIN Cycles 8 CLKIN Cycles LOAD
DATAIN
X
X
LD45 LD44LD43
LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0
CLKIN
Stop
BPLIN
Display
Update
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AS1120 Data Sheet
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Asynchronous Mode
Asynchronous Mode
Data can be preloaded into the AS1120 shift register and then activated via a LOAD pulse. To preload the shift register the LOAD signal must stay high as all 46 data bits are clocked into the internal shift register at the rising edge of CLKIN (see Figure 4). Note: In asynchronous mode, a clock signal must be applied on pin BPLIN. Asynchronous mode does not support the use of the AS1120 internal clock. Figure 4. Timing Diagram for Preloading the Shift Register
46 CLKIN Cycles
LOAD Always High LOAD
DATAIN
X
X
LD45 LD45LD45
LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 Stop
CLKIN
BPLIN
To update the LCD display the LOAD signal must be held low for at least 8 periods of the clock applied at BPLIN, and CLKIN must be set to low. Note that since BPLIN is normally asynchronous in respect to LOAD, it is advisable to keep LOAD low for 8+1 BPLIN cycles. The display will be updated at the 8th BPLIN rising edge while LOAD is Low. In case of internal BPLIN generation through the internal oscillator BPLIN = fOSC/16. Figure 5. Timing Diagram for Updating the Display in Asynchronous Mode
9 BPLIN Cycles LOAD
DATAIN
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CLKIN
CLKIN Always High
BPLIN
Display
Update
R/C Oscillator and Backplane Generation
The AS1120 can generate the backplane signal using an internal R/C oscillator, or an externally generated backplane signal can be supplied. When cascading multiple AS1120 devices (see Figure 7 on page 8), only the first device should have the oscillator running; the other devices must use pin BPLIN to regenerate the backplane signal and to synchronize their LCD output segments with the common backplane.
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AS1120 Data Sheet
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R/C Oscillator and Backplane Generation
The selection of internal or external backplane signal (see Table 4) is initiated after RESETN is disabled - the first rising edge at pin OSC after RESETN is disabled will force pin BPLOUT to deliver the internally generated backplane signal. If there is no rising edge at pin OSC, BPLOUT will simply buffer the signal at pin BPLIN. Table 4. Backplane Source Generation Selection Mode Internal External OSC Pin Running Tied Low BPLOUT fOSC/16 BPLIN
Note: The LCD should never be supplied with static signals. Verify that signals at pins BPLIN and BPLOUT are always running while VDD is supplied; note that pin BPLOUT is stopped during a reset.
Internal Mode - R/C Oscillator Running (Generating the Backplane)
Connect external R/C components to pin OSC as shown in Figure 1 on page 1. When an external REXT and CEXT are connected to pin OSC, a clock signal whose frequency is equal to fOSC divided by 16 will be present at pin BPLOUT. Note: Internal mode requires that pin BPLIN be connected to pin BPLOUT. The oscillation period is approximately tOSC = 1/fOSC = 0.69 x REXT x CEXT, and the error between the expected frequency and the generated frequency increases as indicated in Table 5. Table 5. Oscillator Error Rate Expected Oscillator Frequency 1 kHz 10 kHz 50 kHz 100 kHz Figure 6. AS1120 Clock Circuit
11 BPLIN 43 VDD D Q SEL A 15 OSC Oscillator CLRN fOSC/16 CLRN
Error 1% 5% 20% 40%
12 BPLOUT
B
13 RESETN
AS1120
External Mode: R/C Oscillator Stopped (External Backplane)
Connect pin OSC to VSS in order to block the internal oscillator. In this external mode, an external backplane signal should be presented at pin BPLIN, which will be regenerated and presented at pin BPLOUT.
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AS1120 Data Sheet
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7 Application Information
The AS1120 can support all types of static LCD displays. Note: For proper display operation, ensure that the LCD can safely operate within the full temperature range of the AS1120 (see page 1). Figure 7. Cascaded Configuration
LCD Segments
LCD Segments
LCD Segments
LOAD LCD[0:45] +VDD 43 LCD[0:45] +VDD XOR 46-Bit 6 TEST 9 LOAD 13 RESETN 10 DATAIN 8 CLKIN +VDD 11 BPLIN Divide by 16 Register 46-Bit 6 TEST 9 LOAD 13 RESETN 10 DATAIN 8 CLKIN 11 BPLIN Divide by 16 Register 46-Bit 43 LCD[0:45] +VDD XOR 46-Bit 6 TEST 9 LOAD 13 RESETN 10 DATAIN 8 CLKIN 11 BPLIN Divide by 16 Register 46-Bit 43
AS1120
AS1120
AS1120
XOR 46-Bit
VDD
VDD
VDD
Shift Register 46-Bit
7 DATAOUT
Shift Register 46-Bit
7 DATAOUT
Shift Register 46-Bit
7 DATAOUT
12 BPLOUT OSC
12 BPLOUT
12 BPLOUT OSC
15 OSC
15 OSC
OSC
15 OSC
14 VSSOSC
42 VSS
14 VSSOSC
42 VSS
14 VSSOSC
42 VSS
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AS1120 Data Sheet
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Pin Assignments and Markings
8 Pinout and Packaging
Pin Assignments and Markings
Figure 8. Pin Assignments (Top View) and Markings
LCD41 LCD40 LCD39 LCD38 LCD37 LCD36 LCD35 LCD34 LCD33 LCD32 LCD31 LCD30 LCD29 LCD28 LCD27 N/C N/C LCD42 LCD43 LCD44 LCD45 TEST DATAOUT CLKIN LOAD DATAIN BPLIN BPLOUT RESETN VSSOSC OSC N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AS1120
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
N/C LCD26 LCD25 LCD24 LCD23 VDD VSS LCD22 LCD21 LCD20 LCD19 LCD18 LCD17 LCD16 LCD15 N/C
Pin Descriptions
Table 6. Pin Descriptions Pin Number 1, 16, 32, 33, 48, 49 2:5 6 7 8 9 10 11 12 13 14 15 17:31 34:41 42 43 44:47 50:64 Pin Name N/C LCD42:LCD45 TEST DATAOUT CLKIN LOAD DATAIN BPLIN BPLOUT RESETN VSSOSC OSC LCD0:LCD14 LCD15:LCD22 VSS VDD LCD23:LCD26 LCD27:LCD41 Description Not Connected LCD Output Segments 42:45 Test pin. This pin must be tied to pin VDD. Serial Data Output Shift Register Clock Load Strobe from Shift Register to Latch Serial Data Input Backplane Input Backplane Output Active-Low Asynchronous Reset Internal Oscillator Power Ground Oscillator Pad. a). Internal clock (see page 7) b) External clock; tied to VSSOSC LCD Output Segments 0:14 LCD Output Segments 15:22 Power Ground Positive Power Supply LCD Output Segments 23:26 LCD Output Segments 27:41
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LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14 N/C
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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AS1120 Data Sheet
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Package Drawings and Markings
Package Drawings and Markings
The devices are available in an 64-pin PQFP package. Figure 9. 64-pin PQFP Package
B
0.60
Variation (mm) Min Max
0.30 0.45
ddd
0.20
Notes: 1. Controlling dimension is millimeters. 2. Pin 1 indicator may be chamfer, dot, or both. 3. Center line reference is defined by the mid-point of the center lead or the center space between leads at the package.
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AS1120 Data Sheet
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9 Ordering Information
The device is available as the standard product shown in Table 7. Table 7. Ordering Information Type AS1120 Description 46-Segment LCD Driver Delivery Form Tape and Reel Package PQFP44
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AS1120 Data Sheet
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Copyrights
Copyright (c) 1997-2005, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 e-mail: info@austriamicrosystems.com For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com
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