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December 1998 PRELIMINARY
ML6695 100BASE-X Fiber Physical Layer With 5-bit Interface
GENERAL DESCRIPTION
The ML6695 implements the physical layer of the Fast Ethernet 100BASE-X standard for fiber media. The device provides the 5-bit (or symbol) interface for interface to upper-layer silicon. The ML6695 integrates the data quantizer and the LED driver, allowing the use of low cost optical PMD components. The ML6695 includes 125MHz clock recovery/clock generation, an LED driver, and a data quantizer (post amplifier). The device also offers a power down mode which results in total power consumption of less than 20mA. The ML6695 is suitable for the current 100BASE-FX IEEE 803.2u standard defined using 1300nm optics, as well as for the proposed 100BASE-SX standard defined using lower cost 820nm optics.
FEATURES
s s s s s s
100BASE-FX physical layer with 5-bit interface Optimal 100BASE-SX solution (draft standard) Integrated data quantizer (post-amplifier) Integrated LED driver 125MHz clock generation and recovery Power-down mode
BLOCK DIAGRAM
LPBK TXC CLOCK SYNTHESIZER PWRDN
IOUT TSM4 TSM3 TSM2 TSM1 TSM0 SERIALIZER NRZ TO NRZI ENCODER LED DRIVER IOUT RTSET
SDO
SIGNAL DETECT
RXC RSM4 RSM3 RSM2 RSM1 RSM0 DESERIALIZER CLOCK & DATA RECOVERY NRZI TO NRZ DECODER DATA QUANTIZER (POST AMPLIFIER) VIN-
VIN+
CAPB
CAPDC
1
ML6695
PIN CONFIGURATION
ML6695 44-Pin PLCC (Q44)
TSM0 TSM1 TSM2 TSM3 TSM4 AGND1 TXC AVCC1 LPBK AVCC2 AGND2
6 5 4 3 2 1 44 43 42 41 40 PWRDN RSM4 RSM3 DGND1 RSM2 DVCC1 RSM1 DGND2 RSM0 RXC DGND3 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 IOUT IOUT AGND3 RTSET AVCC3A AVCC3B AVCC4A AGND4A AVCC4B VIN+ VIN-
PIN DESCRIPTION
PIN NAME FUNCTION PIN NAME FUNCTION
1 2
A GND 1 TSM4
Analog ground Transmit data TTL inputs. TSM 0-4 inputs accept TX data symbols from the MII. Data appearing at TSM 0-4 are clocked into the ML6695 on the rising edge of TXCLK . Transmit data TTL inputs. TSM 0-4 inputs accept TX data symbols from the MII. Data appearing at TSM 0-4 are clocked into the ML6695 on the rising edge of TXC. Transmit data TTL inputs. TSM 0-4 inputs accept TX data symbols from the MII. Data appearing at TSM 0-4 are clocked into the ML6695 on the rising edge of TXC.
SDO DVCC2 DGND4C DGND4B DGND4A DVCC5 DGND5B DGND5A CAPDC CAPB AGND4B
TOP VIEW
5
TSM1
Transmit data TTL inputs. TSM 0-4 inputs accept TX data symbols from the MII. Data appearing at TSM 0-4 are clocked into the ML6695 on the rising edge of TXC. Transmit data TTL inputs. TSM 0-4 inputs accept TX data symbols from the MII. Data appearing at TSM 0-4 are clocked into the ML6695 on the rising edge of TXC. Powerdown TTL input. Driving this pin low, or floating the pin, powers the ML6695 down to a lowcurrent, inoperative state. Driving PWRDN high enables the ML6695. Receive data TTL outputs. RSM 04 output may be sampled synchronously with RXC's rising edge.
6
TSM0
3
TSM3
7
PWRDN
4
TSM2
8
RSM4
2
ML6695
PIN DESCRIPTION
PIN NAME
(Continued)
PIN NAME FUNCTION
FUNCTION
9
RSM3
Receive data TTL outputs. RSM 04 output may be sampled synchronously with RXC's rising edge. Digital ground Receive data TTL outputs. RSM 04 output may be sampled synchronously with RXC's rising edge. Digital positive power supply Receive data TTL outputs. RSM 04 output may be sampled synchronously with RXC's rising edge. Digital ground Receive data TTL outputs. RSM 04 output may be sampled synchronously with RXC's rising edge. Recovered receive symbol clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz bit clock recovered from the signal received at VIN+/-. Receive data are clocked out at RSM 0-4 on the falling edges of this clock. Digital ground Signal Detect TTL output. This output goes high when the signal at VIN+/- exceeds the preset amplitude threshold. Digital positive power supply Digital ground Digital ground
26
CAPDC
10 11
DGND1 RSM2
Data quantizer offset-correction loop, offset-storage capacitor input pin. The capacitor tied between this pin and AVCC stores the amplified data quantizer offset voltage and also sets the dominant pole in the offset-correction loop. A 0.1F surface mount is recommended. Data quantizer input bias bypass capacitor input. The capacitor tied between this pin and AVCC filters the quantizer's internal input bias reference. A 0.1F surface-mount capacitor is recommended. Analog ground Receive quantizer input. This differential input pair receives 100BASE-FX NRZI signals from the network opto-coupler. Receive quantizer input. This differential input pair receives 100BASE-FX NRZI signals from the network opto-coupler. Analog positive power supply Analog ground Analog positive power supply Analog positive power supply Analog positive power supply Transmit level bias resistor. For 100BASE-FX, an external 2.32kW, 1% resistor connected between RTSET and AGND3 sets a precision constant bias current that gives a nominal output "on" current of 75mA at IOUT. Analog ground Transmit LED output. This pin connects through an external 15W resistor to AVCC when the part is used to drive a network LED.
27
CAPB
12 13
DVCC1 RSM1
28 29
AGND4B VIN -
14 15
DGND2 RSM0
30
VIN+
16
RXC
31 32 33 34 35 36
AVCC4B AGND4A AVCC4A AVCC3B AVCC3A RTSET
17 18
DGND3 SDO
19 20 21 22 23 24 25
DVCC2 DGND4C DGND4B DGND4 DVCC5 DGND5B DGND5A
37 Digital ground 38 Digital positive power supply Digital ground Digital ground
AGND3 IOUT
3
ML6695
PIN DESCRIPTION
PIN NAME
(Continued)
PIN NAME FUNCTION
FUNCTION
39
IOUT
Transmit LED output. This opencollector current output drives NRZI waveforms into an LED. Output current can be set externally by choosing RTSET value. Analog ground Analog positive power supply Loopback TTL input pin. Tying this pin to ground places the part in loopback mode; data at TSM0 0-4 are serialized, then sent to the quantizer, followed by the receive PLL for clock recovery, and finally to the RSM<4:07> outputs. Floating this pin or tying it to VCC places the part in its normal mode of operation.
43 44
AVCC1 TXC
Analog positive power supply Transmit clock TTL input. This 25MHz clock is phase-aligned with the internal 125MHz TX bit clock. Data appearing at Tsm<4:0> are clocked into the ML6695 on the rising edge of this clock.
40 41 42
AGND2 AVCC2 LPBK
4
ML6695
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Supply Voltage Range ............................ -0.3V to 6V Input Voltage Range Digital Inputs ........................................... -0.3V to VCC VIN+, VIN-,TXC, CAPDC, CAPB ............... -0.3V to VCC Output Current IOUT, IOUT ........................................................ 90mA All Other Outputs ............................................... 10mA Junction Temperature .................................... 0C to 125C Storage Temperature ................................. -65C to 150C Lead Temperature (Soldering, 10 sec) ..................... 260C Thermal Resistance (qJA) PLCC ............................................................... 53C/W
OPERATING CONDITIONS
Temperature Range ....................................... 0C to 70C VCC Supply Voltage .............................. ........... 5V 5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other.
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 5V 5%, TA = Operating Temperature Range (Note 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TTL INPUTS (TSM<4:0>, LPBK, TXC, PWRDN) VIL V IH IIL IIH Input Low Voltage Input High Voltage Input Low Current Input High Current IIL = -400A IIH = 100A VIN = 0.4V VIN = 2.4V -0.3 2.0 -200 100 0.8 VCC+0.3 V V A A
TTL OUTPUTS (RSM<4:0>, RXC, SDO) VOL VOH RECEIVER V ICM V ID RIDR V SDA VIN+/- input common-mode voltage VIN+/- differential input voltage range VIN+/- differential input resistance Signal detect assertion threshold peak-to-peak non-idle signal level at VIN+/- for SDO assertion VCC = 5V 3.5 500 8 2.5 1700 1k 12 V mVP-P W mVP-P Output Low Voltage Output High Voltage IOL = 4mA IOH = -4mA 2.4 0.4 V
AHYST IRT
Input hysteresis RTSET input current RTSET = 2.32kW 1%
1.5 486 540
2 594
dB A
TRANSMITTER ILEDH ILEDL IOUT high output current (Note 2) IOUT/IOUT low output current RTSET = 2.32kW 1% RTSET = 2.32kW 1% 67.5 75 82.5 0.1 mA mA
POWER SUPPLY CURRENT ICC IPD Supply Current, 100BASE-FX operation, transmitting Supply Current, Powerdown Mode Current into all VCC pins, VCC = 5.25V 200 295 20 mA mA
5
ML6695
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 5V 5%, TA = Operating Temperature Range (Note 1)
SYMBOL TRANSMITTER (NOTE 8) tTR/F t TDC IOUT rise/fall time IOUT output duty cycle distortion Note 3 Note 3 -0.5 2 0.5 ns ns PARAMETER CONDITIONS MIN TYP MAX UNITS
SIGNAL DETECT tAS tANS SDO assert time (SDO low to high) SDO deassert time (SDO high to low) VIN>8mVP-P VIN<8mVP-P 350 100 s s
DATA INTERFACE XNTOL t TPWH t TPWL tRPWH tRPWL tTPS t TPH tRCS tRCH tRPCR tRPCF TX input clock frequency tolerance TXC pulse width HIGH TXC pulse width LOW RXC pulse width HIGH RXC pulse width LOW Setup time, TSM 0-4 data valid to TXC rising edge (1.4V point) Hold time, TSM 0-4 data valid after TXC rising edge (1.4V point) Time that RSM0-4 data are valid before RXC falling edge (1.4V point) Time that RSM0-4 data are valid after RXC falling edge (1.4V point) RXC 10%-90% rise time RXC 90%-10% fall time 25MHz frequency -50 14 14 14 14 13 3 10 10 6 6 50 ns ns ns ns ns ns ns ns ns ns ppm
Note 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Note 2. Output current amplitude is IOUT = 207V/RTSET. Note 3. Using the test load shown in Figure 1, transmitting "H" symbols.
6
ML6695
FUNCTIONAL DESCRIPTION
TRANSMIT SECTION The ML6695 transmit section accepts parallel NRZ data nibbles, creates a serial NRZI data stream using the internal 125MHz clock multiplier, and provides an opencollector output IOUT to directly drive an LED. IOUT must be connected to VCC through a 15W resistor. The internal clock multiplier accepts an external 25MHz clock input. The LED driver at IOUT is a current mode switch which develops the output light by sinking current through the network LED into IOUT. RTSET'S value determines the output current: DC offset correction. The quantizer output drives a data comparator with a controlled slicing threshold. The comparator provides a large-amplitude receive signal. The clock recovery circuit extracts 125MHz receive clock from the large-amplitude signal, and provides the clock for the parallel data output registers. Received NRZ data nibbles appear at the RSM outputs synchronously with RXC falling edges. Received signals exceeding the preset signal detect amplitude threshold for more than 5s cause the SDO output to go high. Received signals that fall below the preset threshold for more than 5s cause SDO to go low. OTHER MODES The ML6695 will enter a power down mode when the PWRDN pin is tied low. In this state the ML6695 powers down to a low-current (less than 20mA), inoperative state. Driving it high enables normal operation of the ML6695. Loopback mode is entered when the LPBK is tied to ground. In this mode, the data at TSM0-4 are serialized, then sent to the quantizer, followed by the receive PLL for clock recovery, and finally to the RSM0-4 outputs. Tying LPBK to VCC places the ML6695 in its normal mode of operation.
RTSET =
. 125V 140W IOUT
(1)
where IOUT is the desired output current. RECEIVE SECTION The ML6695 receive section includes a fiber optic quantizer and a 125MHz receive clock recovery circuit. The quantizer is a wide-bandwidth limiting amplifier with
15 38 IOUT
15 39 IOUT
ML6695
Figure 1. Test Load
7
ML6695
PHYSICAL DIMENSIONS
inches (millimeters)
Package: Q44 44-Pin PLCC
0.685 - 0.695 (17.40 - 17.65) 0.650 - 0.656 (16.51 - 16.66) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22) 12
PIN 1 ID 0.650 - 0.656 0.685 - 0.695 (16.51 - 16.66) (17.40 - 17.65) 0.500 BSC (12.70 BSC) 0.590 - 0.630 (14.99 - 16.00)
34
23 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.100 - 0.112 (2.54 - 2.84)
0.013 - 0.021 (0.33 - 0.53)
SEATING PLANE
ORDERING INFORMATION
PART NUMBER ML6695CQ TEMPERATURE RANGE 0C to 70C PACKAGE 44-Pin PLCC (Q44)
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. The circuits contained in this document are offered as possible applications only. Particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications. (c) Micro Linear 2000. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com
8
DS6695-01

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