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DATA SHEET PD78062(A), 78063(A), 78064(A) 8-BIT SINGLE-CHIP MICROCONTROLLER MOS INTEGRATED CIRCUIT DESCRIPTION The PD78062(A), 78063(A), and 78064(A) are products to which a quality assurance program more stringent than that used for the PD78062, 78063, and 78064 (standard models) is applied (NEC classifies these products as "special" quality grade models). PD78062(A), 78063(A), and 78064(A) are products in the PD78064 subseries within the 78K/0 series, which incorporate LCD controller/driver, 8-bit resolution A/D converter, timer, serial interface, interrupt functions and many other peripheral hardwares. Various development tools are also provided. For the details of functional description, refer to the following user's manual.Be sure to read this manual before designing your system. PD78064 78064Y Subseries User's Manual : U10105E 78K/0 Series User's Manual (Instruction : IEU-1372 FEATURES * Large on-chip ROM & RAM Item Product Name PD78062(A) Program Memory (ROM) 16K bytes 24K bytes 32K bytes Data Memory Internal High-Speed RAM LCD Display RAM 512 bytes 1024 bytes 40 x 4 bits Package 100-pin plastic QFP (fine pitch) (14 x 14mm, 0.5 mm pitch) 100-pin plastic QFP (14 x 20 mm, 0.65 mm pitch) 100-pin plastic LQFPNote (fine pitch) (14 x 14 mm, 0.5 mm pitch) PD78063(A) PD78064(A) Note Under planning * Minimum instruction execution time can be varied from high speed (0.4 s) to ultra-low speed (122 s) * I/O ports: 57 (including segment signal output dual-function pins) * LCD controller/driver Supply voltage VDD = 2.0 to 6.0 V (Static display mode) VDD = 2.5 to 6.0 V (1/3 bias) VDD = 2.7 to 6.0 V (1/2 bias) * 8-bit resolution A /D converter : 8 channels * Serial interface : 2 channels * Timer: 5 channels * Supply voltage : VDD = 2.0 to 6.0 V The information in this document is subject to change without notice. Document No. U10335EJ2V0DS00 (2nd edition) Date Published August 1997 N Printed in Japan The mark shows major revised points. (c) 1997 PD78062(A), 78063(A), 78064(A) APPLICATIONS Control units of automobile electronic systems, gas detectors and circuit breakers, various safety systems, hemadynamometers, etc. ORDERING INFORMATION Part Number Package 100-pin plastic QFP (fine pitch) (14 x 14 mm, resin thickness: 1.45 mm) 100-pin plastic LQFP (fine pitch) (14 x 14 mm, resin thickness: 1.40 mm) 100-pin plastic QFP (14 x 20mm) 100-pin plastic QFP (fine pitch) (14 x 14 mm, resin thickness: 1.45 mm) 100-pin plastic LQFP (fine pitch) (14 x 14 mm, resin thickness: 1.40 mm) 100-pin plastic QFP (14 x 20mm) 100-pin plastic QFP (fine pitch) (14 x 14 mm, resin thickness: 1.45 mm) 100-pin plastic LQFP (fine pitch) (14 x 14 mm, resin thickness: 1.40 mm) 100-pin plastic QFP (14 x 20mm) PD78062GC(A)-xxx-7EA PD78062GC(A)-xxx-8EUNote PD78062GF(A)-xxx-3BA PD78063GC(A)-xxx-7EA PD78063GC(A)-xxx-8EUNote PD78063GF(A)-xxx-3BA PD78064GC(A)-xxx-7EA PD78064GC(A)-xxx-8EUNote PD78064GF(A)-xxx-3BA Note Under planning Caution The PD78062GC(A), 78063GC(A), and 78064GC(A) are available in two types of packages (refer to 12. PACKAGE DRAWINGS). For the available packages, consult NEC. Remark xxx indicates a ROM code suffix. QUALITY GRADE Special Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. DIFFERENCES BETWEEN PD78062(A), 78063(A) and 78064(A), and PD78062, 78063 and 78064 Product name Item Quality grade PD78062(A), 78063(A), 78064(A) Special Standard PD78062, 78063, 78064 2 PD78062(A), 78063(A), 78064(A) 78K/0 SERIES DEVELOPMENT The following shows the 78 K/0 Series products development. Subseries names are shown inside frames. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083 Inverter control PD78075BY PD78078Y PD78070AY PD780018AY PD780058YNote PD78058FY PD78054Y PD780034Y PD780024Y PD78018FY PD78014Y PD78002Y EMI noise reduction version of the PD78078. A timer was added to the PD78054, and the external interface function was enhanced. ROM-less versions of the PD78078. Serial I/O of the PD78078Y was enhanced, and only selected functions are provided. Serial I/O of the PD78054 was enhanced, EMI noise reduction version. EMI noise reduction version of the PD78054. UART and D/A converter were added to the PD78014, and I/O was enhanced. An A/D converter of the PD780024 was enhanced. Serial I/O of the PD78018F was enhanced, EMI noise reduction version. EMI noise reduction version of PD78018F. Low-voltage (1.8 V) operation versions of the PD78014 with several ROM and RAM capacities available. An A/D converter and 16-bit timer were added to the PD78002. An A/D converter was added to the PD78002. Basic subseries for control. On-chip UART, capable of operating at a low voltage (1.8 V). 64-pin 64-pin PD780964 PD780924 FIPTM drive An A/D converter of the PD780924 was enhanced. On-chip inverter control circuit and UART, EMI noise reduction version. 100-pin 100-pin 78K/0 Series 80-pin 80-pin PD780208 PD780228 PD78044H PD78044F LCD drive The I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53 The I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48 N-ch open drain input/output was added to the PD78044F, Display output total: 34 Basic subseries for driving FIP, Display output total: 34 100-pin 100-pin 100-pin PD780308 PD78064B PD78064 PD780308Y PD78064Y SIO of the PD78064 was enhanced, and ROM and RAM were expanded. EMI noise reduced version of the PD78064. Basic subseries for driving LCDs, On-chip UART. IEBusTM supported 80-pin 80-pin PD78098B PD78098 Meter control EMI noise reduction version of the PD78098. An IEBus controller was added to the PD78054. 80-pin PD780973 LV On-chip automobile meter driving controller/driver. 64-pin PD78P0914 On-chip PWM output, LV digital code decoder, and Hsync counter. Note Under planning 3 PD78062(A), 78063(A), 78064(A) The following table shows the differences among subseries functions. Function Subseries Name Control Timer ROM Capacity 8-bit 10-bit 8-bit D/A 8-bit 16-bit Watch WDT A/D A/D 1ch 1ch 8ch - Serial Interface I/O 88 VDD MIN. External Value Expansion 1.8 V Available PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083 32 K to 40 K 4ch 1ch 48 K to 60 K - 24 K to 60 K 2ch 48 K to 60 K 16 K to 60 K 8 K to 32 K 2ch 3ch (UART: 1ch) 61 2ch 3ch (time division UART: 1ch) 3ch (UART: 1ch) 68 69 2.7 V 1.8 V 2.7 V 2.0 V - 8ch 8ch - - 3ch (UART: 1ch, time division 3-wire: 1ch) 2ch 51 1.8 V 53 8 K to 60 K 8 K to 32 K 8K 8 K to 16 K - - 1ch - 8 K to 32 K 3ch Note - 1ch - 8ch - 8ch 32 K to 60 K 2ch 1ch 48 K to 60 K 3ch - 1ch 1ch 8ch - 1ch 2ch 1ch 1ch 8ch - - 3ch (time division UART: 1ch) 2ch (UART: 1ch) 57 2.0 V - 8ch - - - 2ch 1ch 74 72 68 2.7 V 4.5 V 2.7 V - - 1ch (UART: 1ch) 2ch (UART: 2ch) 1ch 39 53 33 47 1.8 V 2.7 V 2.7 V - Available - Available Inverter control FIP drive PD780964 PD780924 PD780208 PD780228 PD78044H PD78044F 32 K to 48 K 2ch 1ch 16 K to 40 K 48 K to 60 K 2ch 1ch 32 K 16 K to 32 K 40 K to 60 K 2ch 1ch 32 K to 60 K 24 K to 32 K 3ch 1ch 6ch - LCD drive PD780308 PD78064B PD78064 IEBus PD78098B supported PD78098 Meter control PD780973 1ch 1ch 8ch - 2ch 3ch (UART: 1ch) 69 2.7 V Available 1ch 1ch 5ch - 1ch 8ch - - - - 2ch (UART: 1ch) 2ch 56 54 4.5 V 4.5 V - Available LV PD78P0914 32 K Note 10-bit timer: 1 channel 4 PD78062(A), 78063(A), 78064(A) FUNCTIONAL OUTLINE Product Name Item ROM High-speed RAM LCD display RAM General registers Minimum instruction execution time Internal memory When main system clock selected When subsystem clock selected PD78062(A) 16K bytes 512 bytes PD78063(A) 24K bytes 1024 bytes PD78064(A) 32K bytes 40 x 4 bits 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip minimum instruction execution time cycle modification function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz operation) 122 s (at 32.768 kHz operation) * * * * 16-bit operation Multiplication/division (8 bits x 8 bits,16 bits / 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD correction, etc. Total : 57 * CMOS input : 02 * CMOS I/O : 55 8-bit resolution x 8 channels Segment signal output : Maximum 40 Common signal output : Maximum 4 Bias : 1/2 or 1/3 switchable 3-wire serial I/O/SBI/2-wire serial I/O mode selectable 3-wire serial I/O/UART mode selectable 16-bit timer/event counter : 1 channel 8-bit timer/event counter : 2 channels Watch timer : 1 channel Watchdog timer : 1 channel Instruction set I/O ports (including segment signal output pins) A/D converter LCD controller/driver * * * * * * * * * * Serial interface : 1 channel : 1 channel Timer Timer output 3 (14-bit PWM output capability : 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (at main system clock 5.0 MHz operation) 32.768 kHz (at subsystem clock 32.768 kHz operation) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 5.0 MHz operation) Maskable Non-maskable Softwar Internal : 12, external : Internal : 1 1 Internal: 1, external: 1 6 Clock output Buzzer output Vectored interrupt sources Test input Supply voltage Package VDD = 2.0 to 6.0 V * 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness: 1.45 mm) * 100-pin plastic QFP (14 x 20 mm) * 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness: 1.40 mm, under planning) 5 PD78062(A), 78063(A), 78064(A) CONTENTS 1. 2. 3. PIN CONFIGURATION (TOP VIEW) ........................................................................................................ 7 BLOCK DIAGRAM ................................................................................................................................... 10 PIN FUNCTIONS ...................................................................................................................................... 11 3.1 3.2 3.3 Port Pins .......................................................................................................................................................... Other Pins ........................................................................................................................................................ Pin I/O Circuits and Recommended Connection of Unused Pins ............................................................. 11 13 14 4. 5. MEMORY SPACE ..................................................................................................................................... 18 PERIPHERAL HARDWARE FUNCTION FEATURE ............................................................................... 19 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Port ................................................................................................................................................................... Clock Generator .............................................................................................................................................. Timer/Event Counter ....................................................................................................................................... Clock Output Control Circuit ......................................................................................................................... Buzzer Output Control Circuit ....................................................................................................................... A/D Converter .................................................................................................................................................. Serial Interface ............................................................................................................................................... LCD Controller/Driver ..................................................................................................................................... 19 20 20 23 23 24 24 26 6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS ............................................................................... 27 6.1 6.2 Interrupt Functions ......................................................................................................................................... Test Functions ................................................................................................................................................. 27 31 7. 8. 9. STANDBY FUNCTION ............................................................................................................................. 32 RESET FUNCTION .................................................................................................................................. 32 INSTRUCTION SET ................................................................................................................................. 33 10. ELECTRICAL SPECIFICATIONS ............................................................................................................ 35 11. CHARACTERISTIC CURVES (REFERENCE VALUES) ......................................................................... 56 12. PACKAGE DRAWINGS ........................................................................................................................... 58 13. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 61 APPENDIX A. DEVELOPMENT TOOLS ....................................................................................................... 62 APPENDIX B. RELATED DOCUMENTS ....................................................................................................... 64 6 PD78062(A), 78063(A), 78064(A) 1. PIN CONFIGURATION (TOP VIEW) * 100-pin plastic QFP (fine pitch)(14 x 14 mm, resin thickness: 1.45 mm) PD78062GC(A)-xxx-7EA, 78063GC(A)-xxx-7EA, 78064GC(A)-xxx-7EA * 100-pin plastic LQFP (fine pitch)(14 x 14 mm, resin thickness: 1.40 mm) PD78062GC(A)-xxx-8EUNote, 78063GC(A)-xxx-8EUNote, 78064GC(A)-xxx-8EUNote P72/SCK2/ASCK P113 P112 P111 P110 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVDD AVREF P100 P101 VSS P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 COM0 COM1 COM2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 74 2 73 3 72 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 P71/SO2/TXD P10/ANI0 XT1/P07 VDD AVSS P117 P116 P115 P114 XT2 X1 X2 IC P70/SI2/RXD P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 S20 S19 54 22 53 23 52 24 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 COM3 BIAS VLC0 Note Under planning Cautions 1. Connect directly the IC (Internally Connected) pin to VSS. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. VLC1 VLC2 VSS S18 7 PD78062(A), 78063(A), 78064(A) * 100-pin plastic QFP (14 x 20 mm) PD78062GF(A)-xxx-3BA, 78063GF(A)-xxx-3BA PD78064G(A)-xxx-3BA P25/SI0/SB0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 P26/SO0/SB1 P27/SCK0 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK IC X2 X1 VDD XT1/P07 XT2 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P110 P111 P112 P113 P114 P115 P116 P117 AVSS P10/ANI0 P11/ANI1 P12/ANI2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 79 2 78 3 77 4 S22 S21 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 P4 S3 S2 S1 S0 VSS VLC2 VLC1 VLC0 BIAS COM3 COM2 COM1 COM0 53 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVDD VSS P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ AVREF P100 P101 Cautions 1. Connect directly the IC (Internally Connected) pin to VSS. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. 8 P37 PD78062(A), 78063(A), 78064(A) ANI0-ANI7 ASCK AVDD AVREF AVss BIAS : Analog Input : Asynchronous Serial Clock : Analog Power Supply : Analog Reference Voltage : Analog Ground : LCD Power Supply Bias Control P110-P117 PCL RESET RXD S0-S39 SB0-SB1 SI0, SI2 SO0, SO2 : Port11 : Programmable Clock : Reset : Receive Data : Segment Output : Serial Bus : Serial Input : Serial Output BUZ : Buzzer Clock COM0-COM3 : Common Output IC : Internally Connected INTP0-INTP5 : Interrupt from Peripherals P00-P05, P07 : port0 P10-P17 : Port1 P25-P27 P30-P37 P70-P72 P80-P87 P90-P97 P100-P103 : Port2 : Port3 : Port7 : Port8 : Port9 : Port10 SCK0, SCK2 : Serial Clock TI00, TI01 : Timer Input TI1, TI2 TO0-TO2 TXD VDD VLC0-VLC2 VSS X1, X2 XT1, XT2 : Timer Input : Timer Output : Transmit Data : Power Supply : LCD Power Supply : Ground : Crystal (Main System Clock) : Crystal (Subsystem Clock) 9 PD78062(A), 78063(A), 78064(A) 2. BLOCK DIAGRAM TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 16-bit TIMER/ EVENT COUNTER P00 PORT0 P01-P05 P07 8-bit TIMER/ EVENT COUNTER 1 PORT1 P10-P17 TO2/P32 TI2/P34 8-bit TIMER/ EVENT COUNTER 2 PORT2 P25-P27 PORT3 WATCHDOG TIMER PORT7 WATCH TIMER P30-P37 P70-P72 PORT8 78K/0 CPU CORE P80-P87 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SERIAL INTERFACE 0 ROM PORT9 P90-P97 PORT10 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 SERIAL INTERFACE 2 PORT11 P100-P103 P110-P117 S0-S23 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/P00INTP5/P05 A/D CONVERTER LCD CONTROLLER/ DRIVER INTERRUPT CONTROL RAM S24/P97S31/P90 S32/P87S39/P80 COM0-COM3 VLC0-VLC2 BIAS fLCD RESET X1 X2 XT1/P07 XT2 BUZ/P36 BUZZER OUTPUT PCL/P35 CLOCK OUTPUT CONTROL VDD VSS IC SYSTEM CONTROL Remark The internal ROM and RAM capacities differ depending on the product. 10 PD78062(A), 78063(A), 78064(A) 3. PIN FUNCTIONS 3.1 Port Pins (1/2) DualFunction Pin INTP0/TI00 INTP1/TI01 Input/ output Port 0 7-bit I/O port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. INTP2 Input INTP3 INTP4 INTP5 Input Input only Port 1 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software.Note2 Port 2 3-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. Input XT1 Pin Name P00 P01 P02 P03 P04 P05 P07 Note1 I/O Input Function Input only After Reset Input P10 to P17 Input/ output ANI0 to Input ANI7 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P70 P71 P72 Input/ output Input/ output Input/ output SI0/SB0 Input SO0/SB1 SCK0 TO0 TO1 Port 3 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. TO2 Input TI1 TI2 PCL BUZ ---- Port 7 3-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. SI2/RxD SO2/TxD Input SCK2/ ASCK Notes 1. 2. When using the P07/XT1 pins as an input port, set (1) bit 6 (FRC) of the processor clock control register (PCC) (the on-chip feedback resistor of the subsystem clock oscillator should not be used). When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, port 1 is set to input mode. However, on-chip pull-up resistor is not automatically used. 11 PD78062(A), 78063(A), 78064(A) 3.1 Port Pins (2/2) DualFunction Pin Pin Name I/O Function Port 8 8-bit input/output port Input/output can be specified bit-wise. When used as an input port , on-chip pull-up resistor can be used in software. Input/output port/segment signal output function can be specified in 2-bit unit by the LCD control register (LCDC). Port 9 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. Input/output port/segment signal output function can be specified in 2-bit unit by the LCD control register (LCDC). Port 10 4-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. LED direct drive capability. Port 11 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. Falling edge detection capability. After Reset P80 to P87 Input/ output Input S39 to S32 P90 to P97 Input/ output Input S31 to S24 P100 to P103 Input/ output Input P110 to P117 Input/ output Input 12 PD78062(A), 78063(A), 78064(A) 3.2 Other Pins (1/2) DualFunction Pin P00/TI00 P01/TI01 Input External interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. Input P02 P03 P04 P05 Input SI2 SO0 SO2 SB0 SB1 SCK0 SCK2 RxD TxD ASCK TI00 TI01 Input TI1 TI2 TO0 TO1 TO2 PCL BUZ S0 to S23 S24 to S31 S32 to S39 COM0 to COM3 VLC0 to VLC2 BIAS Output LCD controller/driver common signal output. LCD drive voltage. Split resistors can be incorporated by mask option. LCD drive power supply. Output Output LCD controller/driver segment signal output. Input P87 to P80 Output Output Output Input /output Input /output Input Output Input Serial interface serial data input/output. Input Output Serial interface serial data output. Input P71/TxD P25/SI0 P26/SO0 Serial interface serial clock input/output. Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input. External count clock input to 16-bit timer (TM0). Capture trigger signal input to capture register (CR00). External count clock input to 8-bit timer (TM1). External count clock input to 8-bit timer (TM2). 16-bit timer (TM0) output (shared with 14-bit PWM output). 8-bit timer (TM1) output. 8-bit timer (TM2) output. Clock output (for main system clock, subsystem clock trimming). Buzzer output. Input Input Output P97 to P90 Input Input P33 P34 P30 P31 P32 P35 P36 Input Input Input Input P27 P72/ASCK P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1 Serial interface serial data input. Input P25/SB0 P70/RxD P26/SB1 Pin Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SI0 I/O Function After Reset 13 PD78062(A), 78063(A), 78064(A) 3.2 Other Pins (2/2) I/O Input Input A/D converter analog input. A/D converter reference voltage input. A/D converter analog power supply. Connect to VDD. A/D converter ground potential. Connect to VSS. Input Input Main system clock oscillation crystal connection. X2 XT1 XT2 VDD VSS IC Positive power supply. Ground potential. Internal connection. Connect directly to VSS pin. Input Subsystem clock oscillation crystal connection. ---- ---- ---- ---- ---- ---- ---- ---- System reset input. Function After Reset Input ---- ---- ---- ---- ---- ---- Input DualFunction Pin P10 to P17 ---- ---- ---- ---- ---- ---- P07 Pin Name ANI0 to ANI7 AVREF AVDD AVSS RESET X1 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Input/Output Circuit Type of Each Pin (1/2) Input/output Circuit Type 2 Pin Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 P10/ANI0 to P17/ANI7 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 I/O Input Recommended Connection when not Used Connected to VSS . 8-A Input/output Independently connected to VSS through resistor. 16 11 Input Connected to VDD . 10-A Input/output Independently connected to VDD or VSS through resistor. 5-A 14 PD78062(A), 78063(A), 78064(A) Table 3-1. Input/Output Circuit Type of Each Pin (2/2) Pin Name P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P80/S39 to P87/S32 17-A P90/S31 to P97/S24 8-A 5-A 8-A Input/output Independently connected to VDD or VSS through resistor. 5-A Input/output Circuit Type 8-A I/O Recommended Connection when not Used P100 to P103 5-A P110 to P117 S0 to S23 COM0 to COM3 VLC0 to VLC2 BIAS RESET XT2 AVREF AVDD AVSS IC 8-A 17 18 ---- 2 16 ---- ---- Output Independently connected to VDD through resistor. Leave open. ---- Input Leave open. Connected to VSS . Connected to VDD . Connected to VSS . Connected directly to VSS . ---- 15 PD78062(A), 78063(A), 78064(A) Figure 3-1. Pin Input/Output Circuits (1/2) Type 2 Type 10-A VDD pull-up enable VDD P-ch IN data P-ch IN/OUT open drain output disable N-ch Schmitt-Triggered Input with Hysteresis Characteristic Type 5-A Type 11 VDD pull-up enable VDD data P-ch IN/OUT output disable N-ch output disable Comparator + - VDD pull-up enable data P-ch P-ch VDD P-ch IN/OUT N-ch P-ch N-ch VREF (Threshold Voltage) input enable input enable Type 16 Type 8-A VDD feedback cut-off pull-up enable VDD data P-ch P-ch P-ch IN/OUT output disable N-ch XT1 XT2 16 PD78062(A), 78063(A), 78064(A) Figure 3-1. Pin Input/Output Circuits (2/2) Type 17 Type 17-A VLC0 P-ch VLC1 N-ch P-ch SEG data P-ch VLC2 N-ch N-ch OUT VDD pull-up enable VDD data P-ch P-ch IN/OUT output disable input enable N-ch Type 18 VLC0 P-ch VLC1 N-ch P-ch SEG data N-ch P-ch VLC0 P-ch VLC1 N-ch P-ch COM data P-ch VLC2 N-ch N-ch P-ch OUT N-ch VLC2 N-ch 17 PD78062(A), 78063(A), 78064(A) 4. MEMORY SPACE The memory map of PD78062(A)/78063(A)/78064(A) is shown in Figure 4-1. Figure 4-1. Memory Map FFFFH Special Function Register (SFR) 256 x 8 Bits FF00H FEFFH FEE0H General Registers 32 x 8 Bits Internal High-Speed RAMNote mmmmH mmmmH-1 Data Memory Space FA80H FA7FH LCD Display RAM 40 x 4 Bits FA58H FA57H Use Prohibited nnnnH Program Area 1000H 0FFFH CALLF Entry Area 0800H 07FFH Program Area Use Prohibited 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area nnnnH+1 nnnnH Program Memory Space Internal ROMNote 0000H 0000H Note The Internal ROM and Internal High-Speed RAM capacities differ depending on the product. (refer to the following table.) Last Address of Internal ROM nnnnH 3FFFH 5FFFH 7FFFH Start Address of Internal High-Speed RAM mmmmH FD00H FB00H Product Name PD78062(A) PD78063(A) PD78064(A) 18 PD78062(A), 78063(A), 78064(A) 5. PERIPHERAL HARDWARE FUNCTION FEATURE 5.1 Port There are two kinds of I/O port. * CMOS input (P00, P07) * CMOS input/output (P01 to P05, Port 1 to 3, 7 to 11) Total :2 : 55 : 57 Table 5-1. Functions of Ports Name Pin Name P00, P07 Dedicated input port Function Port 0 P01 to P05 P10 to P17 P25 to P27 P30 to P37 P70 to P72 Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software . Input/output port. Input/output specifialbe bit-wise. When used as input port, on-chip pull-up resistor can be used in software . Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software . Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. 4 Port 1 Port 2 Port 3 Port 7 Port 8 P80 to P87 Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. Input/output port/segment signal output function specifiable in 2-bit units by LCD control register (LCDC). Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. Input/output port/segment signal output function specifiable in 2-bit units by LCD control register (LCDC). Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. Direct LED drive capability. Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. Test flag (KRIF) is set to 1 by falling edge detection. Port 9 P90 to P97 Port 10 P100 to P103 Port 11 P110 to P117 19 PD78062(A), 78063(A), 78064(A) 5.2 Clock Generator There are two kinds of clocks, main system clock and subsystem clock. The minimum instruction execution time can also be changed. * 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (main system clock: in 5.0 MHz operation) * 122 s (subsystem clock: in 32.768 kHz operation) Figure 5-1. Clock Generator Block Diagram XT1/P07 XT2 Subsystem Clock Oscillator fXT Watch Timer Clock Output Function Prescaler X1 X2 Main System Clock Oscillator fX Selector Scaler fX 2 Prescaler fXX fXX 2 fXX 22 fXX 23 1/2 fXX fXT 24 2 Standby Control Circuit Clock to Peripheral Hardware STOP Selector CPU Clock (fCPU) To INTP0 Sampling Clock 5.3 Timer/Event Counter Five timer/event counter channels are incorporated. * 16-bit timer/event counter * 8-bit timer/event counter * Watch timer * Watchdog timer : 1 channel : 2 channels : 1 channel : 1 channel Table 5-2. Timer/Event Counter Types and Functions 16-bit Timer/ Event Counter Type Interval timer External event counter Timer output PWM output Pulse width measurement Square wave output One-shot pulse output Interrupt request Test input 1 channel 1 channel 1 output 1 output 2 inputs 1 output 1 output 2 - 8-bit Timer/ Event Counter 2 channels 2 channels 2 outputs - - 2 outputs - 2 - Watch Timer 1 channel - - - - - - 2 1 input Watchdog Timer 1 channel - - - - - - 1 - Function 20 PD78062(A), 78063(A), 78064(A) Figure 5-2. 16-Bit Timer/Event Counter Block Diagram Internal Bus INTP1 TI01/P01/INTP1 Selector 16-Bit Capture/Compare Register (CR00) PWM Pulse Output Control Circuit INTTM00 Match Watch Timer Output 2fXX fXX fXX/2 fXX/22 TI00/P00/INTP0 Edge Detector Match Selector 16-Bit Timer Register (TM0) Clear Output Control Circuit TO0/P30 4 Selector INTTM01 INTP0 16-Bit Capture/Compare Register (CR01) Internal Bus Figure 5-3. 8-Bit Timer/Event Counter Block Diagram Internal Bus INTTM1 8-Bit Compare Register (CR10) 8-Bit Compare Register (CR20) Selector Match Match Output Control Circuit TO2/P32 fXX/2-fXX/29 fXX/211 TI1/P33 Clear fXX/2-fXX/29 fXX/211 TI2/P34 Output Control Circuit Internal Bus Selector Selector 8-Bit Timer Register 1 (TM1) 8-Bit Timer Register 2 (TM2) Clear Selector INTTM2 Selector TO1/P31 21 PD78062(A), 78063(A), 78064(A) Figure 5-4. Watch Timer Block Diagram fW 214 fXX/27 fXT fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 Selec- fW tor Selector Prescaler fW 213 5-Bit Counter Selector INTWT Selector INTTM3 To 16-Bit Timer/Event Counter To LCD Controller/Driver Figure 5-5. Watchdog Timer Block Diagram fXX 23 fXX 24 fXX 25 fXX 26 Prescaler fXX 27 fXX 28 fXX 29 fXX 211 INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request 22 PD78062(A), 78063(A), 78064(A) 5.4 Clock Output Control Circuit Clocks of the following frequency can be output as clock outputs. * 19.5 kHz/39.1kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (main system clock: in 5.0 kHz operation) * 32.768 kHz (subsystem clock: in 32.768 kHz operation) Figure 5-6. Clock Output Circuit Block Diagram fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXT Selector Synchronization Circuit Output Control Circuit PCL/P35 4 5.5 Buzzer Output Control Circuit Clocks of the following frequency can be output as buzzer outputs. * 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (main system clock : in 5.0 MHz operation) Figure 5-7. Buzzer Output Control Circuit Block Diagram fXX/29 fXX/210 fXX/211 Selector Output Control Circuit BUZ/P36 23 PD78062(A), 78063(A), 78064(A) 5.6 A/D Converter Eight 8-bit resolution A/D converter channels are incorporated. The following two types of start-up method are available. * Hardware start * Software start Figure 5-8. A/D Converter Block Diagram Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Successive Approximation Register (SAR) AVSS Selector Sample & Hold Circuit Voltage Comparator Tap Selector AVDD AVREF INTP3/P03 Edge Detector Control Circuit INTAD INTP3 A/D Conversion Result Register (ADCR) Internal Bus 5.7 Serial Interface Two clocked serial interface channels are incorporated. * Serial interface channel 0 * Serial interface channel 2 Table 5-3. Serial Interface Channel Block Diagram Function 3-wire serial I/O mode SBI (serial bus interface) mode 2-wire serial I/O mode Asynchronous serial interface (UART) mode Serial Interface Channel 0 (MSB/LSB-first switchable) (MSB-first) (MSB-first) ---- Serial Interface Channel 2 (MSB/LSB-first switchable) ---- ---- (Dedicated baud rate generator incorpoorated) 24 PD78062(A), 78063(A), 78064(A) Figure 5-9. Serial Interface Channel 0 Block Diagram Internal Bus SI0/SB0/P25 Selector SO0/SB1/P26 Serial I/O Shift Register 0 (SIO0) Output Latch Selector Bus Release/Command/ Acknowledge Detector Busy/Acknowledge Output Circuit SCK0/P27 Serial Clock Counter Interrupt Request Signal Generator INTCSI0 4 fXX/2-fXX/28 Serial Clock Control Circuit Selector TO2 Figure 5-10. Serial Interface Channel 2 Block Diagram Internal bus Receive Buffer Register (RXB/SIO2) Direction Control Circuit Direction Control Circuit Transmit Shift Register (TXS/SIO2) RXD/SI2/P70 TXD/SO2/P71 Receive Shift Register (RXS) Transmit Control Circuit INTST Receive Control Circuit INTSER INTSR/INTCSI2 SCK Output Control Circuit ASCK/SCK2/P72 Baud Rate Generator fXX-fXX/210 25 PD78062(A), 78063(A), 78064(A) 5.8 LCD Controller/Driver An LCD controller/driver with the following functions is incorporated. * Selection of 5 types of display mode * 16 of the segment signal of outputs can be switched to input/output ports in units of 2. (P80/S39 to P87/S32, P90/S31 to P97/S24) Table 5-4. Display Mode Types and Maximum Number of Display Pixels Bias Method ---- 1/2 1/3 Time Multiplexing Static 2 3 3 4 Common Signal Used COM0 (COM1 to COM3) COM0, COM1 COM0 to COM2 COM0 to COM2 COM0 to COM3 Maximum Number of Display Pixels 40 (40 segments x 1 common) 80 (40 segments x 2 commons) 120 (40 segments x 3 commons) 160 (40 segments x 4 commons) Figure 5-11. LCD Controller/Driver Block Diagram Internal Bus Prescaler Display Data Memory Timing Controller Segment Data Selector Port Output Data LCD Drive Voltage Generator Segment Driver Common Driver LCDCL Selector fW 29 fW 28 fW 27 fW 26 S0 S23 S24/P97 S39/P80 COM0 COM1 COM2 COM3 VLC2 VLC1 VLC0 BIAS 26 PD78062(A), 78063(A), 78064(A) 6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6.1 Interrupt Functions The following three types, 20 sources of interrupt functions are available: * Non-maskable : 1 * Maskable * Software : 18 :1 27 PD78062(A), 78063(A), 78064(A) Table 6-1. Interrupt Source List Interrupt Type Nonmaskable Default Priority Note1 Interrupt Source Name INTWDT INTWDT INTP0 INTP1 INTP2 Pin input edge detection INTP3 INTP4 INTP5 INTCSI0 INTSER INTSR Serial interface channel 0 transfer termination Serial interface channel 2 UART reception error generation Serial interface channel 2 UART reception termination Serial interface channel 2 3-wire transfer termination Serial interface channel 2 UART transmission termination Reference time interval signal from watch timer 16-bit timer register and capture/compare register (CR00) match signal generation 16-bit timer register and capture/compare register (CR01) match signal generation 8-bit timer/event counter 1 match signal generation 8-bit timer/event counter 2 match signal generation A/D converter conversion termination BRK instruction execution Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Internal/ External Vector Table Address Basic Configuration Type Note2 (A) ---- 0 1 2 3 4 5 6 7 8 Internal Watchdog timer overflow (with interval timer mode selected) 0004H (B) 0006H 0008H 000AH (C) External 000CH 000EH 0010H 0014H 0018H (D) Maskable 9 INTCSI2 10 11 12 13 14 15 16 INTST INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD BRK 001AH 001CH Internal 001EH 0020H 0022H 0024H 0026H 0028H ---- 003EH (E) (B) Software ---- Notes 1. 2. Default priority is a priority order when more than one maskable interrupt request is generated simultaneously. 0 is the highest and 16 the lowest. Basic configuration types (A) to (E) correspond to those shown in Figure 6-1. 28 PD78062(A), 78063(A), 78064(A) Figure 6-1. Basic Configuration of Interrupt Functions (1/2) (A) Internal non-maskable interrupt Internal Bus Interrupt Request Priority Control Circuit Vector Table Address Generator Standby Release Signal (B) Intrnal maskable interrupt Internal Bus MK IE PR ISP Interrupt Request IF Priority Control Circuit Vector Table Address Generator Standby Release Signal (C) External maskable interrupt (INTP0) Internal Bus Sampling Clock Select Register (SCS) External Interrupt Mode Register (INTM0) MK IE PR ISP Interrupt Request Sampling Clock Edge Detector IF Priority Control Circuit Vector Table Address Generator Standby Release Signal 29 PD78062(A), 78063(A), 78064(A) Figure 6-1. Basic Configuration of Interrupt Functions (2/2) (D) External maskable interrupt (except INTP0) Internal Bus External Interrupt Mode Register (INTM0, INTM1) MK IE PR ISP Interrupt Request Edge Detector IF Priority Control Circuit Vector Table Address Generator Standby Release Signal (E) Software interrupt Internal Bus Interrupt Request Priority Control Circuit Vector Table Address Generator IF IE : Interrupt request flag : Interrupt enable flag ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specification flag 30 PD78062(A), 78063(A), 78064(A) 6.2 Test Functions There are two sources of test functions as shown in Table 6-2. Table 6-2. Test Input Source List Test Input Source Name INTWT INTPT11 Trigger Watch timer overflow Port 11 falling edge detection Internal/External Internal External Figure 6-2. Basic Configuration of Test Function Internal Bus MK Test Input Signal IF Standby Release Signal IF : Test input flag MK : Test mask flag 31 PD78062(A), 78063(A), 78064(A) 7. STANDBY FUNCTION The standby function is a function to reduce the consumption current and there are the following two kinds of standby functions. q HALT mode : Halts CPU operating clock and can reduce average consumption current by the intermittent operation along with the normal operation. STOP mode : Halts main system clock oscillation. Halts all operations with the main system clock and sets ultra-low consumption current state with subsystem clock only. Figure 7-1. Standby Function CSS=1 q Main System Clock Operation CSS=0 STOP Instruction Interrupt Request STOP Mode Main System Clock Oscillation Halted Interrupt Request HALT Instruction Subsystem Clock OperationNote HALT Instruction Interrupt Request ( ) ( HALT Mode Clock Supply to CPU Halted, Oscillation Maintained ) ( HALT ModeNote Clock Supply to CPU Halted, Oscillation Maintained ) Note Halting the main system clock enables the consumption current to be reduced. When the CPU is operated by the subsystem clock, the main system clock should be halted by setting the bit 7 (MCC) of the processor clock control register (PCC). The STOP instruction is not available. Caution When the main system clock is stopped and the system is operated by the subsystem clock, the main system clock should be returned to after securing the oscillation stabilization time in software. 8. RESET FUNCTION There are the following two kinds of resetting methods. * External reset by RESET pin. * Internal reset by watchdog timer hung-up time detection. 32 PD78062(A), 78063(A), 78064(A) 9. INSTRUCTION SET (1) 8-bit instruction MOV, XCH, ADD, ADDC, SUB, SUBS, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ 2nd operand #byte 1st operand A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP DBNZ MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV MOV DBNZ INC DEC MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP A rNote sfr saddr !addr16 PSW [DE] [HL] [HL+byte] [HL+B] $addr16 [HL+C] 1 ROR ROL RORC ROLC None MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP r MOV INC DEC B, C sfr saddr !addr16 PSW [DE] [HL] [HL+byte] [HL+B] [HL+C] X C MOV MOV MOV MOV MOV PUSH POP ROR4 ROL4 MULU DIVUW Note Except r = A 33 PD78062(A), 78063(A), 78064(A) (2) 16-bit instruction MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd operand #word 1st operand A ADDW SUBW CMPW MOVW MOVW MOVW MOVW MOVW XCHW MOVWNote MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW AX rpNote sfrp saddrp !addr16 SP None rp sfrp saddrp !addr16 SP INCW, DECW PUSH, POP Note Only when rp=BC, DE, HL (3) Bit manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR 2nd operand A.bit 1st operand A.bit MOV1 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 sfr.bit saddr.bit PSW.bits [HL].bit CY $addr16 None sfr.bit MOV1 saddr.bit MOV1 PSW.bit MOV1 [HL].bit MOV1 CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 (4) Call instruction/branch instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DNZB 2nd Operand 1st Operand Basic instruction Compound Instruction BR CALL BR CALLF CALLT BR, BC, BNC, BZ, BNZ BT, BF, BTCLR DBNZ AX !addr16 !addr11 [addr5] $addr16 (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 34 PD78062(A), 78063(A), 78064(A) 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 C) Parameter Symbol VDD AVDD Test Conditions Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 Unit V V V V V V V mA mA mA mA mA mA mA mA mA mA mA C C Supply voltage AVREF AVSS Input voltage Output voltage Analog input voltage VI VO VAN P10 to P17 1 pin Output current high IOH Total for P00 to P05, P07, P10 to P17, P100, P101 & P110 to P117 Total for P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P102 & P103 Peak value 1 pin rms value Total for P00 to P05, P10 to P17, P100, P101 & P110 to P117 Output current low IOL Note Total for P30 to P37, P102 & P103 Total for P25 to P27, P70 to P72, P80 to P87 & P90 to P97 Operating ambient temperature Storage temperature Peak value rms value Peak value rms value TA Tstg Peak value rms value 15 100 70 100 70 50 20 -40 to +85 -65 to +150 Analog input pin AVSS - 0.3 to AVREF + 0.3 -10 -15 -15 30 Note The rms value should be calculated as follows: [rms value] = [Peak value] x Duty Caution The product quality may be damaged even if a value of only one of the above parameters exceeds the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That is, the absolute maximum rating is a rating value which may cause a product to be damaged physically. The absolute maximum rating values must therefore be observed in using the product. Remark Unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins. 35 PD78062(A), 78063(A), 78064(A) Permissible Inrush Current Characteristics of Pins on Application of Overvoltage (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Parameter Positive inrush current (VIN > VDD) Symbol IIJH1 1 pin Conditions Input ports other than ANIn (n = 0 to 7) ANIn (n = 0 to 7)Note 1 Peak value Mean value Peak value Mean value IIJH3 Total of Input ports other than all input ANIn (n = 0 to 7) pins ANIn (n = 0 to 7)Note 2 Peak value Mean value Peak value Mean value Negative inrush current (VIN < VSS) IIJL1 1 pin Input ports other than ANIn (n = 0 to 7) ANIn (n = 0 to 7)Note 1 Peak value Mean value Peak value Mean value IIJL3 Total of Input ports other than all input ANIn (n = 0 to 7) pins ANIn (n = 0 to 7)Note 2 Peak value Mean value Peak value Mean value MIN. TYP. MAX. 5.00 0.50 1.50 0.15 40.0 4.00 1.50 0.15 -0.50 -0.05 -0.50 -0.05 -4.00 -0.40 -1.50 -0.15 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA IIJH2 IIJH4 IIJL2 IIJL4 Notes 1. If an inrush current flows to one analog input pin (ANIn: n = 0 to 7), the A/D conversion result of the analog input pin is the value when the inrush current does not flow 2 LSB. 2. If an inrush current flows to two or more analog input pins (ANIn: n = 0 to 7), the A/D conversion result of the analog input pin is the value when the inrush current does not flow 4 LSB. Remarks 1. The mean value (absolute value) of the inrush current of a pin can be calculated by the following expression: Mean value = ((1/T) T | i (t) | 0 3/2 dt)2/3 where i (t) is a pin inrush current, and the maximum value of |i (t)| is the peak value. 2. VIN is the input voltage applied to the pin. Capacitance (TA = 25 C, VDD = VSS = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Test Conditions f = 1 MHz unmeasured pins returned to 0 V. MIN. TYP. MAX. 15 15 15 Unit pF pF pF 36 PD78062(A), 78063(A), 78064(A) Main System Clock Oscillator Characteristics (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Recommended circuit IC X2 X1 Oscillator Parameter Oscillator frequency (fX) Note1 Oscillation stabilization time Note2 Oscillator frequency (fX) Note1 Oscillation stabilization time Note2 X1 input frequency (fX) Note1 X1 input high/low level width (tXH , tXL) Test conditions VDD = Oscillator voltage range After VDD reaches oscillator voltage range MIN. MIN. TYP. MAX. Unit 1 5 MHz Ceramic oscillator C2 C1 4 ms IC Crystal resonator X2 X1 1 5 10 MHz C2 C1 VDD = 4.5 to 6.0 V ms 30 1.0 5.0 MHz X2 External clock X1 PD74HCU04 85 500 ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS. * Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. 2. If the main system clock oscillator is operated by the subsystem clock when the main system clock is stopped, reswitching to the main system clock should be performed after the stable oscillation time has been obtained by the program. 37 PD78062(A), 78063(A), 78064(A) Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 6.0 V) Resonator Recommended Circuit Parameter Oscillator frequency (fXT) Note1 Test Conditions MIN. TYP. MAX. Unit IC XT1 XT2 R2 32 32.768 35 kHz Crystal resonator C3 C4 Oscillation stabilization time Note2 VDD = 4.5 to 6.0 V 1.2 2 10 s XT1 XT2 XT1 input frequency (fXT) Note1 32 100 kHz External clock XT1 input high-/low-level width (tXTH/tXTL) 5 15 s Notes 1. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Time required to stabilize oscillation after VDD has reached the minimum oscillation voltage range. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS. * Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. 2. The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption current, causing misoperation by noise more frequently than the main system clock oscillation circuit. Special care should therefore be taken to wiring method when the subsystem clock is used. Cautions 1. 38 PD78062(A), 78063(A), 78064(A) Recommended Oscillator Constant Main system clock: ceramic oscillator (TA = -40 to +85 C) Recommended Circuit Constant C1 (pF) Murata Mfg. Co., Ltd. CSA5.00MG CST5.00MGW EF0GC5004A4 Matsushita Electronics Components Co., Ltd. EF0EC5004A4 EF0EN5004A4 EF0S5004B5 KBR-5.0MSA Kyocera Corporation PBRC5.00A KBR-5.0MKS KBR-5.0MWS 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 30 Built-in Built-in Built-in 33 Built-in 33 33 Built-in Built-in C2 (pF) 30 Built-in Built-in Built-in 33 Built-in 33 33 Built-in Built-in Oscillator Voltage Range MIN. (V) 2.2 2.7 2.7 2.0 2.7 2.7 2.7 2.7 2.7 2.7 MAX. (V) 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 Lead type Round lead type Lead type Chip type Lead type Chip type Lead type Chip type Manufacturer Product Name Frequency (MHz) Remarks Subsystem clock: crystal resonator (TA = -40 to +60 C) Recommended Circuit Constant C3 (pF) Kyocera Corporation KF-38G-12P0200Note (Load capacitance 12 pF) 32.768 15 C4 (pF) 22 R2 (k) 220 Oscillator Voltage Range MIN. (V) 2.0 MAX. (V) 6.0 Manufacturer Product Name Frequency (kHz) Note KF-38G-12P0200 is a maintenance product. Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation. However, they do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 39 PD78062(A), 78063(A), 78064(A) DC Characteristics (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Parameter Symbol Test Conditions P10 to P17, P30 to P32, VIH1 P35 to P37, P80 to P87, P90 to P97, P100 to P103 VIH2 Input voltage high VIH3 P00 to P05, P25 to P27, P33, P34, P70 to P72, P110 to P117, RESET VDD = 2.7 to 6.0 V X1, X2 VDD-0.2 4.5 V VDD 6.0 V VIH4 XT1/P07, XT2 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V P10 to P17, P30 to P32, VIL1 P35 to P37, P80 to P87, P90 to P97, P100 to P103 P00 to P05, P25 to P27, VIL2 Input voltage low VIL3 P33, P34, P70 to P72, P110 to P117, RESET VDD = 2.7 to 6.0 V X1, X2 0 4.5 V VDD 6.0 V VIL4 XT1/P07, XT2 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 VNote Output voltage high VOH VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = -100 A P100 to P103 VOL1 Output voltage low P00 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P110 to P117 VDD = 4.5 to 6.0 V, IOL = 15 mA 0 0 0 VDD-1.0 VDD-0.5 0.4 0.2 0.2 VDD 0.1 VDD 0.1 VDD VDD VDD 2.0 V V V V V V V 0 0 0.15 VDD 0.4 V V VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V Note MIN. 0.7 VDD 0.8 VDD TYP. MAX. VDD VDD VDD VDD VDD VDD VDD VDD VDD 0.3 VDD 0.2 VDD 0.2 VDD Unit V V V V V V V V V V V V VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V 0.8 VDD 0.85 VDD VDD-0.5 0.8 VDD 0.9 VDD 0.9 VDD 0 0 0 VDD = 4.5 to 6.0 V, IOL = 1.6 mA 0.4 V VOL2 VOL3 SB0, SB1, SCK0 IOL = 400 A 4.5 V VDD 6.0 V, open-drain, pulled high (R = 1 k) 0.2 VDD V 0.5 V Note When P07/XT1 is used as P07, the inverse phase of P07 should be input to XT2. Remark Unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins. 40 PD78062(A), 78063(A), 78064(A) DC Characteristics (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Parameter Symbol Test Conditions P00 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117 X1, X2, XT1/P07, XT2 P00 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117 X1, X2, XT1/P07, XT2 VO = VDD VO = 0 V VI = 0 V, P01 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117 5.00 MHz, Crystal oscillation (fXX = 2.5 MHz)Note2 operating mode 5.00 MHz, Crystal oscillation (fXX = 5.0 MHz)Note3 operating mode 5.00 MHz, Crystal oscillation (fXX = 2.5 MHz)Note2 HALT mode 5.00 MHz, Crystal oscillation (fXX = 5.0 MHz)Note3 HALT mode MIN. TYP. MAX. Unit Input leakage current high ILIH1 VI = VDD 3 A ILIH2 20 A Input leakage current low ILIL1 VI = 0 V -3 A ILIL2 Output leakage current high Output leakage current low ILOH ILOL -20 3 -3 A A A 4.5 V VDD 6.0 V 15 40 90 k Software pull-up resistor R 2.7 V VDD < 4.5 V VDD = 5.0 V 10 %Note4 VDD = 3.0 V 10 % VDD = 2.2 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 2.2 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % Note5 Note5 Note4 Note5 20 4 0.6 0.35 6.5 0.8 1.4 500 280 1.6 650 500 12 1.8 1.05 19.5 2.4 4.2 1500 840 4.8 1950 k mA mA mA mA mA mA IDD1 Supply currentNote1 A A mA IDD2 A Notes 1. Not including currents flowing in on-chip pull-up resistors or LCD split resistors. 2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 3. Main system clock fXX = fX operation (when OSMS is set to 01H) 4. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 5. Low-speed mode operation (when PCC is set to 04H) Remark Unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins. 41 PD78062(A), 78063(A), 78064(A) DC Characteristics (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Parameter Symbol Test Conditions 32,768 kHz, Crystal oscillation operating modeNote2 32,768 kHz, Crystal oscillation HALT modeNote2 XT1 = VDD STOP mode When feedback resistor is connected XT1 = VDD STOP mode When feedback resistor is disconnected VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD = = = = = = = = = = = = 5.0 3.0 2.2 5.0 3.0 2.2 5.0 3.0 2.2 5.0 3.0 2.2 V V V V V V V V V V V V 10 10 10 10 10 10 10 10 10 10 10 10 % % % % % % % % % % % % MIN. TYP. 60 32 24 25 5 2.5 1 0.5 0.3 0.1 0.05 0.05 MAX. 120 64 48 55 15 12.5 30 10 10 30 10 10 Unit IDD3 IDD4 Supply currentNote1 IDD5 IDD6 A A A A A A A A A A A A Notes 1. Not including currents flowing in on-chip pull-up resistors or LCD split resistors. 2. When the main system clock is stopped. 42 PD78062(A), 78063(A), 78064(A) DC Characteristics (TA = -10 to +85 C) (1) Static display mode (VDD = 2.0 to 6.0 V) Parameter LCD drive voltage LCD split resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS IO = 5 A IO = 1 A 2.0 V VLCD VDD VLCD0 = VLCD Test Conditions MIN. 2.0 60 0 0 TYP. MAX. VDD 150 0.2 0.2 Unit V k V V 100 Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). (2) 1/3 bias method (VDD = 2.5 to 6.0 V) Parameter LCD drive voltage LCD split resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS IO = 5 A IO = 1 A 2.5 V VLCD VDD VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 Test Conditions MIN. 2.5 60 0 0 TYP. MAX. VDD 150 0.2 0.2 Unit V k V V 100 Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). (3) 1/2 bias method (VDD = 2.7 to 6.0 V) Parameter LCD drive voltage LCD split resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS IO = 5 A IO = 1 A 2.7 V VLCD VDD VLCD0 = VLCD VLCD1 = VLCD x 1/2 VLCD2 = VLCD1 Test Conditions MIN. 2.7 60 0 0 TYP. MAX. VDD 150 0.2 0.2 Unit V k V V 100 Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). 43 PD78062(A), 78063(A), 78064(A) AC Characteristics (1) Basic operation (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Parameter Cycle time (Minimum instruction execution time) TI00 input frequency TI00 input high/ low-level width TI01 input high/ low-level width TI1, TI2 input high/ low-level width TI1, TI2 input high/ low-level width Interrupt input high/low-level width RESET low level width Symbol Test Conditions Operating on main system clock VDD = 2.7 to 6.0 V 4.5 VDD 6.0 V 2.7 VDD < 4.5 V MIN. 0.8 2.2 0.4 0.8 40Note3 0 2/fsam+0.1Note 4 2/fsam+0.2Note 4 2/fsam+0.5Note 4 10 20 0 0 100 1.8 8/fsamNote4 10 20 10 20 TYP. MAX. 64 64 32 32 125 1/tTI00 Unit TCY fTI00 fTIH00, tTIL00 fTIH01, tTIL01 fTI1 (fXX = 2.5 MHz) Note1 Operating on main system clock (fXX = 5.0 MHz) Note2 Operating on subsystem clock tTI00 = tTIH00 + tTIL00 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 2.7 V VDD 6.0 V VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V INTP0 INTP1 to INTP5, P110 to P117 VDD = 2.7 to 6.0 V 122 s s s s s MHz s s s s s MHz kHz ns 4 275 tTIH1, tTIL1 tINTH, tINTL tRSL s s s s s s VDD = 2.7 to 6.0 V Notes 1. 2. 3. 4. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) Main system clock fXX = fX operation (when OSMS is set to 01H) This is the value when the external clock is used. The value is 114 s (min.) when the crystal resonator is used. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is possible between fXX/2N, fXX/32, fXX/64 and fXX/128 (when N = 0 to 4). 44 PD78062(A), 78063(A), 78064(A) TCY vs VDD (At main system clock fXX = fX/2 operation) TCY vs VDD (At main system clock fXX = fX operation) 60 60 32 Cycle Time TCY [ s] 10 Guaranteed Operation Range Cycle Time TCY [ s] 10 Guaranteed Operation Range 2.0 2.0 1.0 0.8 0.4 1.0 0.8 0.4 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Supply Voltage VDD [V] Supply Voltage VDD [V] 45 PD78062(A), 78063(A), 78064(A) (2) Serial Interface (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0... Internal clock output) Parameter Symbol Test Conditions 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V VDD = 4.5 to 6.0 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 tKCY1/2-50 tKCY1/2-100 100 150 300 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns SCK0 cycle time tKCY1 tKH1, tKL1 tSIK1 SCK0 high/low-level width SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 tKSI1 tKSO1 C = 100 pFNote 300 ns Note C is the load capacitance of SCK0, SO0 output line. (ii) 3-wire serial I/O mode (SCK0...External clock input) Parameter Symbol Test Conditions 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 400 800 1600 100 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns SCK0 cycle time tKCY2 SCK0 high/low-level width tKH2, tKL2 tSIK2 tKSI2 tKSO2 tR2, tF2 SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 rise, fall time C = 100 pFNote 300 ns 1000 ns Note C is the load capacitance of SO0 output line. 46 PD78062(A), 78063(A), 78064(A) (iii) SBI mode (SCK0...Internal clock output) Parameter SCK0 cycle time Symbol tKCY3 3200 SCK0 high/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKH3, tKL3 tSIK3 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKCY3/2-50 tKCY3/2-150 100 300 tKSI3 tKCY3/2 ns ns ns ns ns ns Test Conditions VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. Unit ns R = 1 k , tKSO3 tKSB tSBK tSBH C = 100 pFNote VDD = 4.5 to 6.0 V 0 0 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns tSBL tKCY3 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line. (iv) SBI mode (SCK0...External clock input) Parameter SCK0 cycle time Symbol tKCY4 3200 SCK0 high/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK0 rise, fall time tKH4, tKL4 tSIK4 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 300 tKSI4 tKCY4/2 ns ns ns ns ns ns Test Conditions VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. Unit ns R = 1 k , tKSO4 tKSB tSBK tSBH C = 100 pF Note VDD = 4.5 to 6.0 V 0 0 tKCY4 tKCY4 tKCY4 300 1000 ns ns ns ns ns tSBL tR4, tF4 tKCY4 1000 ns ns Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line. 47 PD78062(A), 78063(A), 78064(A) (v) 2-wire serial I/O mode (SCK0... Internal clock output) Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 Symbol tKCY5 tKH5 tKL5 R = 1 k, C = 100 pFNote Test Conditions VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V VDD = 4.5 to 6.0 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V MIN. 1600 3200 tKCY5/2-160 tKCY5/2-190 tKCY5/2-50 tKCY5/2-100 300 350 400 600 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns tSIK5 tKSI5 tKSO5 Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line. (vi) 2-wire serial I/O mode (SCK0... External clock input) Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SCK0 rise, fall time Symbol tKCY6 tKH6 tKL6 tSIK6 tKSI6 tKSO6 tR6, tF6 Test Conditions VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V MIN. 1600 3200 650 1300 800 1600 100 tKCY6/2 TYP. MAX. Unit ns ns ns ns ns ns ns ns R = 1 k, VDD = 4.5 to 6.0 V C = 100 pFNote 0 0 300 500 1000 ns ns ns Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line. 48 PD78062(A), 78063(A), 78064(A) (b) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2... Internal clock output) Parameter Symbol Test Conditions 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V VDD = 4.5 to 6.0 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 tKCY1/2-50 tKCY1/2-100 100 150 300 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns SCK2 cycle time tKCY7 tKH7, tKL7 tSIK7 SCK2 high/low-level width SI2 setup time (to SCK2) SI2 hold time (from SCK2) SO2 output delay time from SCK2 tKSI7 tKSO7 C = 100 pFNote 300 ns Note C is the load capacitance of SCK2, SO2 output line. (ii) 3-wire serial I/O mode (SCK2...External clock input) Parameter Symbol Test Conditions 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 400 800 1600 100 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns SCK2 cycle time tKCY8 SCK2 high/low-level width tKH8, tKL8 tSIK8 tKSI8 tKSO8 tR8, tF8 SI2 setup time (to SCK2) SI2 hold time (from SCK2) SO2 output delay time from SCK2 SCK2 rise, fall time C = 100 pFNote 300 ns 1000 ns Note C is the load capacitance of SO2 output line. 49 PD78062(A), 78063(A), 78064(A) (iii) UART mode (Dedicated baud rate generator output) Parameter Symbol Test Conditions 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V MIN. TYP. MAX. 78125 39063 19531 Unit bps bps bps Transfer rate (iv) UART mode (External clock input) Parameter Symbol Test Conditions 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 400 800 1600 39063 19531 9766 1000 TYP. MAX. Unit ns ns ns ns ns ns bps bps bps ns ASCK cycle time tKCY9 ASCK high/low-level width tKH9, tKL9 Transfer rate ASCK rise, fall time tR9, tF9 50 PD78062(A), 78063(A), 78064(A) AC Timing Test Point (Excluding X1, XT1 Input) 0.8 VDD 0.2 VDD Test Points 0.8 VDD 0.2 VDD Clock Timing 1/fX tXL tXH VIH3 (MIN.) VIL3 (MAX.) X1 Input 1/fXT tXTL XT1 Input tXTH VIH4 (MIN.) VIL4 (MAX.) TI Timing tTIL00, tTIL01 tTIH00, tTIH01 TI00, TI01 1/fTI1 tTIL1 tTIH1 TI0-TI2 51 PD78062(A), 78063(A), 78064(A) Serial Transfer Timing 3-wire serial I/O mode: tKCY 1, 2, 7, 8 tKL1, 2, 7, 8 tR2, 8 SCK0, SCK2 tKH1, 2, 7, 8 tF2, 8 tSIK1, 2, 7, 8 tKSI1, 2, 7, 8 SI0, SI2 tKSO1, 2, 7, 8 Input Data SO0, SO2 Output Data SBI mode (bus release signal transfer): tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 tF4 SB0, SB1 tKSO3, 4 SBI mode (command signal transfer): tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBK tSIK3, 4 tKSI3.4 tKH3, 4 tF4 SB0, SB1 tKSO3, 4 52 PD78062(A), 78063(A), 78064(A) 2-wire serial I/O mode: tKCY5.6 tKL5, 6 tR6 SCK0 tSIK5, 6 tKSO5, 6 SB0, SB1 tKSI5, 6 tKH5, 6 tF6 UART mode: tKCY9 tKL9 tR9 ASCK tKH9 tF9 A/D Converter (TA = -40 to +85 C, AVDD = VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V) Parameter Resolution 2.7 V AVREF 6.0 V Overall error Note Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 0.6 1.4 Unit bit % % Conversion time Sampling time Analog input voltage Reference voltage AVREF-AVSS resistance tCONV tSAMP VIAN AVREF RAIREF 19.1 12/fXX AVSS 2.0 4 14 200 s s AVREF AVDD V V k Note Quantization error (1/2 LSB) is not included. This is expressed in proportion to the full-scale value. 53 PD78062(A), 78063(A), 78064(A) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillation stabilization wait time tWAIT Release by interrupt Note ms Symbol VDDDR VDDDR = 1.8 V Subsystem clock stopped and feed-back resistor disconnected 0 Release by RESET 217/fx Test Conditions MIN. 1.8 TYP. MAX. 6.0 Unit V IDDDR 0.1 10 A s ms tSREL Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS), selection of 212/fXX and 214/fXX to 217/fXX is possible. Data retention timing (STOP mode release by RESET) Internal Reset Operation HALT Mode STOP Mode Operating Mode Data Retention Mode VDD STOP Instruction Execution RESET VDDDR tSREL tWAIT Data retention timing (STOP mode release by standby release signal: Interrupt signal) HALT Mode STOP Mode Operating Mode Data Retention Mode VDD STOP Instruction Execution Standby Release Signal (Interrupt Request) VDDDR tSREL tWAIT 54 PD78062(A), 78063(A), 78064(A) Interrupt input timing tINTL tINTH INTP0-INTP5 RESET input timing tRSL RESET 55 PD78062(A), 78063(A), 78064(A) 11. CHARACTERISTIC CURVES (REFERENCE VALUES) IDD vs VDD (Main System Clock: 5.0 MHz) (TA = 25 C) 10.0 PCC=00H 5.0 PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT (X1 Oscillation, XT1 Oscillation) 1.0 0.5 Supply Current IDD (mA) 0.1 PCC=B0H 0.05 HALT (X1 Stop, XT1 Oscillation) STOP (X1 Stop, XT1 Oscillation) 0.01 0.005 f XX = 5.0 MHz f XT = 32.768 kHz 0.001 0 1 2 3 4 5 6 7 8 Supply Voltage VDD (V) 56 PD78062(A), 78063(A), 78064(A) IDD vs VDD (Main System Clock: 2.5 MHz) (TA = 25 C) 10.0 5.0 PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT (X1 Oscillation, XT1 Oscillation) 1.0 0.5 Supply Current IDD (mA) 0.1 PCC=B0H 0.05 HALT (X1 Stop, XT1 Oscillation) STOP (X1 Stop, XT1 Oscillation) 0.01 0.005 f XX = 2.5 MHz f XT = 32.768 kHz 0.001 0 1 2 3 4 5 6 7 8 Supply Voltage VDD (V) 57 PD78062(A), 78063(A), 78064(A) 12. PACKAGE DRAWINGS 100 PIN PLASTIC QFP (FINE PITCH) ( A B 14) 75 76 51 50 detail of lead end C D S 100 1 26 25 F G H I M J K P N NOTE L ITEM MILLIMETERS A B C D F G H 16.00.2 14.00.2 14.00.2 16.00.2 1.0 1.0 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.17 +0.03 -0.07 0.10 1.45 0.1250.075 55 1.7 MAX. INCHES 0.6300.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6300.008 0.039 0.039 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.004 0.057 0.0050.003 55 0.067 MAX. P100GC-50-7EA-2 Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. Remark Dimensions and materials of ES products are same as those of mass production product. M I J K L M N P Q R S 58 Q R PD78062(A), 78063(A), 78064(A) 100 PIN PLASTIC QFP (14 x 20) A B 80 81 51 50 detail of lead end D C S 100 1 31 30 F G H IM J K P N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H L P100GF-65-3BA1-2 MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 0.8 0.6 0.30 0.10 0.15 0.65 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.031 0.024 0.012+0.004 -0.005 0.006 0.026 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX. Remark Dimensions and materials of ES products are same as mass production product. I J K L M N P Q S M 55 Q 59 PD78062(A), 78063(A), 78064(A) 100 PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end CD S Q R 100 1 26 25 F G P H I M J K M N NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. L ITEM A B C D F G H MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX. INCHES 0.6300.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6300.008 0.039 0.039 0.0090.002 0.003 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.003 0.0550.002 0.0040.002 3 +7 -3 0.063 MAX. S100GC-50-8EU Remark Dimensions and materials of ES products are same as mass production product. I J K L M N P Q R S 60 PD78062(A), 78063(A), 78064(A) 13. RECOMMENDED SOLDERING CONDITIONS The PD78062(A)/78063(A)/78064(A) should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our sales personnel. Table 13-1. Surface Mounting Type Soldering Conditions (1/2) (1) PD78062GC(A)-xxx-7EA : 100-pin plastic QFP (Fine pitch) PD78063GC(A)-xxx-7EA : 100-pin plastic QFP (Fine pitch) (14 x 14mm, resin thickness: 1.45 mm) (14 x 14mm, resin thickness: 1.45 mm) (14 x 14mm, resin thickness: 1.45 mm) Recommended Condition Symbol PD78064GC(A)-xxx-7EA : 100-pin plastic QFP (Fine pitch) Soldering Method Soldering Conditions Infrared reflow Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking required at 125C) IR35-107-2 VPS VP15-107-2 Partial heating -- Note For the storage period after dry-pack decapsulation, storage conditions are max. 25C, 65% RH. (2) PD78062GF(A)-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) PD78063GF(A)-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) PD78064GF(A)-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: Thrice max. Package peak temperature: 215C, Duration: 40 sec. (at 200C or above), Number of times: Thrice max. Solder bath temperature: 260C max., Duration: 10 sec. max., Number of times: Once, Preliminary heat temperature: 120C max. (Package surface temperature) Pin temperature: 300C max. Duration: 3 sec. max. (per device side) Recommended Condition Symbol IR35-00-3 VPS VP15-00-3 Wave soldering WS60-00-1 Partial heating -- Cautions 1. Use of more than one soldering method should be avoided (except in the case of partial heating). 2. The PD78062GC(A)-xxx-8EU, 78063GC(A)-xxx-8EU, and 78064GC(A)-xxx-8EU are under planning. Therefore, soldering conditions for these products have not been specified. 61 PD78062(A), 78063(A), 78064(A) APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using PD78062(A)/78063(A)/78064(A). Language Processing Software RA78K/0 CC78K/0 DF78064 Note 1, 2, 3, 4 78K/0 series common assembler package 78K/0 series common C compiler package Note 1, 2, 3, 4 Note 1, 2, 3, 4 PD78064 subseries device file 78K/0 series common C compiler library source file CC78K/0-L Note 1, 2, 3 ,4 PROM Writing Tools PG-1500 PA-78P0308GC (or PA-78P064GC) PA-78P0308GF (or PA-78P064GF) PA-78P0308KL-T PG-1500 controller Notes 1, 2 PROM programmer Programmer adapters connected to PG-1500 PG-1500 control program Debugging Tools IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78064-R-EM Note 8 IE-780308-R-EM IE-78000-R-SV3 IE-70000-98-IF-B 78K/0 series common in-circuit emulator 78K/0 series common in-circuit emulator (for integrated debugger) 78K/0 series common break board PD78064 subseries evaluation emulation board PD780308 subseries common emulation board Interface adapter and cable when EWS is used as host machine (for IE-78000-R-A) Interface adapter when PC-9800 series (except notebook type) is used as host machine (for IE78000-R-A) Interface adapter and cable when notebook type PC-9800 series is used as host machine (for IE78000-R-A) Interface adapter when IBM PC/ATTM is used as host machine (IE-78000-R-A) IE-70000-98N-IF IE70000-PC-IF-B EP-78064GC-R EP-78064GF-R TGC-100SDW PD78064 subseries common emulation probes Adapter to be mounted on a target system board made for 100-pin plastic QFP (GC-7EA, GC-8EU type) TGC-100SDW is a product from Tokyo Eletech Corp. (TEL (03) 5295-1661) When purchasing this product, please consult with our sales offices. Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) 78K/0 series common system simulator IE-78000-R-A integrated dubugger IE-78000-R screen debugger EV-9200GF-100 SM78K0 Note 5, 6, 7 ID78K0 Note 4, 5, 6, 7 SD78K/0 Note 1, 2 DF78064 Note 1, 2, 4, 5, 6, 7 PD78064 subseries device file 62 PD78062(A), 78063(A), 78064(A) Real-Time OS RX78K/0 Note 1, 2, 3, 4 MX78K0 Note 1, 2, 3, 4 78K/0 series real-time OS 78K/0 series OS Fuzzy Inference Development Support System FE9000 Note 1, FE9200 Note 6 FT9080 Note 1, FT9085 Note 2 FI78K/0 Note 1, 2 FD78K/0 Note 1, 2 Fuzzy knowledge data creation tool Translator Fuzzy inference module Fussy inference debugger Notes 1. 2. 3. 4. 5. 6. 7. 8. PC-9800 series (MS-DOSTM) based IBM PC/AT and compatible (PC DOSTM/IBM DOSTM/MS-DOS) based HP9000 series 300TM (HP-UXTM) based HP9000 series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS-4800 series (EWS-UX/V) based PC-9800 series (MS-DOS + WindowsTM) based. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based NEWSTM (NEWS-OSTM) based IE-78064-R-EM is a maintenance product. Remarks 1. 2. For third party development tools, refer to the 78K/0 Series Selection Guide (U11126E). RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78064. 63 PD78062(A), 78063(A), 78064(A) APPENDIX B. RELATED DOCUMENTS Device Related Documents Document No. Document Name Japanese U10335J U10105J U12326J U10903J U10904J IEM-5568 IEA-767 IEA-718 English This document U10105E IEU-1372 -- -- -- U10182E IEA-1289 PD78062(A), 78063(A) 78064(A) Data Sheet PD78064, 78064Y Subseries User's Manual 78K/0 Series User's Manual - Instruction 78K/0 Series Instruction Table 78K/0 Series Instruction Set PD78018F Subseries Special Function Register Table 78K/0 Series Application Note Fundamental (III) Floating-Point Arithmetic Program Development Tools Related Documents (User's Manual) (1/2) Document No. Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language CC78K Series C Compiler Operation Language CC78K/0 C Compiler Operation Language CC78K/0 C Compiler Application Note CC78K Series Library Source File IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78064-R-EM IE-780308-R-EM EP-78064 Programming Know-how Japanese EEU-809 EEU-815 EEU-817 U11802J U11801J U11789J EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J EEU-810 U10057J EEU-867 EEU-905 U11362J EEU-934 English EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E EEU-1280 EEU-1284 U11517E U11518E EEA-1208 -- U11376E U10057E EEU-1427 EEU-1443 U11362E EEU-1469 Caution The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 64 PD78062(A), 78063(A), 78064(A) Development Tools Documents (User's Manual) (2/2) Document No. Document Name SM78K Series System Simulator External Components User Open Interface Reference Reference Reference Guide Introduction Reference Introduction Reference Japanese U10092J English U10092E SM78K0 System Simulator Windows Based ID78K0 Integrated Debugger EWS Based ID78K0 Integrated Debugger PC Based ID78K0 Integrated Debugger Windows Based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based SD78K/0 Screen Debugger IBM PC/AT (PC DOS) Based U10181J U11515J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J U10181E -- U11539E U11649E U10539E -- EEU-1414 U11279E Embedded Software Documents (User's Manual) Document No. Document Name 78K/0 Series Real-Time OS Fundamental Installation 78K/0 Series OS MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System - Translator 78K/0 Series Fuzzy Inference Development Suport System - Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System - Fuzzy Inference Debugger EEU-921 EEU-1458 EEU-858 EEU-1441 Fundamental Japanese U11537J U11536J U12257J EEU-829 EEU-862 English -- -- -- EEU-1438 EEU-1444 Other Documents Document No. Document Name IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Device Guide for Products Related to MicroComputer: Other Companies Japanese C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J C10535E C11531E C10983E -- C11893E -- English Caution The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 65 PD78062(A), 78063(A), 78064(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 66 PD78062(A), 78063(A), 78064(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 67 PD78062(A), 78063(A), 78064(A) FIP is a registered trademark of NEC Corporation. IEBus is a trademark of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM-DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. Some of related document may be preliminary, but is not marked as such. Please keep this in mind as you refer to this information. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 |
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