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W27E040 512K x 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27E040 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 524288 x 8 bits that operates on a single 5 volt power supply. The W27E040 provides an electrical chip erase function.
FEATURES
* High speed access time: * * * *
90/120 nS (max.) Read operating current: 15 mA (typ.) Erase/Programming operating current 15 mA (typ.) Standby current: 5 A (typ.) Single 5V power supply
* +14V erase/+12V programming voltage * Fully static operation * All inputs and outputs directly TTL/CMOS
compatible
* Three-state outputs * Available packages: 32-pin 600 mil DIP,
450 mil SOP, PLCC and TSOP
PIN CONFIGURATIONS
V PP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27
BLOCK DIAGRAM
V CC A18 A17 A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3
CE OE
CONTROL
OUTPUT BUFFER
Q0 . . Q7
32-pin DIP
26 25 24 23 22 21 20 19 18 17
A0 . . A18 VCC GND VPP
DECODER
CORE ARRAY
A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 Q0 5 6 7 8 9 10 11 12 13
A 1 5 3
A 1 6 2
VV PC PC
A 1 8
A 1 7
1 32 31 30 29 28 27 A14 A13 A8 A9 A11 OE A10 CE Q7
32-pin PLCC
26 25 24 23 22 21
PIN DESCRIPTION
SYMBOL A0-A18 Q0-Q7
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program/Erase Supply Voltage Power Supply Ground No Connection
14 15 16 17 18 19 20
Q 1
QGQ 2N3 D
Q 4
Q 5
Q 6
A11 A9 A8 A13 A14 A17 A18 VCC VPP A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3
CE OE VPP VCC GND NC
32-pin TSOP
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Publication Release Date: June 2000 Revision A2
W27E040
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27E040 has two control functions, both of which produce data at the outputs. OE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE , if TACC and TCE timings are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27E040 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE = VIL, (0.8V or below but higher than GND), OE = VIH (2V or above but lower than VCC), A9 = VHH (14V), A0 = VIL, and all other address pins equal VIL and data input pins equal VIH.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE = VIH, and OE = VIL.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V), VCC = VCP (5V), CE = VIL, OE = VIH, the address pins equal the desired address, and the input pins equal the desired inputs.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE = VIH, OE = VIL and VCC = VCP (5V).
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE = VIH, VPP = VPP/VPE (12V/14V), and VCC = 5V, erasing or programming of nontarget chips is inhibited, so that except for the CE and VPP, and VCC, the W27E040 may have common inputs.
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W27E040
Standby Mode
The standby mode significantly reduces VCC current. This mode is entered when CE = VIH, VPP = 5V, and VCC = 5V. In standby mode, all outputs are in a high impedance state, independent of OE .
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27E040 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
TABLE OF OPERATING MODES
(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X = VIH or VIL)
MODE
CE OE
PINS A0 X X X X X X X VIL X X VIL VIH A9 X X X X X X X VPE X X VHH VHH VCC VCC VCC VCC VCC VCP VCP VCP VCE VCE VCE VCC VCC VPP VCC VCC VCC VCC VPP VPP VPP VPE VPE VPE VCC VCC OUTPUTS DOUT High Z High Z High Z DIN DOUT High Z DIH DOUT High Z DA (Hex) 86 (Hex)
Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Erase Erase Verify Erase Inhibit Product Identifier-manufacturer Product Identifier-device
VIL VIL VIH VCC 0.3V VIL VIH VIH VIL VIH VIH VIL VIL
VIL VIH X X VIH VIL X VIH VIL X VIL VIL
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Publication Release Date: June 2000 Revision A2
W27E040
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Ambient Temperature with Power Applied Storage Temperature Voltage on all pins with Respect to Ground Except VPP, A9 and VCC pins Voltage on VPP Pin with Respect to Ground Voltage on A9 Pin with Respect to Ground Voltage on VCC Pin with Respect to Ground RATING -55 to +125 -65 to +125 -0.5 to VCC +0.5 -0.5 to +14.5 -0.5 to +14.5 -0.5 to +7 UNIT C C V V V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC Erase Characteristics
(TA = 25 C 5 C, VCC = 5.0V 10%, VHH = 14V)
PARAMETER
SYM.
CONDITIONS MIN.
LIMITS TYP. 14 14 5.0 MAX. 10 30 30 0.8 5.5 0.45 14.25 14.25 5.5
UNIT A mA mA V V V V V V
Input Load Current VCC Erase Current VPP Erase Current Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Erase Voltage VPP Erase Voltage VCC Supply Voltage (Erase)
ILI ICP IPP VIL VIH VOL VOH VID VPE VCE
VIN = VIL or VIH CE = VIL CE = VIL IOL = 2.1 mA IOH = -0.4 mA -
-10 -0.3 2.4 2.4 13.75 13.75 4.5
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
CAPACITANCE
(VCC = 5V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Output Capacitance
SYMBOL CIN COUT
CONDITIONS VIN = 0V VOUT = 0V
MAX. 6 12
UNIT pF pF
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W27E040
AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0 to 3.0V 5 nS 1.5V/1.5V CL = 30 pF, IOH/IOL = -0.4 mA/2.1 mA
AC Test Load and Waveform
+1.3V (IN914)
3.3K ohm
DOUT
100 pF (Including Jig and Scope)
Input
Test Point 3.0V
1.5V
Output
Test Point
1.5V
0V
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Publication Release Date: June 2000 Revision A2
W27E040
READ OPERATION DC CHARACTERISTICS
(VCC = 5.0V 10%, TA = 0 to 70 C)
PARAMETER
SYM.
CONDITIONS MIN.
LIMITS TYP. 5 MAX. 5 10 1.0 100 30
UNIT A A mA A mA
Input Load Current Output Leakage Current VCC Standby Current
ILI ILO ISB ISB1
VIN = 0V to VCC VOUT = 0V to VCC CE = VIH CE = VCC 0.2V CE = VIL IOUT = 0 mA f = 5 MHz VPP = VCC IOL = 2.1 mA IOH = -0.4 mA -
-5 -10 -
VCC Operating Current
ICC
VPP Operating Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Operating Voltage
IPP VIL VIH VOL VOH VPP
-0.3 2.0 2.4 VCC -0.7
-
10 0.8 VCC +0.5 0.4 VCC
A V V V V V
READ OPERATION AC CHARACTERISTICS
(VCC = 5.0V 10%, TA = 0 to 70 C)
PARAMETER
SYM.
W27E040-90 MIN. MAX. 90 90 40 30 -
W27E040-12 MIN. 120 0 MAX. 120 120 55 30 -
UNIT
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time OE High to High-Z Output Output Hold from Address Change
TRC TCE TACC TOE TDF TOH
90 0
nS nS nS nS nS nS
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
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W27E040
DC PROGRAMMING CHARACTERISTICS
(VCC = 5.0V 10%, TA = 25 C 5 C)
PARAMETER Input Load Current VCC Program Current VPP Program Current Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Silicon I.D. Voltage VPP Program Voltage VCC Supply Voltage (Program)
SYM. ILI ICP IPP VIL VIH VOL VOH VID VPP VCP
CONDITIONS MIN. VIN = VIL or VIH CE = VIL CE = VIL IOL = 2.1 mA IOH = -0.4 mA -10 -0.3 2.4 2.4 11.5 11.75 4.5
LIMITS TYP. 12.0 12.0 5.0 MAX. 10 30 30 0.8 5.5 0.45 12.5 12.25 5.5
UNIT A mA mA V V V V V V V
AC PROGRAMMING/ERASE CHARACTERISTICS
(VCC = 5.0V 10%, TA = 25 C 5 C)
PARAMETER VPP Setup Time Address Setup Time Data Setup Time CE Program Pulse Width CE Erase Pulse Width Data Hold Time OE Setup Time Data Valid from OE OE High to Output High Z Address Hold Time Address Hold Time after CE High (Erase)
SYM. MIN. TVPS TAS TDS TPWP TPWE TDH TOES TOEV TDFP TAH TAHC 2.0 2.0 2.0 95 95 2.0 2.0 0 0 2.0
LIMITS TYP. 100 100 MAX. 105 105 150 130 -
UNIT S S S S mS S S nS nS S S
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
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Publication Release Date: June 2000 Revision A2
W27E040
TIMING WAVEFORMS
AC Read Waveform
VIH Address VIL VIH CE VIL Address Valid
TCE
VIH OE VIL TACC Outputs High Z TOE TOH Valid Output High Z TDF
Erase Waveform
Read Manufacturer
Read Device Chip Erase A9 = 14.0V Erase Verify Blank Check Read Verify
SID SID A9 = 12.0V A0= VIH Others = V IL A0 = VIL Others = VIL VIL TACC DA TACC 86
VIH Address
Others = VIL Address Stable TAS TARC Data All One TDS TAHC TDFP DOUT TAH 5V TVPS DOUT Address Stable Address Stable TACC DOUT
Data
14.0V 5.0V VPP VIH CE VIL TOE VIH OE VIL TOEV T OE TPWE TOES TOE TCE
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W27E040
Timing Waveforms, continued
Programming Waveform
Program VIH Address VIL TAS Address Stable
Program Verify Address Stable TDFP
Read Verify Address Valid
TACC DOUT DOUT
Data
Data In Stable
DOUT
TDS 12.0V VPP 5.0V VIH CE VIL VIH OE VIL TPWP
TDH
TAH
5V TVPS
TOE TOES
TOEV
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Publication Release Date: June 2000 Revision A2
W27E040
SMART PROGRAMMING ALGORITHM
Start
Address = First Location
Vcc = 5V Vpp = 12V
X=0
Program One 100 S Pulse
Increment X Yes X = 25? No Fail
Verify One Byte
Fail
Verify One Byte
Pass Increment Address No Last Address? Yes
Pass
*Program whole chip without data verification and read
Vcc = 5V Vpp = 5V
Compare All Bytes to Original Data
Pass Pass Device
Fail
Fail Device
*: Program the whole chip again without data verification and read.
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W27E040
SMART ERASE ALGORITHM
Start
X=0
Vcc = 5V Vpp = 14V
A9 = 14V; A0 = V IL Chip Erase 100 mS Pulse
Address = First Location
Increment X No Erase Verify Pass Yes Increment Address No Last Address? Yes Vcc = 5V Vpp = 5V Fail X = 20?
Compare All Bytes to FFs (HEX) Pass Pass Device
Fail
Fail Device
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Publication Release Date: June 2000 Revision A2
W27E040
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 90 120 90 120 90 120 90 120 POWER SUPPLY CURRENT MAX. (mA) 30 30 30 30 30 30 30 30 STANDBY VCC CURRENT MAX. (A) 100 100 100 100 100 100 100 100 PACKAGE
W27E040-90 W27E040-12 W27E040S-90 W27E040S-12 W27E040P-90 W27E040P-12 W27E040T-90 W27E040T-12
Notes:
600 mil DIP 600 mil DIP 450 mil SOP 450 mil SOP 32-pin PLCC 32-pin PLCC Type One TSOP Type One TSOP
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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W27E040
PACKAGE DIMENSIONS
32-pin P-DIP
Symbol
Dimension in inches
Dimension in mm
Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.155 0.160 0.018 0.050 0.022 0.054 0.014 1.660 0.610 0.555 0.110 0.140 15
Min. Nom. Max.
5.33 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 4.06 0.56 1.37 0.36
D
32 17
E1
A A1 A2 B B1 c D E E1 e1 L
a
0.008 0.010 1.650 0.590 0.545 0.090 0.120 0 0.630 0.650 0.600 0.550 0.100 0.130
41.91 42.16 14.99 15.24 13.84 2.29 3.05 0 16.51 15.49
13.97 14.10 2.54 3.30 2.79 3.56 15 17.02 2.16
1
16
eA S Notes:
E c
0.670 16.00 0.085
S
A A2 L B B1
A1
Base Plane Seating Plane
e1
a
eA
1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches 6. General appearance spec. should be based on final visual inspection spec.
32-Lead SO Wide Body
Symbol
17
Dimension In Inches
Dimension In mm
Min. Nom. Max.
0.118 0.004 0.101 0.014 0.006 0.106 0.016 0.008 0.805 0.440 0.044 0.546 0.023 0.047 0.445 0.050 0.556 0.031 0.055 0.111 0.020 0.012 0.817 0.450 0.056 0.556 0.039 0.063 0.036 0.004 0 10
Min. Nom. Max.
3.00 0.10 2.57 0.36 0.15 2.69 0.41 0.20 20.45 11.18 1.12 13.87 0.58 1.19 11.30 1.27 14.12 0.79 1.40 2.82 0.51 0.31 20.75 11.43 1.42 14.38 0.99 1.60 0.91 0.10 0 10
32
e1
E HE
L
Detail F
1
b
16
e1 c A2 S y e A
A A1 A2 b c D E e HE L LE S y
Notes:
D
A1
LE
See Detail F
Seating Plane
1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec.
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Publication Release Date: June 2000 Revision A2
W27E040
Package Dimensions, continued
32-Lead PLCC
HE E 4 1 32 30
Dimension In Inches
Dimension In mm
Symbol
5 29
Min. Nom. Max.
0.140 0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.51 0 0.410 0.590 0.49 0 0.090 0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004 0 10
Min. Nom. Max.
3.56 0.50 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.9 5 10.41 14.99 12.45 2.29 2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10 0 10
GD D HD
13
21
14
20
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
L A2 A
e
Seating Plane
GE
b b1
A1 y
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on fina visual inspection sepc.
32-Lead TSOP
HD
Symbol Min. Nom.
Dimension In Inches Max. 0.047
Dimension In mm Min. Nom. Max. 1.20 0.15 1.05 0.23 0.17 18.50 8.10
D c
A A1 A2
__
0.002 0.037
__ __
0.006
__
0.05 0.95 0.17 0.12
__ __
1.00 0.20 0.15
0.039 0.041 0.009 0.007
M
e E
b c D E HD e L L1
A A2
0.007 0.008 0.005 0.006 0.720 0.724 0.311 0.315 0.780
0.10(0.004)
0.728 18.30 18.40 0.319 7.90 8.00
b
0.787 0.795 19.80 20.00 20.20 0.020
__
__
0.024 __ 0.004 5
__
0.40
0.50 0.50 0.80
__
0.60
0.016 0.020
__
0.000 1
0.031
__
0.00 1
__
0.10 5
Y Y
__
3
__
3
L L1
A1
Note:
Controlling dimension: Millimeters
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W27E040
VERSION HISTORY
VERSION A1 A2 DATE May 1997 June 2000 PAGE 5 Initial Issued Modify Input Pulse Levels in AC Test Conditions DESCRIPTION
Headquarters
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886 -2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change withou t notice.
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Publication Release Date: June 2000 Revision A2

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