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L6285
3 CHANNELS MULTIPOWER SYSTEM
ADVANCE DATA
CHANNEL-A AND CHANNEL-B FOR UNIPOLAR STEPPER MOTORS - LOW SIDE: RDSON = 1.2 - HIGH SIDE ; R DSON = 1.2 CHANNEL-C FOR DC MOTORS - LOW SIDE: RDSON = 1.7 - HIGH SIDE: RDSON = 1.2 CHOPPING MODE DRIVING FOR C.L. CURRENT CONTROL ON CHA AND CHB AND O.L. VOLTAGE CONTROL ON CHC. INTERNAL FOUR DRIVING LATCHES 16 BIT INTERNAL SHIFT REGISTER DIRECT INTERFACE TO P SERIAL DRIVING SEQUENCE LOADING CMOS COMPATIBLE INPUTS PRE-ALARM OUTPUT SIGNAL THERMAL SHUTDOWN DESCRIPTION This Combo Motor Driver uses large scale integration to incorporate several functions into the same chip. 1) Two unipolar stepper motor driver 2) A full bridge DC motor driver BLOCK DIAGRAM
MULTIPOWER BCD TECHNOLOGY
PLCC44
SDIP42
ORDERING NUMBERS: L6285 L6285S
3) Serial microprocesor interface The power output stages are DMOS and the input can be interfaced to a CMOS Microprocessor logic. The phase current in the unipolar stepper motor windings is controlled by two external sensing resistors in fixed frequency chopping mode. The oscillator block provides clocks each other 180 out of phase to the two stepper motor driver in order to avoid symultaneous current peaks. For the DC motor driver is used a bridge; the RMS voltage to supply this motor is fixed by a
May 1994
1/16
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6285
simple PWM open loop. The 3 motors are controlled by the micro through 4 latches of 4 bit each. The loading of these registers is in serial mode. The I.C. operates at 5V supply for the logic and at PIN CONNECTION (Top view)
COM3,4A COM1,2A COM1,2B COM3,4B PWGND PWGND OUT2C OUT1C
OUT2C COM1,2A VP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
D94IN060A
24V supply for the power stages. The packages are SDIP42 and PLCC44 with 6 pins devoted to ground and to sink out the heat produced by power dissipation.
S1,2C
42 41 40 39 38 37 36 35 34
S1,2C OUT1C COM1,2B VP COM3,4B PWGND OUT1B S1,2B OUT2B CLAMPB OUT3B S3,4B OUT4B VLOW COSC GND V2 OSC RESET A1TH A0TH VS
VP
6 PWGND OUT1A S1,2A OUT2A CLAMPA OUT3A S3,4A OUT4A BOOT1 BOOT3 GND 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 PWGND OUT1B S1,2B OUT2B CLAMPB OUT3B S3,4B OUT4B VLOW COSC GND
VP
COM3,4A N.C. PWGND OUT1A S1,2A OUT2A CLAMPA OUT3A S3,4A OUT4A BOOT1 BOOT3 GND N.C.
PLCC44
SDIP42
33 32 31 30 29 28 27 26 25 24 23 22
34 33 32 31 30 29
18 19 20 21 22 23 24 25 26 27 28 VS SID STB N.C. SCK N.C. A0TH A1TH OSC RESET BOOT2 V2
D94IN067
BOOT2 SID SCK STB
ABSOLUTE MAXIMUM RATINGS
Symbol VP VS Vin ILOW IHIGH IpLOW IpHIGH Vbou t Vsense 1;2 Vsense 3 fdDC fdpk Ptot Top Tstg Power Supply Voltage Logic Supply Voltage Logic Input Voltage Low Side DMOS max DC Current High Side DMOS max DC Current Low Side DMOS max Peak Current (1s On; 50s OFF) High Side DMOS max Peak Current (1s On; 50s OFF) Max Output Voltage of Stepper Motor Driver (transient rcirculation) Max Voltage ON Vsense (CHA/CHB) Max Voltage ON Vsense (CHC) Max DC Current of Forward Diode (DMOS Source Drain Diode) Max Peak Current of Forward Diode (DMOS Source Drain Diode) (1s On; 50s OFF) Total Power Dissipation (Tpins = 90C) With minimized dissipating copper area (Tamb = 70C) Operating Temperature Range Storage Temperature Range Parameter Value 30 7 -0.3 to VS + 0.3 1 1 2 2 60 -1 to 2 -1 to 2 1 2 5 1.6 0 to 150 -40 to 150 Unit V V V A A A A V V V A A W W C C
THERMAL DATA (PLCC44)
Symbol R th j-pins R th j-amb 2/16 Description Thermal Resistance Junction-pins Thermal Resistance Junction-ambient Max. Max. SDIP42 15 48 PLCC44 12 50 Unit C/W C/W
L6285
PIN DESCRIPTION
SDIP42 No 42 1,41 2 3,39 4 6,37 7,9, 11,14 8 PLCC44 No 1 2,44 3 4,42 5 6,7,39,40 8,10 12,14 9 Name S1,2C OUT 1C, OUT 2C COM 1,2A Vp COM 3,4A GND OUT 1A, OUT 2A OUT 3A, OUT 4A S1,2A Functions Full bridge common source output to separate between power GND and logic GND. Output of the channel C bridge. High side DMOS channel A for current chopping in the windings connected pins to OUT 1A, OUT 2A. Power Supply Voltage. High side DMOS channel A for current chopping in the windings connected to pins OUT 3A, OUT 4A. PowerGround and heatsink pins. Low side DMOS outputs of channel A stepper motor driver. Channel A sources of the DMOS OUT 1A, OUT 2A. A sensing resistor has to be connected from this pin and ground, for current control of phase 1,2 A. These pins have to be connected to an external zener diode to clamp the output voltage spikes of channel A/B. Channel A sources of the DMOS OUT 3A, OUT 4A. A sensing resistor has to be connected from this pin and ground, for current control of phase 3,4 A. A capacitor between this pin and Vp stores the overvoltage for each high side DMOS driver gate. A capacitor between this pin and internal diodes allows the change pump to transfer energy to the capacitor at the pin BOOT 1. Logic Ground and Heatsink pins. Charge pump oscillator output. Serial data input. Serial clock for serial data input. Strobe to transfer the 16 bit shift register contents to the latch registers. Not connected. Logic Supply Voltage. Open collector outputs for thermal informations to the P. An RC network connected to this pin defines the oscillator frequency for stepper drivers. When OSC/RES is <1V, a reset signal is internally generated. A voltage to this pin defines the output duty cycle of Channel C. A capacitor connected to this pin defines the chopping frequency of channel C. This pin is low when the chopping low voltage (V2 low level) is selected; it is in high impedance when the chopping high voltage (V2 high level) is selected. Only for CHC operation. Low side DMOS outputs of channel B stepper motor driver. Same as S 3, 4A, but for channel B. Same as S 1, 2A, but for channel B. Same as COM 3, 4A, but for channel B. Same as COM 1, 2A, but for channel B.
10,33 12
11,35 13
CLAMP A, CLAMP B S3,4A
14 15 16,27 18 19 20 21 5,17 22,39 23,24 25
15 16 17,29 18 19 20 21 22,24 23 25,26 27
BOOT 1 BOOT 3 GND BOOT 2 SID SCK STB NC Vs A0TH / A1TH OSC/ RESET
26 28 29
28 30 31
V2 Cosc Vlow
30,32, 34,36 31 35 38 40
32,34 36,38 33 37 41 43
OUT4B, OUT3B OUT2B ,OUT1B S 3, 4B S 1, 2B COM 3, 4B COM 1, 2B
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L6285
ELECTRICAL CHARACTERISTICS (Tj = 25 C, Vs = 5V, Vp = 24V unless othewise specified)
Symbol Vp Ip Vs Is Parameter Power Supply Voltage Quiescent Power Supply Current Logic Supply Voltage Quiescent Logic Supply Current (note 1) (note 1) 4.5 Test Conditions Min. 9 Typ. Max. 26.5 7 5.5 20 Unit V mA V mA
LOGIC LEVEL
Symbol VinL VinH IinL IinH Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current Vin = VinL Vin = VinH Test Conditions Min. -0.3 3.15 -10 10 Typ. Max. 1.35 VS+0.3 Unit V V A A
CHANNEL A AND CHANNEL B (UNIPOLAR MOTORS)
Symbol RDSONL R DSONH IDSSL IDSSH VREF Parameter Low Side DMOS ON Res. High Side DMOS ON Res. Low Side DMOS Leakage Current High Side DMOS Leakage Current Voltage reference to the Comparator Test Conditions IDS = 0.7A IDS = 0.7A VDS = 60V; output OFF VP = 30V; VO= 0V LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4 -1.5 100 220 340 465 125 250 375 500 150 280 410 535 1 Min. Typ. Max. 1.2 1.2 2 Unit mA mA mV mV mV mV s
Td
Turn OFF Delay on HIGH Side DMOS after the Sensing Current Reach the Threshold Value Max Chopping Frequency
(note 2)
fmax
40
KHz
CHANNEL C (DC MOTORS) (see Fig. 5)
Symbol fosc DC Ib2 Vlow R DSONH RDSONL ILH ILL Vfddc fmax Vboot IL bo ot 4/16 Parameter Oscillator Frequency Duty Cycle Comparator Input Bias Open Drain Output High Side DMOS ON Res. Low Side DMOS ON Res. HSD MOS Leakage Current LSD MOS Leakage Current Forward Diode DC Voltage (DMOS Diode) Max Chopping Frequency Voltage on pin Boot1 Leakage Current on pin Boot1 Vbo tt = Vp +12V; Vp = 26.5V Vp +7 200 Test Conditions Cosc = 3.3nF; V1 = 2/3VS V2 = 1/2VS V2 = 200mV I = 5mA IDS = 0.7A IDS = 0.7A VP = 30V; VO = 0V VO = 30V; Vsense = 0V Ifdcc = 0.7A -1 -1.5 1.4 2 40 Min. 17 72 -1 0.2 0.4 1.2 1.7 Typ. 22 75 Max. 28 81 Unit KHz % A V mA mA V KHz V A
L6285
ELECTRICAL CHARACTERISTICS (continued) OSCILLATOR (see Fig. 6)
Symbol fosc Tdsc Vreset Parameter Oscillator Frequency Pin OSC/RESET Capacitor Discharge Time (protect dead time) Reset Threshold Voltage Test Conditions COSC = 3.3nF; ROSC = 10K COSC = 3.3nF; ROSC = 10K (see Fig. 1) Min. 27 0.8 1 Typ. 41 1.4 Max. 46 2 Unit KHz s V
INTERFACE TIMING
Symbol t1 t2 t3 t4 t5 Parameter SCK Data Clock Cycle SCK Data Set-upTime SCK Data Hold Time SCK-STB Interval Time STB Pulse Width Test Conditions (see Fig. 2) Min. 200 30 20 30 100 Typ. Max. Unit ns ns ns ns ns
Note 1: No output loaded; all register to low condition; no reset applied; V P = 26.5V; V S = 5.5V Note 2: The effect of the internal filter (RC Network) is not considered.
Figure 1: Discharge time tdsc or Protection Time
Figure 2: Interface Timing (Serial loading Mode)
Serial Input Data
b15 D15 D3
b14
b13
b12 D0
b11 D3
b10
b9
b8 D0
b7 D3
b6
b5
b4 D0
b3 D3
b2
b1
D2 D1 Register 4
D2 D1 Register 3
D2 D1 Register 2
D2 D1 Register 1
b0 D0 D0
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L6285
BLOCK DIAGRAM DESCRIPTION (see Block Diagram) Inside the I.C. there are two unipolar stepper motor drivers, one bridge driver for DC motor, 4x4 bit latch registers, one shift register. the input logic, the charge pump, and the thermal protection. The following conditions are valid for all the 3 driver sections: 1)When the osc/res pin is tied to GND, an internal reset signal is generated which switches off all the outputs and resets the internal registers. 2)The conditions 1 is valid also during power on and power off transitions. 3)During power on and power off, the I.C. is safe for any conditions of V S and Vp 3)If Vp is present and VS desappears, the outputs are switched off. Input Logic The input CMOS logic interfaces the microprocessor logic to the 4 registers. An integrated Schmitttrigger circuit is used to improve noise immunity at each logic input. The data is introduced in the 16bit shift register by the SID pin. The first bit b 15 after 16 clock applied to SCK pin will be the D15 of the shift register. On the falling edge of STB the 16 bits of the shift register are transferred to the outputs of the 4 latch registers. Fig 2 shows the timing. CHA and CHB Stepper Motor Drivers
Registers The Combo Motor Driver controls the 3 channels using 4 latch registers of 4 bit each:
REGISTER 1 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 = = = = = = = = = = = = = = = = PHASE 1A NPHASE 2A PHASE 3A NPHASE 4A PHASE 1B NPHASE2B PHASE 3B NPHASE4B D/A D/A D/A D/A CHANNEL CHANNEL CHANNEL CHANNEL A A B B CHANNEL A CHANNEL A CHANNEL A CHANNEL A CHANNEL B CHANNEL B CHANNEL B CHANNEL B LEAST MOST LEAST MOST CHANNEL C CHANNEL C CHANNEL C CHANNEL C
REGISTER 2
REGISTER 3
REGISTER 4
INPUT 1 INPUT 2 V2 VOLTAGE V2 VOLTAGE
Register 1/2 Output Status (CHA and CHB) . See note 1
D0 0 1 1 0 0 0 0 0 1 D1 D2 D3 0 0 0 0 0 0 1 1 1 OUT1 A/B OFF ON ON OFF OFF OFF OFF OFF ON OFF OUT2 A/B OFF OFF OFF OFF ON ON ON OFF OFF OFF OUT3 A/B OFF OFF ON ON ON OFF OFF OFF OFF OFF OUT4 A/B OFF OFF OFF OFF OFF OFF ON ON ON OFF
0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 0 0 0 ALL THE OTHERS
Register 3 Current Reference (D/A OUTPUT)
DO 0 0 1 1 6/16 D1 0 1 0 1 REFER. VOLTAGE CHANNEL A 0.125 0.250 0.375 0.500 V V V V D2 0 0 1 1 D3 0 1 0 1 REFER. VOLTAGE CHANNEL B 0.125 0.250 0.375 0.500 V V V V
L6285
REGISTER 4 (CHC). See note 2
D0 X 0 1 0 1 1 0 1 0 0 1 0 1 D1 X 0 0 1 1 0 1 0 1 0 1 0 1 D2 0 1 1 1 1 1 1 0 0 1 1 0 0 D3 0 1 1 1 1 0 0 1 1 0 0 1 1 OUT1 C OFF OFF VP GND GND VP CHOPPING; V2 LOW LEVEL VP CHOPPING; V2 HIGH LEVEL OFF VP OFF VP OUT2 C OFF OFF GND VP GND CHOPPING; V2 LOW LEVEL VP CHOPPING; V2 HIGH LEVEL VP OFF VP OFF VP
Note 1: Low side DMOS status (DM1/2 in Fig. 4) Note 2: Bridge status (see Fig. 3): OFF = tristate; V P =, DM3/4ON; GND = DM1/2 ON
Figure 3: CHC Chopping Characteristics
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L6285
These two channels drive two unipolar stepper motors in chopping mode. The basic channel configuration is shown in Fig 4. by considering well known the PWM Current Control Loop behaviour here below only particular trick are underlined. During DM3 off period the low side DMOS DM1 and DM2 are switched on to reduce the power dissipation. Figure.4: Unipolar motor driver CHA (or CHB) The drain overvoltages generated because of the stray inductance of the motor windings are limited by connecting the DZ1 external zener diode to the clamp pin.. The diodes CL1 and CL2 are integrated as far as the CL3 diode which limits the negative voltage at pin COM1.2. An internal RC network (1s) is realized to filter the sensing resistor signal.
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L6285
CHC DC Motor Driver The DC motor driver is a DMOS full bridge with a PWM Open Loop Voltage Control. Fig.5 shows the theory of operation. The Cosc Capacitor is charged by a constant current source. The oscillating voltage value is from 0V to the V1 level internally fixed at V1 = 2/3 VS. The output duty cyFigure.5: DC Motor Driver CHC cle is controlled by the V2 voltage. The operational range of V2 is from 200mV to V1. Fig.3 shows the DMOS status during PWM: tON and tOFF bridge configurations. While the PWM Duty Cycle defines the motor speed (not controlled since the loop is open),the logic level of IN1 and IN2 can choose the direction of the motor.
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L6285
Oscillator For Clock and Reset Generation The oscillator block provides for two functions: 1)Generate an internal reset signal when the voltage at pin osc/res is below 1V. The reset signal switches off all the outputs and resets the logic registers. 2)Generate, when the pin osc/res is left free two syncro signals p1 and p2 for the clock of the PWM Current Control of the two stepper driver blocks The oscillator operates like the 555 concept in Figure 6: Oscillator Concept which the capacitor voltage oscillates between 1/3VS 2/3VS (Fig. 6). The oscillator frequency is 2 times the chopping frequency in order to generate the two syncro signals at operative 20KHz PWM. The tCH = charge time of Cosc is defined by Rosc, VTH1 and VTH2 ( threshold voltages)and Cosc. The discharge time Tdsc is practically only defined by Cosc and the internal discarge resistor Rdsc. The tdsc is also the time lockout during which the RS FF cannot read the Comparator output (see Fig. 4)
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L6285
Charge Pump The charge pump circuitry generates the overvoltage needed to drive the gate of the high side output DMOS power transistors.It is realized by using two external capacitors (C1 and C2) and two integrated diodes that operate as a full wave rectiFigure 7: Charge Pump Circuit fier (see Fig. 7). The oscillator peak to peak output voltage is stored by C2 and summed to the Power Supply Voltage Vp.. The voltage present at the pin BOOT1, is then the overvoltage needed to supply the gate of the high side DMOS drivers.
THERMAL PROTECTION The thermal protection shuts down the chip beA0TH 0 1 1 0 A1TH 0 0 1 1
fore it can reach a dangerous temperature. Additional informations to the microprocessor are available at the A0TH, A1TH pins.
CIRCUIT STATUS OPERATING OPERATING THERMAL SHUTDOWN
THERMAL PROTECTION OK PREALARM ALARM NOT POSSIBLE
APPLICATION INFORMATION A typical application circuit is shown in Fig.8. By this application it is possible to drive two unipolar stepper motors (M1,M2) and one DC motor (M3). As it can be seen, only two external Zener diodes (D1,D2) are needed to clamp the voltage transients generated by the stray inductance of the motor windings. This is recommended when the peak current is not more than three to four hundred mAmps. For a power supply voltage of VP=24V 10%, D1=D2 must be 30V 5%-1W (1N4751A or equivalent). Both the VP and the VS pins need bypass capacitors (C1,C2,C3); to supply the high-side DMOS (Source Transistors) at pin.15 ,only two external capacitors (C4,C5) complete the charge pump circuitry. The oscillator frequency, that is twice the chopping frequency for M1 and M2, is mainly defined by the network R6C6: fosc = [0.69 (Rch + Rdsc) Cosc ]-1 , where Rch = R6 ; R dsc = 600 ohm typ.
At the same time, the lockout duration (or protection window) needed for a correct chopping behavior, is given by : Tlockout = 0.69 Rdsc Cosc The shown values (fig.8) give a nominal frequency a little bit more than 41KHz and a protection window of 1.4 s roughly. The Schottky diode D3 and the pull-up resistor R5 driven via an opencollector transistor can generate the Reset function. The chopping current is sensed across R1 A/B; R2 A/B that must be of a not inductive type. The DC motor PWM Open Loop Voltage Control operates at a frequency defined by C7, charged with a typical constant current source (I = 240 A), up to V1 = 0.67 VS. Since the discharge time is very short, it can be written : fosc = I / Cosc V1, where Cosc = C7. Tha values indicated in figure give a typical frequency of about 22 KHz.
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L6285
Figure 8: Typical Application Circuit
The duty cycle DC can be chosen between two possibilities (High and Low ) than can be defined externally by the resistors R7, R8 and R9: Fig.5 let well understand how to calculate the dividers that fix V2 H (wider ton ) and V2 L (wider toff ). It may be needed to drive stepper motors that require a higher peak current than told above. In this case each motor phase requires a particular application arrangement (see Fig.9b). In Fig.9a all Figure 9a: Output Configuration as it is obtained by the Application Circuit
the protection components are integrated with the exception of Z1. In Fig.9b the clamp of the voltage spikes generated by the stray inductance Ls is achieved using Transil protection T1 and T2 that works also as additional diodes during current recirculation at the phase change. The diode D1, externally connected, is recommended at the highest working current levels and/or when the supplied voltage (plus Back EMF) at the end of the motor winding is too much unbalanced. Figure 9b: Output Configuration at Higher Operating Currents
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L6285
THERMAL CHARACTERISTICS The cooling of the device is obtained by soldering its ground pins on a proper p.c.b copper side , acting as a true heatsink. By considering four squared side as in Fig.10, the junction to ambient Figure 10: Four "on board" Square Heatsink thermal resistance has been measured (see Fig.11). The typical transient thermal resistance versus values of single pulse width of power is shown in Fig.12. In general these thermal characteristics are very important to the designer to optimize the L6285 applications.
Figure 11: Typical Rth j-amb vs. lenght "l" (Fig. 10)
Figure 12: Typical Transient Thermal Resistance vs. Time or Pulse Width
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L6285
SDIP42 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B B1 c D E E1 e e1 e2 e3 L 2.54 3.30 0.51 3.05 0.36 0.76 0.23 37.85 15.24 12.70 13.72 1.778 15.24 18.54 1.52 3.56 0.10 0.130 3.81 0.46 1.02 0.25 38.10 4.57 0.56 1.14 0.38 38.35 16.00 14.48 mm TYP. MAX. 5.08 0.020 0.120 0.0142 0.030 0.0090 1.490 0.60 0.50 0.540 0.070 `0.60 0.730 0.060 0.140 0.150 0.0181 0.040 0.0098 1.50 0.180 0.0220 0.045 0.0150 1.510 0.629 0.570 MIN. inch TYP. MAX. 0.20
E E1
A1
A2
B
B1
e
L
A
e1 e2
D c E 42 22
F
.015 0,38 Gage Plane
1
21
SDIP42
e3 e2
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L6285
PLCC44 PACKAGE MECHANICAL DATA
DIM. MIN. A B C D d1 d2 E e e3 F F1 G M M1 1.16 1.14 14.99 1.27 12.7 0.46 0.71 0.101 0.046 0.045 17.4 16.51 3.65 4.2 2.59 0.68 16 0.590 0.050 0.500 0.018 0.028 0.004 mm TYP. MAX. 17.65 16.65 3.7 4.57 2.74 MIN. 0.685 0.650 0.144 0.165 0.102 0.027 0.630 inch TYP. MAX. 0.695 0.656 0.146 0.180 0.108
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L6285
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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