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19-2245; Rev 0; 10/01
KIT ATION EVALU ABLE AVAIL
Quad ECL/PECL Differential Buffers/Receivers
General Description Features
o Differential Double-Swing ECL/PECL Outputs o Input Compatible with LVECL/LVPECL o Guaranteed 900mV Differential Output at 3.0GHz Clock Rate o 365ps Propagation Delay in Asynchronous Mode o 10ps Channel-to-Channel Skew in Synchronous Mode o Integrated 100 Input Terminations (MAX9404) o Compatible +3.3V/+5.0V Nominal Supplies o Selectable Synchronous/Asynchronous Operation
MAX9401/MAX9404
The MAX9401/MAX9404 are extremely fast and lowskew quad ECL/PECL differential buffers/receivers for data and clock signals. The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. The MAX9401 has high-impedance (open) input and the MAX9404 has an integrated 100 differential input termination, which reduces external component count. Both devices have double amplitude swing open emitter outputs suitable for driving long cables. The MAX9401/MAX9404 operate over a VCC - VEE = +3.0V to +5.5V supply range, and are specified for operation from -40C to +85C. These devices are offered in space-saving 32-pin 5mm x 5mm QFN exposed-paddle (EP) and TQFP packages.
Ordering Information
PART TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 32 QFN-EP** (5mm x 5mm) 32 TQFP (5mm x 5mm) 32 QFN-EP** (5mm x 5mm) 32 TQFP (5mm x 5mm) INPUT IMPEDANCE Open Open 100 100
Applications
Data and Clock Driver and Buffer Central Office Backplane Clock Distribution DSLAM Backplane Base Station ATE
MAX9404EHJ MAX9404EGJ* MAX9401EGJ* MAX9401EHJ
Functional Diagram appears at end of data sheet.
*Future product--contact factory for availability. **EP = Exposed paddle
Pin Configurations
OUT0 OUT0 OUT0 VCC VEE IN0 IN0 IN1 IN1 VCC
TOP VIEW
OUT0
VEE
IN0
IN0
32
31
30
29
28
27
26
25
32
31
30
29
28
27
26
IN1
25 24 VCC 23 OUT1 22 OUT1 21 VEE
*
VCC SEL SEL CLK CLK EN EN VCC 1 2 3 4 5 6 7 8
*
24 23 22 VCC OUT1 OUT1 VEE VEE OUT2 OUT2 VCC VCC SEL SEL CLK CLK EN EN VCC 1 2 3 4 5 6 7 8 9 IN3 10 IN3 11 VCC 12 OUT3 13 OUT3 14 VEE 15 IN2 16 IN2
MAX9401/ MAX9404
21 20 19
MAX9401 MAX9404
IN1 20 VEE 19 OUT2 18 OUT2 17 VCC
*
18 17
*
10 11 12 13 14 15 IN3 VEE IN3 OUT3 OUT3 VCC IN2 IN2 16 9
*
QFN-EP*
*EXPOSED PAD AND CORNER PINS ARE CONNECTED TO VEE
TQFP
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Quad ECL/PECL Differential Buffers/Receivers MAX9401/MAX9404
ABSOLUTE MAXIMUM RATINGS
VCC to VEE .............................................................-0.3V to +6.0V All Other Pins to VEE ...................................-0.3V to (VCC + 0.3V) Differential Input Voltage....................................................3.0V Continuous Output Current .................................................70mA Surge Output Current..... ..................................................100mA Continuous Power Dissipation (TA = +70C) 32-Pin 5mm x 5mm TQFP (derate 9.5mW/C above +70C)..............................................................761mW 32-Pin 5mm x 5mm QFN-EP (derate 21.3mW/C above +70C)..................................................................1.7W Junction-to-Ambient Thermal Resistance in Still Air 32-Pin TQFP............................................................+105C/W 32-Pin QFN-EP.... .....................................................+47C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 32-Pin TQFP..............................................................+73C/W Junction-to-Case Thermal Resistance 32-Pin TQFP..............................................................+25C/W 32-Pin QFN-EP... ........................................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (Inputs and Outputs) .................>1.25kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +3.0V to +5.5V, outputs terminated with 50 1% to VCC - 3.3V, inputs are driven, unless otherwise noted. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25C, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS MIN VEE + 2.0 VEE 0.2 EN, EN, SEL, SEL, IN_, IN_, CLK, or CLK = VIHD or VILD EN, EN , SEL, SEL, CLK, or CLK = VIHD or VILD -10 -10 86 TYP MAX UNITS INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL) Differential Input High Voltage Differential Input Low Voltage Differential Input Voltage VIHD VILD VID Figure 3 Figure 3 Figure 3 MAX9401 Input Current IIH, IIL MAX9404 IN to IN Differential Input Resistance OUTPUTS (OUT_, OUT_) Differential Output Voltage Output Common-Mode Voltage POWER SUPPLY Supply Current IEE (Note 4) 84 118 mA VOH - VOL VOCM Figure 3 Figure 3 1.2 VCC 1.8 1.4 VCC 1.4 V V RIN MAX9404 VCC VCC 0.2 3.0 25 A 25 114 V V V
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Quad ECL/PECL Differential Buffers/Receivers
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +3.0V to +5.5V, outputs terminated with 50 1% to VCC - 3.3V, outputs are enabled, input transition time = 125ps (20% to 80%), fCLK = 3.0GHz, fIN = 1.5GHz, VIHD = VEE +2.0V to VCC, VILD = VEE to VCC - 0.2V, VIHD - VILD = 0.2 to 3.0V, unless otherwise noted. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25C, unless otherwise noted.) (Notes 1, 5)
PARAMETER IN to OUT Differential Propagation Delay CLK to OUT Differential Propagation Delay IN to OUT Channel-to-Channel Skew CLK to OUT Channel-toChannel Skew Maximum Clock Frequency Maximum Data Frequency Added Random Jitter (Note 7) SYMBOL tPLH1, tPHL1 tPLH2, tPHL2 tSKD1 tSKD2 fCLK(MAX) fIN(MAX) tRJ CONDITIONS SEL = high, Figure 4 SEL = low, Figure 5 SEL = high (Note 6) SEL = low (Note 6) VOH - VOL 900mV, SEL = low SEL = high, VOH - VOL 900mV SEL = low, fIN = 1.5GHz, fCLK = 3.0GHz, clock SEL = high, fIN = 1.5GHz Added Deterministic Jitter (Note 7) IN to CLK Setup Time CLK to IN Hold Time Output Rise Time Output Fall Time Propagation Delay Temperature Coefficient SEL = low, fCLK = 3.0GHz, IN_ = 1.5Gbps, 223-1 PRBS pattern tDJ SEL = high, IN_ = 1.5Gbps, 223-1 PRBS pattern Figure 5 Figure 5 Figure 4 Figure 4 80 80 116 115 145 145 1 3.0 1.5 1.4 0.9 20 36 2.5 2.7 30 psp-p 55 ps ps ps ps ps/C MIN 300 580 TYP 365 620 15 10 MAX 550 758 55 40 UNITS ps ps ps ps GHz GHz ps
(RMS)
MAX9401/MAX9404
tS tH tR tF tPD/T
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to VEE except VID and VOD. Note 3: DC parameters are production tested at TA = +25C. DC limits are guaranteed by design and characterization over the full operating range. Note 4: Outputs are open. Inputs driven high or low. Note 5: Guaranteed by design and characterization. Limits are set to 6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 7: Device jitter added to the input signal.
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Quad ECL/PECL Differential Buffers/Receivers MAX9401/MAX9404
Typical Operating Characteristics
(Outputs terminated with 50 to VCC - 3.3V, VCC - VEE = +3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, output is enabled, SEL = high, SEL = low, input transition time = 125ps (20% to 80%), fCLK = 3.0GHz, fIN = 1.5GHz, TA = +25C, unless otherwise noted.)
DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL) vs. IN_ FREQUENCY
MAX9401/04 toc01
SUPPLY CURRENT vs. TEMPERATURE
100 OUTPUTS ARE OPEN; INPUTS ARE HIGH OR LOW 94 SUPPLY CURRENT (mA) 1.6 DIFFERENTIAL OUTPUT VOLTAGE (mV)
1.2
88
0.8
82
0.4
76
70 -40 -15 10 35 60 85 TEMPERATURE (C)
0 0 0.5 1.0 1.5 2.0 2.5 3.0 IN_ FREQUENCY (GHz)
TRANSITION TIME vs. TEMPERATURE
MAX9401/04 toc03
PROPAGATION DELAY vs. TEMPERATURE
MAX9401/04 toc04
130
700 CLK-TO-OUT DELAY
tR 118 tF
PROPAGATION DEALY (ps)
124 TRANSITION TIME (ps)
620
540
112
460 IN-TO-OUT DELAY
106
380
100 -40 -15 10 35 60 85 TEMPERATURE (C)
300 -40 -15 10 35 60 85 TEMPERATURE (C)
Pin Description
PIN 1, 8, 11, 17, 24, 30 2 NAME VCC FUNCTION Positive Supply Voltage. Bypass VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four channels to operate in synchronized mode. Inverting Differential Select Input Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs to the outputs when SEL = low. Noninverting Differential Clock Input
SEL SEL CLK CLK
3 4 5
4
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MAX9401/04 toc02
Quad ECL/PECL Differential Buffers/Receivers
Pin Description (continued)
PIN 6 7 9 10 12 13 14, 20, 21, 27 15 16 18 19 22 23 25 26 28 29 31 32 -- NAME EN EN IN3 IN3 OUT3 OUT3 VEE IN2 IN2 OUT2 OUT2 OUT1 OUT1 IN1 IN1 OUT0 OUT0 IN0 IN0 EP* FUNCTION Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high) enables the outputs. Setting EN = low and EN = high (differential low) sets the outputs to logic low. Inverting Differential Output Enable Input Noninverting Differential Input 3 Inverting Differential Input 3 Inverting Differential Output 3 Noninverting Differential Output 3 Negative Supply Voltage Noninverting Differential Input 2 Inverting Differential Input 2 Inverting Differential Output 2 Noninverting Differential Output 2 Noninverting Differential Output 1 Inverting Differential Output 1 Inverting Differential Input 1 Noninverting Differential Input 1 Noninverting Differential Output 0 Inverting Differential Output 0 Inverting Differential Input 0 Noninverting Differential Input 0 Exposed Paddle. EP is electrically connected to VEE. Solder EP to PC board.
MAX9401/MAX9404
*QFN-EP package only.
Detailed Description
The MAX9401/MAX9404 are extremely fast, low-skew quad ECL/PECL buffers/receivers designed for highspeed data and clock driver applications. These devices feature ultra-low propagation delay of 365ps and channel-to-channel skew of 15ps in asynchronous mode with 84mA supply current, making them ideal for driving long cables and double termination applications (Functional Diagram). The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input
provides the ability to force all the outputs to a differential low state.
Data Input Termination
Figure 1 shows the input and output configuration of the MAX9401/MAX9404. The MAX9401 has highimpedance inputs and requires external termination. The MAX9404 has integrated 100 differential input termination resistors across each of the four inputs (IN_ to IN_), reducing external component count.
Outputs
The MAX9401/MAX9404 have double-swing open-emitter outputs as shown in Figure 1. The double-amplitude swing outputs can drive double-terminated links or long
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Quad ECL/PECL Differential Buffers/Receivers MAX9401/MAX9404
IN_ IN_ 100 IN_ MAX9401 IN_ MAX9404 VCC
nal should be set to either logic low or high state to minimize noise coupling.
Synchronous Operation
Setting SEL = low and SEL = high enables all four channels to operate in synchronous mode. In this mode, buffered inputs are clocked into flip-flops simultaneously on every rising edge of the differential clock input (CLK and CLK).
Differential Signal Input Limit
The maximum differential input signal magnitude is 3.0V.
OUT_ OUT_ MAX9401 MAX9404
Supply Voltages
For interfacing to differential PECL signals, the VCC range is from +3.0V to +5.5V (with VEE grounded). For interfacing to differential ECL, the VEE range is -3.0V to -5.5V (with V CC grounded). Output levels are referenced to V CC and are considered PECL or ECL, depending on the level of the VCC supply.
Figure 1. MAX9401/MAX9404 Input and Output Configurations
Applications Information
cables. External termination is required. See the Output Termination section.
Input Bias
Unused inputs should be biased to avoid noise coupling that might cause toggling at the unused outputs. See Figure 2 for the biasing network.
Enable
Setting EN = high and EN = low enables the outputs. Setting EN = low and EN = high forces the outputs to a differential low when disabled. All changes on CLK, SEL, and IN_ are ignored.
Output Termination
Terminate the outputs through 50 to VCC - 3.3V or use an equivalent Thevenin termination. Use identical terminations on each OUT for the lowest skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if OUT_ is used as a single-ended output, terminate both OUT_ and OUT_.
Asynchronous Operation
Setting SEL = high and SEL = low enables four channels to operate independently as a buffer/receiver (CLK is ignored). In asynchronous mode, the CLK sig-
VCC
VCC
IN_ 100 IN_ 1k MAX9401
IN_ 100 IN_ 1k MAX9404
VEE
VEE
Figure 2. Input Bias Circuits for Unused Pins for MAX9401/MAX9404 6 _______________________________________________________________________________________
Quad ECL/PECL Differential Buffers/Receivers MAX9401/MAX9404
VCC VID VID = 0 VILD (MAX) VOH - VOL VIHD (MIN) VID VEE INPUT VOLTAGE DEFINITION VID = 0 VILD (MIN) OUTPUT VOLTAGE DEFINITION VEE VOCM VOL VOH VIHD (MAX) VCC
Figure 3. Input and Output Voltage Definitions
IN_ VIHD - VILD IN_
tPLH1 OUT_ VOH - VOL OUT_
tPHL1
80%
VOH - VOL
80%
OUT_ - OUT_
DIFFERENTIAL OUTPUT WAVEFORM
20%
VOH - VOL
20%
tR
tF (SEL = HIGH, EN = HIGH)
Figure 4. IN to OUT Propagation Delay Timing Diagram
Ensure that the output currents do not exceed the current limits as specified in the Absolute Maximum Ratings. Under all operating conditions, the device's total thermal limits should be observed.
possible, with the 0.01F capacitor closest to the device pins. Use multiple bypass vias for connection to minimize inductance.
Circuit Board Traces
Input and output trace characteristics affect the performance of the MAX9401/MAX9404. Connect each of the inputs and outputs to a 50 characteristic impedance trace. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by main7
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to maximize the performance and noise immunity. Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors as close to the device as
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Quad ECL/PECL Differential Buffers/Receivers MAX9401/MAX9404
CLK VIHD - VILD CLK
tH IN_
tS
tH
VIHD - VILD IN_
tPLH2 OUT_ VOH - VOL OUT_
tPHL2
(SEL = LOW, EN = HIGH)
Figure 5. CLK to OUT Propagation Delay Timing Diagram
taining the distance between differential traces and avoid sharp corners. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces.
Chip Information
TRANSISTOR COUNT: 748 PROCESS: Bipolar
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Quad ECL/PECL Differential Buffers/Receivers
Functional Diagram
IN0 1 IN0 D D CLK CLK IN1 1 IN1 D D CLK CLK IN2 1 IN2 D D CLK CLK IN3 1 IN3 D D CLK CLK Q Q OUT3 0 OUT3 Q Q OUT2 0 OUT2 Q Q OUT1 0 OUT1 Q Q OUT0 0 OUT0
MAX9401/MAX9404
CLK CLK SEL SEL EN EN
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Quad ECL/PECL Differential Buffers/Receivers MAX9401/MAX9404
Package Information
32L,TQFP.EPS 10 ______________________________________________________________________________________
Quad ECL/PECL Differential Buffers/Receivers
Package Information (continued)
MAX9401/MAX9404
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Quad ECL/PECL Differential Buffers/Receivers MAX9401/MAX9404
Package Information (continued)
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Quad ECL/PECL Differential Buffers/Receivers MAX9401/MAX9404
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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