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INTEGRATED CIRCUITS
DATA SHEET
P83C434; P83C834 8-bit microcontrollers with LCD-driver
Product specification Supersedes data of 1996 Oct 16 File under Integrated Circuits, IC20 1997 Jul 03
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
CONTENTS 1 1.1 1.2 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 FEATURES Differences from the 80C51 core Memory GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION Input/Output (I/O) Oscillator Interrupts Reduced power modes Reset Special Function Registers (SFRs) LCD driver unit 7 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 15 16
P83C434; P83C834
LIMITING VALUES HANDLING DC CHARACTERISTICS LCD DRIVER CHARACTERISTICS AC CHARACTERISTICS Characteristic curves APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction SDIP QFP DEFINITIONS LIFE SUPPORT APPLICATIONS
1997 Jul 03
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
1 FEATURES
P83C434; P83C834
* Timer 0 external input replaced by a direct connection to the 32 kHz oscillator output. * Timer 1 external input is connected to pin P0.0 (Port 0); alternate function of P0.0. * Standard serial interface and its control register is not present. * Adjustable on-chip oscillator without external components. * Wake-up from Power-down mode is also possible by means of an interrupt. * Extended external interrupts. 1.2 Memory ROM/RAM sizes MEMORY DEVICE ROM P83C434 P83C834 2 4 kbytes 8 kbytes RAM 128 bytes 256 bytes
* 80C51 type core * System clock derived from an internal free running Current Controlled Oscillator (CCO); no external components required. Clock frequency can be adjusted by software. * Optimized for EMC (Electromagnetic Compatibility) * Clock frequency fclk = 1 to 12 MHz * 12 I/O lines, quasi-bidirectional * Gated interrupt on 8 I/O lines: - P0.0 to P0.3 when LOW - P0.4 to P0.7 when LOW or HIGH * LCD driver clock, 32 kHz, which also provides the time base for a Real Time Clock * 1-second interrupt by internal 15-bit counter * On-chip Liquid Crystal Display (LCD) drivers with 26 outputs, comprising: - 22, 23 or 24 segment drivers - 1 to 4 backplanes * LCD multiplexing rates: 1 : 1 (static), 1 : 2, 1 : 3 or 1 : 4 * Operating temperature: -40 to +85 C * Single power supply: - Operating voltage: 3.5 to 5.5 V - Power-down mode: 1.8 V. 1.1 Differences from the 80C51 core
Table 1
GENERAL DESCRIPTION
The P83C434 and P83C834 are low-cost microcontrollers of the 80C51 family, with LCD drivers. Main application is in the user-interface (keypad, display) of consumer products, e.g. portable radios, CD-players, etc. This data sheet details the specific properties of the P83C434 and P83C834. The shared characteristics of the 80C51 family of microcontrollers are described in "Data Handbook IC20", which should be read in conjunction with this data sheet.
* Port 0 quasi-bidirectional instead of open-drain. * No external memory connection. Signals EA, ALE and PSEN are not present. * Port 1, Port 2 (pins P2.4 to P2.7) and Port 3 are not present. 3 ORDERING INFORMATION
PACKAGE TYPE NUMBER NAME P83C434CFP; P83C834CFP DESCRIPTION VERSION SOT270-1 SDIP42 plastic shrink dual in-line package; 42 leads (600 mil)
TEMP. RANGE (C) -40 to +85
QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); SOT307-2 body 10 x 10 x 1.75 mm
1997 Jul 03
3
4
1997 Jul 03
VDD(C) RESET XTAL1 MCON.5 OSC XTAL2 32 kHz
Philips Semiconductors
BLOCK DIAGRAM
handbook, full pagewidth
VDD(P)
VSS
P2.0 P2.1 P2.2 P2.3 1-SECOND COUNTER
MCON.4 CCO D/A OSCON
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
0 1 P2.0 to P2.3 2 T0 3 T1 EI1 0 80C51 CORE 1 2 3 P0.0 to P0.7 4 5 6 CLOCK 7 EI0 internal bus
8-bit microcontrollers with LCD-driver
8 8
4
8 INTERRUPT GATES 8 MCON LCD UNIT 8 INTERRUPT GATES REGISTER (IG). internal MCON.3
(1)
MCON.0
CLOCK
MCON.1
MCON.2
S00 S22/ S23/ BP1 BP0 to BP3 BP2 MGG012 S21
(1) Drive lines S00 and S21 are not available with the SDIP42 (SOT270-1) package.
P83C434; P83C834
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
5 5.1 PINNING INFORMATION Pinning
P83C434; P83C834
handbook, halfpage
S23/BP2 BP1 BP0 P2.0 P2.1 P2.2 P2.3 RESET VDD(P)
1 2 3 4 5 6 7 8 9
42 S22/BP3 41 S20 40 S19 39 S18 38 S17 37 S16 36 S15 35 S14 34 S13
VSS 10 VDD(C) 11 XTAL1 12 XTAL2 13 P0.0 14 P0.1 15 P0.2 16 P0.3 17 P0.4 18 P0.5 19 P0.6 20 P0.7 21
P83C434 P83C834
33 S12 32 S11 31 S10 30 S09 29 S08 28 S07 27 S06 26 S05 25 S04 24 S03 23 S02 22 S01
MGG011
Fig.2 Pinning diagram for SDIP42 (SOT270-1).
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
40 S23/BP2
handbook, full pagewidth
43 P2.0
42 BP0
39 S22/BP3
44 P2.1
41 BP1
38 S21
37 S20
36 S19
35 S18
P2.2 P2.3 RESET VDD(P) VSS VDD(C) XTAL1 XTAL2 P0.0
1 2 3 4 5 6 7 8 9
34 S17
33 S16 32 S15 31 S14 30 S13 29 S12
P83C434 P83C834
28 S11 27 S10 26 S09 25 S08 24 S07 23 P06
P0.1 10 P0.2 11
P0.3 12
P0.4 13
P0.5 14
P0.6 15
P0.7 16
S04 21
S00 17
S01 18
S02 19
S03 20
S05 22
MGG010
Fig.3 Pinning diagram for QFP44 (SOT307-2).
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
5.2 Pin description Pin description for SDIP42 and QFP44 PIN SYMBOL S23/BP2 BP1 BP0 P2.0 to P2.3 RESET VDD(P) VSS VDD(C) XTAL1 XTAL2 P0.0 to P0.7 S00 S01 to S20 S21 S22/BP3 Notes 1. For proper VDD supply to VDD(P) and VDD(C) see Section 6.1.1. SDIP42 (SOT270-1) 1 2 3 4 to 7 8 9 10 11 12 13 14 to 21 - 22 to 41 - 42 QFP44 (SOT307-2) 40 41 42 3 4 5 6 7 8 9 to 16 17 18 to 37 38 39 Port 0: quasi-bidirectional I/O lines segment drive line 0; see note 2 segment drive line 1 to 20 segment drive line 21; see note 2 backplane drive line 1 backplane drive line 0 reset input
P83C434; P83C834
Table 2
DESCRIPTION segment drive line 23/Backplane drive line 2
43, 44, 1 and 2 quasi-bidirectional I/O line power supply (+) for periphery and LCD unit; see note 1 ground; double bonded power supply for the core; see note 1 oscillator, XTAL connections
segment drive line 22/Backplane drive line 3
2. In package SDIP42 (SOT270-1) segment drive lines S00 and S21 are not connected, so the total number of drive lines is 22.
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6 FUNCTIONAL DESCRIPTION
P83C434; P83C834
* The power supply and ground pins are placed next to each other. * Double bonding VSS pins, i.e. 2 bondpads for each pin. * Limiting the drive capability of: - clock drivers and prechargers. - segment drivers and backplane drivers for the LCD. * External decoupling of the of the CPU supply VDD(C); to avoid interference on the VDD line, the VDD(C) and VDD(P) pins should be connected as illustrated in Fig.4.
The block diagram is shown in Fig.1. The P83C434 and P83C834 provide all functions that are required for a user interface. This is illustrated in the radio application detailed in Chapter 12. In the following sections the functions of the device are described. 6.1 Input/Output (I/O)
A total of 12 I/O lines are available. Port 0 P0.0 to P0.7 (8 lines). Port configuration: Quasi-bidirectional (push-pull in emulation mode). For the Interrupt generation see Fig.10. If one of the port lines P0.0 to P0.3 is a logic 0 or one of the port lines P0.4 to P0.7 is equal to the corresponding bit in the Miscellaneous Control Register (MCON) and the corresponding bit in the Interrupt Gate Register (IG) is a logic 1, then an INT0 interrupt is generated. Port 2 P2.0 to P2.3 (4 lines). Port configuration: Quasi-bidirectional (push-pull in emulation mode). When writing to Port 2, bits P2.4 to P2.7 have to be fixed at HIGH. Data to be written should be `1111XXXXB'. 6.1.1 EMC (ELECTROMAGNETIC COMPATIBILITY)
handbook, halfpage
VDD
2.2 H
VDD(C)
VDD(P) P83C434 P83C834
MGG019
In order to reduce EMI (Electromagnetic Interference) the following design measures have been taken: * Slope control is implemented on all the I/O lines. Rise and fall time (10% to 90%) are: 20 ns < rise/fall time < 50 ns. Fig.4 Avoiding interference on VDD.
handbook, full pagewidth
strong pull-up 2 oscillator periods p1
VDD
p2 p3
I/O PIN Q from port latch n I1 input data read port pin INPUT BUFFER
MLC926 - 1
Fig.5 Standard output with switched pull-up current source.
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.2 6.2.1 Oscillator CPU CLOCK Table 3
P83C434; P83C834
Oscillator status during Power-down mode 32 kHz OSCILLATOR running stopped
RUN32 HIGH LOW 6.2.3
The internal timing circuits of the CPU are clocked by a Current Controlled Oscillator (CCO). The oscillator is free running and is adjusted by means of the Oscillator Control Register (OSCON; see Section 6.6.4) and a digital-to-analog converter; it does not require external components. The frequency of the CPU clock can be measured by means of Timer T0 which is clocked by the 32 kHz oscillator (see Section 6.2.2). Adjustments can be made by changing the contents of the OSCON register (see Fig.9). Over the range 0 to 31 the frequency step size is constant (deviation 10%). The frequency variation per step of the register is: 0.5 MHz < step size < 2 MHz. At Power-on-reset the oscillator frequency will be: 1 MHz < fOSC < 4 MHz. Stability of the oscillator: frequency change with time 1.5%. The maximum operating frequency is: 12 MHz at VDD 4.5 V. The minimum operating frequency is 1 MHz. In Power-down mode the oscillator is stopped. 6.2.2 LCD DRIVER CLOCK: 32 KHZ OSCILLATOR
15-BIT COUNTER (1-SECOND TIMER)
An interrupt is generated every second by the 15-bit counter. This 1-second timer is a 15-bit counter, clocked by the 32 kHz oscillator output. When this counter overflows it generates an INT1 interrupt by setting SECINT in the Miscellaneous Control Register (MCON). Reset of this interrupt is carried out via software by clearing bit SECINT.
handbook, halfpage
XTAL1
XTAL2
MLC928
A 32 kHz oscillator provides the clocking of the LCD timing generator and may also be used as the time base for a Real Time Clock. The output of the 32 kHz oscillator is also used as an input of Timer/Counter 0. The frequency of the 32 kHz oscillator need not be exactly 32 kHz, and is determined by the component(s) connected between pins XTAL1 and XTAL2. See Chapter 11. The oscillator is suitable for use with either: * A crystal; connected as shown in Fig.6a * External drive; connected as shown in Fig.6b. During Power-down mode, the control bit RUN32 in the Miscellaneous Control Register (MCON) determines whether the oscillator is stopped or running continuously; see Table 3. The output of the oscillator (XTAL2) is used as an input to the Timer/Counter 0. This can be useful for accurate time measurements and generation of time-slots. For example it may be used to determine (and possibly adjust) the frequency of the CCO that is used for the CPU clock.
a. Crystal oscillator.
handbook, halfpage
XTAL1
XTAL2 n.c.
external clock (not TTL compatible)
MBE312
b. External clock drive.
Fig.6 Oscillator configurations P83C434/P83C834.
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
MBE313
handbook, halfpage
16
f osc (MHz) 12 OSCON = FH
handbook, halfpage
16
MBE314
f osc (MHz) 12
OSCON = FH
8 8 7H 4 4 1H 0 50 0 50 T ( oC) 100 0 2 3 4 VDD (V) 5 1H 7H
Fig.7
fosc as function of temperature; at VDD = 5 V.
Fig.8 fosc as function of VDD.
handbook, halfpage
36
MBE315
f osc (MHz) 24
(1)
(2)
(3)
12
0 0 10 20 30 40 contents of OSCON (decimal) 31(max)
(1) Fast case; VDD = 5.5 V, Tamb = -40 C. (2) Typical case; VDD = 4.0 V, Tamb = 25 C. (3) Slow case; VDD = 2.0 V, Tamb = 85 C.
Fig.9 fosc as function of OSCON.
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.3 Interrupts
P83C434; P83C834
In the interrupt routine SECINT should be reset by software so that with the next 1-second overflow another interrupt may be generated. Timer 0 and Timer 1 interrupts are generated by TF0 and TF1 which are set by an overflow of their respective Timer/Counter registers (except for Timer 0 in mode 3; see "Data Handbook IC20, 80C51 Family, Chapter Timer/Counters"). When a timer interrupt is generated, the flag that generated it is cleared by the internal hardware when the LCALL is executed for the vector address. All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in software. Each of these interrupts sources can be individually enabled or disabled by setting or clearing the bit in Special Function Register IE (see Table 5). IE also contains a global disable bit EA, which disables all interrupts at once.
The P83C434 and P83C834 have 4 interrupt sources; these are shown Fig.10. Interrupt INT0 is generated when one of the I/O lines (P0.0 to P0.3) becomes LOW; or one of I/O lines (P0.4 to P0.7) equals the corresponding bit in the MCON register (ILVL0 to ILVL3). By means of bit IT0 in the TCON register this interrupt can be chosen to be: * Level sensitive, when IT0 = LOW; INT0 must be inactive before a return from interrupt is given, otherwise the same interrupt will occur again. * Edge sensitive, when IT0 = HIGH; the internal hardware will reset the latch when the LCALL is executed for the vector address (see Table 7). Interrupt INT1 is generated by the overflow of the 1-second counter. The overflow signal is latched. The output of the latch will set the SECINT bit in the MCON register. When SECINT is set the overflow latch will be reset. Interrupt INT1 is selected as edge or level sensitive by the state of the IT1 bit in the TCON register. However, it is recommended to always set IT1 to HIGH (edge sensitive) so that IE1 will be reset by the internal hardware when the LCALL is executed for the vector address. 6.3.1 Table 4 7 EA Table 5 BIT 7 INTERRUPT ENABLE REGISTER (IE) Interrupt Enable Register (address A8H) 6 - Description of IE bits SYMBOL EA 5 - 4 -
3 ET1
2 EX1
1 ET0
0 EX0
DESCRIPTION Disable all interrupts. If EA is: LOW, then no interrupt will be acknowledged. HIGH, then each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
6 to 4 3 2 1 0
- ET1 EX1 ET0 EX0
Reserved. Enables or disables the Timer 1 Overflow Interrupt. If ET1 is LOW then the Timer 1 interrupt is disabled. Enables or disables the External Interrupt 1. If EX1 is LOW then the External 1 interrupt is disabled. Enables or disables the Timer 0 Overflow Interrupt. If ET0 is LOW then the Timer 0 interrupt is disabled. Enables or disables the External Interrupt 0. If EX0 is LOW then the External 0 interrupt is disabled.
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handbook, full pagewidth
1997 Jul 03
9 IT0 '1' IE0 IE0 INT0 3 '0' 1 2 1 2 3 4 5 6 7 8 3 1 2 3 interrupt gates
P0.0
P0.1
Philips Semiconductors
P0.2
P0.3
P0.4
1 2
3
P0.5
1 2
3
P0.6
1 2
P0.7
8-bit microcontrollers with LCD-driver
MCON: ILVL0 to ILVL3
12
TF0 LATCH 3 SECINT INT1 '1' IE1 '0' IT1 1 2 TF1
Timer 0 overflow
TF0
interupt sources
1-sec counter overflow
1 2
3
IE1
Timer 1 overflow
TF1
MLC919 - 1
P83C434; P83C834
Product specification
Fig.10 Interrupt sources.
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.3.2 PRIORITY LEVEL STRUCTURE
P83C434; P83C834
Condition 2 ensures that the instruction in progress will be completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one more instruction will be executed before the interrupt is vectored to. The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if an interrupt flag is active but not being responded to for one of the above mentioned conditions, if the flag is still inactive when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new. The polling cycle/LCALL sequence is illustrated in "Data Handbook IC20, 80C51 Family, Fig.20". Note that if an interrupt of higher priority level becomes active prior to S5P2 of the machine cycle labelled C3 ("Data Handbook IC20, 80C51 Family, Fig.20"), then in accordance with the above rules it will be vectored to during C5 and C6, without any instruction of the lower priority routine having been executed. Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine. The hardware generated LCALL pushes the contents of the Program Counter on to the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to as shown in Table 7. Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Execution of the interrupted program continues from where it left off. Note that a simple RET instruction would also return execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future interrupts impossible. Table 7 Vector addresses VECTOR ADDRESS 0003H 000BH 0013H 001BH
The priority level of each interrupt source can be individually programmed by setting or clearing a bit in the Interrupt Priority Register (IP; see Section 6.3.4). A low priority interrupt can itself be interrupted by a high priority interrupt, but not by another low priority interrupt. A high priority interrupt can not be interrupted by another interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If request of the same priority level is received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level there is a second priority structure determined as shown in Table 6. The IP register contains a number of not implemented bits. IP.7, IP.6 and IP.5 are reserved in the 80C51. User software should not write logic 1's to these positions, since they may be used in other 8051-Family products. Table 6 Priority within levels PRIORITY WITHIN LEVEL(1) 1 (highest) 2 3 4 (lowest)
SOURCE IE0 TF0 IE1 TF1 Note
1. The `Priority within level' structure is only used to resolve simultaneous requests of the same priority level. 6.3.3 HOW INTERRUPTS ARE HANDLED
The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware generated LCALL is not blocked by any of the following conditions: 1. An interrupt of equal priority or higher priority level is already in progress. 2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress. 3. The instruction in progress is RETI or any write to the IE or IP registers.
SOURCE IE0 TF0 IE1 TF1
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Product specification
8-bit microcontrollers with LCD-driver
6.3.4 Table 8 7 - Table 9 BIT 7 to 4 3 2 1 0 - PT1 PX1 PT0 PX0 INTERRUPT PRIORITY REGISTER (IP) Interrupt Priority Register (address B8H) 6 - Description of IP bits SYMBOL Reserved. DESCRIPTION 5 - 4 - 3 PT1 2 PX1
P83C434; P83C834
1 PT0
0 PX0
Defines the Timer 1 Overflow Interrupt priority level. When PT1 is HIGH, Timer 1 Overflow Interrupt is assigned a high priority level. Defines the External Interrupt 1 priority level. When PX1 is HIGH, External Interrupt 1 is assigned a high priority level. Defines the Timer 0 Overflow Interrupt priority level. When PT0 is HIGH, Timer 0 Overflow Interrupt is assigned a high priority level. Defines the External Interrupt 0 priority level. When PX0 is HIGH, External Interrupt 0 is assigned a high priority level. To terminate the Power-down mode with an external interrupt, INT0 or INT1 must be switched to level-sensitive and must be enabled. The external interrupt input signal INT0 and INT1 must be kept LOW until the oscillator has restarted and stabilized. An instruction following the instruction that puts the device in the Power-down mode will be executed. The control bits for the reduced power modes are in the Special Function Register PCON. To wake-up the microcontroller by a reset, the RESET pin must be kept HIGH for a minimum of 36 s. 6.5 Reset
6.4 6.4.1
Reduced power modes IDLE MODE
In the Idle mode, the CPU puts itself to sleep while all of the on-chip peripherals remain active. The instruction to invoke the Idle mode is the last instruction executed in the normal operating mode before the Idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The Idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. 6.4.2 POWER-DOWN MODE
In the Power-down mode, the CCO oscillator (processor clock) is stopped; as the instruction to invoke Power-down mode is the last instruction executed. Whether the 32 kHz oscillator is stopped depends on bit RUN32 in the MCON register (MCON5). The Power-down mode can be terminated by a RESET in same way as in the 80C51 or in addition by one of two external interrupts, INT0 or INT1. A termination with an external interrupt does not affect the internal data memory and does not affect the Special Function Registers. This makes it possible to exit Power-down without changing the port output levels.
Reset is accomplished either at power-on when the supply voltage rises above Power-on-reset threshold or by a logic 1 signal at the RESET pin. The Power-on-reset threshold is minimum 1.8 V and maximum 3.0 V. The RESET signal should be active (HIGH) for at least 2 machine cycles (24 oscillator periods). The reset algorithm puts registers and flip-flops in a defined state (see 80C51 Family specification in "Data Handbook IC20" and Section 6.6.1). The I/O ports are set to a logic 1 at reset. To wake-up from power-down the RESET signal must be kept HIGH for a minimum of 36 s.
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Product specification
8-bit microcontrollers with LCD-driver
6.6 6.6.1 Special Function Registers (SFRs) CHANGES W.R.T. 80C51 KERNEL
P83C434; P83C834
* Removed SFRs: P3, P1, SCON and SBUF * Added SFRs: IG, MCON, OSCON, LCDCON and LCD0 to LCD11. Table 10 Overview of the additional SFRs All SFRs are Read/Write registers. REGISTER IG MCON OSCON LCDCON LCD0 to LCD5 LCD6 to LCD11 6.6.2 DESCRIPTION Interrupt Gate Register Miscellaneous Control Register Oscillator Control Register LCD Control Register LCD segment display registers ADDRESS 97H 98H B7H B9H 9AH to 9FH BAH to BFH RESET VALUE 00H 00H 01H 0CH 00H 00H
INTERRUPT GATE REGISTER (IG)
Table 11 Interrupt Gate Register (address 97H) 7 IG.7 6 IG.6 5 IG.5 4 IG.4 3 IG.3 2 IG.2 1 IG.1 0 IG.0
Table 12 Description of IG bits BIT 7 to 0 SYMBOL IG.7 to IG.0 DESCRIPTION gate signals for interrupt from I/O lines P0.7 to P0.0. If signal IG.n is: LOW, then no interrupt is possible HIGH, then interrupt is possible
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Product specification
8-bit microcontrollers with LCD-driver
6.6.3 MISCELLANEOUS CONTROL REGISTER (MCON)
P83C434; P83C834
This register is bit-addressable. Table 13 Miscellaneous Control Register (address 98H) 7 - 6 - 5 RUN32 4 SECINT 3 ILVL3 2 ILVL2 1 ILVL1 0 ILVL0
Table 14 Description of MCON bits BIT 7 and 6 5 - RUN32 SYMBOL Reserved. Prevent stop of 32 kHz oscillator in Power-down mode. If RUN32 is: HIGH, then the 32 kHz oscillator is not stopped in Power-down mode. LOW, then the 32 kHz oscillator is stopped in Power-down mode. 4 SECINT 1-second interrupt flag. Is set by hardware on overflow of the 1-second counter. Can be Set/Reset via software. If SECINT is: HIGH, then there is an interrupt on overflow. LOW, then there is no interrupt on overflow. 3 to 0 ILVL3 to ILVL0 The state of these bits determine the signal level of the inputs P0.m (m = 4 to 7) which will generate the interrupt EI0 (dependent on bits IG.4 to IG.7 respectively). If ILVLn (n = 0 to 3) is: LOW, then P0.m = LOW, will cause an interrupt. HIGH, then P0.m = HIGH, will cause an interrupt. 6.6.4 OSCILLATOR CONTROL REGISTER (OSCON) DESCRIPTION
Table 15 Oscillator Control Register (address B7H) 7 - 6 - 5 - 4 OSCON.4 3 OSCON.3 2 OSCON.2 1 OSCON.1 0 OSCON.0
Table 16 Description of OSCON bits BIT 7 to 5 4 to 0 - OSCON.4 to OSCON.0 SYMBOL Reserved. These 5 bits can hold a decimal value in the range of 0 to 31, that will be converted to a current that controls the frequency of the CCO of the CPU clock; can be set by software. The register value is converted to an analog current that controls the oscillator (see Section 6.2.1). DESCRIPTION
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Product specification
8-bit microcontrollers with LCD-driver
6.6.5 LCD CONTROL REGISTER (LCDCON)
P83C434; P83C834
After an external or Power-on-reset the LCD Control Register holds the value 0CH (see Table 10) resulting in: * The LCD is disabled. All segment and backplane drivers are set to the VSS level. * BIAS is set to generate 13VDD(P). * Bits MD0 and MD1 reset the multiplex ratio to the 1 : 4 mode. Table 17 LCD Control Register (address B9H) 7 - 6 - 5 - 4 - 3 MD1 2 MD0 1 BIAS 0 ENLCD
Table 18 Description of LCDCON bits BIT 7 to 4 3 2 1 - MD1 MD0 BIAS The BIAS bit sets the LCD voltage bias generator. If BIAS is: HIGH, then the LCD voltage bias generator is set to 12VDD(P). LOW, then the LCD voltage bias generator is set to 13VDD(P). 0 ENLCD Enable LCD. If ENLCD is: LOW, then the LCD is disabled. All segment and backplane drivers are set to the VSS level. HIGH, then the LCD is enabled and character display is possible. Table 19 Multiplex ratio mode selection MD1 0 0 1 1 6.6.6 MD0 0 1 0 1 MULTIPLEX RATIO MODE static 1:2 1:3 1:4 SYMBOL Reserved. Mode bits. MD0 and MD1 determine the multiplex rate; see Table 19. DESCRIPTION
LCD SEGMENT DISPLAY REGISTERS (LCD0 TO LCD11)
The 12 display registers, LCD0 to LCD11, are 8-bit derivative (Read/Write) registers which store LCD segment data. For detailed information, regarding the LCD0 to LCD11, see Table 23 in Section 6.7.7.
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7 LCD driver unit
P83C434; P83C834
The display configurations possible with the P83C434 and P83C834 depend on the number of active backplane outputs required. A selection of display configurations is given in Table 21. The appropriate biasing voltages for the multiplexed LCD wave forms are generated internally. At power-on all the LCD driver control register bits are cleared. The LCD driver is not affected by executing Idle or Power-down modes. 6.7.2 LCD BIAS GENERATION
The LCD driver unit has 24 segment drivers, two of which can also serve as backplane drivers. Selection will be done automatically, depending on the multiplex ratio as shown in Table 20. 6.7.1 FUNCTIONAL DESCRIPTION OF THE LCD DRIVER
The P83C434 and P83C834 have a display driver which interfaces to almost any LCD which has a low multiplex rate. The interface delivers drive signals for any static or multiplexed LCD panel that contains up to 4 backplanes and up to 24 segments. Figure 11 shows the block diagram of the LCD driver. The following features are incorporated: * Selection of backplane drive configuration: - static - 2, 3 or 4 backplane multiplexing * Selection of display bias configuration: - -
1 2 1 3
The LCD operating voltage: Vop = VDD(P) - VSS. Vop should be chosen so that the off voltage (Voff(rms)) is just below the threshold voltage (Vth), typically when the LCD exhibits 10% contrast. Fractional LCD biasing voltages are obtained from an internal voltage divider of three resistors connected between VSS and VDD(P). The centre resistor may be switched out of circuit to provide a 1 bias voltage level for a 1 : 2 multiplex configuration. 2 6.7.3 LCD VOLTAGE SELECTOR
internal LCD bias generation internal LCD bias generation The LCD voltage selector coordinates the multiplexing of the LCD according to the selected drive configuration. The operation of the voltage selector is controlled by the MODE bits in the LCD control byte. The biasing configurations that apply to the preferred mode of operation, together with the biasing characteristics as functions of Vop = VDD(P) - VSS and the resulting discrimination ratios (D), are given in Table 22.
* 24 individual segment drivers can be used to provide: - up to twelve 7-segment numeric characters - up to six 14-segment alphanumeric characters - graphic using up to 88 elements - twelve 8-bit derivative registers for display data bits.
handbook, full pagewidth
LCD VOLTAGE SELECTOR SEGMENT REGISTERS 24 LCD DRIVERS 8 SEGMENT internal bus 22 MUX. BACKPLANE 4
CLOCK VDD(P)
LCD BIAS GENERATION
LCD CONTROL REGISTER
MGG013
S0 to S21 S22/BP3 S23/BP2 BP1 BP0
VSS
Fig.11 Block diagram of the LCD driver.
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
Table 20 Mode selection Segments/Backplanes MULTIPLEX RATIO 1 : 1 (static) 1:2 1:3 1:4 SEGMENTS S00 to S21, S22/BP3, S23/BP2 S00 to S21, S22/BP3, S23/BP2 S00 to S21, S22/BP3 S00 to S21
P83C434; P83C834
BACKPLANES BP0 BP0, BP1 BP0, BP1, S23BP2 BP0, BP1, S23/BP2, S22/BP3
Table 21 Selection of display configurations NUMBER OF BACKPLANES SEGMENTS 4 3 2 1 88 69 48 24 7-SEGMENTS NUMERIC DIGITS 12 9 6 3 INDICATOR SYMBOLS 4 6 6 3 14-SEGMENTS ALPHANUMERIC DOT MATRIX CHARACTERS 6 4 3 1 INDICATOR SYMBOLS 4 13 6 10 88 dots (4 x 22) 69 dots (3 x 23) 48 dots (2 x 24) 24 dots (1 x 24)
Table 22 LCD drive modes and characteristics NUMBER OF LCD DRIVE MODE BACKPLANES static 1:2 1:2 1: 3(1) 1 : 4(1) Note 1. Multiplex drive ratios of 1 : 3 and 1 : 4 with 12 bias are possible, but the discrimination contrast ratios are reduced; for 1 : 3, D = 1.732 and for 1 : 4, D = 1.528. However, there is an advantage that leads to reduction of Vop as follows: a) for 1 : 3 multiplex (12 bias), Vop = 2.449 x Voff(rms). b) For 1 : 4 multiplex (12 bias), Vop = 2.309 x Voff(rms). This compared to Vop = 3 x Voff(rms) when 13 bias is used. 1 2 2 3 4 LEVELS 2 3 4 4 4 LCD BIAS CONFIGURATION static
1 1 1 1 2 3 3 3
V off(rms) -------------------V op 0 0.354 0.333 0.333 0.333
V on(rms) -------------------V op 1 0.791 0.745 0.638 0.577
V on(rms) D = -------------------V off(rms) 2.236 2.236 1.915 1.7321
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7.4 LCD DRIVE MODE WAVEFORMS
P83C434; P83C834
6.7.4.1
Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms are shown in Fig.12.
handbook, full pagewidth
Tframe VDD(P) BP0 VSS VDD(P) Sn VSS VDD(P) Sn+1 VSS (a) waveforms at driver Vop state 1 (on) state 2 (off) LCD elements
state 1
0
-Vop Vop V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = V op state 2 0 V state2(t) = V S
n+1
(t) - V BP0(t)
V off(rms) = 0 V -Vop (b) resultant waveforms at LCD element
MGG014
Fig.12 Static drive mode waveforms (Vop = VDD(P) - VSS).
1997 Jul 03
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7.4.2 1 : 2 multiplex drive mode
P83C434; P83C834
When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies. The P83C434; P83C834 allows use of 1 or 1 bias in this mode as shown in Figs 13 and 14. 2 3
full pagewidth
Tframe VDD(P) BP0 (VDD(P)+VSS)/2 VSS VDD(P) BP1 (VDD(P)+VSS)/2 VSS VDD(P) Sn VSS VDD(P) Sn+1 VSS (a) waveforms at driver Vop Vop/2 state 1 0 -Vop/2 -Vop Vop Vop/2 state 2 0 -Vop/2 -Vop (b) resultant waveforms at LCD element V state1(t) = V S (t) - V BP0(t)
n
LCD elements
state 1 state 2
V on(rms) = 0.791V op V state2(t) = V S (t) - V BP0(t)
n
V off(rms) = 0.354V op
MGG015
Fig.13 Waveforms for the 1 : 2 multiplex mode with 12 bias (Vop = VDD(P) - VSS).
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
agewidth
Tframe BP0 VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS LCD elements
state 1 state 2
BP1
VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS
Sn
VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS (a) waveforms at driver Vop 2Vop/3 Vop/3 0 -Vop/3 -2Vop/3 -Vop Vop 2Vop/3 Vop/3 0 -Vop/3 -2Vop/3 -Vop
Sn+1
state 1
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = 0.745V op V state2(t) = V S (t) - V BP0(t)
n
state 2
V off(rms) = 0.333V op
(b) resultant waveforms at LCD element
MGG016
Fig.14 Waveforms for the 1 : 2 multiplex mode with 13 bias (Vop = VDD(P) - VSS).
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7.4.3 1 : 3 multiplex drive mode
P83C434; P83C834
When three backplanes are provided in the LCD, the 1 : 3 multiplex mode applies, as shown in Fig.15.
book, full pagewidth
Tframe VDD(P) BP0 VSS+2Vop/3 VSS+Vop/3 VSS VDD(P) BP1 VSS+2Vop/3 VSS+Vop/3 VSS VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS LCD elements
state 1 state 2
BP2/S23
Sn
Sn+1
Sn+2
VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS
(a) waveforms at driver Vop 2Vop/3 Vop/3 state 1 0 -Vop/3 -2Vop/3 -Vop Vop 2Vop/3 Vop/3 state 2 0 -Vop/3 -2Vop/3 -Vop
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = 0.638V op V state2(t) = V S (t) - V BP0(t)
n
V off(rms) = 0.333V op
(b) resultant waveforms at LCD element
MGG017
Fig.15 Waveforms for the 1 : 3 multiplex drive mode (Vop = VDD(P) - VSS).
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7.4.4 1 : 4 multiplex drive mode
P83C434; P83C834
When four backplanes are provided in the LCD, the 1 : 4 multiplex mode applies, as shown in Fig.16.
handbook, full pagewidth
VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS VDD(P)
Tframe LCD elements
BP0
state 1 state 2
BP1
VSS+2Vop/3 VSS+Vop/3 VSS
BP2/S23
VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS
BP3/S22
VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS
Sn
VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS
Sn+1
VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS
Sn+2
VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS
Sn+3
VDD(P) VSS+2Vop/3 VSS+Vop/3 VSS
(a) waveforms at driver Vop 2Vop/3 Vop/3 state 1 0 -Vop/3 -2Vop/3 -Vop Vop 2Vop/3 Vop/3 state 2 0 -Vop/3 -2Vop/3 -Vop
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = 0.577V op V state2(t) = V S (t) - V BP0(t)
n
V off(rms) = 0.333V op
(b) resultant waveforms at LCD element
MGG018
Fig.16 Waveforms for the 1 : 4 multiplex drive mode (Vop = VDD(P) - VSS).
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7.5 LCD SEGMENT DRIVER OUTPUTS
P83C434; P83C834
If less than 4 backplane outputs are required then the unused backplane driver outputs should be left open. 6.7.7 LCD SEGMENT DISPLAY REGISTERS
The LCD drive section includes 24 segment outputs (S00 to S23) which should be connected directly to the LCD. The segment data bits are multiplexed to the outputs in accordance with the backplane signals. If less than the 24 segment outputs are required then the unused driver outputs should be left open. 6.7.6 BACKPLANE OUTPUTS
There is a one-to-one relationship between the LCD segment register bits and the segment outputs. A segment register bit which is set to: * Logic 1 indicates the `ON' state of the corresponding LCD segment. * Logic 0 indicates the `OFF' state of the corresponding LCD segment. Table 23 shows the display register bit map.
The LCD drive sections includes 4 backplane outputs (BP0, BP1, S23/BP2 and S22/BP3) which should be connected directly to the LCD. These backplane output signals are generated in accordance with the selected LCD drive mode. Table 23 Display register bit map REGISTER ADDRESS BIT 7 BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Segments corresponding to backplane BP0 LCD0 LCD1 LCD2 9AH 9BH 9CH S07 S15 S23 S06 S14 S22 S05 S13 S21 S04 S12 S20 S03 S11 S19 S02 S10 S18 S01 S09 S17 S00 S08 S16
Segments corresponding to backplane BP1 LCD3 LCD4 LCD5 9DH 9EH 9FH S07 S15 S23 S06 S14 S22 S05 S13 S21 S04 S12 S20 S03 S11 S19 S02 S10 S18 S01 S09 S17 S00 S08 S16
Segments corresponding to backplane S23/BP2 LCD6 LCD7 LCD8 BAH BBH BCH S07 S15 -(1) S06 S14 S22 S05 S13 S21 S04 S12 S20 S03 S11 S19 S02 S10 S18 S01 S09 S17 S00 S08 S16
Segments corresponding to backplane S22/BP3 LCD9 LCD10 LCD11 Note 1. These bits are not connected to a segment and can be used for other purposes. BDH BEH BFH S07 S15 -(1) S06 S14 -(1) S05 S13 S21 S04 S12 S20 S03 S11 S19 S02 S10 S18 S01 S09 S17 S00 S08 S16
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI Isource(max) Isink(max) Ptot Tstg Tamb Note 1. VDD represents both VDD(P) and VDD(C). 8 HANDLING supply voltage; note 1 input voltage (all inputs) total maximum source current for all port lines total maximum sink current for all port lines total power dissipation storage temperature operating ambient temperature (for all devices) PARAMETER
P83C434; P83C834
MIN. 3.3 -0.5 - - - -60 -40
MAX. 5.5 VDD + 0.5 25 25 100 +150 +85 V V
UNIT
mA mA mW C C
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices" ). 9 DC CHARACTERISTICS VDD = 3.3 to 5.5 V; VSS = 0 V; Tamb = -45 to +85 C; all voltages with respect to VSS unless otherwise specified. SYMBOL Supply VDD IDD normal operating supply voltage; note 1 operating supply current fosc = 12 MHz fosc = 5 MHz fosc = 1 MHz IDD(ID) supply current in Idle mode fosc = 12 MHz fosc = 5 MHz fosc = 1 MHz IDD(PD) Inputs RINP IL VIL VIH input resistance RESET leakage current; RESET pin VDD = 3.3 to 5.5 V VDD = 5 V 20 - 60 - 220 10 k A V supply current in Power-down mode all functions down 3.3 - - - - - - - - 15 7.5 1.6 2.1 0.9 205 18 5.5 22 10 2.5 3.0 1.4 300 50 V mA mA mA mA mA A A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
PORTS P0, P2 AND RESET LOW level input voltage HIGH level input voltage VSS - 0.5 - 0.7VDD - 0.3VDD VDD + 0.5 V
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
SYMBOL PORTS P0 AND P2 IIL IIT
PARAMETER
CONDITIONS
MIN. -10 - - -
TYP. -40 -12 - -
MAX. -100 -50 -1000 -500 - - -
UNIT A A A A
input current Ports P0 and P2 input transition current Ports P0 and P2
VI = 0.4 V; VDD = 5 V VI = 0.4 V; VDD = 3.3 V VI = 0.5VDD; VDD = 5 V
Outputs: Ports P0, P2 IOL LOW level output sink current VO 0.4 V; VDD = 5 V VO 0.4 V; VDD = 3.3 V VO 1.0 V; VDD = 5 V IOH HIGH level pull-up output source current strong pull-up during 2 clock cycles weak pull-up VO = VDD - 0.4 V; VDD = 5 V VO = VDD - 0.4 V; VDD = 5 V 6 30 9 6 40 25 - - - - mA mA A A VO = VDD - 0.4 V; VDD = 3.3 V 4 VO = VDD - 0.4 V; VDD = 3.3 V 15 Note 1. VDD represents both VDD(P) and VDD(C). 10 LCD DRIVER CHARACTERISTICS VDD = 3.3 to 5.5 V; VSS = 0 V; Tamb = -45 to +85 C; all voltages with respect to VSS unless otherwise specified. SYMBOL Supply VDD(P) VS operating supply voltage; periphery and LCD part DC voltage component; all backplane and segment drivers VDD(P) = 5 V; IBP = 100 A; outputs measured one at a time VDD(P) = 5 V; IS = 100 A; outputs measured one at a time ratio: 1 : 1, 1 : 2, 1 : 4; note 2 ratio: 1 : 3; note 2 Notes 1. VDD(P) > 3 V for 13 bias. 2. Oscillator frequency = 32 kHz. note 1 3.3 - - - VDD 100 V mV PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 8 5 20 13 10 25 mA mA mA
LCD driver outputs RBP output impedance BP0, BP1, S23/BP2 and S22/BP3 output impedance S0 to S21, S22/BP3 and S23/BP2 LCD scan frequency 50 - 200 k
RS
50
-
200
k
fLCD
- -
64 85
- -
Hz Hz
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
11 AC CHARACTERISTICS VDD = 5 V; Tamb = -45 to +85 C. SYMBOL System (CPU) clock fclk fxtal 11.1 system clock 1.0 PARAMETER CONDITIONS
P83C434; P83C834
MIN.
TYP. - -
MAX.
UNIT
12.0
MHz
32 kHz LCD oscillator crystal frequency Characteristic curves
MBE321
16
40
kHz
25 I OL (mA) 20
(2) (1)
MBE322
25 I OH (mA) 20
15
(3)
15
(1) (2)
10
10
(3)
5
5
0 2 3 4 5 VDD (V) 6
0 2 3 4 5 VDD (V) 6
Port 0 (P0.0 to P0.7) and Port 2 (P2.0 to P2.3); VO = 0.4 V. (1) Tamb = -40 C. (2) Tamb = 25 C. (3) Tamb = 85 C.
Port 0 (P0.0 to P0.7) and Port 2 (P2.0 to P2.3); VO = VDD - 0.4 V. (1) Tamb = -40 C. (2) Tamb = 25 C. (3) Tamb = 85 C.
Fig.17 Typical LOW level output sink current as a function of the supply voltage.
Fig.18 Typical HIGH level pull-up output source current as a function of the supply voltage.
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
12 APPLICATION INFORMATION Figure 19 shows a typical portable/personal radio system application which uses the device in conjunction with the Self Tuned Radio (STR) TEA5757. This application provides the following functions: * Scanning the keypad * Transfer of commands and information to and from the rest of the radio system * Display of information on a LCD * Storage of preset frequencies * Real Time Clock (not always required). Control between the TEA5757 and the microcontroller is performed by a 4 line interface bus.
P83C434; P83C834
The advantage of the TEA5757 is that it works independently from the microcontroller, e.g. once tuned to a station, the microcontroller could be removed and the tuner stays tuned. The system is designed such that the microcontroller is switched to Power-down mode when no actions are required; this increases the lifetime of the batteries. The microcontroller is activated by an interrupt, e.g. when a key on the keyboard is pressed, or by the 1 second timer (updating the real-time clock function). After the appropriate actions are taken the microcontroller will enter the Power-down mode again.
handbook, full pagewidth
TUNER
F/E IF AMP/DET. MPX
L
R
TEA5757H
SYNTH.
HEADPHONE AMPLIFIER TDA8542(T), TDA7050(T) or TDA1308T
L
R
volume
MICROCONTROLLER P83Cx34
LCD DISPLAY
KEYPAD
MSB622
Fig.19 Application diagram with the STR (TEA5757).
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
13 PACKAGE OUTLINES SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
P83C434; P83C834
SOT270-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 wM (e 1) MH b 42 22
pin 1 index E
1
21
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 38.9 38.4 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.9 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT270-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-02-13 95-02-04
1997 Jul 03
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e Q E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 A1 (A 3) Lp L
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 Q 0.85 0.75 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
14 SOLDERING 14.1 Introduction
P83C434; P83C834
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 C. 14.3.2 WAVE SOLDERING
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 14.2 14.2.1 SDIP SOLDERING BY DIPPING OR BY WAVE
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.3.3 REPAIRING SOLDERED JOINTS
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 14.3 14.3.1 QFP REFLOW SOLDERING
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). 1997 Jul 03 32
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
P83C434; P83C834
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
NOTES
P83C434; P83C834
1997 Jul 03
34
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
NOTES
P83C434; P83C834
1997 Jul 03
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/00/03/pp36
Date of release: 1997 Jul 03
Document order number:
9397 750 02549

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