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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES IF Sampling up to 400MHz IF Mode select for optimized SINAD and SFDR On Chip Clock Duty Cycle Stabilization On-chip reference and track/hold SFDR Optimization circuit Excellent Linearity: - DNL = +/- 0.25 lsb (typ) - INL = +/- 0.5 lsb (typ) 750 MHz Full Power Analog Bandwidth SNR = 67dB @ Fin up to Nyquist SFDR = 85dBc @ Fin up to 125 MHz SFDR = 80dBc @ Fin up to 250 MHz THD = 90dBc @ Fin up to 250 MHz Power dissipation = 1.3W typical at 125Msps Input voltage of 1Vp-p or 2Vp-p Two's complement or Offset binary data format +5.0V Analog Supply Operation +2.5V to 3.3V TTL/CMOS outputs. APPLICATIONS Wireless and Wired Broadband Communications - Wideband carrier frequency systems Communications Test Equipment "IF Sampling" schemes Radar and Satellite sub-systems
GENERAL INTRODUCTION
12-Bit, 105/125 MSPS IF Sampling A/D Converter
T
AD9433
DFS SFDR
U
V CC V DD
AD9433
AIN AIN/ T/H
Pipeline ADC 12 Select#1 Select#2 D
11
O
12
-D
0
ENCODE ENCODE/
ENCODE TIMING
REF
GND
REF OUT
REF IN
AD9433 FUNCTIONAL BLOCK DIAGRAM
The AD9433 is a 12-bit monolithic sampling analog-to- digital converter with an on-chip track-and-hold circuit and is designed for ease of use. The product operates up to 125 Msps conversion rate and is optimized for outstanding dynamic performance in wideband and high IF carrier systems. The ADC requires a +5V analog power supply and a differential encode clock for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3V or 2.5V logic.
A user selectable on-chip circuit optimizes SFDR performance of 90dBc from DC to 70MHz. A user select allows optimized SINAD vs SFDR for a particular input frequency range. The encode clock supports either differential or singleended input and is PECL compatible and an output data format select option of two's complement or offset binary are also supported. Fabricated on an advanced BiCMOS process, the AD9433 is available in a 52 pin surface mount plastic package (52 LQFP) specified over the industrial temperature range (- 40C to +85C) and is pin compatible with the AD9432.
REV. PrD 12/19/2000 10:46 AM
1
Analog Devices Preliminary Specification
Characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing or sale of this product. Last Revision TBD. For latest specification e-mail highspeed.converters@analog.com .
PRELIMINARY TECHNICAL DATA AD9433
DC SPECIFICATIONS (VDD = 3.3 V, VCC = 5.0 V; external reference; differential encode input, unless otherwise noted)
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error1 Differential Nonlinearity (DNL) Integral Nonlinearity (INL) REFERENCE Internal Reference Voltage (VREFOUT) Output Current (VREFOUT) Input Current (VREFIN) Input Resistance (VREFIN) ANALOG INPUTS Differential Input Voltage Range (AIN, AIN) Baseband, IF Sampling I Modes IF Sampling II Mode Common Mode Voltage Input Resistance Input Capacitance Analog Bandwidth, Full Power TEMPERATURE DRIFT Offset Error Gain Error1 Reference SWITCHING PERFORMANCE Encode Rate Encode Pulse Width High (t EH ) Encode Pulse Width Low (t EL ) Aperture Delay (t A ) Aperture Uncertainty (Jitter) Output Valid Time (t V )2 Output Propagation Delay (t PD )2 Output Rise Time (t R) Output Fall Time (t F) Out of Range Recovery Time Transient Response Time Latency DIGITAL INPUTS Encode Input Common Mode Differential Input (ENC - ENC) Input Voltage Range Input Resistance Input Capacitance POWER SUPPLY VCC VDD Power Dissipation3 Power Supply Rejection Ratio (PSRR) IVCC3 IVDD 3 Temp Test Level AD9433-105 Min Typ Max 12
Guaranteed
AD9433-125 Min Typ Max 12
Guaranteed
Unit Bits
Full Full 25C 25C Full 25C Full 25C Full Full Full
VI VI I I VI I VI I V V V
-5 -0.6
0 1 0.25 0.5
+5 +0.6
-5 -0.6
0 1 0.3 0.5
+5 +0.6
mV % FS LSB LSB
2.4
2.5
2.6
2.4
2.5
2.6
V uA uA k
Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C Full Full Full Full 25C 25C Full Full Full Full Full 25C Full Full Full 25C Full Full
V V V V V V V V V VI VI VI V V VI VI V V V V IV V V IV VI V IV IV VI I VI VI
2
2.0 1.0 4.0 3 3 750
4
2.0 1.0 4.0 3 3 750
V V V k pF MHz ppm/ C ppm/ C ppm/ C 125 5.6 5.6 Msps ns ns ns ps rms ns ns ns ns ns ns Cycles V mV V k pF 5.25 3.3 V V mW mV/V mA mA
150 50 1 2.9 2.9 0.25 4.0 4.0 2.1 1.9 2 2 10 3.75 500 -0.5 6 3 4.75 2.7 5.0 1250 5 250 12.5 5.25 3.3 4.75 2.7 -0.5 105 6.7 6.7 1 2.4 2.4
150 50
0.25 4.0 4.0 2.1 1.9 2 2 10 3.75 500 6 3 5.0 1350 270 16
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PRELIMINARY TECHNICAL DATA AD9433
DC SPECIFICATIONS continued (VDD = 3.3 V, VCC = 5.0 V; external reference; differential encode input, unless otherwise noted)
Parameter DIGITAL OUPUTS Logic "1" Voltage Logic "0" Voltage Output Coding Temp Full Full Test Level VI VI AD9433-105 Min Typ Max
VDD-0.05
Mi n
AD9433-125 Typ Max
VDD-0.05
Unit V V
0.05
Twos Compliment or Offset Binary
0.05
AC SPECIFICATIONS (VDD = 3.3 V, VCC = 5.0 V; internal reference; differential encode input, unless otherwise noted)
Parameter DYNAMIC PERFORMANCE4 Signal to Noise Ratio (SNR) (Without Harmonics) fIN=10.3MHz fIN=49MHz fIN=70MHz fIN=150MHz fIN=250MHz Signal to Noise Ratio (SINAD) (With Harmonics) fIN=10.3MHz fIN=49MHz fIN=70MHz fIN=150MHz fIN=250MHz Effective Number of Bits fIN=10.3MHz fIN=49MHz fIN=70MHz fIN=150MHz fIN=250MHz 2nd & 3rd Harmonic Distortion(SNR) fIN=10.3MHz fIN=49MHz fIN=70MHz fIN=150MHz fIN=250MHz Worst other Harmonic or Spur (Excluding 2nd & 3rd ) fIN=10.3MHz fIN=49MHz fIN=70MHz fIN=150MHz fIN=250MHz Two Tone Imtermod Distortion (IMD) fIN1=29.3MHz, fIN2=30.3MHz fIN1=150MHz, fIN2=151MHz fIN1=250MHz, fIN2=251MHz Temp Test Level AD9433-105 Min Typ Max
Guaranteed
AD9433-125 Min Typ Max
Guaranteed
Units
25C 25C 25C 25C 25C
I I I V V
68.0 66.8 67.0 65.5 63.5.5
67.5 65.0 64.5 62.0 60.0
dB dB dB dB dB
25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C
I I I V V I I I V V I I I V V
67.8 67.2 66.5 65.0 63.0 11.0 11.0 10.8 10.6 10.2 85 85 80 80 75
67.2 65.4 63.6 60.0 57.0 10.4 10.4 10.2 9.8 9.5 83 80 80 80 75
dB dB dB dB dB Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc
25C 25C 25C 25C 25C 25C 25C 25C
I I I V V V V V
90 90 90 90 90
90 85 85 83 80
dBFS dBFS dBFS dBFS dBFS dBc dBc dBc
NOTES 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input). 2 t V and t PD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of 40 i A. Rise and fall times measured from 10% to 90%. 3 Power dissipation measured with rated encode and a dc analog input (Outputs Static, IVDD = 0.). IVCC and IVDD measured with 10.3MHz analog input @ 0.5dBFS. Typical JA for LQFP package = 50C/W. 4 SNR/harmonics based on an analog input voltage of -0.5 dBFS referenced to a 2 V full-scale input range.
Specifications subject to change without notice. REV. PrD 12/19/2000 10:46 AM
3
Analog Devices Preliminary Specification
Characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing or sale of this product. Last Revision TBD. For latest specification e-mail highspeed.converters@analog.com .
PRELIMINARY TECHNICAL DATA AD9433
ABSOLUTE MAXIMUM RATINGS 1
Parameter ELECTRICAL VDD Voltage VCC Voltage Analog Input Voltage Analog Input Current Digital Input Voltage Digital Output Current ENVIRONMENTAL 6 Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Maximum Case Temperature Storage Temperature Range (Ambient) Min -0.5 -0.5 -0.5 TBD Max 6.0 6.0 VCC +0.5 TBD VCC +0.5 20 Units V V V mA V mA C C C C C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
-55
-65
125 175 TBD 150 150
EXPLANATION OF TEST LEVELS Test Level I 100% production tested. II 100% production tested at +25C and guaranteed by design and characterization at specified temperatures. III Sample Tested Only IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at +25C and guaranteed by design and characterization for industrial temperature range.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9433 features proprietary protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE Model AD9433BST -105 AD9433BST -125 AD9433/PCB
Temperature Range -40C to +85C (Ambient) -40C to +85C (Ambient) +25C
Package Description 52-Lead Plastic Quad Flatpack 52-Lead Plastic Quad Flatpack Evaluation Board with AD9433-125
Package Option ST-52 ST-52
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PRELIMINARY TECHNICAL DATA AD9433
PIN FUNCTION DESCRIPTIONS
Pin No. 1,3,4,9,11,12,33,34,35, 38,43,48,51 2,5,6,10,36,37,44,47,52 7 8 14 15-20, 25-30 13,22,23,32 21,24,31 39 40 41 42 Name GND Vcc ENCODE ENCODE OR D11-0 Vdd DGND SELECT#1 SELECT#2 DFS SFDR MODE Function Analog Ground Analog Supply (+5V) Encode Clock for ADC - Complementary Encode Clock for ADC - True - (ADC samples on rising edge of ENCODE) Out of Range Output. Digital Output Digital Output Power Supply (+3V) Digital Output Ground User select option #1 User select option #2 Data format select. Low = Two's compliment, High = Binary CMOS control pin that enables (SFDR MODE=1) a proprietary circuit that may improve the spurious free dynamic range (SFDR) performance of the AD9433. It is useful in applications where the dynamic range of the system is limited by discrete spurious frequency content caused by non-linearities in the ADC transfer function. SFDR MODE=0 for normal operation. Reference input for ADC (2.5V typical) Internal reference output (2.5V typical); bypass with 0.1uF to Ground. Analog input - True Analog input - Complement
SFDR MODE
45 46 49 50
VREFIN VREFOUT AIN AIN
52
51
50
49
48
47
46
45
44
43
42
41
GND VC C GND GND
1 2 3 4
40 39 38 37 36 35
SELECT#2
VREFOUT
VREFIN
GND
GND
GND
DFS
AIN
AIN
VC C
VC C
VC C
SELECT#1 GND VC C VC C GND GND GND VD D DGND D0 (LSB) D1 D2 D3
V CC 5 VC C ENCODE ENCODE GND VC C GND 6 7 8 9 10 11
AD9433BST TOP VIEW (not to scale)
34 33 32 31 30 29 28 27
DGND 12 VD D 13 O R 14 15 D 1 0 16 17 18 19 20 DGND 21 22 23 DGND 24 25 D5 26 D4
D9
D8
D7
D6
VD D
(MSB) D11
PIN CONFIGURATION
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. REV. PrD 12/19/2000 10:46 AM
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Analog Input Resistance, Differential Analog Input Capacitance and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. 5 Analog Devices Preliminary Specification
Characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing or sale of this product. Last Revision TBD. For latest specification e-mail highspeed.converters@analog.com .
VD D
PRELIMINARY TECHNICAL DATA AD9433
DEFINITIONS OF SPECIFICATIONS (cont'd)
Differential Analog Input Voltage Range The peak to peak differential voltage that must be applied to the converter to generate a fullscale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak to peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. Then the difference is computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits The effective number of bits (ENOB) is calculated from the measured SNR based on the equation:
FullScale _ Amplitude SNRMEASURED - 1.76dB + 20 log( ) Input _ Amplitude ENOB = 6.02
Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The maximum encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Noise (for any range within the ADC)
FS dBm - SNRdBc - SignaldBFS 10
Vnoise = Z * .001 *10
Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic "1" state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing t ENCH in text. At a give clock rate, these specs define an acceptable Encode duty cycle. Fullscale Input Power Expressed in dBm. Computed using the following equation:
2 VFullscalerms Z Input PowerFullscale = 10 log .001
Where Z is the input impedance, FS is the fullscale of the device for the frequency in question, SNR is the value for the particular input level and Signal is the signal level within the ADC reported in dB below fullscale. This value includes both thermal and quantization noise. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 1dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but ex cluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e. degrades as signal level is lowered), or dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone (f1, f2) to the rms value of the worst third order intermodulation product; reported in dBc. Products are located at 2f1-f2 and 2f2-f1. Two-Tone SFDR The ratio of the rms value of either input tone (f1, f2) to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e. degrades as signal level is lowered), or in dBFS (always related back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the 2nd and 3rd harmonic) reported in dBc.

Gain Gain error is the difference between the measured and ideal full scale input voltage range of the ADC. Harmonic Distortion, 2 nd The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, 3 rd The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
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PRELIMINARY TECHNICAL DATA AD9433
Timing Diagram
Sample N Sample N-1 Sample N+9 Sample N+10
AIN
tA t EH tEL Sample N+1 Sample N+8 1/ f
S
ENCODE
ENCODE
t PD tV
D11-D0
Data N-10
Data N-9
N-8
N-2
Data N-1
Data N
Data N+1
AD9433 Timing Diagram
Equivalent Circuits
VD D V CC
V CC
VREFIN DX
VREFOUT
Figure TBD. Digital Output
VC C 3.75K A IN A IN 15K 15K 3.75K
Figure TBD. Reference Output
VC C
8K 8K
Figure TBD. Reference Input
+ ENCODE ENCODE
24K
24K
Figure TBD. Analog Input
Figure TBD. Encode Inputs
REV. PrD 12/19/2000 10:46 AM
7
Analog Devices Preliminary Specification
Characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing or sale of this product. Last Revision TBD. For latest specification e-mail highspeed.converters@analog.com .
PRELIMINARY TECHNICAL DATA AD9433
TYPICAL PERFORMANCE CURVES
0 -20 Signal Level (dBFS) -40 -60 -80 -100 -120 0 25 Frequency (MHz) 50
Encode: 100Msps AIN: 30.3MHz @ 0.5dBFS SNR: 67.0dB ENOB: 10.85 Bits
0 -20 Signal Level (dBFS) -40 -60 -80 -100 -120 0 25 Frequency (MHz) 50
Encode: 100Msps AIN: 240.3MHz @ 0.5dBFS SNR: 61.5dB ENOB: 9.7 Bits
FFT: 100MSPS, 30.3MHz @ -0.5dBFS, Baseband Mode, SFDR MODE Enabled
FFT: 100MSPS, 240.3MHz @ -0.5dBFS, IF II Mode, SFDR MODE Enabled
0
0 Signal Level (dBFS) Signal Level (dBFS) -20 -40 -60 -80 -100 -120 0 25 Frequency (MHz) 50
Encode: 100Msps AIN: 140.3MHz @ 0.5dBFS SNR: 65.0dB ENOB: 10.5 Bits
-20 -40 -60 -80 -100 -120 0
Encode: 100Msps AIN: 396MHz @ -0.5dBFS SNR: 60.0dB ENOB: 8.8 Bits SFDR: 84dBFS
25 Frequency (MHz)
50
FFT: 100MSPS, 140.3MHz @ -0.5dBFS, IF I Mode, SFDR MODE Enabled
FFT: 100MSPS, 396MHz @ -0.5dBFS, IF II Mode, SFDR MODE Enabled
PrD 12/19/2000 10:46 AM
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PRELIMINARY TECHNICAL DATA AD9433
Theory of Operation The AD9433 is a multibit pipeline converter that uses a switched capacitor architecture. Optimized for high speed, this converter provides flat dynamic performance up to and beyond the Nyquist limit. DNL transitional errors are calibrated at final test to a typical accuracy of 0.25 LSB or less. USING THE AD9433
ENCODE Input
0.1uF
AD9433
ENCODE
0.1uF 50 SINE SOURCE
ENCODE
50 25
Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track/hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD9433, and the user is advised to give commensurate thought to the clock source. The AD9433 has an internal clock duty cycle stabilization circuit that locks to the rising edge of ENCODE (falling edge of ENCODE if driven differentially), and optimizes timing internally. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern, and is not reduced by the internal stabilization circuit. The ENCODE and ENCODE inputs are internally biased to 3.75V (nominal), and support either differential or single ended signals. For best dynamic performance, a differential signal is recommended. Good performance is obtained using an MC10EL16 in the circuit to directly drive the encode inputs, as illustrated in Fig. TBD.
AD9433
ENCODE
PECL GATE
ENCODE Voltage Level Definition
Figure TBD. Single ended 50 Sine Source Encode Circuit
The voltage level definitions for driving ENCODE and ENCODE in single-ended and differential mode are shown in Figure TBD. ENCODE Inputs
Description Differential Signal Amplitude (VID) Input Voltage Range (VIHD,VILD,VIHS,VILS) Internal Common Mode Bias (VICM) External Common Mode Bias (VECM)
ENCODE VI H D V ID V I C M ,V EC M ENCODE VI L D
Minimum 200mV -0.5V
Nominal 750mV
Maximum 5.5V VCC +0.5V
3.75 V 2.5V 4.5V
ENCODE
VI H S V I C M ,V E C M
ENCODE 0.1uF V ILS
ENCODE
5 1 0 510
Analog Input
Figure TBD. Differential and Single Ended Input Levels
Figure TBD. Using PECL to drive the ENCODE Inputs Often, the cleanest clock source is a crystal oscillator producing a pure, single ended sine wave. In this configuration, or with any roughly symmetrical, single ended clock source, the signal can be ac-coupled to the ENCODE input. To minimize jitter, the signal amplitude should be maximized within the input range described in Table TBD. The ENCODE input should be bypassed with a capacitor to ground to reduce noise. This ensures that the internal bias voltage is centered on the encode signal. For best dynamic performance, impedances at ENCODE and ENCODE should match.
The dynamic performance of the AD9433 can be optimized for different signal bandwidths by configuring the mode of the analog input circuit. CMOS inputs SELECT#1 and SELECT#2 optimize performance and analog input voltage swing as defined in the table below. Table X. Setting the Analog Input Circuit Mode
Mode Differential Analog Input Range () 2Vp-p 1Vp-p 2Vp-p Optimize d Analog Bandwidt h (MHz) 100 - 250 250 - 350 DC to 100 SELECT #1 (Pin 39) SELECT #2 (Pin 40)
IF Sampling I IF Sampling II Baseband
0 1 0
0 1 1
REV. PrD 12/19/2000 10:46 AM
9
In all modes, the analog input to the AD9433 is a differential buffer. The input buffer is self-biased by an on-chip resistor divider that sets the dc common-mode voltage to a nominal 4V (see Equivalent Circuits section). Rated performance is achieved by driving the input differentially. Minimum input offset voltage is obtained when driving from a source with a low differential source impedance such as a transformer in ac applications (See figure TBD). Capacitive coupling at the inputs will increase the input offset voltage by as much as 25 mV. Analog Devices Preliminary Specification
Characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing or sale of this product. Last Revision TBD. For latest specification e-mail highspeed.converters@analog.com .
PRELIMINARY TECHNICAL DATA AD9433
AIN 25 W 0 . 1 50

transfer function may be inappropriate for some time domain applications of the converter. Connecting the SFDR MODE pin to ground will disable this function. The typical performance curves section of the data sheet illustrates the improvement in the linearity of the converter and it's effect on spurious free dynamic range. Digital Outputs
AD9433
1:1 25 AIN
Figure TBD. Transformer-Coupled Analog Input Circuit In the highest frequency applications, two transformers connected in series may be necessary to minimize even order harmonic distortion. The first transformer will isolate and convert the signal to a differential signal, but the grounded input on the primary side will degrade amplitude balance on the secondary winding. This imbalance is caused by capacitive coupling between the windings. Since one input to the first transformer is grounded, there is little or no capacitive coupling, resulting in an amplitude mismatch at the first transformers output. A second transformer will improve the amplitude balance, and thus improve the harmonic distortion. A wideband transformer, such as the ADT1-1WT from Mini Circuits, is recommended for these applications, as the bandwidth through the two transformers will be be reduced by the 2.
The digital outputs are 3V (2.7 V to 3.3 V) TTL/CMOScompatible for lower power consumption. The output data format is selectable through the data format select (DFS) CMOS input. DFS=1 selects offset binary; DFS=0 selects two's compliment coding.
Code 4095 * * 2048 2047 * * 0 Table TBD. Offset Binary Output Coding (DFS=1, VREF =+2.5V) AIN-AIN (V) AIN-AIN (V) Digital Range=2Vp-p Range=1Vp-p Output 1.000 0.500 1111 1111 1111 * * * * * * 0 0 1000 0000 0000 -0.00049 -0.000245 0111 1111 1111 * * * * * * -1.000 -0.5000 0000 0000 0000
AIN 25 0.1F
50 Analog Signal Source 1:1 1:1
AD9433
25 AIN
Table I. Two's Complement Output Coding (DFS=0, VREF =+2.5V) Code AIN-AIN (V) AIN-AIN (V) Digital Range=2Vp-p Range=1Vp-p Output +2047 1.000 0.500 0111 1111 1111 * * * * * * * * 0 0 0 0000 0000 0000 -1 -0.00049 -0.000245 1111 1111 1111 * * * * * * * * -2048 -1.000 -0.5000 1000 0000 0000 Voltage Reference
Figure TBD. Driving the Analog Input with 2 transformers for improved even order harmonics Driving the ADC single-ended will degrade performance, particularly even order harmonics. For best dynamic performance, impedances at AIN and AIN should match. Special care was taken in the design of the analog input section of the AD9433 to prevent damage and corruption of data when the input is overdriven. When the nominal input range is set for 2.0Vp-p, each analog input will be 1 V p-p when driven differentially. When set for 1.0Vp-p, each analog input will be 0.5Vp-p when driven differentially.
SFDR Optimization The SFDR MODE pin enables (SFDR MODE=1) a proprietary circuit that may improve the spurious free dynamic range (SFDR) performance of the AD9433. It is useful in applications where the dynamic range of the system is limited by discrete spurious frequency content caused by non-linearities in the ADC transfer function. Enabling this circuit will give the circuit a dynamic transfer function, meaning that the voltage threshold between two adjacent output codes may change from clock cycle to clock cycle. While improving spurious frequency content, this dynamic aspect of the
A stable and accurate 2.5 V voltage reference is built into the AD9433 (VREFOUT). In normal operation the internal reference is used by strapping Pin 45 to Pin 46 and placing a 0.1 F decoupling capacitor at VREFIN. The input range can be adjusted by varying the reference voltage applied to the AD9433. No appreciable degradation in performance occurs when the reference is adjusted 5%. The full-scale range of the ADC tracks reference voltage changes linearly.
Timing
The AD9433 provides latched data outputs, with 10 pipeline delays. Data outputs are available one propagation delay (t PD ) after the rising edge of the encode command (see Timing Diagram). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9433; these transients can detract from the converter's dynamic performance. The minimum guaranteed conversion rate of the AD9433 is 1 MSPS. At internal clock rates below 1 MSPS, dynamic performance may degrade.
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PRELIMINARY TECHNICAL DATA AD9433
Replacing the AD9432 with the AD9433 The AD9433 is pin compatible with the AD9432, although there are 4 control pins on the AD9433 that are "do not connect (DNC), supply (VCC) or ground connections on the AD9432. They are summarized in the table below. Pin # AD9432 AD9433 39 GND SELECT #1 40 GND SELECT #2 41 DNC DFS 42 VCC SFDR MODE Using the AD9433 in an AD9432 pin assignment will configure the AD9433 as follows: * SELECT #1 and SELECT # 2 will both be connected to ground, putting the device in IF Sampling I mode (2V differential analog input range, performance optimized for 100-250MHz). * The SFDR improvement circuit will be enabled. * The DFS pin will float LOW, selecting Two's Compliment coding for the digital outputs. Other differences between the AD9432 and AD9433 are summarized as follows: Attribute ENCODE / ENCODE VCOMMON MODE AIN / AIN VCOMMON MODE AD9432 1.6V 3.0V AD9433 3.75V 4.0V
AD9433BST OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
ST-52 Package
REV. PrD 12/19/2000 10:46 AM
11
Analog Devices Preliminary Specification
Characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing or sale of this product. Last Revision TBD. For latest specification e-mail highspeed.converters@analog.com .

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