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W86L388D Winbond Host Interface SD/MMC Memory Card Bridge
W86L388D Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 9 10 Dates 08/2001 Version 0.50 Version on Web First published. Main Contents
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W86L388D
Preliminary Table of Content
1. GENERAL DESCRIPTION.............................................................................................................................1 2. FEATURES........................................................................................................................................................1 3. PIN CONFIGURATION ..................................................................................................................................2 4. PIN DESCRIPTIONS .......................................................................................................................................3 5. BLOCK DIAGRAM..........................................................................................................................................5 5.1 BLOCK DIAGRAM ...........................................................................................................................................5 6. REGISTER ........................................................................................................................................................6 7. FUCNTIONAL DESCRIPTION......................................................................................................................8 7.1 HOST INTERFACE............................................................................................................................................8 7.2 CARD INSERTING AND REMOVING ................................................................................................................13 7.3 RESET ACTION..............................................................................................................................................13 7.4 CLOCK SOURCE ............................................................................................................................................14 8. ELECTRICAL CHARACTERISTICS .........................................................................................................15 8.1 MAXIMUM RATINGS* ...................................................................................................................................15 8.2 RECOMMENDED OPERATING CONDITIONS....................................................................................................15 8.3 POWER SUPPLY CHARACTERISTICS ..............................................................................................................15 8.4. DIGITAL CHARACTERISTICS ........................................................................................................................16 8.5. TIMING CHARACTERISTICS ..........................................................................................................................16 9. HOW TO READ THE TOP MARKING ......................................................................................................22 10.PACKAGE DIMENSIONS ...........................................................................................................................23 11. REFERENCE SCHEMATIC .......................................................................................................................24
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Publication Release Date: August 2001 Revision 0.50
W86L388D PRELIMINARY
1. GENERAL DESCRIPTION
The W86L388D is a SD/MMC host interface bridge used between host microprocessor and SD/MMC. The data width of host microprocessor can be 8-bit or 16-bit. W86L388D can support synchronous or asynchronous type of host interface. It also supports DMA or Interrupt type of transfer mode to improve data transfer performance between host microprocessor and SD/MMC. W86L388D is fit for most of IA devices, such as PDA, Cellular Phone, DSC, and MP3 player.
2. FEATURES
* * * * * * * * * * Compliant with SD spec. Version 1.0 Compliant with MMC spec. Version 2.2 Support two types of host microprocessor interface access--synchronous and asynchronous mode DMA and Interrupt transfer mode supported Host microprocessor 8/16 bit data bus Built-in crystal driver circuit, support external oscillator or crystal clock Extra 5 programmable GPIO supported Wide range of clock input from 3.58MHz up to 25MHz 3.3V opereation 48-pin LQFP package
Ordering Information
Part Number W86L388D Package Type 48-PIN LQFP Production Flow Commercial, 0oC to +70oC
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Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
3. PIN CONFIGURATION
XDAKN/XASN
XCSN
XDRQN/XRDYN
XWRLN/XBE1
XWRHN/XBE0
XRDN/XRWN
HCKI
GIO0
GIO1
26
36
35
34
33
32
VSS
A3
31
30
29
28
27
A2 A1 XTYP2 D15/A0 D14 VSS VDD D13 D12 D11 D10 D9
37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11
GIO2
25 24 23 22 21 20 19 18 17 16 15 14 13 12
GIO3 GIO4 SD6 SD5 SD4 VDD VSS SD3 SD2 SD1 XTO XTI
D8
D7
D6
D5
D4
D3
D2
D1
D0
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XINTN
Publication Release Date: August 2001 Revision 0.50
RSTN
VSS
W86L388D
Preliminary
4. PIN DESCRIPTIONS
Pin SD Interface: 21 22 15 16 17 20 13 14 28 35 36:38 40 SD5 SD6 SD1 SD2 SD3 SD4 XTI XTO HCKI XCSN A[3:1] D15/A0 DO/DI DO/DI DO/DI DO/DI DO DO DI DO DI DI DI DI/DO SD connection #5 SD connection #6 SD connection #1 SD connection #2 SD connection #3 SD connection #4 Clock driver input signal, may be used as external clock input. Clock driver output signal. Host clock input. Chip select input pin, active low. Address input pins. Data bus D15 pin, D[15:8] is the high byte of the data bus, D15 also used as A0 when 8-bit CPU data size. In 8-bit mode, internal register high byte (D15:8) will accessed at data bus [7:0] when A0 = 1, low byte (D7:0) will accessed at data bus [7:0] when A0 = 0. Data bus D14 pin. Data bus [13:9] pins. Data bus [8:4] pins, D[7:0] is the low byte of the data bus. Data bus [3:0] pins. Type 1: High byte (D15 to D8) write control pin, active low. Type 2: High byte (D15 to D8) data valid pin, active low. Type 1: Low byte (D7 to D0) write control pin, active low. Type 2: Low byte (D7 to D0) data valid pin, active low. Name Type Description
Crystal Driver:
Host Interface Signal:
41 44:48 1:5 7:10 33
D14 D[13:9] D[8:4] D[3:0] XWRHN/ XBE0
DI/DO DI/DO DI/DO DI/DO DI
34
XWRLN/ XBE1
DI
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Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
4. PIN DESCRIPTIONS, CONTINUED
Pin 32
Name XRDN/ XRWN DI
Type Type 1:
Description Read control pin, active low. Type 2: Read write control pin, 1: read 0: write
11 30
XINTN XDAKN/ XASN
DO DI
Interrupt request pin,active low. Type 1: DMA transfer acknowledge pin, active low. Type 2: Bus access cycle start pin, active low.
29
XDRQN/ XRDYN
DO
Type 1: DMA transfer request pin, active low. Type 2: Bus cycle complete pin, active low.
39
XTYP2
DI
Host interface type 2 select pin, 0 : type 1 mode. 1 : type 2 mode.
General I/O Port Signal (SD I/F): 27:23 GIO[0:4] DI/DO 5-bit general input output port signals. GIO0 pin can be used as dedicate card detecttion. Reset input, hardware reset input, active low. Power supply 3.3V Ground
Other Signal: 12 Power: 19,43 6,18, 31,42 Type: DP is Power, DI is Digital Input, DO is Digital Output. VDD VSS DP DP RSTN DI
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Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
5. BLOCK DIAGRAM
5.1 Block Diagram
HCKI
XTYP2
RSTN
VDD
VSS
XCSN A[3:1] XASN XRDYN XWRLN/XBE1 XWRHN/XBE0 XRDN/XRWN
Address Decode
Host I/F Type Select
General Port Registers SD Access Circuit
GIO[4:0]
Read /Write Controller
Register File
17 Byte Rsp Reg
SD4
D[15:0]/ D[7:0]
6 Byte CMD Reg Data Packing Circuit 8 Byte FIFO 8 Byte FIFO
Serial to Parallel or Parallel to Serial Serial to Parallel or Parallel to Serial
Command Response Data Packing Circuit
SD3
SD1,SD2 SD5,SD6
XDRQN XDAKN XINTN
DMA Circuit Interrupt Circuit
Crystal Driver
XTI
XTO
Fig. 5-1 Block Diagram of W86L388
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Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
6. REGISTER
The registers in the W86L388 are direct access registers and indirect access registers. The direct access registers and indirect access registers are listed as follows:
Addr A[3:1] Register Name (note 1) B 15 B 14 B 13 B 12 B 11 B 10 Content (note 2) B 9 B 8 B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0
Direct Access Registers: 000 Command Pipe Reg. (WO) Response Reg. (RO) 001 001 010 010 011 011 100 100 101 101 110 111 Status Reg. (RO) 0 Control Reg. (R/W) Receive Data Buffer (R/O) Transmit Data Buffer (WO) Interrupt Status Reg. (RC) Interrupt Enable Reg. (R/W) General I/O Port Data Reg. (R/W) General I/O Port Control Reg. (R/W) General IP Interrupt Status Reg. (RC) General IP Interrupt Enable Reg. (R/W) Index Address Reg. (R/W) Index Data Register X X X X X X 0 0 Command pipe registers / Response registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 X 0 0 X 0 0 X 0 0 X 0 0 X 0 GIO data 0 0 0 X X X X X 0 GIO interrupt status 0 0 0 0 0 0 0 0 0 0 X X X 0 X 0 X 0 0 GIO interrupt enable 0 0 X 0 0 X 0 0 X 0 0 X 0 0 X Index address 0 0 0 GIO control 0 0 0 0 0 X 0 0 X 0 0 0 Interrupt enable 0 0 0 1 1 0 0 X 0 0 X 0 0 X Control 0 0 X 0 0 X 0 0 X 1 0 X 0 0 X 0 0 0 0 0 0 0 -
Status 0 1 -
Receive data buffer Transmit data buffer Interrupt status
Index data register
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W86L388D
Preliminary
continued
Addr A[3:1]
Register Name (note 1) B 15 B 14 B 13 B 12 B 11 B 10
Content (note 2) B 9 B 8 B 7 0 0 0 0 0 0 1 Setting register 1 0 1 0 0 1 Test 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 1 Data length 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 80 0 1 Nac time out register 0 0 1 0 0 1 0 0 1 0 0 Status F 0 B 6 B 5 B 4 B 3 B 2 B 1 B 0 -
Indirect Access Registers: 000 000 001 010 011 100 Extend Status Reg. (RO) Setting Reg. (R/W) Data Format Register (R/W) Nac Time-out Register (R/W) Error Status Reg. (RO) Ready & Data Size Register (R/W) Extend status 0 W 0 0 0 0 0 0 0 0 -
Note 1: R/W means the register can be read and write. RO means the register is read only. RC means the register is read only and read clear. WO means the register is write only. Note 2: The data bit in the content is the initial value during hardware reset. 0: the bit value is 0. 1: the bit value is 1. X: the bit value is unknow. -: Undefined bit in the register and the value will read 0.
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Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
7. FUCNTIONAL DESCRIPTION
7.1 Host Interface
The Host interface type may be type 1 or type. The read cycle always 16-bit access and the write cycle may be 16-bit access or high byte or low byte access. Host Interface Type 1: The Host interface type 1 is selected when XTYP2 pin is low. Figure 7-1 shows the timing of CPU read and write in type 1. Figure 7-2 is the timing of CPU write high byte and write low byte.
A[3:1] D[15:0] XCSN XRDN XWRHN XWRLN
DO[15:0] DI[15:0]
Fig. 7-1 16-bit Read and Write Access in Host I/F Type 1.
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W86L388D
Preliminary
A[3:1] D[15:0] XCSN XWRHN XWRLN
DI[15:8] DI[7:0]
Fig. 7-2 High Byte and Low Byte Write Access in Host I/F Type 1.
Host Interface Type 2: The Host interface type 2 is selected when XTYP2 pin is high. Figure 7-3 shows the timing of CPU read write in type 2 and the access cycle is 3-cycle access, figure 7-4 shows the timing of CPU read write in type 2 and the access cycle is 2-cycle access.
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W86L388D
Preliminary
HCKI A[3:1] D[15:0] XCSN XASN XRDYN XRWN XBE[1:0]
Read cycle Write cycle DO[15:0] DI[15:0]
Fig. 7-3 Read and Write Timing in Host I/F Type 2, 3-Cycle Access.
HCKI A[3:1] D[15:0] XCSN XASN XRDYN XRWN XBE[1:0]
Read cycle Write cycle DO[15:0] DI[15:0]
Fig. 7-4 Read and Write Timing in Host I/F Type 2, 2-Cycle Access.
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W86L388D
Preliminary
DMA Access: DMA request XDRQN is used to notify the Host that the Host should write data to the transmit data buffer or read data from the receive data buffer in data write to the card or data read from the card. During data transmit to the card, the XDRQN will active if the data write command has been transfer to the card and the transmit data buffer have not enough data to transmit to the card. The XDRQN will not active if the transmit data buffer have enough data to transmit to the card. During data receive from the card, the XDRQN will active if the data read command has been transfer to the card and the data have been received in the receive data buffer. The XDRQN will not active if the data read command has been executed completedly and the receive data buffer is read out. There are two types of DMA acknowledge waveform, the first type is configured if DAKEN = low, XDAKN is ignore and XDRQN will inactive after each access receive or transmit data buffer, the XDRQN will re-active after four clock later. Figure 7-5 shows the waveform of DMA access receive data buffer in DAKEN = low. The second type is configured if DAKEN = high, XDAKN is used to count the transfer count of the data buffer, XDRQN will hold at active state until the data has been transferred completedly. Figure 7-6 is the waveform of DMA access transmit data buffer in DAKN = high.
System Clock A[3:1] D[15:0] XCSN XRDN XDRQN XDAKN
010 010
Fig. 7-5 DMA Access Receive Data Buffer (DAKEN = low).
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W86L388D
Preliminary
System_ Clock A[3:1] D[15:0] XCSN XWRHN XWRLN XDRQN XDAKN
010 010
Fig. 7-6 DMA Access Transmit Data Buffer (DAKEN = high).
Interrupt: Interrupt pin XINTN will active (low) at the falling edge of system clock if any bit in the interrupt register is high, the XINTN pin will return to high when read the interrupt register and if the interrupt source is not existed. Figure 7-7 is the timing of interrupt.
System_ Clock A[3:1] D[15:0] XCSN XRDN XINTN
011
Fig. 7-7 Timing of Interrupt in.
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Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
7.2 Card Inserting and Removing
There are two method for Host to detect SD/MMC card inserting or removing through W86L388, the first method is detected by CD/DAT3 pin, the second method is a dedicate switch on the SD/MMC slot can be connected to the GIO0 pin and set GIO0 to input direction. These two methods can be performed even if the W86L388 is in power down state. Method 1, CD/DAT3 as card detection: The CD/DAT3 of SD bus can be used as card detection if no data transfer on the DAT3, if SIEN bit on the control register is low and INS_IE and INT_E on the interrupt enable register are all high, card inserting or removing will generate interrupt. Host must read the interrupt status register and re-check the card state by read the CD bit on the extend status register. This detection method will not effective when wide bus on the SD bus is transfer. MMC card may not support this detection method. Method 2, GIO0 as card detection: Some SD/MMC slot support external switch for card existing detection, the switch will on when SD or MMC is exist. GIO0 with a pull high resister can be used as card detection, the Host can disable the GOEN0 bit on the general I/O port control register and enable the GIT_EN0 bit on the general I/O port interrupt enable register and enable GIT_IE and INT_E bits on the interrupt enable register. SD or MMC card inserting or removing will change the switch state then change the state of GIO0 pin and then general interrupt to the Host. Host may re-check the card state by read the GIN0 bit on the general I/O port data register.
7.3 Reset Action
Hardware Reset: Hardware reset is performed by setting RSTN pin to low state for at least 1 mS. The CPU data size will set to 16-bit default, all the registers will set to default value. The receive and transmit data buffer will be cleared; all the internal logic will be reset to initial state. Software Reset: Software reset is executed by write the RST bit of the control register to 1, all the internal logic will be reset to initial state and receive and transmit data buffer will be cleared, but the content of registers are not affected. Data Buffer Reset: Data buffer reset is used to reset the receive data buffer and transmit data buffer simutaneously, the serial interface command will affected if the data receive or transmit command is progressing. Internal logic state and the content of registers are not affected. Publication Release Date: August 2001 Revision 0.50
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W86L388D
Preliminary
7.4 Clock Source
The clock source of W86L388 is the waveform of XTO pin, if crystal is connected, the frequency may be from 3.58MHz to 25MHz, if the clock source is from external clock, XTI may be used as clock input and the maximum frequency is 25MHz.
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Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
8. ELECTRICAL CHARACTERISTICS
8.1 Maximum Ratings*
Parameter 1 2 3 Supply Voltage with respect to VVSS Current at any pin other than supplies Storage Temperature * Exceeding these values may cause permanent damage. Tst Symbol VVDD Rating -0.3 to 6 0 to 10 -65 to 150 Units V mA
8.2 Recommended Operating Conditions
Characteristics 1 Operation Voltage (referenced to VSS pin). 2 Operation Voltage (referenced to VSS pin) (Note) 3 Clock Frequency at XTI pin 4 Operation Temperature Note: Clock frequency not guaranteed up to 25MHz. Symbol VVDD VVDD fXTL Top Rating 3.0 to 3.6 2.7to 3.0 25 0 to 70 Unit V V MHz
8.3 Power Supply Characteristics
Parameter 1 Standby Supply Current 2 Operating Supply Current 3 Operating Supply Current Condition Power Supply (VVDD = 3.3V) Symbol IQ IVDD IVDD Min Typ 2 TBD TBD Max 20 TBD Units uA mA mA Test Test 1 Test 2 Test 3
: Typical figure are at VDIVDD = 3.3V and temperature = 25 and are for design aid only, not guaranteed and not subject to production testing. Test 1: All input pins are VVDD or VVSS, configured as power down mode, output without loading and no clock input on the XTI and HCKI pins. Test 2: 20 MHz external clock input on the XTI pin, output without loading. Test 3: 20 MHz crystal connected at XTI and XTO pins, output without loading.
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Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
8.4. Digital Characteristics
Parameter 1 Output High Voltage 2 Output Low Voltage 3 Output High Voltage at SD4 output 4 Output Low Voltage at SD4 output 5 High Level Input Voltage 6 Low Level Input Voltage 7 Input Current 8 Input Capacitance Condition 2mA load 2mA sink 3mA load 3mA sink Symbol VOH VOL VOH VOL VIH VIL Iin Cin 10 0.7 0.3 1 0.9 0.1 Min 0.9 0.1 Typ Max Units VDD VDD VDD VDD VDD VDD uA pF Notes 1 1
: Typical figure are at VDVDD = 3.3V and temperature = 25 and are for design aid only, not guaranteed and not subject to production testing. Notes: 1: All output pins except SD4 output.
8.5. Timing Characteristics
Parameter Clock (figure 8-1) 1 XTI 2 XTI high pulse width 3 XTI low pulse width 4 XTI rise time 5 XTI fall time 5 XTO delay time 6 XTI crystal driver 7 HCLK frequency 8 HCLK high pulse width 9 HCLK low pulse width 10 HCLK rise time 11 HCLK fall time fXTI tXTIwh tXTIwl tXTIr tXTIf tXTOd fXTI fHCLK tHCLKwh tHCLKwl tHCLKI tHCLKf 1 10 10 3.58 1 10 10 20 5 5 5 25 40 5 5 MHz nS nS nS nS nS MHz MHz nS nS nS nS 1 1 1 1 1 2 3 Symbol Min Typ Max Units Notes
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W86L388D
Preliminary
8.5. Timing Characteristics , continued
Parameter Reset 1 RSTN Host Interface at Type 1 (figure 8-2, 8-3) 1 Access time 2 Address setup time 3 Address hold time 4 D[15:0] output delay time 5 D[15:0] output hold time 6 D[15:0] input setup time 7 D[15:0] input hold time 8 DMA request delay time 9 DMA request hold time Host Interface at Type 2 (figure 8-5) 1 Input signals setup time 2 Input signals hold time 3 Address setup time 4 Address hold time 5 XRDYN delay time 6 XRDYN hold time 7 D[15:0] output delay time 8 D[15:0] output hold time 9 D[15:0] input setup time 10 D[15:0] input hold time Interrupt (figure 8-4) 1 Interrupt delay time 2 Interrupt hold time
Symbol tRST tacc tAsu tAh tDod tDoh tDsu tDh tDRQd tDRQh tIF2su tIF2h tA2su tA2h tRDYd tRDYh tDod tDoh tDsu tDh tINTd TINTh
Min 4 100 10 5 10 10 5 5 10 5 10 5 5 10 10 5 5
Typ -
Max 30 20 20 20 30 20 20
Units cycle nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
Notes
4
5,6 5,7 8 9 2 2 10 10
2 2 5 5
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W86L388D
Preliminary
8.5. Timing Characteristics , continued
Parameter 1 SD3 output delay 3 SD3 input setup time 4 SD3 input hold time 2 SD1,SD2,SD5,SD6 output delay time 3 SD1,SD2,SD5,SD6 input setup time 4 SD1,SD2,SD5,SD6 input hold time Note 1: External clock input. Note 2: 20 pF output loading. Note 3: Crystal driver.
Symbol tSD3d tSD3Dsu tSD3h tSDnd* tSDnsu tSDnh
Min 5 10 5 10 5
Typ -
Max 15 30 -
Units nS nS nS nS nS nS
Notes 2
Serial Interface Signals (figure 8-6, 8-7, 8-8, 8-9)
2
Note 4: Minimum active pulse width of (XCSN and XRDN) or (XCSN and XWRHN and XWRLN). Note 5: 40 pF output loading. Note 6: From the last active signal of XCSN or XRDN. Note 7: From the first in-active signal of XCSN or XRDN. Note 8: To the first in-active signal of XCSN, XWRHN or XWRLN, XWRHN or XWRLN related to the D[15:8] or D[7:0]. Note 9: From the first in-active signal of XCSN, XWRHN or XWRLN, XWRHN or XWRLN related to the D[15:8] or D[7:0]. Note 10: XCSN, XASN, XRWN and XBE[1:0] signals. Note 11: SDn: SD1, SD2, SD5, SD6
XTI
tXTOd
tXTIwh tXTIf
tXTIwl tXTIr
XTO
HCKI
tHCKIr
tHCKIwh tHCKIf
tHCKIwl
Fig. 8-1 Timing Characteristic of XTI, XTO and HCKI.
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Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
A[3:1]
tAsu tAh
DO[15:0] DI[15:0]
D[15:0]
tDod
tDoh
tDsu tDh
XCSN XRDN
tacc
XWRHN XWRLN
tacc
Fig. 8-2 Host Access Timing Characteristic in Host I/F Type 1.
XTO
tDRQd
XDRQN
tDRQh
XDAKN (Note 1)
Fig. 8-3 DMA Timing Characteristic. Note 1: May be XRDN or XWRHN or XWRLN signals when XDAKEN = low.
XTO
tINTd
XINTN
tINTh
XRDN
Fig. 8-4 Interrupt Timing Characteristic.
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W86L388D
Preliminary
HCKI XCSN,XASN, XRWN,XBE[1:0]
tIF2su tIF2h
tA2su
tA2h
A[3:1]
tRDYd tRDYh
XRDYN
tDsu tDh
DI
tDod tDoh
DO
Fig. 8-5 Host Interface Type 2 Timing Characteristic.
SD4
tSD3d tSD3d
SD3
(output)
tSD3su
tSD3h
SD3
(input)
Fig. 8-6 Serial Interface SD3 Timing Characteristic (SD Mode).
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W86L388D
Preliminary
SD4
tSDnd tSDnd
SDn
(output)
tSDnsu tSDnh
SDn
(input)
Fig. 8-7 Serial Interface SDn Timing Characteristic (SD Mode).
SDn: SD1, SD2, SD5, SD6
SD4
tSD3d tSD3d
SD3
(output)
tCMDh
tSD3su
tSD3h
tSD3su
SD3
(input)
Fig. 8-8 Serial Interface SD3 Timing Characteristic (MMC Mode).
SD4
tSDnd tSDnd
SDn
(output)
tSDnsu tSDnh
SDn
(input)
Fig. 8-9 Serial Interface SDn Timing Characteristic (MMC Mode).
SDn: SD1, SD2, SD5, SD6
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Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
9. HOW TO READ THE TOP MARKING
The top marking of W86L388D
SMART@IO
W86L388D
118GA01ASB
1st line: Winbond logo and SMART@IO Mark 2nd line: Part number of W86L388D 3rd line: Tracking code G: 118 G A 01A SB 118: packages made in '01, week 18 assembly house ID; A means ASE, O means OSE, G means GR A: IC revision; A means version A, B means version B 01A: for internal use SB: for internal use
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Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
10.PACKAGE DIMENSIONS
48-LQFP(7x7x1.4mm footprint 2.0mm)
H
36
25 24
37
H
48
13
1
12
Controlling dimension : Millimeters
Symbol
Dimension in inch
Dimension in mm
Min Nom Max
0.002 0.004 0.053 0.055 0.006 0.008 0.004 0.006 0.272 0.276 0.272 0.276 0.014 0.350 0.350 0.018 0.020 0.354 0.354 0.024 0.039 0.004 0 7 0.006 0.057 0.010 0.008 0.280 0.280 0.026 0.358 0.358 0.030
Min Nom Max
0.05 1.35 0.15 0.10 6.90 6.90 0.35 8.90 8.90 0.45 0.10 1.40 0.20 0.15 7.00 7.00 0.50 9.00 9.00 0.60 1.00 0.10 0 7 0.15 1.45 0.25 0.20 7.10 7.10 0.65 9.10 9.10 0.75
A A1 A2 b c D E e HD HE L L1 Y 0
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W86L388D
Preliminary
11. REFERENCE SCHEMATIC
W86L388D Reference Circuit
VCC33 VCC33 A[1..3] D[0..15] U1 VDD VDD RSTN XTYP1 Q1 NDS352P 12 39 13 14 28 11 35 32 34 33 29 30 15 16 17 20 21 22 27 26 25 24 23 CD LED_INS LED_RW SD_PWEN WP NRESET XTI XTO XINT NCS5 NOE NWE R1 0 R2 10K R3 SD_PWEN VCC33
D D
19 43 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A1 A2 A3 10 9 8 7 5 4 3 2 1 48 47 46 45 44 41 40 38 37 36 6 18 31 42
XTI D0 XTO D1 HCKI D2 D3 XINT D4 XCSN D5 D6 XRDN/XRDWRN D7 XWRLN/XBELN D8 XWRHN/XBEHN D9 D10 XDRQN/XRDY XDAKN/XAS D11 D12 SD1 D13 SD2 D14 D15/A0 SD3 SD4 A1 SD5 A2 SD6 A3 GIO0 GIO1 VSS GIO2 VSS GIO3 VSS GIO4 VSS W86L388D_LQFP
+ 10K
C1 10uF
+
C2 0.1u
R4 R5 R6 R7 R8 R9 R10 R11
D
D
R12 R13 R14 R15 R16 R17
47 47 47 47 47 47
20K 20K 20K 20K 20K 20K 20K 20K
CON1 1 2 3 4 5 6 7 8 9 10 11 12 SD2 SD3 VSS VDD SD4 VSS SD5 SD6 SD1 WP CD Case SD/MMC Card Scoket
D
D
A[1..3] XTO NRESET XTI Q2 XINT NCS5 NOE 20MHz C3 20p C4 20p NWE D[0..15] RESET XINT NCS5 NOE NWE
To Intel StrongARM interface (16 bit)
D
D
VCC33
VCC33
VCC33
R18 330
R19 330
+
C5 0.1u
+
C6 0.1u
+
C7 10u
+
C8 0.1u
+
C9 0.1u
+
C10 0.1u
+
C11 0.1u
Card Insert
D1 LED_INS D2 LED_RW
D
D
Card Access
LED_INS LED_RW Size Date:
WINBOND ELECTRONICS CORP_ Document Number W86L388D Reference Schematic (for StrongARM) Tuesday, October 02, 2001 Sheet 1 of 1
inbond
Rev 2.2
- 24 -
Publication Release Date: August 2001 Revision 0.50
W86L388D
Preliminary
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, M in-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
- 25 -
Publication Release Date: August 2001 Revision 0.50

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