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Ordering number : ENN*6843
CMOS IC
LC876694B/78B/62B
8-Bit Single-Chip Microcontroller
Preliminary Overview
The LC876694B/LC876678B/LC876662B are 8 bit single chip microcontrollers with the following on-chip functional blocks : - CPU: operable at a minimum bus cycle time of 100ns - On-chip ROM Maximum Capacity : LC876694B 96K bytes LC876678B 80K bytes LC876662B 64K bytes - On-chip RAM: 2048 bytes - VFD automatic display controller / driver - 16 bit timer / counter (can be divided into two 8 bit timers) - 16 bit timer / PWM (can be divided into two 8 bit timers) - timer for use as date / time clock - High speed clock counter - System clock divider function - synchronous serial I/O port (with automatic block transmit / receive function) - asynchronous / synchronous serial I/O port - 12-channel x 8-bit AD converter - Weak signal detector - 15-source 10-vectored interrupt system All of the above functions are fabricated on a single chip.
Features
(1) Read-Only Memory (ROM): LC876694B LC876678B LC876662B 98304 x 8 bits 81920 x 8 bits 65536 x 8 bits
(2) Random Access Memory (RAM): LC876694B/78B/62B 2048 x 9 bits (3) Minimum Bus Cycle Time: 100ns (10MHz) Note: The bus cycle time indicates ROM read time. (4) Minimum Instruction Cycle Time: 300ns (10MHz)
Ver.1.01 51000
11901 RM (IM) SK No.6843-1/23
LC876694B/78B/62B (5) Ports - Input/output ports Data direction programmable for each bit individually : 20 (P1n, P70 to P73, P8n) - 15V withstand input/output ports Data direction programmable in nibble units : 8 (P0n) (When N-channel open drain output is selected, data can be input in bit units.) Data direction programmable for each bit individually : 8 (P3n) - Input ports : 2 (XT1,XT2) - VFD output ports Large current outputs for digits : 9 (S0 / T0 to S8 / T8) Large current outputs for digits / segments : 7 (S9 / T9 to S15 / T15) digit / segment outputs : 8 (S16 to S23) segment outputs : 28 (S24 to S51) Other functions Input/output ports : 12(PFn, PG0 to 3) Input ports : 24 (PCn, PDn, PEn) - Oscillator pins : 2 (CF1,CF2) - Reset pin : 1 (RES#) - Power supply : 6 (VSS1 to 2, VDD1 to4) - VFD power supply : 1 (VP) (6) VFD automatic display controller - Programmable segment/digit output pattern Output can be switched between digit/segment waveform output (pins 9 to 24 can be used for output of digit waveforms). parallel-drive available for large current VFD. - 16-step dimmer function available (7) Weak signal detection (MIC signals etc) - Counts pulses with width greater than a preset value - 2 bit counter (8) Timers - Timer 0: 16 bit timer / counter with capture register Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit Counter with 8-bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register - Timer 1: PWM / 16 bit timer toggle output Mode 0: 2 channel 8 bit timer (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer (with toggle output) Toggle output also possible using lower order 8 bits. Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output. - Base Timer 1) The clock signal can be selected from any of the following : Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0 2) Interrupts can be selected to occur at one of five different times. (9) High speed clock counter 1) Capable of counting maximum: 20MHz clock (Using main clock 10MHz) 2) Real time output
No.6843-2/23
LC876694B/78B/62B (10) Serial-interface - SIO 0: 8 bit synchronous serial Interface 1) LSB first / MSB first function available 2) Internal 8 bit baud-rate generator (maximum transmit clock period 4 / 3 Tcyc) 3) Continuous automatic data communication (1-256 bits) - SIO 1: 8 bit asynchronous / synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2-512 Tcyc) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8-2048Tcyc) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2-512 Tcyc) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) (11) AD converter -8 bits x 12 channels (12) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal) -Noise rejection function (noise rejection filter time constant can selected from 1 / 32 / 128 Tcyc) (13) Watchdog timer - The watching timer period is set using an external RC. - Watchdog timer can produce interrupt, system reset (14) Interrupts: 15-source, 10-vectored interrupts 1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is refused. 2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. (15) Subroutine stack levels: 1024 levels max. (16) Multiplication and division - 16 bit x 8 bit (executed in 5 cycles) - 24 bit x 16 bit (12 cycles) - 16 bit / 8 bit (8 cycles) - 24 bit / 16 bit (12 cycles) (17) Oscillation circuits - On-chip RC oscillation circuit for system clock use. - On-chip CF oscillation circuit for system clock use. (Rf built in) - On-chip Crystal oscillation circuit low speed system clock use. (Rd, Rf external) (18) System clock divider function - Able to reduce current consumption Available minimum instruction cycle time: 300ns, 600ns, 1.2s, 4.8s, 9.6s, 19.2s, 38.4s, 76.8s. (Using 10MHz main clock) Stack is located in RAM.
No.6843-3/23
LC876694B/78B/62B (19) Standby function - HALT mode HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate but VFD display and some serial transfer operations stop. 1) Oscillation circuits are not stopped automatically. 2) Release occurs on system reset or by interrupt. -HOLD mode HOLD mode is used to reduce power consumption. Both program execution and peripheral circuits are stopped. 1)CF, RCand crystal oscillation circuits stop automatically. 2) Release occurs on any of the following conditions. (1) input to the reset pin goes low (2) a specified level is input at least one of INT0, INT1, INT2 (3) an interrupt condition arises at port 0 -X'tal HOLD made X'tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1) CF and RC oscillation circuits stop automatically. 2) Crystal oscillator is maintained in its state at HOLD mode inception. 3) Release occurs on any an any of the following conditions (1) input to the reset pin goes low (2) a specified level is input to at least one of INT0, INT1, INT2 (3) an interrupt condition arises at port 0 (4) an interrupt condition arises at the base-timer (20) Factory shipment -delivery form QIP100E (21) Development tools - Evaluation chip: LC876095 - Emulator: EVA62S + ECB876600 (Evaluation chip board) + SUB876500 + POD100QFP - Flash ROM version: LC87F66C8A
No.6843-4/23
Pin Assignment
S48/PG0 S49/PG1 S50/PG2 S51/PG3 P00 P01 P02 P03 VSS2 VDD2 P04 P05 P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
LC876694B/78B/62B
P16/T1PWML P17/T1PWMH/BUZ P30 P31 P32 P33 P34 P35 P36 P37 RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN P73/INT3/T0IN S0/T0 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S19/PC3 S18/PC2 S17/PC1 S16/PC0 VDD3 S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 VDD4 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 VP
SANYO: QIP100E
No.6843-5/23
LC876694B/78B/62B
System Block Diagram
Interrupt Control
IR
PLA
Stand-by Control
ROM
RC X'tal
Clock Generator
CF
PC
Bus Interface
ACC
SIO0
Port 0
B Register
SIO1
Port 1
C Register
Timer 0
(High speed clock counter)
Port 3 ALU
Timer 1
Port 7
Base Timer
Port 8
PSW
VFD Controller
ADC
RAR
INT0-3 Noise Rejection Filter
Weak Signa Detector
RAM
Stack Pointer
Watch Dog Timer
No.6843-6/23
LC876694B/78B/62B
Pin Assignment
Pin name VSS1 VSS2 VDD1 VDD2 VDD3 VDD4 VP PORT0 P00 to P07 I/O Function * Power supply (-) * Power supply (+) Option No No
I/O
* Power supply (-) * 8bit input/output port * data direction programmable in nibble units * Use of pull-up resistor can be specified in nibble units * Input for HOLD release * Input for port 0 interrupt * 15V withstand at N-channel open drain output * 8bit input/output port * data direction programmable for each bit * Use of pull-up resistor can be specified for each bit * Other pin functions P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input/bus input/output P15 SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output * 8bit Input/output port * Data direction can be specified for each bit * Use of pull-up resistor can be specified for each bit * 15V withstand at N-channel open drain output * 4bit Input/output port * Data direction can be specified for each bit * Use of pull-up resistor can be specified for each bit * Other functions P70: INT0 input/HOLD release input/Timer0L capture Input/output for watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input/High speed clock counter input P73: INT3 input(noise rejection filter attached input)/timer 0 event input/Timer 0H capture input AD input port: AN8(P70), AN9(P71) The following types of interrupt detection are possible: Rising INT0 INT1 INT2 INT3 Yes Yes Yes Yes Falling Yes Yes Yes Yes Rising/ falling No No Yes Yes H level Yes Yes No No L level Yes Yes No No
No Yes
PORT1 P10 to P17
I/O
Yes
PORT3 P30 to P33
I/O
Yes
PORT7 P70 to P73
I/O
No
No.6843-7/23
LC876694B/78B/62B
Pin name PORT8 P80 to P87 I/O I/O Function description * 8bit Input/output port * Input/output can be specified in a bit unit * Other functions: AD input port: AN0 to AN7 Weak signal detector input port: MICIN(P87) * Large current output for VFD display controller digit (can be used for segment) * Large current output for VFD display controller digit (can be used for segment) * Large current output for VFD display controller segment/digit * Output for VFD display controller segment/digit * Other functions: High voltage input port: PC0 to PC7 * Output for VFD display controller segment * Other functions: High voltage input port: PD0 to PD7 * Output for VFD display controller segment * Other functions High voltage input port: PE0 to PE7 * Output for VFD display controller segment * Other functions: High voltage input/output port: PF0 to PF7 * Output for VFD display controller segment * Other functions: High voltage input/output port: PG0 to PG3 Reset terminal * Input for 32.768kHz crystal oscillation * Other functions: General purpose input port When not in use, connect to VDD1. AD input port: AN10 * Output for 32.768kHz crystal oscillation * Other functions: General purpose input port When not in use, set to oscillation mode and leave open circuit. AD input port: AN11 Input terminal for ceramic oscillator Output terminal for ceramic oscillator Option No
S0/T0 to S6/T6 S7/T7 to S8/T8 S9/T9 to S15/T15 S16 to S23
O O O I/O
Yes No No No
S24 to S31
I/O
No
S32 to S39
I/O
Yes
S40 to S47
I/O
Yes
S48 to S51
I/O
No
RES XT1
I I
No No
XT2
I/O
No
CF1 CF2
I O
No No
No.6843-8/23
LC876694B/78B/62B
Port Output Configuration
Output configuration and pull-up/pull-down resistor options are shown in the following table. Input /output is possible even when port is set to output mode.
Terminal P00 to P07 Option applies to: Options 1 bit units 1 2 P10 to P17 each bit 1 2 P30 to P37 each bit 1 2 P70 P71 to P73 P80 to P87 S0/T0 to S6/T6 each bit None None None 1 2 S7/T7 to S15/T15 S16 to S31 S32 to S47 each bit None 1 2 S48 to S51 XT1 XT2 None None None CMOS 15 voltage Nch-open drain CMOS Nch-open drain CMOS 15V Nch-open drain Nch-open drain CMOS Nch-open drain High voltage Pch-open drain High voltage Pch-open drain High voltage Pch-open drain High voltage Pch-open drain High voltage Pch-open drain High voltage Pch-open drain Input only Output for 32.768kHz crystal oscillation Output Format Pull-up resistor Programmable (Note 1) None Programmable Programmable Programmable None Programmable Programmable None None None Pull-down resistor Fixed None fixed Fixed None None -
Note 1 Programmable pull-up resisters of Port 0 can be attatched in nibble units (P00-03, P04-07). * Note 1: Connect as follows to reduce noise on VDD and increase the back-up time. VSS1, and VSS2 must be connected together and grounded. *Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports. When the VDD2 is not backed up, the port level does not become "H" even if the port latch is in the "H" level. Therefore, when the VDD2 is not backed up and the port latch is "H" level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD2 is not backed up, output "L" by the program or pull the port to "L" by the external circuit in the HOLD mode so that the port level becomes "L" level and unnecessary current consumption is prevented.
LSI VDD1 Back-up capacitors *2
Power Supply
VDD2 VDD3 VDD4 VSS1 VFD Powers VSS2
No.6843-9/23
LC876694B/78B/62B 1. Absolute Maximum Ratings at Ta=25C and VSS1=VSS2=0V
Parameter Supply voltage Input voltage Output voltage Input/Output voltage Symbol Pins Conditions VDD1=VDD2= VDD3=VDD4 Ratings typ. max. +7.0 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 unit V
VDD[V]
VDDMAX VDD1,VDD2, VDD3,VDD4 VI(1) XT1,XT2,CF1, RES VI(2) VO(1) VIO(1) VP S0/T0 to S15/T15 *Port 0: CMOS output option *Port 1 *Port 3: CMOS output option *Port 7 *Port 8 *Port 0 open drain *Port 3 open drain S16 to S51 Port 0, 1, 3
min. -0.3 -0.3 VDD-45 VDD-45 -0.3
VIO(2) VIO(3) IOPH(1)
-0.3 VDD-45 -10
15 VDD+0.3 mA
High level output current
Peak output current
Total output current
Low level output current
Peak output current Total output current
IOPH(2) IOPH(3) IOPH(4) IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOAH(5) IOAH(6) IOAH(7) IOPL(1) IOPL(2) IOPL(3) IOAL(1) IOAL(2)
IOAL(3) Maximum power Pdmax dissipation Operating temperature range Storage temperature range Topr
Port71,72,73 S0/T0 to S15/T15 S16 to S51 Port 0 Port 1,3 Port 7 S0/T0 to S15/T15 S16 to S27 S28 to S39 S40 to S51 Port 02,03 *Port 00,01,04 to 07 *Port 1,3 Port 7,8 Port 00,01,02,03 *Port 04,05,06,07 *Port 1,3 Ports 7,8 QIP100E
*CMOS output selected *Current at each pin Current at each pin Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins For each pin For each pin For each pin For each pin For each pin For each pin Ta = -30 to+70C
-3 -30 -15 -30 -30 -5 -65 -60 -60 -60 30 20 5 60 50 20 mW -30 70 C
Tstg
-55
125
No.6843-10/23
LC876694B/78B/62B 2. Recommended Operating Range at Ta=-30C to +70C, VSS1=VSS2=0V
Parameter Symbol Pins VDD1=VDD2=VDD3 =VDD4 VDD1 Conditions 0.294s Tcyc 200s RAM and the register data are kept in HOLD mode. 4.5 to 6.0 Output disable Ratings typ. max. 6.0 unit V
VDD[V]
Operating VDD(1) supply voltage range Hold voltage VHD
min. 4.5
2.0
6.0
Pull-down voltage Input high voltage
VP VIH(1)
VP *Port 0,3: CMOS output option *Port 8 Port 0,3: N-ch open drain output *Port 1 *Port71,72,73 *P70 port input/interrupt S16 to S51 P70 Weak signal input Port 70 Watchdog timer XT1, XT2, CF1, RES *Port 0,3: CMOS output option *Port 8 Port 0,3: N-ch open drain output *Port 1 *Port 71,72,73 *P70 port input/interrupt S16 to S51 Output disable
-35
VDD VDD
4.5 to 6.0 0.3VDD +0.7 4.5 to 6.0 0.3VDD +0.7 4.5 to 6.0 0.3VDD +0.7 4.5 to 6.0 0.3VDD +1.0 4.5 to 6.0 0.75VDD 4.5 to 6.0 0.9VDD 4.5 to 6.0 0.75VDD 4.5 to 6.0 VSS
VIH(2) VIH(3)
Output disable Output disable
13.5 VDD
VIH(4) VIH(5) VIH(6) VIH(7) Input low voltage VIL(1)
Output P-channel Tr. OFF Output disable Output disable
VDD VDD VDD VDD 0.15VDD +0.4 0.15VDD +0.4 0.1VDD +0.4 0.2VDD 0.25VDD 0.8VDD -1.0 0.25VDD 200 10 s
MHz
VIL(2) VIL(3)
Output disable Output disable
4.5 to 6.0 4.5 to 6.0
VSS VSS
VIL(4) VIL(5) VIL(6) VIL(7) Operation tCYC cycle time External system fEXCF(1) clock frequency
Output P-channel Tr. OFF Port 87 weak signal input Output disabled Port 70 Output disabled Watchdog timer XT1,XT2,CF1, RES
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
-35 VSS VSS VSS 0.294 0.1
CF1
*CF2 open circuit 4.5 to 6.0 *system clock divider set to 1/1 *external clock DUTY = 5050% *CF2 open circuit 4.5 to 6.0 *system clock divider set to 1/2
0.2
20
Continued
No.6843-11/23
LC876694B/78B/62B
Ratings typ. max. 10
Parameter Oscillation stabilizing time period (Note 1)
Symbol FmCF(1)
Pins CF1, CF2
Conditions 10MHz ceramic resonator oscillation
Refer to figure 1
VDD[V] 4.5 to 6.0
min.
unit
FmCF(2)
CF1, CF2
4MHz ceramic resonator oscillation
Refer to figure 1
4.5 to 6.0
4
FmRC
RC oscillation
4.5 to 6.0
0.3
1.0
2.0
FsX'tal
XT1, XT2
32.768kHz crystal resonator oscillation
Refer to figure 2
4.5 to 6.0
32.768
(Note 1) The oscillation constant is shown in table 1 and table 2.
No.6843-12/23
LC876694B/78B/62B 3. Electrical Characteristics at Ta=-30C to +70C, VSS1=VSS2=0V
Parameter Input high current Symbol IIH(1) Pins Ports 0,3: N-ch open drain output Conditions Ratings typ. unit A
IIH(2)
Port 0,1,3,7,8
IIH(3)
S16 to S51 without pull-down resister (Port C,D,E,F,G)
RES XT1,XT2
IIH(4) IIH(5)
*Output disabled *VIN=13.5V (including OFF state leak current of the output Tr.) 4.5 to 6.0 *Output disabled *Pull-up resister OFF. *VIN=VDD (including OFF state leak current of the output Tr.) When configured as an input 4.5 to 6.0 port VIN=VDD VIN=VDD 4.5 to 6.0 When configured as an input port VIN=VDD VIN=VDD VIN=VBIS+0.5V (VBIS : Bias voltage) *Output disabled *VIN=VSS (including OFF state leak current of the output Tr.) VIN=VSS When configured as an input port VIN=VSS VIN=VSS VIN=VBIS-0.5V (VBIS : Bias voltage) IOH=-1.0mA IOH=-0.1mA IOH=-0.4mA IOH=-20.0mA IOH=-1.0mA IOH at any single pin is not over 1mA. IOH=-5.0mA IOH=-1.0mA IOH at any single pin is not over 1mA. IOL=30mA IOL=10mA IOL=1.6mA VOH=0.9VDD 4.5 to 6.0
VDD[V] 4.5 to 6.0
min.
max. 5
1
60
1 1
IIH(6) IIH(7) Input low current IIL(1)
CF1 P87/AN7/MICIN weak signal input Port 0,1,3,7,8
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
4.2 -1
8.5
15 15
IIL(2) IIL(3)
RES XT1,XT2
4.5 to 6.0 4.5 to 6.0
-1 -1
IIL(4) IIL(5) Output high voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5)
CF1 P87/AN7/MICIN weak signal input Port 0,1,3: CMOS output option Port 7 S0/T0-S15/T15
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
-15 -15 VDD-1 VDD-0.5 VDD-1 VDD-1.8 VDD-1
-8.5
-4.2 V
VOH(6) VOH(7)
S2+ to S51
4.5 to 6.0 VDD-1.8 4.5 to 6.0 VDD-1
Output low voltage Pull-up resistor
VOL(1) VOL(2) VOL(3) Rpu
Port 02, 03 Port 0,1,3 Port 0,1,3,7
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
15
40
1.5 1.5 0.4 70
k
Continued
No.6843-13/23
LC876694B/78B/62B
Ratings typ.
Parameter Output offleak current
Symbol IOFF(1) IOFF(2)
Pins S0/T0 to S15/T15, S16 to S51 without pull-down resistor S16 to S51
Conditions *Output P-ch Tr. OFF *VOUT=VSS *Output P-ch Tr. OFF *VOUT=VDD-40V *Output P-ch Tr. OFF
VDD[V] 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
min. -1 -30
Max.
unit A
Resistance of the low level hold Tr. High voltage pull-down resistor Hysteresis voltage
Rinpd
200
k
Rpd
VHIS(1) VHIS(2)
Pin capacitance
CP
S0/T0 to S15/T15, S16 to S51 with pull-down resistor *Port 1,7 * RES Port 87 weak signal input All pins
*Output P-ch Tr. OFF *VOUT=3V *Vp=-30V
5.0
60
100
200
4.5 to 6.0 4.5 to 6.0 *All other terminals connected to VSS. *f=1MHz *Ta=25C 4.5 to 6.0
0.1VDD 0.1VDD 10
V
pF
Input sensitivity
Vsen
Port 87 weak signal input
4.5 to 6.0 0.12VDD
Vpp
No.6843-14/23
LC876694B/78B/62B 4. Serial Input/Output Characteristics at Ta=-30C to +70C, VSS1=VSS2=0V
Parameter Cycle Time Low Level pulse width Symbol tSCK(1) tSCKL(1) tSCKLA(1) Input clock High Level pulse width tSCKH(1) tSCKHA(1) Cycle Time Low Level pulse width Serial clock High Level pulse width Cycle Time Low Level pulse width Output clock tSCK(2) tSCKL(2) tSCKH(2) tSCK(3) tSCKL(3) tSCKLA(2) High Level pulse width tSCKH(3) tSCKHA(2) Cycle Time Low Level pulse width High Level pulse width Serial input Data set-up time Data hold time Output time Serial output delay tSCK(4) tSCKL(4) tSCKH(4) tsDI thDI tdDO SI0(P10), SI1(P13), SB0(P11), SB1(P14) SO0(P12), SO1(P15), SB0(011), SB1(P14) *Measured with respect to SI0CLK leading edge. *Refer to figure 6 *Measured with respect to SI0CLK trailing edge. *When port is open drain: Time delay from SI0CLK trailing edge to the SO data change. *Refer to figure 6 4.5 to 6.0 0.03 0.03 4.5 to 6.0 1/3 tCYC +0.05 SCK1(P15) *CMOS output option *Refer to figure 6 4.5 to 6.0 2 1/2 1/2 s SCK0(P12) *CMOS output option *Refer to figure 6 4.5 to 6.0 SCK1(P15) Refer to figure 6 4.5 to 6.0 Pins SCK0(P12) Conditions Refer to figure 6 Ratings typ. unit tCYC
VDD[V] 4.5 to 6.0
min. 4/3 2/3 2/3 2/3 3 2 1 1 4/3
max.
1/2 3/4 1/2 2
tSCK
tCYC tSCK
No.6843-15/23
LC876694B/78B/62B 5. Pulse Input Conditions at Ta=-30C to +70C, VSS1=VSS2=0V
Parameter High/low level pulse width Symbol Pins Conditions *Interrupt acceptable *Events to timer 0 can be input. *Interrupt acceptable *Events to timer 0 can be input. *Interrupt acceptable *Events to timer 0 can be input. *Interrupt acceptable *Events to timer 0 can be input. *Weak signal detection counter enabled *High speed clock counter countable *Reset possible Ratings typ. unit tCYC
tPIH(1) INT0(P70), tPIL(1) INT1(P71), INT2(P72) tPIH(2) INT3(P73) tPIL(2) (Noise rejection ratio set to 1/1.) tPIH(3) INT3(P73) tPIL(3) (Noise rejection ratio set to 1/32.) tPIH(4) INT3(P73) tPIL(4) (Noise rejection ratio set to 1/128.) tPIH(5) MICIN(P87) tPIL(5) tPIH(6) NKIN(P72) tPIL(6) tPIL(7) RES
VDD[V] 4.5 to 6.0
min. 1
max.
4.5 to 6.0
2
4.5 to 6.0
64
4.5 to 6.0
256
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
1 1/12 200 s
6. AD Converter Characteristics at Ta=-30C to + 70C, VSS1=VSS2=0V
Parameter Resolution Absolute precision Conversion time Symbol N ET TCAD Pins AN0(P80) to AN7(P87) AN8(P70), AN9(P71) AN10(XT1), AN11(XT2) Conditions (Note2) AD conversion time = 32 x tCYC (ADCR2=0) (Note 3) AD conversion time = 64 x tCYC (ADCR2=1) (Note 3) Ratings typ. 8 unit
VDD[V] 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
min.
max.
15.62 (tCYC= 0.488s) 18.82 (tCYC= 0.294s)
bit LSB 1.5 97.92 s (tCYC= 3.06s) 97.92 (tCYC= 1.53s) VDD 1 V A
Analog input voltage range Analog port input current
VAIN IAINH IAINL VAIN=VDD VAIN=VSS
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
VSS
-1
(Note 2) Absolute precision not including quantizing error (1/2 LSB). (Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to register.
No.6843-16/23
LC876694B/78B/62B 7. Current Dissipation Characteristics at Ta=-30C to +70C, VSS1=VSS2=0V
Parameter Current dissipation during basic operation (Note 4) Symbol IDDOP(1) Pins Conditions Ratings typ. unit mA
IDDOP(2)
IDDOP(3)
IDDOP(4)
VDD1= *FmCF=10MHz for VDD2= Ceramic resonator VDD3= oscillation VDD4 *FsX'tal=32.768kHz for crystal oscillation *System clock: CF oscillation *Internal RC oscillation stopped. *Divider set to 1/1 4.5 to 6.0 *CF1=20MHz for external clock *FsX'tal=32.768kHz for crystal oscillation vSystem clock: CF oscillation *Internal RC oscillation stopped. *Divider set to 1/2 *FmCF=4MHz Ceramic 4.5 to 6.0 resonator oscillation *FsX'tal=32.768kHz for crystal oscillation *System clock: CF oscillation *Internal RC oscillation stopped. *Divider set to 1/1 4.5 to 6.0 *FmCF=0Hz (No oscillation) *FsX'tal=32.768kHz for crystal oscillation *System clock: RC oscillation *Divider set to 1/2 4.5 to 6.0 *FmCF=0Hz (No oscillation) *FsX'tal=32.768kHz for crystal oscillation *System clock: 32.768kHz *Internal RC oscillation stopped. *Divider set to 1/2
VDD[V] 4.5 to 6.0
min.
max
IDDOP(5)
A
Continued
No.6843-17/23
LC876694B/78B/62B
Ratings typ.
Parameter Current dissipation HALT mode (Note 4)
Symbol IDDHALT(1)
Pins
Conditions
IDDHALT(2)
VDD1= HALT mode VDD2= *FmCF=10MHz for VDD3= Ceramic resonator oscillation VDD4 *FsX'tal=32.768kHz for crystal oscillation *System clock : CF oscillation *Internal RC oscillation stopped. *Divider: 1/1 HALT mode *CF1=20MHz for external clock *FsX'tal=32.768kHz for crystal oscillation *System clock : CF oscillation *Internal RC oscillation stopped. *Divider 1/2
VDD[V] 4.5 to 6.0
min.
max.
unit mA
4.5 to 6.0
IDDHALT(3)
4.5 to 6.0 HALT mode *FmCF=4MHz for Ceramic resonator oscillation *FsX'tal=32.768kHz for crystal oscillation *System clock : CF oscillation *Internal RC oscillation stopped. *Divider: 1/2 HALT mode *FmCF=0Hz (When oscillation stops.) *FsX'tal=32.768kHz for crystal oscillation *System clock : RC oscillation *Divider: 1/2 4.5 to 6.0 A
IDDHALT(4)
IDDHALT(5)
HALT mode *FmCF=0Hz (When oscillation stops.) *FsX'tal=32.768kHz for crystal oscillation *System clock : 32.768kHz *Internal RC oscillation stopped. *Divider: 1/2
4.5 to 6.0
Continued
No.6843-18/23
LC876694B/78B/62B
Ratings typ.
Parameter Current dissipation HOLD mode
Symbol IDDHOLD(1)
Pins VDD1
Conditions
Current dissipation Date/time clock HOLD mode
IDDHOLD(2)
VDD1
HOLD mode *CF1=VDD or open circuit (when using external clock) Date/time clock HOLD 4.5 to 6.0 mode *CF1=VDD or open circuit (when using external clock) *FmX'tal=32.768kHz for crystal oscillation
VDD[V] 4.5 to 6.0
min.
max.
unit A
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6843-19/23
LC876694B/78B/62B Main system clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Circuit parameters Frequency Manufacturer Oscillator C1 10MHz C2 Rd1 Operating supply voltage range Oscillation stabilizing time typ max Notes
4MHz
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure4)
Subsystem clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator
Frequency 32.768kHz Manufacturer Oscillator C3 Circuit parameters C4 Rf Rd2 Operating supply voltage range Oscillation stabilizing time typ max Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure4) (Notes) * Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close tothe oscillation pins as possible with the shortest possible pattern length.
CF1
CF2 Rd1
XT1
XT2
Rf Rd2
C1
CF
C2
C3 X'tal
C4
Figure 1
Ceramic oscillation circuit
Figure 2
Crystal oscillation circuit
No.6843-20/23
LC876694B/78B/62B
0.5VDD
Figure 3
AC timing measurement point
VDD Power Supply VDD limit 0V Reset time RES
Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2
Operation mode
Unfixed
Reset
Instruction execution mode
Reset time and oscillation stable time
HOLD release signal
Without HOLD Release signal
HOLD release signal VALID
Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2
Operation mode
HOLD
HALT
HOLD release signal and oscillation stable time
Figure 4
Oscillation stablization time
No.6843-21/23
LC876694B/78B/62B
VDD
RRES
RES CRES
(Note) Set CRES, RRES values such that reset time exceeds 200s.
Figure 5
Reset circuit
SIOCLK
DATAIN
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transmission period (only SIO0)
DO8
tSCK tSCKL SIOCLK tsDI DATAIN tdDO DATAOUT thDI tSCKH
Data RAM transmission period (only SIO0) tSCKLA SIOCLK tsDI DATAIN tdDO DATAOUT thDI tSCKHA
Figure 6
Serial input / output test condition
No.6843-22/23
LC876694B/78B/62B
tPIL
tPIH
Figure 7 memo :
Pulse input timing condition
PS No.6843-23/23

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