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LTC1595/LTC1596 Serial 16-Bit Multiplying DACs
DESCRIPTION
The LTC(R)1595/LTC1596 are serial input, 16-bit multiplying current output DACs. The LTC1595 is pin and hardware compatible with the 12-bit DAC8043 and comes in 8-pin PDIP and SO packages. The LTC1596 is pin and hardware compatible with the 12-bit DAC8143/AD7543 and comes in 16-pin PDIP and SO wide packages. Both are specified over the industrial temperature range. Sensitivity of INL to op amp VOS is reduced by five times compared to the industry standard 12-bit DACs, so most systems can be easily upgraded to true 16-bit resolution and linearity without requiring more precise op amps. These DACs include an internal deglitching circuit that reduces the glitch impulse by more than ten times to less than 1nV-s typ.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
FEATURES
s s s s
s s s s
s s
SO-8 Package (LTC1595) DNL and INL: 1LSB Max Low Glitch Impulse: 1nV-s Typ Pin Compatible with Industry Standard 12-Bit DACs: DAC8043 and DAC8143/AD7543 4-Quadrant Multiplication Low Supply Current: 10A Max Power-On Reset 3-Wire SPI and MICROWIRETM Compatible Serial Interface Daisy-Chain Serial Output (LTC1596) Asynchronous Clear Input (LTC1596)
APPLICATIONS
s s s s
Process Control and Industrial Automation Software Controlled Gain Adjustment Digitally Controlled Filter and Power Supplies Automatic Test Equipment
TYPICAL APPLICATION
SO-8 Multiplying 16-Bit DAC Has Easy 3-Wire Serial Interface
VIN 5V 8 CLOCK DATA LOAD 7 6 5 CLK SRI LD GND 4 LTC1595 OUT1 1 1.0 0.8
INTEGRAL NONLINEARITY (LSB)
2 RFB
33pF
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 - 0.8 -1.0 0 49152 16384 32768 DIGITAL INPUT CODE 65535
1595/96 TA02
VDD VREF
+
-
3
LT (R)1001
VOUT
1595/96 TA01
U
U
U
Integral Nonlinearity
1
LTC1595/LTC1596 ABSOLUTE MAXIMUM RATINGS
VDD to AGND .............................................. - 0.5V to 7V VDD to DGND .............................................. - 0.5V to 7V AGND to DGND ............................................ VDD + 0.5V DGND to AGND ............................................. VDD + 0.5V VREF to AGND, DGND............................................. 25V RFB to AGND, DGND .............................................. 25V Digital Inputs to DGND .................. - 0.5V to VDD + 0.5V VOUT1, VOUT2 to AGND ................... - 0.5V to VDD + 0.5V Maximum Junction Temperature .......................... 150C Operating Temperature Range LTC1595C/LTC1596C ............................. 0C to 70C LTC1595I/LTC1596I .......................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER LTC1595ACN8 LTC1595ACS8 LTC1595BCN8 LTC1595BCS8 LTC1595CCN8 LTC1595CCS8 LTC1595AIN8 LTC1595AIS8 LTC1595BIN8 LTC1595BIS8 LTC1595CIN8 LTC1595CIS8 S8 PART MARKING 1595A 1595B 1595C
Consult factory for Military grade parts.
TOP VIEW OUT1 OUT2 AGND STB1 LD1 SRO SRI STB2 1 2 3 4 5 6 7 8 16 RFB 15 VREF 14 VDD 13 CLR 12 DGND 11 STB4 10 STB3 9 LD2
TOP VIEW VREF RFB OUT1 GND 1 2 3 4 8 7 6 5 VDD CLK SRI LD
N8 PACKAGE 8-LEAD PDIP
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 130C/W (N) TJMAX = 150C, JA = 190C/W (S)
1595AI 1595BI 1595CI
VDD = 5V 10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted. LTC1595A/96A
SYMBOL PARAMETER Accuracy Resolution Monotonicity INL DNL GE Integral Nonlinearity Differential Nonlinearity Gain Error (Note 1) TA = 25C TMIN to TMAX TA = 25C TMIN to TMAX (Note 2) TA = 25C TMIN to TMAX
q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
2
U
U
W
WW U
W
ORDER PART NUMBER LTC1596ACN LTC1596ACSW LTC1596BCN LTC1596BCSW LTC1596CCN LTC1596CCSW LTC1596AIN LTC1596AISW LTC1596BIN LTC1596BISW LTC1596CIN LTC1596CISW
N PACKAGE 16-LEAD PDIP
SW PACKAGE 16-LEAD PLASTIC SO WIDE
TJMAX = 150C, JA = 100C/W (N) TJMAX = 150C, JA = 130C/W (SW)
LTC1595B/96B
TYP MAX
LTC1595C/96C
MIN 16 15 TYP MAX UNITS Bits Bits 4 4 2 2 32 32 LSB LSB LSB LSB LSB LSB
MIN 16 16
TYP MAX MIN 16 16 0.25 1 0.35 1 0.2 0.2 2 3 1 1 16 16
2 2 1 1 16 32
LTC1595/LTC1596
VDD = 5V 10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL ILEAKAGE PARAMETER Gain Temperature Coefficient OUT1 Leakage Current Zero-Scale Error PSRR RREF Power Supply Rejection VREF Input Resistance Output Current Settling Time Midscale Glitch Impulse Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error THD Total Harmonic Distortion Equivalent DAC Thermal Noise Voltage Density Analog Outputs (Note 3) COUT Output Capacitance (Note 3) DAC Register Loaded to All 1s COUT1 DAC Register Loaded to All 0s COUT1 Digital Inputs VIH VIL IIN CIN VOH VOL Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Input Capacitance Digital Output High Voltage Digital Output Low Voltage (Note 3) VIN = 0V IOH = 200A IOL = 1.6mA
q q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS (Note 3) Gain/Temperature (Note 4) TA = 25C TMIN to TMAX TA = 25C TMIN to TMAX VDD = 5V 10% (Note 5) (Notes 6, 7) Using LT1122 Op Amp, CFEEDBACK = 33pF Full-Scale Transition, VREF = 0V, Using LT1122 Op Amp, CFEEDBACK = 33pF VREF = 10V, 10kHz Sine Wave (Note 8) (Note 9) f = 1kHz
q q q q
MIN
TYP 1
MAX 2 3 15 0.2 1
UNITS ppm/C nA nA LSB LSB LSB/V k s nV-s nV-s mVP-P dB nV/Hz
1 5 7 1 1 2 1 108 11
2 10
Reference Input
q
AC Performance
115 70 2.4
130 80
pF pF V
0.8 0.001 1 8 4 0.4
V A pF V V
Digital Outputs: SRO (LTC1596)
q q
VDD = 5V 10%, VREF = 10V, VOUT1 = GND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL tDS tDH tSRI tCH tCL tLD tASB PARAMETER Serial Input to CLK Setup Time Serial Input to CLK Hold Time Serial Input Data Pulse Width Clock Pulse Width High Clock Pulse Width Low Load Pulse Width LSB Clocked into Input Register to DAC Register Load Time CONDITIONS
q q q q q q q
MIN 30 30 60 60 60 60 0
TYP 5 5
MAX
UNITS ns ns ns ns ns ns ns
Timing Characteristics (LTC1595)
3
LTC1595/LTC1596
ELECTRICAL CHARACTERISTICS
SYMBOL tDS1 tDS2 tDS3 tDS4 tDH1 tDH2 tDH3 tDH4 tSRI tSTB1 to tSTB4 tSTB1 to tSTB4 tLD1, tLD2 tASB tCLR tPD1 tPD Serial Input Data Pulse Width Strobe Pulse Width Strobe Pulse Width LD Pulse Width LSB Strobed into Input Register to Load DAC Register Time Clear Pulse Width STB1 to SRO Propagation Delay STB2, STB3, STB4 to SRO Propagation Delay Supply Voltage Supply Current Digital Inputs = 0V or VDD CL = 50pF CL = 50pF (Note 10) (Note 11) Serial Input to Strobe Hold Time PARAMETER Serial Input to Strobe Setup Time Timing Characteristics (LTC1596) STB1 Used as the Strobe STB2 Used as the Strobe STB3 Used as the Strobe STB4 Used as the Strobe STB1 Used as the Strobe STB2 Used as the Strobe STB3 Used as the Strobe STB4 Used as the Strobe
q q q q q q q q q q q q q q q q
VDD = 5V 10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
CONDITIONS MIN 30 20 25 20 30 40 35 40 60 60 60 60 0 100 30 30 150 200 TYP 5 -5 0 -5 5 15 10 15 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Power Supply VDD IDD
q q
4.5
5 1.5
5.5 10
V A
The q denotes specifications which apply over the full operating temperature range. Note 1: 1LSB = 0.0015% of full scale = 15.3ppm of full scale. Note 2: Using internal feedback resistor. Note 3: Guaranteed by design, not subject to test. Note 4: IOUT1 with DAC register loaded with all 0s. Note 5: Typical temperature coefficient is 100ppm/C. Note 6: OUT1 load = 100 in parallel with 13pF. Note 7: To 0.0015% for a full-scale change, measured from the falling edge of LD1, LD2 or LD.
Note 8: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s; op amp = LT1007. Note 9: Calculation from en = 4kTRB where: k = Boltzmann constant (J/K); R = resistance (); T = temperature (K); B = bandwidth (Hz). Note 10: Minimum high time for STB1, STB2, STB4. Minimum low time for STB3. Note 11: Minimum low time for STB1, STB2, STB4. Minimum high time for STB3.
4
LTC1595/LTC1596 TYPICAL PERFOR A CE CHARACTERISTICS
Midscale Glitch Inpulse
1.0
+10
OUTPUT VOLTAGE (mV)
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 - 0.8
DIFFERENTIAL NONLINEARITY (LSB)
INTEGRAL NONLINEARITY (LSB)
1nV-s TYP USING LT1122 OP AMP CFEEDBACK = 33pF VREF = 10V
0 LD FALLING EDGE
-10
0
1
2 TIME (s)
3
Full-Scale Settling Waveform
1.0 DAC OUTPUT 5V/DIV GATED SETTLING WAVEFORM 500V/DIV 1s/DIV USING LT1122 OP AMP CFEEDBACK = 33pF
1595/96 G04
DIFFERENTIAL NONLINEARITY (LSB)
INTEGRAL NONLINEARITY (LSB)
Multiplying Mode Frequency Response vs Digital Code
0 -20
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ALL BITS OFF ALL BITS ON
- 40 - 60 - 80
VREF = 10V 1
DIFFERENTIAL NONLINEARITY (LSB)
INTEGRAL NONLINEARITY (LSB)
ATTENUATION (dB)
-100 -120 100
USING LT1122 OP AMP CFEEDBACK = 33pF
1k
100k 10k FREQUENCY (Hz)
UW
4
1595/96 G01
Integral Nonlinearity (INL)
1.0 0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 -1.0
Differential Nonlinearity (INL)
0.8
-1.0 0 49152 16384 32768 DIGITAL INPUT CODE 65535
1595/96 TA02
0
49152 32768 16384 DIGITAL INPUT CODE
65535
1595/96 G03
Integral Nonlinearity vs Reference Voltage
1.0
Differential Nonlinearity vs Reference Voltage
0.5
0.5
0 -10 - 8 - 6 - 4 - 2 0 2 4 6 REFERENCE VOLTAGE (V)
8
10
0 -10 - 8 - 6 - 4 - 2 0 2 4 6 REFERENCE VOLTAGE (V)
8
10
1595/96 G05
1595/96 G06
Integral Nonlinearity vs Supply Voltage
2 1.0
Differential Nonlinearity vs Supply Voltage
0.5
VREF = 2.5V 0 2 3 4 8 6 5 7 SUPPLY VOLTAGE (V) 9 10
0 2 3 4 8 6 5 7 SUPPLY VOLTAGE (V) 9 10
1M
10M
1595/96 G07
1595/96 G08
1595/96 G09
5
LTC1595/LTC1596 TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Logic Input Voltage
1.0 0.9 0.8
SUPPLY CURRENT (mA)
VDD = 5V
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
LOGIC THRESHOLD (V)
0
1
PIN FUNCTIONS
LTC1595
VREF (Pin 1): Reference Input. RFB (Pin 2): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp. OUT1 (Pin 3): Current Output Pin. Tie to inverting input of current to voltage converter op amp. GND (Pin 4): Ground Pin. LD (Pin 5): The Serial Interface Load Control Input. When LD is pulled low, data is loaded from the shift register into the DAC register, updating the DAC output. SRI (Pin 6): The Serial Data Input. Data on the SRI pin is latched into the shift register on the rising edge of the serial clock. Data is loaded MSB first. CLK (Pin 7): The Serial Interface Clock Input. VDD (Pin 8): The Positive Supply Input. 4.5V VDD 5.5V. Requires a bypass capacitor to ground. AGND (Pin 3): Analog Ground Pin. STB1, STB2, STB3, STB4 (Pins 4, 8, 10, 11): Serial Interface Clock Inputs. STB1, STB2 and STB4 are rising edge triggered inputs. STB3 is a falling edge triggered input (see Truth Tables). LD1, LD2 (Pins 5, 9): Serial Interface Load Control Inputs. When LD1 and LD2 are pulled low, data is loaded from the shift register into the DAC register, updating the DAC output (see Truth Tables). SRO (Pin 6): The Output of the Shift Register. Becomes valid on the active edge of the serial clock. SRI (Pin 7): The Serial Data Input. Data on the SRI pin is latched into the shift register on the active edge of the serial clock. Data is loaded MSB first. DGND (Pin 12): Digital Ground Pin. CLR (Pin 13): The Clear Pin for the DAC. Clears DAC to zero scale when pulled low. This pin should be tied to VDD for normal operation. VDD (Pin 14): The Positive Supply Input. 4.5V VDD 5.5V. Requires a bypass capacitor to ground. VREF (Pin 15): Reference Input. RFB (Pin 16): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp.
LTC1596
OUT1 (Pin 1): True Current Output Pin. Tie to inverting input of current to voltage converter op amp. OUT2 (Pin 2): Complement Current Output Pin. Tie to analog ground.
6
UW
Logic Threshold vs Supply Voltage
3.0 2.5 2.0 1.5 1.0 0.5 0
3 2 INPUT VOLTAGE (V)
4
5
1595/96 G10
0
5 SUPPLY VOLTAGE (V)
10
1595/96 G11
U
U
U
LTC1595/LTC1596
TRUTH TABLES
Table 1. LTC1596 Input Register
CONTROL INPUTS STB1 STB2 STB3 STB4 0 0 0 0 1 X X X 0 0 X 1 X X 1 1 1 X X 0 X X X X 1 0 0 0 Input Register and SRO Operation Serial Data Bit on SRI Loaded into Input Register, MSB First Data Bit or SRI Appears on SRO Pin After 16 Clocked Bits No Input Register Operation No SRO Operation
Table 2. LTC1596 DAC Register
CONTROL INPUTS CLR 0 1 1 1 LD1 X 1 X 0 LD2 X X 1 0 DAC Register Operation Reset DAC Register and Input Register to All 0s (Asynchronous Operation) No DAC Register Operation Load DAC Register with the Contents of Input Register
BLOCK DIAGRA
VREF 1 56k
56k
VDD 8 DECODER
LD 5
CLK 7
TI I G DIAGRA
CLK INPUT
SRI
PREVIOUS WORD
LD tLD
1595 TD
W
W
tDS
(LTC1595)
56k 56k 2 RFB 56k 56k 56k 56k 56k 112k 112k 112k 112k 7k
3 OUT1 4 GND
D15 (MSB) LOAD
D14
D13
D12
D11
***
DAC REGISTER
D0 (LSB)
CLK
INPUT 16-BIT SHIFT REGISTER
IN
6 SRI
1595 BD
UW
(LTC1595)
tDH tCL tSRI tCH
D15 MSB
D14
D1
D0 LSB tASB
7
LTC1595/LTC1596
BLOCK DIAGRA
VREF 15 56k
56k
VDD 14 DECODER CLR 13 LD1 5 LD2 9
STB1 4 STB2 8 STB3 10 STB4 11
TI I G DIAGRA
STROBE INPUT STB1, STB2, STB4 (INVERT FOR STB3)
SRI
LD1, LD2 t PD t PD1 SRO D15 (MSB) PREVIOUS WORD D14 PREVIOUS WORD D13 PREVIOUS WORD D0 (LSB) PREVIOUS WORD
8
W
W
(LTC1596)
56k 56k 16 RFB 56k 56k 56k 56k 56k 112k 112k 112k 112k 7k
1 OUT1 2 OUT2 3 AGND
CLR LOAD
D15 (MSB)
D14
D13
D12
D11
***
DAC REGISTER
D0 (LSB)
CLR CLK OUT INPUT 16-BIT SHIFT REGISTER IN 7 SRI
1596 BD
6 SRO DGND 12
UW
(LTC1596)
t DS1 t DS2 t DS3 t DS4
t DH1 t DH2 t DH3 t DH4
t STB1 t STB2 t STB3 t STB4
t STB1 t STB2 t STB3 t STB4 D13 t SRI D1 t ASB t LD1 t LD2 D0 LSB
D15 MSB
D14
D15 (MSB) CURRENT WORD
1596 TD
LTC1595/LTC1596
APPLICATIONS INFORMATION
Description The LTC1595/LTC1596 are 16-bit multiplying DACs which have serial inputs and current outputs. They use precision R/2R technology to provide exceptional linearity and stability. The devices operate from a single 5V supply and provide 10V reference input and voltage output ranges when used with an external op amp. These devices have a proprietary deglitcher that reduces glitch impulse to 1nV-s over a 0V to 10V output range. Serial I/O The LTC1595/LTC1596 have SPI/MICROWIRE compatible serial ports that accept 16-bit serial words. Data is accepted MSB first and loaded with a load pin. The 8-pin LTC1595 has a 3-wire interface. Data is shifted into the SRI data input on the rising edge of the CLK pin. At the end of the data transfer, data is loaded into the DAC register by pulling the LD pin low (see LTC1595 Timing Diagram). The 16-pin LTC1596 can operate in identical fashion to the LTC1595 but offers additional pins for flexibility. Four clock pins are available STB1, STB2, STB3 and STB4. STB1, STB2 and STB4 operate like the CLK pin of the LTC1595, capturing data on their rising edges. STB3 captures data on its falling edge (see Truth Table 1). The LTC1596 has two load pins, LD1 and LD2. To load data, both pins must be taken low. If one of the pins is grounded, the other pin will operate identically to LTC1595's LD pin. An asynchronous clear input (CLR) resets the LTC1596 to zero scale when pulled low (see Truth Table 2). The LTC1596 also has a data output pin SRO that can be connected to the SRI input of another DAC to daisy-chain multiple DACs on one 3-wire interface (see LTC1596 Timing Diagram). Unipolar (2-Quadrant Multiplying) Mode (VOUT = 0V to -VREF) The LTC1595/LTC1596 can be used with a single op amp to provide 2-quadrant multiplying operation as shown in Figure 1. With a fixed -10V reference, the circuits shown give a precision unipolar 0V to 10V output swing.
VREF -10V TO 10V
5V
0.1F 13 10 4 7 5 6 9 8 11 14 15 16 33pF OUT1 STB3 CLR VDD VREF RFB STB1 SRI LD1 LTC1596 SRO LD2 STB2 STB4 DGND AGND 12 TO NEXT DAC FOR DAISY-CHAINING 3
1595/96 F01a
OUT2
2
5V 0.1F 7 P 6 5 8 1 VDD VREF CLK SRI LD
VREF -10V TO 10V 2 RFB OUT1 3 33pF
(a)
Table 1. Unipolar Binary Code Table
DIGITAL INPUT BINARY NUMBER IN DAC REGISTER LSB MSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 ANALOG OUTPUT VOUT -VREF (65,535/65,536) -VREF (32,768/65,536) = -VREF/ 2 -VREF (1/65,536) 0V
LTC1595 GND 4
LT1001
VOUT 0V TO -VREF
1595/96 F01b
(b)
Figure 1. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to - VREF
+
-
P
U
W
+
-
U
U
1
LT1001
VOUT 0V TO -VREF
9
LTC1595/LTC1596
APPLICATIONS INFORMATION
Bipolar (4-Quadrant Multiplying) Mode (VOUT = - VREF to VREF) The LTC1595/LTC1596 can be used with a dual op amp and three external resistors to provide 4-quadrant multiplying operation as shown in Figure 2. With a fixed 10V reference, the circuits shown give a precision bipolar -10V to 10V output swing. Op Amp Selection Because of the extremely high accuracy of the 16-bit LTC1595/LTC1596, thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Op amp offset will contribute mostly to output offset and gain and will have minimal effect on INL and DNL. For
VREF -10V TO 10V
5V
0.1F 10 4 7 5 6 9 8 11
13
14
15
16 33pF OUT1
1/2 LT1112 OUT2 (20k / 2) 2
12 TO NEXT DAC FOR DAISY-CHAINING
3
1595/96 F02a
RESISTORS: CADDOCK T914-20K-010-02 (OR EQUIVALENT) 20k, 0.01%, TC TRACK = 2ppm/C
(a)
R2 20k R3 20k
VREF -10V TO 10V 5V 0.1F 7 P 6 5 8 1 VDD VREF CLK SRI LD GND 4
Table 2. Bipolar Offset Binary Code Table
2 RFB OUT1 3 33pF
LTC1595
1/2 LT1112
(20k / 2)
(b) Figure 2. Bipolar Operation (4-Quadrant Multiplication) VOUT = - VREF to VREF
10
+
-
R1 10k
1/2 LT1112
VOUT -VREF TO VREF
1595/96 F02b
DIGITAL INPUT BINARY NUMBER IN DAC REGISTER LSB MSB 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000
+
-
+
-
P
STB3 CLR VDD VREF RFB STB1 SRI LD1 LTC1596 SRO LD2 STB2 STB4 DGND AGND
U
W
+
-
U
U
example, a 500V op amp offset will cause about 0.55LSB INL degradation and 0.15LSB DNL degradation with a 10V full-scale range. The main effects of op amp offset will be a degradation of zero-scale error equal to the op amp offset, and a degradation of full-scale error equal to twice the op amp offset. For example, the same 500V op amp offset will cause a 3.3LSB zero-scale error and a 6.5LSB full-scale error with a 10V full-scale range. Op amp input bias current (IBIAS) contributes only a zeroscale error equal to IBIAS(RFB) = IBIAS(RREF) = IBIAS(7k). Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding should be used. IOUT2 (LTC1596) and GND (LTC1595) must be tied to the star ground with as low a resistance as possible.
R2 20k R3 20k
1
R1 10k
1/2 LT1112
VOUT -VREF TO VREF
ANALOG OUTPUT VOUT VREF (32,767/32,768) VREF (1/32,768) 0V -VREF (1/32,768) -VREF
LTC1595/LTC1596
PACKAGE DESCRIPTION
0.300 - 0.325 (7.620 - 8.255)
N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.045 - 0.065 (1.143 - 1.651) 0.130 0.005 (3.302 0.127) 0.400* (10.160) MAX 8 7 6 5
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 0.003 (0.457 0.076)
(
+0.035 0.325 -0.015 +0.889 8.255 -0.381
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988) 0.053 - 0.069 (1.346 - 1.752) 0.004 - 0.010 (0.101 - 0.254) 8 7 6 5
0.016 - 0.050 0.406 - 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.300 - 0.325 (7.620 - 8.255) 0.130 0.005 (3.302 0.127) 0.020 (0.508) MIN 0.045 - 0.065 (1.143 - 1.651) 0.770* (19.558) MAX 16 15 14 13 12 11 10 9
0.009 - 0.015 (0.229 - 0.381)
(
+0.035 0.325 -0.015 +0.889 8.255 -0.381
)
0.125 (3.175) MIN
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
SW Package 16-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620)
0.291 - 0.299** (7.391 - 7.595) 0.010 - 0.029 x 45 (0.254 - 0.737) 0.093 - 0.104 (2.362 - 2.642) 0.037 - 0.045 (0.940 - 1.143) 16 15 0.398 - 0.413* (10.109 - 10.490) 14 13 12 11 10 9
0 - 8 TYP
0.009 - 0.013 (0.229 - 0.330)
NOTE 1 0.016 - 0.050 (0.406 - 1.270)
NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 1 2 3 4 5 6 7 8
S16 (WIDE) 0396
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
Dimensions in inches (millimeters) unless otherwise noted.
0.255 0.015* (6.477 0.381)
1
2
3
4
N8 1197
0.100 0.010 (2.540 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
SO8 0996
1
2
3
4
0.065 (1.651) TYP 0.100 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076)
0.255 0.015* (6.477 0.381)
1
2
3
4
5
6
7
8
N16 1197
0.050 (1.270) TYP
NOTE 1 0.004 - 0.012 (0.102 - 0.305)
0.394 - 0.419 (10.007 - 10.643)
0.014 - 0.019 (0.356 - 0.482) TYP
11
LTC1595/LTC1596
TYPICAL APPLICATIONS
Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to - VREF
VREF -10V TO 10V 5V
0.1F 13 10 4 7 5 6 9 8 11 14 15 16 33pF OUT1 STB3 CLR VDD VREF RFB STB1 SRI LD1 LTC1596 SRO LD2 STB2 STB4 DGND AGND 12 TO NEXT DAC FOR DAISY-CHAINING 3
1595/96 F01a
OUT2
2
P
SRI LD
5
LTC1595 GND 4
(a) Bipolar Operation (4-Quadrant Multiplication) VOUT = - VREF to VREF
VREF -10V TO 10V R2 20k 5V R3 20k
(b)
0.1F 10 4 7 5 6 9 8 11
13
14
15
16 33pF OUT1
1/2 LT1112 OUT2 (20k / 2) 2
12 TO NEXT DAC FOR DAISY-CHAINING
3
1595/96 F02a
RESISTORS: CADDOCK T914-20K-010-02 (OR EQUIVALENT) 20k, 0.01%, TC TRACK = 2ppm/C
(a)
VREF -10V TO 10V 5V 0.1F 7 P 6 5 8 1 VDD VREF R2 20k R3 20k
2 RFB OUT1 3
33pF
CLK SRI LD GND 4 LTC1595
1/2 LT1112
(20k / 2)
(b)
RELATED PARTS
PART NUMBER LTC1590 LTC7541A LTC7543/LTC8143 LTC7545A LTC8043 DESCRIPTION Dual Serial I/O Multiplying IOUT 12-Bit DAC Parallel I/O Multiplying IOUT 12-Bit DAC Serial I/O Multiplying IOUT 12-Bit DACs Parallel I/O Multiplying IOUT 12-Bit DAC Serial I/O Multiplying IOUT 12-Bit DAC COMMENTS 16-Pin SO and PDIP, SPI Interface 12-Bit Wide Parallel Input Clear Pin and Serial Data Output (LTC8143) 12-Bit Wide Latched Parallel Input 8-Pin SO and PDIP
15956f LT/TP 0598 4K * PRINTED IN USA
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
+
-
R1 10k
1/2 LT1112
1595/96 F02b
+
-
+
-
P
STB3 CLR VDD VREF RFB STB1 SRI LD1 LTC1596 SRO LD2 STB2 STB4 DGND AGND
1
R1 10k
1/2 LT1112
VOUT -VREF TO VREF
VOUT -VREF TO VREF
(c) LINEAR TECHNOLOGY CORPORATION 1997
+
-
+
-
+
-
P
U
1
5V
LT1001 VOUT 0V TO -VREF
VREF -10V TO 10V 2 RFB OUT1 3 33pF
0.1F 7 6
8 1 VDD VREF CLK
LT1001
VOUT 0V TO -VREF
1595/96 F01b

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