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| LH531000B FEATURES * 131,072 words x 8 bit organization * Access time: 150 ns (MAX.) * Low power consumption: Operating: 192.5 mW (MAX.) Standby: 550 W (MAX.) * Programmable CE/OE/OE * Static operation * TTL compatible I/O * Three-state outputs * Single +5 V power supply * Packages: 28-pin, 600-mil DIP 28-pin, 450-mil SOP * Mask ROM specific pinout CMOS 1M (128K x 8) MROM DESCRIPTION The LH531000B is a mask-programmable ROM organized as 131,072 x 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 28-PIN DIP 28-PIN SOP TOP VIEW A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A14 A13 A8 A9 A11 A16 A10 CE /OE/OE D7 D6 D5 D4 D3 531000B-1 Figure 1. Pin Connections for DIP and SOP Packages 1 LH531000B CMOS 1M MROM A16 22 A15 1 A14 27 A13 26 A10 21 A9 24 A8 25 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 ADDRESS DECODER ADDRESS BUFFER A12 2 A11 23 MEMORY MATRIX (131,072 x 8) COLUMN SELECTOR SENSE AMPLIFIER CE/OE/OE 20 CE/OE BUFFER TIMING GENERATOR OUTPUT BUFFER 28 14 VCC GND 11 D0 12 D1 13 D2 15 D3 16 D4 17 D5 18 D6 19 D7 531000B-2 Figure 2. LH531000B Block Diagram PIN DESCRIPTION SIGNAL PIN NAME NOTE SIGNAL PIN NAME NOTE A0 - A16 D0 - D7 CE/OE/OE Address input Data output Chip Enable input or Output Enable input 1 VCC GND Power supply (+5 V) Ground NOTE: 1. Active level of CE/OE/OE is mask-programmable. TRUTH TABLE PIN 20 CE OE/OE MODE D0 - D7 SUPPLY CURRENT CE type OE type L H - - - - H/L L/H Selected Non selected Selected Non selected DOUT High-Z DOUT High-Z Operating (ICC) Standby (ISB) Operating (ICC) 2 CMOS 1M MROM LH531000B ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage Input voltage Output voltage Operating temperature Storage temperature VCC VIN VOUT Topr Tstg -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 0 to +70 -65 to +150 V V V C C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage VCC 4.5 5.0 5.5 V DC CHARACTERISTICS (VCC = 5 V 10%, TA = 0 to +70C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Input `Low' voltage Input `High' voltage Output `Low' voltage Output `High' voltage Input leakage current Output leakage current VIL V IH VOL VOH | ILI | | ILO | ICC1 ICC2 ICC3 ICC4 ISB1 ISB2 CIN COUT I OL = 2.0 mA I OH = -400 A V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 150 ns t RC = 1 s t RC = 150 ns t RC = 1 s CE = VIH CE = VCC - 0.2 V f = 1 MHz T A = 25C -0.3 2.2 2.4 0.8 VCC + 0.3 0.4 10 10 35 25 30 20 2 100 10 10 V V V V A A mA mA mA A pF pF 1 2 3 Operating current Standby current Input capacitance Output capacitance NOTES: 1. CE/OE = VIH, OE = VIL 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC - 0.2 V) or 0.2 V. CE = 0.2 V, outputs open AC CHARACTERISTICS (VCC = 5 V 10%, TA = 0 to +70C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE Read cycle time Address access time Chip enable access time Output enable time Output hold time CE to output in High-Z OE to output in High-Z tRC tAA tACE tOE tOH tCHZ tOHZ 150 150 150 70 5 70 70 ns ns ns ns ns ns ns 1 NOTE: 1. This is the time required for the output to become high-impedance. 3 LH531000B CMOS 1M MROM AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude Input rise/fall time Input reference level Output reference level Output load condition 0.6 V to 2.4 V 10 ns 1.5 V 0.8 V and 2.2 V 1TTL +100 pF tRC A0 - A16 tAA (NOTE) CE tACE (NOTE) OE OE tOE (NOTE) tOH tOHZ tCHZ D0 - D7 NOTE: Data becomes valid after tAA, tACE, and tOE from address input, chip enable, and output enable, respectively have been met. DATA VALID 531000B-3 Figure 3. Timing Diagram 4 CMOS 1M MROM LH531000B PACKAGE DIAGRAMS 28DIP (DIP028-P-0600) 28 15 DETAIL 13.45 [0.530] 12.95 [0.510] 1 36.30 [1.429] 35.70 [1.406] 14 0 TO 15 0.30 [0.012] 0.20 [0.008] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 0.51 [0.020] MIN. DIMENSIONS IN MM [INCHES] 28DIP-2 28-pin, 600-mil DIP 28SOP (SOP028-P-0450) 1.27 [0.050] TYP. 1.70 [0.067] 15 8.80 [0.346] 8.40 [0.331] 12.40 [0.488] 11.60 [0.457] 0.50 [0.020] 0.30 [0.012] 28 10.60 [0.417] 1 18.20 [0.717] 17.80 [0.701] 14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP 28-pin, 450-mil SOP 5 LH531000B CMOS 1M MROM ORDERING INFORMATION LH531000B Device Type X Package D 28-pin, 600-mil DIP (DIP028-P-0600) N 28-pin, 450-mil SOP (SOP028-P-0450) CMOS 1M (128K x 8) Mask Programmable ROM Example: LH531000BD (CMOS 1M (128K x 8) Mask Programmable ROM, 28-pin, 600-mil DIP) 531000B-7 6 |
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