|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
19-2269; Rev 3; 11/04 KIT ATION EVALU ABLE AVAIL +3.3V, 2.5Gbps Low-Power Limiting Amplifiers General Description Features Single +3.3V Power Supply 33mA Supply Current 5ps Deterministic Jitter 90ps Edge Speed Output Squelch Function Programmable Loss-of-Signal Function CML Output Interface 20-Pin 4mm 4mm QFN or Thin QFN Package Selectable Output Polarity MAX3272/MAX3272A The MAX3272/MAX3272A 2.5Gbps limiting amplifiers accept a wide range of input voltages and provide a constant-level output voltage with controlled edge speeds. Additional features include power detectors with programmable loss-of-signal (LOS) indication, an optional squelch function that mutes the data output signal when the input voltage falls below a programmable threshold, and an output polarity selector. These parts exhibit excellent jitter performance and have low power dissipation. The MAX3272/MAX3272A feature current-mode logic (CML) data outputs that are tolerant of inductive connectors, and are available in a 4mm 4mm QFN package or in die form (MAX3272 only). Along with the MAX3271, the MAX3272/MAX3272A are ideal for lowpower, compact optical receivers. Ordering Information PART MAX3272EGP MAX3272E/D MAX3272AEGP TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 20 QFN Dice* 20 QFN PACKAGE CODE G2044-3 -- G2044-3 Applications Gigabit Ethernet Optical Receivers Fibre Channel Optical Receivers System Interconnects 2.5Gbps Optical Receivers SONET/SDH Receivers MAX3272AETP+ -40C to +85C 20 Thin QFN T2044-3 + Denotes Lead-Free Package. *Dice are designed and guaranteed to operate from -40C to +85C, but are tested only at TA = +25C. Pin Configuration appears at end of data sheet. Typical Operating Circuit CAZ +3.3V +3.3V CAZ1 OUTPOL CAZ2 VCC MAX3272/ MAX3272A SDI+ +3.3V VCC IN+ 0.1F 0.1F IN100 OUT+ SDO+ SDO- MAX3873 OUTSDICDR SCLKO+ SCLKOGND MAX3271 CLOS TH CCLOS RTH LOSS OF SIGNAL SQUELCH GND LOS LOS LEVEL Typical Operating Circuits continue at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A ABSOLUTE MAXIMUM RATINGS Power-Supply Voltage (VCC) .................................-0.5V to +6.0V Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V) Voltage at SQUELCH, CAZ1, CAZ2, TH, CLOS ...............................................-0.5V to (VCC + 0.5V) Voltage at LOS, LOS (MAX3272)...........................-0.5V to +6.0V Voltage at LOS, LOS (MAX3272A) .............-0.5V to (VCC + 0.5V) Voltage at LEVEL...................................................-0.5V to +2.0V Voltage at OUTPOL ...............................................-0.5V to +6.0V Current into LOS, LOS ..........................................-1mA to +9mA Differential Input Voltage (IN+ - IN-).................................2.5VP-P Continuous Current at IN+, IN- ...........................................50mA Continuous Current at CML Outputs (OUT+, OUT-) .........................-25mA to +25mA Continuous Power Dissipation at +85C 20-Pin Thin QFN (derate 16.9mW/C above +85C) ......1.1W 20-Pin QFN (derate 20mW/C above +85C) .................1.3W Storage Ambient Temperature Range (TSTG) .................................................-55C to +150C Operating Junction Temperature Range (TJ) .....................................................-55C to +150C Die Attach Temperature...................................................+400C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 1) PARAMETER Supply Current Input Data Rate Input Voltage Range Output Deterministic Jitter Random Jitter Data Output Edge Speed (20% to 80%) Differential Input Resistance Input-Referred Noise CML Output Voltage Output Signal when Squelched Power-Supply Noise Rejection Low Frequency Cutoff Output Resistance Single-Ended Output Return Loss Differential Input Return Loss OUTPOL Input Limits LOS Hysteresis LOS Assert/Deassert Time Low LOS Assert Level Low LOS Deassert Level Medium LOS Assert Level Medium LOS Deassert Level High LOS Assert Level VIL VIH (Notes 3, 4, 8) CCLOS = open (Notes 3, 9, 10) CCLOS = 0.01F (Notes 3, 9, 10) RTH = 20k (Notes 3, 10) RTH = 20k (Notes 3, 10) RTH = 1k (Notes 3, 10) RTH = 1k (Notes 3, 10) RTH = 80 (Notes 3, 10) 24.3 7.8 2.3 4.5 2.4 2 3.3 1 50 6.5 9.5 12.9 17.4 48 22.4 12.7 100 PSNR fOC ROUT VOUT LEVEL open, RLOAD = 50 Outputs AC-coupled f 2MHz (Note 7) CAZ = open CAZ = 0.1F Single ended to VCC 2.5GHz 2.5GHz to 4.0GHz 4.0GHz 42.5 550 RIN VIN Differential (Notes 3, 4, 5) (Notes 4, 6) (Notes 3, 4) IN+ to IN15mVP-P < VIN 30mVP-P 30mVP-P VIN 1200mVP-P 95 15 5 3 90 90 100 220 750 2.2 30 0.9 1.5 50 10 9 10 0.8 57.5 1200 130 115 105 SYMBOL ICC (Note 2) CONDITIONS MIN TYP 33 2.5 1200 27 MAX 44 UNITS mA Gbps mVP-P psP-P psRMS ps VRMS mVP-P mVP-P dB MHz kHz dB dB V dB s mVP-P mVP-P mVP-P mVP-P mVP-P 2 _______________________________________________________________________________________ +3.3V, 2.5Gbps Low-Power Limiting Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) PARAMETER High LOS Deassert Level LOS Output High Voltage LOS Output Low Voltage Squelch Input Current SYMBOL Sinking 30A Sourcing 1.2mA CONDITIONS RTH = 80 (Notes 3, 10) 2.4 0.4 400 MIN TYP 73 MAX 124.7 UNITS mVP-P V V A MAX3272/MAX3272A Dice are designed and guaranteed from -40C to +85C but are tested only at TA = +25C. Supply current measurement excludes the current of the CML output stage (16mA typical). See Figure 1, Power-Supply Current Measurement. Note 3: Guaranteed by design and characterization. Note 4: Input edge speed is controlled using 4-pole, lowpass Bessel filters with bandwidth approximately 75% of the maximum data rate. Note 5: Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). Deterministic jitter is the peak-to-peak deviation from ideal time crossings, measured at the zero-level crossings of the differential output per ANSI X3.230, Annex A. Note 6: Random jitter is measured with the minimum input signal. For Fibre Channel and Gigabit Ethernet applications, the peakto-peak random jitter is 14.1 times the RMS random jitter. Note 7: Power-supply noise rejection (PSNR) is calculated by the equation PSNR = 20log (VCC/(VOUT)), where VOUT is the change in differential output voltage due to the power-supply noise, VCC. See Power-Supply Noise Rejection vs. Frequency in the Typical Operating Characteristics. Note 8: Hysteresis is defined as: 20 log(VLOS-DEASSERT/VLOS-ASSERT). Note 9: Response time to a 10dB change in input power. For the specification guaranteed, the power is assumed to switch back and forth between two levels (separated by 10dB and equidistant from assert and deassert levels) outside of the two hysteresis thresholds. Note 10: All power-detect AC parameters are guaranteed with a 223 - 1 PRBS, 2.5Gbps input, with the longest possible run of 80CID. Note 1: Note 2: Typical Operating Characteristics (VCC = +3.3V, TA = +25C, unless otherwise noted.) OUTPUT AMPLITUDE vs. INPUT AMPLITUDE MAX3272 toc01 SUPPLY CURRENT vs. AMBIENT TEMPERATURE MAX3272 toc02 DETERMINISTIC JITTER vs. INPUT AMPLITUDE 18 DETERMINISTIC JITTER (psP-P) 16 14 12 10 8 6 4 2 0 MAX3272 toc03 1000 950 900 VOUT (mVP-P) 850 800 LEVEL = OPEN 750 700 650 600 0 10 20 30 40 LEVEL = GND 70 65 60 SUPPLY CURRENT (mA) 55 50 45 40 35 30 25 20 20 50 -40 -15 10 35 60 85 1 10 100 1000 10,000 VIN (mVP-P) AMBIENT TEMPERATURE (C) INPUT AMPLITUDE (mVP-P) _______________________________________________________________________________________ 3 +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25C, unless otherwise noted.) RANDOM JITTER vs. INPUT AMPLITUDE MAX3272 toc04 LOS HYSTERESIS vs. AMBIENT TEMPERATURE MAX3272 toc05 LOSS-OF-SIGNAL WITH SQUELCH VIN MAX3272 toc06 10 9 8 RANDOM JITTER (psRMS) 7 6 5 4 3 2 1 0 1 10 100 1000 5.0 4.5 HYSTERESIS (dB) 4.0 RTH = 80 3.5 3.0 2.5 2.0 VOUT RTH = 20k RTH = 1k VLOS CCLOS = 0.01F 10,000 -40 -15 10 35 60 85 20s/div INPUT AMPLITUDE (mVp-p) AMBIENT TEMPERATURE (C) LOSS OF SIGNAL TRESHOLD vs. RTH XXXXXXXX DATA OUTPUT EYE DIAGRAM (MINIMUM INPUT) MAX3272 toc08 DATA OUTPUT EYE DIAGRAM (MAXIMUM INPUT) 2.5Gbps 223 -1 PRBS 1200mVP-P INPUT MAX3272 toc09 50 45 40 LOS ASSERT (mV) 35 30 25 20 15 10 5 0 10 100 1k 10k 100k 2.5Gbps 223 -1 PRBS 15mVP-P INPUT 150mV/ div 150mV/ div 1M 100ps/div 100ps/div RTH () POWER-SUPPLY NOISE REJECTION vs. FREQUENCY MAX3272 toc10 INPUT RETURN LOSS vs. FREQUENCY MAX3272 toc11 OUTPUT RETURN LOSS vs. FREQUENCY 40 OUTPUT RETURN LOSS (dB) 35 30 25 20 15 10 5 0 MAX3272 toc12 60 POWER-SUPPLY NOISE REJECTION (dB) 50 40 30 20 10 0 1k 10k 100k FREQUENCY (Hz) 1M 45 40 INPUT RETURN LOSS (dB) 35 30 25 20 15 10 5 0 45 10M 10M 100M 1G 10G 10M 100M 1G 10G FREQUENCY (Hz) FREQUENCY (Hz) 4 _______________________________________________________________________________________ +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25C, unless otherwise noted.) COMMON-MODE REJECTION RATIO vs. FREQUENCY MAX3272 toc13 LOS ASSERT AND DEASSERT LEVELS vs. DATA RATE MAX3272 toc14 19.0 COMMON-MODE REJECTION RATIO (dB) 18.5 18.0 12 10 8 VIN (mVP-P) 6 ASSERT 4 DEASSERT 17.5 17.0 16.5 16.0 15.5 15.0 100k 1M 10M 100M FREQUENCY (Hz) 2 0 0 223 - 1 PRBS PATTERN RTH = 20k CIN = 0.1F 500 1000 1500 2000 2500 DATA RATE (Mbps) Pin Description PIN 1, 4, 17 2 3 5 6, 12, 15, 20 7 8 NAME GND IN+ INTH VCC CLOS SQUELCH Supply Ground Noninverted Input Signal Inverted Input Signal Loss-of-Signal Threshold Pin. Resistor to ground sets the LOS threshold. Power Supply LOS Time-Constant Capacitor Connection. For SONET applications, CCLOS = 0.01F is recommended. Squelch Input. The squelch function is disabled when SQUELCH is not connected or set to TTL low level. When SQUELCH is set to TTL high level and LOS is asserted, the data outputs (OUT+, OUT-) are forced to static levels. Noninverted Loss-of-Signal Output. LOS is asserted TTL high when the signal drops below the assert threshold set by the TH input. The MAX3272 does not have ESD protection on this pin. The MAX3272A has ESD protection on this pin. Inverted Loss-of-Signal Output. LOS is asserted TTL low when the signal drops below the assert threshold set by the TH input. The MAX3272 does not have ESD protection on this pin. The MAX3272A has ESD protection on this pin. Output Current Level. When this pin is not connected, the CML output current is approximately 16mA. When this pin is connected to ground, the output current increases to about 20mA. Inverted Data Output Noninverted Data Output Output Polarity Control Input. Connect to GND for an inversion of polarity through the limiting amplifier and connect to VCC for normal operation. Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and CAZ1 extends the time constant of the offset correction loop. Typical value of CAZ is 0.1F. Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and CAZ2 extends the time constant of the offset correction loop. Typical value of CAZ is 0.1F. Connect the exposed paddle to board ground for optimal electrical and thermal performance. FUNCTION 9 LOS 10 LOS 11 13 14 16 18 19 EP LEVEL OUTOUT+ OUTPOL CAZ2 CAZ1 EXPOSED PAD _______________________________________________________________________________________ 5 +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A VCC Detailed Description ICC IOUT 50 50 Figure 2 is a functional diagram of the MAX3272/ MAX3272A, comprising a CML input buffer, power detector and loss-of- signal indicators, gain stage, offsetcorrection loop, and CML output buffer. CML Input Buffer The input buffer (Figure 3) provides 100 input impedance between IN+ and IN-. DC-coupling the inputs is not recommended; this prevents the DC offset-correction circuitry from functioning properly. SQUELCH OPEN Power Detect and Loss-of-Signal Indicator The MAX3272/MAX3272A are equipped with loss-of-signal (LOS) circuitry that indicates when the input signal is below a programmable threshold, set by resistor RTH at the TH pin (see the Typical Operating Characteristics for appropriate resistor selection). An averaging peakpower detector compares the input signal amplitude with this threshold and feeds the signal-detect information to the LOS outputs, which are internally terminated to 8k (Figure 4). TH CLOS MAX3272/ MAX3272A CONTROL LEVEL OPEN CML SUPPLY CURRENT (ICC) RTH Figure 1. Power-Supply Current Measurement MAX3272/ MAX3272A TTL POWER DETECTOR TTL LOS LOS POWER DETECTOR AND LOS INDICATOR CONTROL SQUELCH IN+ 100 INCML INPUT BUFFER CML OUTPUT BUFFER OUT+ OUT- LOWPASS FILTER OFFSET CORRECTION LEVEL OUTPOL 0.1F CAZ1 CAZ2 Figure 2. Functional Diagram 6 _______________________________________________________________________________________ +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A Interface Schematics VCC VCC 540 0.25pF IN+ 540 8k 110 IN0.25pF ESD STRUCTURE ESD STRUCTURES GND LOS Figure 4a. LOS Output Circuit for MAX3272 VCC GND Figure 3. Input Circuit Two control voltages VASSERT, and VDEASSERT, define the LOS assert and deassert levels. To prevent LOS chatter in the region of the programmed threshold, approximately 3.3dB of hysteresis is built into the LOS assert/deassert function. Once asserted, LOS is not deasserted until the input amplitude rises to the required level (VDEASSERT). To facilitate interfacing with +5V modules, the LOS and LOS pins on the MAX3272 do not have internal ESD protection. If ESD protection is desired, a low-capacitance Schottky diode or diode array structure, such as the MAX3202E, is recommended (see the Typical Operating Circuits). The LOS and LOS pins on the MAX3272A include ESD protection and, as a result, cannot be interfaced with +5V modules. 8k LOS ESD STRUCTURE GND Figure 4b. LOS Output Circuit for MAX3272A Offset-Correction Loop Due to the high gain of the amplifier, the MAX3272/ MAX3272A are susceptible to DC offsets in the signal path. In communications systems using NRZ data with a 50% duty cycle, pulse-width distortion present in the signal or generated by the transimpedance amplifier appears as input offset and is removed by the offsetcancellation loop. An external capacitor is required between CAZ1 and CAZ2 to decouple the offset-cancellation loop and determine the lower 3dB frequency of the signal path. Gain Stage The high-bandwidth gain stage provides approximately 42dB of gain. _______________________________________________________________________________________ 7 +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A VCC ESD STRUCTURES 50 50 OUT+ OUT- Design Procedure Program the LOS Assert Threshold External resistor R TH programs the loss-of-signal threshold. See the LOS Threshold vs. RTH graph in the the Typical Operating Characteristics section to select the appropriate resistor. Select the Coupling Capacitors When AC-coupling, input and output coupling capacitors (CIN and COUT) should be selected to minimize the receiver's deterministic jitter. Jitter is decreased as the input low-frequency cutoff (fIN) is decreased: fIN = 1 / [2(50)(CIN)] For ATM/SONET or other applications using scrambled NRZ data, select (CIN, COUT) 0.1F, which provides fIN < 32kHz. For Fibre Channel, Gigabit Ethernet, or other applications using 8B/10B data coding, select (CIN, COUT) 0.01F, which provides fIN < 320kHz. Refer to application note HFAN-1.1: Choosing ACCoupling Capacitors. GND LEVEL Select the Offset-Correction Capacitor The capacitor between CAZ1 and CAZ2 determines the time constant of the signal path DC offset-cancellation loop. To maintain stability, it is important to keep a onedecade separation between fIN and the low-frequency cutoff (fOC) associated with the DC offset-cancellation circuit. For ATM/SONET or other applications using scrambled NRZ data, f IN < 32kHz, so f OCMAX < 3.2kHz. Therefore, CAZ = 0.1F (fOC = 2kHz). For Fibre Channel or Gigabit Ethernet applications, leave pins CAZ1 and CAZ2 open. Figure 5. CML Output Circuit CML Output Buffer The MAX3272/MAX3272A CML output circuit (Figure 5) provides high tolerance to impedance mismatches and inductive connectors. The output current can be set to two levels using the LEVEL pin. When LEVEL is unconnected, the output current is approximately 16mA. Connecting LEVEL to ground sets the output current to approximately 20mA. The squelch function is enabled when the SQUELCH pin is set to a TTL high. This function holds OUT+ and OUT- to a static level whenever the input signal amplitude drops below the loss-of-signal threshold. This circuit is also equipped with a polarity selector, programmed by the OUTPOL pin. When this pin is connected to VCC, no inversion will occur. When connected to ground, the output signal will be inverted. Program the LOS Time Constant External capacitor CCLOS programs the LOS assert and deassert times. When inputting data with many consecutive identical digits (CIDs), a longer time constant may be advantageous, so LOS does not flag incorrectly. In this case, connect the CLOS pin to a 0.01F capacitor to set the assert time in the range of 2s to 100s. For scrambled data where the mark density is kept at 50%, a shorter time constant may be desirable. Leave the CLOS pin open for a shorter time constant of about 1s. 8 _______________________________________________________________________________________ +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A Pin Configuration PAD OUTPOL Pad Coordinates NAME GND IN+ INGND TH VCC CLOS SQUELCH LOS LOS LEVEL VCC OUTOUT+ VCC OUTPOL GND CAZ2 CAZ1 N.C. VCC COORDINATES (m) 47, 836 47, 603 47, 425 47, 237 47, 47 255, -154 436, -154 645, -154 850, -154 1063, -154 1331, 37 1331, 212 1331, 421 1331, 573 1331, 780 1119, 1042 957, 1042 773, 1042 583, 1042 422, 1042 268, 1042 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CAZ1 CAZ2 18 20 19 17 GND VCC TOP VIEW 16 GND IN+ INGND TH 1 2 3 4 5 15 14 VCC OUT+ OUTVCC LEVEL MAX3272/ MAX3272A 13 12 11 6 VCC 7 CLOS 8 SQUELCH 9 LOS GND 10 LOS OUTPOL QFN* NOTE: EXPOSED PAD MUST BE CONNECTED TO SUPPLY GROUND. CAZ1 CAZ2 VCC 20 19 18 17 16 Coordinates are for the center of the pad. Coordinate 0, 0 is the lower left corner of the passivation opening for pad 5. GND IN+ INGND TH 1 2 3 4 5 + 15 14 VCC OUT+ OUTVCC LEVEL Applications Information Optical Hysteresis In an optical receiver, the electrical power change at the limiting amplifier is 2 times the optical power change. As an example, if a receiver's optical input power (x) increases by a factor of two, and the preamplifier is linear, then the voltage input to the limiting amplifier also increases by a factor of two. The optical power change is 10log(2x / x) = 10log(2) = +3dB. At the limiting amplifier, the electrical power change is: 10log MAX3272A 13 12 11 6 VCC 7 CLOS 8 SQUELCH 9 LOS 10 LOS THIN QFN* NOTE: EXPOSED PAD MUST BE CONNECTED TO SUPPLY GROUND. (2VIN )2 / RIN VIN2 / RIN = 10log(22 ) = 20log(2) = + 6dB The MAX3272 typical voltage hysteresis is 3.3dB. This provides an optical hysteresis of 1.65dB. _______________________________________________________________________________________ 9 +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A Typical Operating Circuit (continued) CAZ +3.3V +3.3V CAZ1 OUTPOL CAZ2 VCC MAX3272 +3.3V VCC IN+ 0.1F 0.1F IN100 OUT+ SDI+ SDO+ SDO- MAX3873 OUTSDICDR SCLKO+ SCLKOGND MAX3271 CLOS TH CCLOS RTH LOSS OF SIGNAL *THE MAX3202E PROVIDES ESD PROTECTION ON THE LOS PIN SQUELCH GND LOS LOS LEVEL +3.3V VCC I/01 MAX3202E* GND Wire Bonding Die For high-current density and reliable operation, the MAX3272 uses gold metallization. Make connections to the dice with gold wire only, and use ball-bonding techniques (wedge bonding is not recommended). Die pad dimensions are 94.4 microns by 94.4 microns. Die thickness is 15 mils (0.375mm). 10 ______________________________________________________________________________________ +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A Chip Information VCC (PAD 21) N.C. (PAD 20) CAZ1 (PAD 19) CAZ2 (PAD 18) GND (PAD 17) OUTPOL (PAD 16) GND (PAD 1) VCC (PAD 15) IN+ (PAD 2) OUT+ (PAD 14) IN(PAD 3) OUT(PAD 13) 62 mils 1.57mm GND (PAD 4) VCC (PAD 12) TH (PAD 5) LEVEL (PAD 11) VCC (PAD 6) CLOS (PAD 7) SQUELCH (PAD 8) 66 mils 1.68mm LOS (PAD 9) LOS (PAD 10) TRANSISTOR COUNT: 726 PROCESS: SiGe Bipolar SUBSTRATE: Insulator, Connect to GND DIE SIZE: 1.68mm 1.57mm DIE THICKNESS: 15 mils ______________________________________________________________________________________ 11 +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 12,16,20, 24L QFN.EPS PACKAGE OUTLINE 12,16,20,24L QFN, 4x4x0.90 MM 21-0106 E 1 2 12 ______________________________________________________________________________________ +3.3V, 2.5Gbps Low-Power Limiting Amplifiers Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3272/MAX3272A PACKAGE OUTLINE 12,16,20,24L QFN, 4x4x0.90 MM 21-0106 E 2 2 ______________________________________________________________________________________ 13 +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 1 2 PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
Price & Availability of MAX3272 |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |