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| Data Sheet No. PD94138 IRU1260 DUAL 6A AND 1A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR DESCRIPTION The IRU1260 uses a proprietary process and combines a dual low dropout adjustable output regulator in a single package with one output having a minimum of 6A and the other one having a 1A output current capability. This product is specifically designed to provide well regulated supplies for low voltage ICs such as 3.3V to 1.5V and 2.5V supplies for the GTL+ termination and the new clock for Pentium IITM applications. Other applications include low cost dual supply for processors such as Intel P55CTM where 2.8V and 3.3V are needed for the Core and the I/O supplies from the 5V input. FEATURES Guaranteed <1.3V Dropout at 6A (Output #2) Guaranteed <0.6V Dropout at 1A (Output #1) Fast Transient Response 1% Voltage Reference Initial Accuracy Built-In Thermal Shutdown APPLICATIONS Providing a Single Package Solution for GTL+ and High Speed Bus Termination Dual Supply P55CTM Applications TYPICAL APPLICATION 3.3V C1 R1 C2 VOUT1 VIN 2.5V / 1A 7 6 5 4 3 2 R5 C4 R2 U1 VOUT2 Gnd VFB2 VFB1 VCTRL 1.5V / 6A R3 C3 R4 IRU1260 1 C5 5V Figure 1 - Typical application of IRU1260 in the Pentium IITM design with the 1.5V output providing for GTL+ termination while 2.5V supplies the clock chip. Notes: Pentium IITM is trademark of Intel Corp. P55CTM is trademark of Intel Corp. PACKAGE ORDER INFORMATION TJ (C) 0 To 150 7-PIN PLASTIC TO-263 (M) IRU1260CM 7-PIN PLASTIC Ultra Thin-PakTM (P) IRU1260CP Rev. 2.1 09/19/02 www.irf.com 1 IRU1260 ABSOLUTE MAXIMUM RATINGS Input Voltage (VIN) .................................................... Power Dissipation ..................................................... Storage Temperature Range ...................................... Operating Junction Temperature Range ..................... 7V Internally Limited -65C To 150C 0C To 150C PACKAGE INFORMATION 7-PIN PLASTIC TO-263 (M) 7 6 5 4 3 2 1 7-PIN ULTRA THIN-PAK (P) 7 6 5 4 3 2 1 VOUT1 VIN VOUT2 Gnd VFB2 VFB1 VCTRL VOUT1 VIN VOUT2 Gnd VFB2 VFB1 VCTRL JA=308C/W for 1"sq pad JA=308C/W for 1"sq pad ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over CIN=1mF, COUT=10mF and TJ=0 to 150C. Typical values refer to TJ=25C. IFL=6A for output #1 and IFL=1A for output #2. VFB=VOUT for both outputs. VCTRL=VIN=3.3V. PARAMETER VCTRL Input Voltage Reference Voltage Line Regulation Load Regulation (Note 1) Dropout Voltage (Output #2) (Note 2) Dropout Voltage (Output #1) (Note 2) Current Limit (Output #2) Current Limit (Output #1) Thermal Regulation Ripple Rejection Feedback Pin Input Current Temperature Stability Long Term Stability RMS Output Noise Minimum Load Current (Note 3) SYM VREF TEST CONDITION Io=10mA, TJ=25C Io=10mA Io=10mA, VOUT+1.3V 1.0 0.7 0.5 0.6 1.3 V A A %/W dB mA % % %VO mA ICL2 ICL1 0.02 IFB 1 Note 1: Low duty cycle pulse testing with Kelvin connections is required in order to maintain accurate data. Note 2: Dropout voltage is defined as the minimum differential voltage between VIN and VOUT required to maintain regulation at VOUT. It is measured when the output voltage drops 1% below its nominal value. Note 3: Minimum load current is defined as the minimum current required at the output in order for the output voltage to maintain regulation. Typically the resistor divider values are selected such that this current is automatically maintained. 2 www.irf.com Rev. 2.1 09/19/02 IRU1260 PIN DESCRIPTIONS PIN # 1 PIN SYMBOL VCTRL PIN DESCRIPTION The control input pin of the regulator. This pin via a 10V resistor is connected to the 5V supply to provide the base current for the pass transistor of both regulators. This allows the regulator to have very low dropout voltage which allows one to generate a well regulated 2.5V supply from the 3.3V input. A high frequency, 1mF capacitor is connected between this pin and VIN pin to insure stability. A resistor divider from this pin to VOUT1 pin and ground sets the output voltage. See application circuit for the divider setting for 2.5V output. A resistor divider from this pin to the VOUT2 pin and ground sets the output voltage. See application circuit for the divider setting for 1.5V output. This pin is connected to ground. It is also the tab of the package. The output #2 (high current) of the regulator. A minimum of 100mF capacitor must be connected from this pin to ground to insure stability. The power input pin of the regulator. Typically a large storage capacitor is connected from this pin to ground to insure that the input voltage does not sag below the minimum dropout voltage during the load transient response. This pin must always be higher than both VOUT pins by the amount of the dropout voltage in order for the device to regulate properly.(See data sheet) The output #1 (low current) of the regulator. A minimum of 100mF capacitor must be connected from this pin to ground to insure stability. 2 VFB1 3 VFB2 4 5 Gnd VOUT2 6 VIN 7 VOUT1 BLOCK DIAGRAM VIN 6 VCTRL 1 2 VFB1 7 VOUT1 THERMAL SHUTDOWN 1.20V + 4 Gnd 3 VFB2 5 VOUT2 Figure 2 - Simplified block diagram of the IRU1260. Rev. 2.1 09/19/02 www.irf.com 3 IRU1260 APPLICATION INFORMATION Introduction The IRU1260 is a dual adjustable Low Dropout (LDO) regulator which can easily be programmed with the addition of two external resistors to any voltages within the range of 1.20 to 5.5V. This voltage regulator is designed specifically for applications that require two separate regulators such as the Intel Pentium IITM processors requiring 1.5V and 2.5V supplies, eliminating the need for a second regulator which results in lower overall system cost. When VCTRL pin is connected to a supply which is at least 1V higher than VIN, the dropout voltage improves by 30% which makes it ideal for applications requiring less than the standard 1.3V dropout given in the LDO products such as IRU10XX series. The IRU1260 also provides an accurate 1.20V voltage reference common to both regulators for programming each output voltage. Other features of the device include: fast response to sudden load current changes, such as GTL+ termination application for Pentium IITM family of microprocessors. The IRU1260 also includes thermal shutdown protection to protect the device if an overload condition occurs. Output Voltage Setting The IRU1260 can be programmed to any voltages in the range of 1.20V to 5.5V with the addition of R1 and R2 external resistors according to the following formula: VOUT = VREF3 1+ The IRU1260 keeps a constant 1.2V between the VFB pin and ground pin. By placing a resistor R1 across these two pins a constant current flows through R1, adding to the IFB current and into the R2 resistor producing a voltage equal to the (1.2/R1)3R2 + IFB3R2 which will be added to the 1.2V to set the output voltage as shown in the above equation. Since the input bias current of the amplifier (IFB) is only 0.02mA typically, it adds a very small error to the output voltage and for most applications can be ignored. For example, in a typical 1.5V GTL+application if R1=10.2KV and R2=2.55KV the error due to the I DJ is only 0.05mV which is less than A 0.004% of the nominal set point. The effective input impedance seen by the feedback pins (The parallel combination of R1 and R2) must always be higher than 1.8KV in order for the regulator to start up properly. Load Regulation Since the IRU1260 does not provide a separate ground pin for the reference voltage, it is not possible to provide true remote sensing of the output voltage at the load. Figure 4 shows that the best load regulation is achieved when the bottom side of R1 resistor is connected directly to the ground pin of IRU1260 (preferably to the tab of the device) and the top side of R2 resistor is connected to the load. In fact, if R1 is connected to the load side, the effective resistance between the regulator and the load is gained up by the factor of (1+R2/R1), or the effective resistance will be, RP(eff)=RP3(1+R2/R1). It is important to note that for high current applications, this can represent a significant percentage of the overall load regulation and one must keep the path from the regulator to the load as short as possible to minimize this effect. VIN VIN VIN VOUT V IN VOUT ( R2 R1 ) +R23IB Where: VREF = 1.20V Typically IB = 0.02mA Typical R1 and R2 as shown in Figure 3: VOUT R2 IB IRU1260 VCTRL V CTRL Gnd R1 VFB R2 RL IRU1260 VCTRL VCTRL Gnd VREF VFB R1 RP Figure 3 - Typical application of the IRU1260 for programming the output voltage. (Only one output is shown here) PARASITIC LINE RESISTANCE Figure 4 - Schematic showing connection for best load regulation. (Only one output is shown here) 4 www.irf.com Rev. 2.1 09/19/02 IRU1260 Stability The IRU1260 requires the use of an output capacitor as part of the frequency compensation in order to make the regulator stable. Typical designs for the microprocessor applications use standard electrolytic capacitors with typical ESR in the range of 50 to 100mV and the output capacitance of 500 to 1000mF. Fortunately as the capacitance increases, the ESR decreases resulting in a fixed RC time constant. The IRU1260 takes advantage of this phenomena in making the overall regulator loop stable. For most applications a minimum of 100mF aluminum electrolytic capacitor with the maximum ESR of 0.3V such as Sanyo, MVGX series, Panasonic FA series as well as the Nichicon PL series insures both stability and good transient response. The IRU1260 also requires a 1mF ceramic capacitor connected from VIN to VCTRL and a 10V, 0.1W resistor in series with VCTRL pin in order to further insure stability. Thermal Design The IRU1260 incorporates an internal thermal shutdown that protects the device when the junction temperature exceeds the maximum allowable junction temperature. Although this device can operate with junction temperatures in the range of 1508C, it is recommended that the selected heat sink be chosen such that during maximum continuous load operation the junction temperature is kept below this number. The example given shows the steps in selecting the proper regulator heat sink for driving the Pentium IITM processor GTL+ termination resistors and the Clock IC using the IRU1260 TO-263 package. Example: Assuming the following specifications: VIN = 3.3V VOUT1 = 2.5V VOUT2 = 1.5V IOUT1(MAX) = 0.2A IOUT2(MAX) = 1.5A TA = 358C The steps for selecting a proper heat sink to keep the junction temperature below 1358C is given as: 1) Calculate the maximum power dissipation using: PD = IOUT13(VIN - VOUT1) + IOUT23(VIN - VOUT2) PD = 0.23(3.3 - 2.5) + 1.53(3.3 - 1.5) = 2.86W 2) Assuming a TO-263 surface mount package, the junction to ambient thermal resistance of the package is: uJA = 308C/W for 1" square pad area 3) The maximum junction temperature of the device is calculated using the equation below: TJ = TA + PD3uJA TJ = 35 + 2.86330 = 1218C Since this is lower than our selected 1358C maximum junction temperature (1508C is the thermal shutdown of the device), TO-263 package is a suitable package for our application. Rev. 2.1 09/19/02 www.irf.com 5 IRU1260 Layout Consideration The IRU1260 like all other high speed linear regulators need to be properly laid out to insure stable operation. The most important component is the output capacitor, which needs to be placed close to the output pin and connected to this pin using a plane connection with a low inductance path. IRU1260 in Ultra LDO, Single Output Application The IRU1260 can also be used in single supply applications where the difference between input and output is much lower than the standard 1.5V dropout that is obtainable with standard LDO devices. The schematic in Figure 7 shows the application of the IRU1260 in a single supply with the second LDO being disabled. In this application, the IRU1260 is used on the VGA card to convert 3.3V supply to 2.7V to power the Intel 740 chip rather than the conventional LDO which due to its 1.5V minimum dropout spec must use the 5V supply to achieve the same result. The difference is a substantial decrease in the power dissipation as shown below. The maximum power dissipation of the Intel 740 chip is 5.8W, which at 2.7V results in: Io = 5.8 = 2.15A 2.7 a) Using standard LDO, the power dissipated in the device is: PD = (VIN - Vo)3Io = (5 - 2.7)32.15 = 4.94W Using surface mount TO-263 package with 258C/W junction to air thermal resistance results in: TJ = PD3uJA + TA = 4.94325 + 25 = 1488C This is very close to the thermal shutdown of the IC. b) Using IRU1260, the power dissipated in the device is drastically reduced by using 3.3V supply instead of 5V. PD = (VIN - Vo)3Io = (3.3 - 2.7)32.15 = 1.3W Using surface mount TO-263 package with 258C/W junction to air thermal resistance results in: TJ = PD3uJA + TA = 1.3325 + 25 = 578C A reduction of 918C in junction temperature. 6 www.irf.com Rev. 2.1 09/19/02 IRU1260 TYPICAL APPLICATION PENTIUM TM APPLICATION 3.3V C1 R1 C2 VOUT 1 VIN 2.5V / 1A 7 6 5 4 3 2 1 C4 R2 U1 VOUT 2 Gnd VFB2 VFB1 VCTRL 1.5V / 6A R3 C3 R4 R5 C5 IRU1260 5V Figure 5 - Typical application of IRU1260 in the Pentium TM design with the 1.5V output providing for GTL+ termination while 2.5V supplies the clock chip. Note: Pentium is trademark of Intel Corp. Ref Desig U1 C1, C3 C2 C4 C5 R1 R2, R4 R3 R5 HS1 Description Dual LDO Regulator Capacitor Capacitor Capacitor Capacitor Resistor Resistor Resistor Resistor Heat Sink Qty 1 2 1 1 1 1 2 1 1 Part # Manuf IRU1260CM IR Elect, 680mF, EEUFA1A681L Panasonic Elect, 220mF, 6.3V, ECAOJFQ221 Panasonic Ceramic, 0.1mF, SMT, 0805 Panasonic Elect,100mF, 6.3V, ECAOJFQ101 Panasonic 11KV, 1%, SMT, 0805 Panasonic 10.2KV, 1%, SMT, 0805 Panasonic 2.55KV, 1%, SMT, 0805 Panasonic 3V, 5%, SMT, 0805 Panasonic Use 1" Square Copper Pad area if IOUT2<1.7A & IOUT1<0.2A. For IOUT2<3A & IOUT1<0.5A, use IRU1260CT and Thermalloy 6030B Rev. 2.1 09/19/02 www.irf.com 7 IRU1260 TYPICAL APPLICATION RAMBUS APPLICATION 5V C1 R1 C2 VOUT1 VIN 2.5V 7 6 5 4 3 2 1 R2 U1 VOUT2 Gnd VFB 2 VFB 1 VCTRL 3.3V R3 C3 R4 IRU1260 Figure 6 - Typical application of IRU1260 in the Rambus TM design with the 2.5V output providing for memory termination while 3.3V supplies the on board logic. Note: Rambus TM is trademark of Rambus Corp. Ref Desig U1 C1, C2, C3 R1 R2, R4 R3 HS1 Description Dual LDO Regulator Capacitor Resistor Resistor Resistor Heat Sink Qty 1 3 1 2 1 Part # Manuf IRU1260CM IR Elect, 220mF, 6.3V, ECAOJFQ221 Panasonic 11KV, 1%, SMT, 0805 Panasonic 10.2KV, 1%, SMT, 0805 Panasonic 17.8KV, 1%, SMT, 0805 Panasonic 1" Square Copper Pad area if IOUT2<1.2A & IOUT1<0.5A. For IOUT2<3A & IOUT1<0.5A, use Thermalloy 6030B 8 www.irf.com Rev. 2.1 09/19/02 IRU1260 TYPICAL APPLICATION INTEL 740 GRAPHICS CHIP APPLICATION 3.3V C1 VOUT1 VIN 7 6 5 4 3 2 1 C5 R4 R5 C4 R3 C3 U1 VOUT2 Gnd VFB 2 VFB 1 VCTRL 2.7V IRU1260 5V Figure 7 - Typical application of IRU1260 to provide 2.7V from the 3.3V bus for the Intel 740 graphics chip. Ref Desig U1 C1, C3 C4 C5 R4 R3 R5 Description Qty Dual LDO Regulator 1 Capacitor 2 Capacitor 1 Capacitor 1 Resistor 1 Resistor 1 Resistor 1 Part # IRU1260CM Elect, 680mF, EEUFA1A681L Ceramic, 0.1mF, SMT, 0805 Elect,100mF, 6.3V, ECAOJFQ101 10.2KV, 1%, SMT, 0805 12.7KV, 1%, SMT, 0805 3V, 5%, SMT, 0805 Manuf IR Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01 Rev. 2.1 09/19/02 www.irf.com 9 IRU1260 (M) TO-263 Package 7-Pin A K S V B H M E U L P G D N C R C L SYMBOL A B C D E G H K L M N P R S U V MIN MAX 10.05 10.31 8.28 8.53 4.31 4.57 0.66 0.91 1.14 1.40 1.27 REF 14.73 15.75 1.40 1.68 0.00 0.25 2.49 2.74 0.43 0.58 2.29 2.79 08 88 2.41 2.67 6.50 REF 7.75 REF NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. 10 www.irf.com Rev. 2.1 09/19/02 IRU1260 (P) Ultra Thin-PakTM 7-Pin A A1 K E U V B H M L P G D N C R C L SYMBOL A A1 B C D E G H K L M N P R U V MIN MAX 9.27 9.52 8.89 9.14 7.87 8.13 1.78 2.03 0.63 0.79 0.25 NOM 1.27 10.41 10.67 0.76 1.27 0.03 0.13 0.89 1.14 0.25 0.79 1.04 38 68 5.59 NOM 7.49 NOM NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. Rev. 2.1 09/19/02 www.irf.com 11 IRU1260 PACKAGE SHIPMENT METHOD PKG DESIG M P TO-263 Ultra Thin-Pak TM PACKAGE DESCRIPTION PIN COUNT 7 7 PARTS PER TUBE 50 75 PARTS PER REEL 750 2500 T&R Orientation Fig A Fig B 1 1 1 1 1 1 Feed Direction Figure A Feed Direction Figure B IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01 12 www.irf.com Rev. 2.1 09/19/02 |
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