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| LTC1274/LTC1277 12-Bit, 10mW, 100ksps ADCs with 1A Shutdown FEATURES s s s DESCRIPTIO s s s s s s s Low Power Dissipation: 10mW Sample Rate: 100ksps Samples Inputs Beyond Nyquist, 72dB S/(N + D) and 82dB THD at fIN = 100kHz Single Supply 5V or 5V Operation Power Shutdown to 1A in Sleep Mode 180A Nap Mode (LTC1277) with Instant Wake-Up Internal Reference Can Be Overdriven Internal Synchronized Clock 0V to 4.096V or 2.048V Input Ranges (1mV/LSB) 24-Lead SO Package The LTC (R)1274/LTC1277 are 8s sampling 12-bit A/D converters which draw only 2mA (typ) from single 5V or 5V supplies. These easy-to-use devices come complete with a 2s sample-and-hold, a precision reference and an internally trimmed clock. Unipolar and bipolar conversion modes add to the flexibility of the ADCs. Two power-down modes are available in the LTC1277. In Nap mode, the LTC1277 draws only 180A and the instant wake-up from Nap mode allows the LTC1277 to be powered down even during brief inactive periods. In Sleep mode only 1A will be drawn. A REFRDY signal is used to show the ADC is ready to sample after waking up from Sleep mode. The LTC1274 also provides the Sleep mode and REFRDY signal. The A/D converters convert 0V to 4.096V unipolar inputs from a single 5V supply or 2.048V bipolar inputs from 5V supplies. The LTC1274 has a single-ended input and a 12-bit parallel data format. The LTC1277 offers a differential input and a 2-byte read format. The bipolar mode is formatted as 2's complement for the LTC1274 and offset binary for the LTC1277. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATI s s s s s s S Battery-Powered Portable Systems High Speed Data Acquisition for PCs Digital Signal Processing Multiplexed Data Acquisition Systems Audio and Telecom Processing Spectrum Analysis TYPICAL APPLICATI Single 5V Supply, 10mW, 100kHz, 12-Bit ADC LTC1277 ANALOG 1 AIN+ DIFFERENTIAL INPUTS 2 AIN- (0V TO 4.096V) 3 2.42V VREF VREF OUTPUT + 4 AGND 0.1F 10F 5 REFRDY 6 SLEEP 7 NAP 8 D7 9 D6 10 D5 8-BIT 11 D4 PARALLEL 12 BUS DGND VDD VSS BUSY CS RD CONVST HBEN VLOGIC D0/8 D1/9 D2/10 D3/11 24 23 22 21 20 19 18 17 16 15 14 13 OPTIONAL 3V SUPPLY TO INTERFACE WITH 3V PROCESSOR 10F P CONTROL LINES 5V 10000 CREF = 4.7F 0.1F + SUPPLY CURRENT (A) 1000 100 NAP = REFRDY (SLEEP MODE) 10 NAP = 5V (SLEEP MODE) 1 0.1 LTC1274/77 * TA01 U Supply Current vs Sample Rate with Sleep and Nap Modes WITHOUT SLEEP OR NAP NAP MODE 1 10 100 1k 10k 100k SAMPLE RATE (Hz) LTC1274/77 * TA02 UO UO 1 LTC1274/LTC1277 ABSOLUTE (Notes 1, 2) AXI U RATI GS Digital Output Voltage Unipolar Operation ................... - 0.3V to VDD + 0.3V Bipolar Operation...................... - 0.3V to VDD + 0.3V Power Dissipation ............................................. 500mW Operating Temperature Range Commercial ............................................ 0C to 70C Industrial ........................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C Supply Voltage (VDD) ................................................ 7V Negative Supply Voltage (VSS) Bipolar Operation Only .......................... - 6V to GND Total Supply Voltage (VDD to VSS) Bipolar Operation Only ....................................... 12V Analog Input Voltage (Note 3) Unipolar Operation ................... - 0.3V to VDD + 0.3V Bipolar Operation............... VSS - 0.3V to VDD + 0.3V Digital Input Voltage (Note 4) Unipolar Operation .............................. - 0.3V to 12V Bipolar Operation.......................... VSS - 0.3V to 12V PACKAGE/ORDER I FOR ATIO TOP VIEW AIN VREF AGND D11 (MSB) D10 D9 D8 D7 D6 1 2 3 4 5 6 7 8 9 24 VDD 23 VSS 22 BUSY 21 CS 20 RD 19 CONVST 18 SLEEP 17 REFRDY 16 D0 15 D1 14 D2 13 D3 ORDER PART NUMBER LTC1274CS LTC1274IS D5 10 D4 11 DGND 12 SW PACKAGE 24-LEAD PLASTIC SO TJMAX = 110C, JA = 130C/W Consult factory for Military grade parts. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Unipolar Offset Error (Note 7) CONDITIONS Bipolar Offset Error Gain Error Gain Error Tempco (Note 8) q IOUT(REF) = 0 2 U U W WW U W TOP VIEW AIN+ AIN- VREF AGND REFRDY SLEEP NAP D7 D6 1 2 3 4 5 6 7 8 9 24 VDD 23 VSS 22 BUSY 21 CS 20 RD 19 CONVST 18 HBEN 17 VLOGIC 16 D0/8 15 D1/9 14 D2/10 13 D3/11 (D11 = MSB) ORDER PART NUMBER LTC1277CS LTC1277IS D5 10 D4 11 DGND 12 SW PACKAGE 24-LEAD PLASTIC SO TJMAX = 110C, JA = 130C/W U With Internal Reference (Notes 5, 6) MIN q q q q TYP MAX 1 1 6 8 8 10 20 UNITS Bits LSB LSB LSB LSB LSB LSB LSB ppm/C 12 q 10 45 LTC1274/LTC1277 A ALOG I PUT SYMBOL PARAMETER VIN IIN CIN Analog Input Range (Note 10) Analog Input Leakage Current Analog Input Capacitance DY A IC ACCURACY SYMBOL PARAMETER S/(N + D) Signal-to-Noise Plus Distortion Ratio THD Total Harmonic Distortion Up to 5th Harmonic Peak Harmonic or Spurious Noise IMD Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth [S/(N + D) 68dB] I TER AL REFERE CE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Load Regulation CONDITIONS IOUT = 0 IOUT = 0 4.75V VDD 5.25V - 5.25V VSS - 4.75V - 5mA IOUT 70A DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL PARAMETER VIH VIL IIN CIN VOH High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage, All Logic Outputs VDD = 4.75V IO = - 10A IO = - 200A VLOGIC = 2.7V (LTC1277) IO = - 10A IO = - 200A VOL Low Level Output Voltage, All Logic Outputs VDD = 4.75V IO = 160A IO = 1.6mA VLOGIC =2.7V (LTC1277) IO = 160A IO = 1.6mA CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD U U U U WU U U (Note 5) CONDITIONS 4.75V VDD 5.25V (Unipolar) 4.75V VDD 5.25V, - 5.25V VSS - 2.45V (Bipolar) CS = High Between Conversions (Sample Mode) During Conversions (Hold Mode) q q q MIN TYP 0 to 4.096 2.048 MAX UNITS V V 1 45 5 A pF pF (Notes 5, 9) CONDITIONS 50kHz Input Signal 100kHz Input Signal 50kHz Input Signal 100kHz Input Signal 50kHz Input Signal 100kHz Input Signal fa = 96.95kHz, fb = 97.68kHz 2nd Order Terms 3rd Order Terms q q q MIN 70 TYP 73 72.5 - 84 - 82 - 84 - 82 - 78 - 81 2 350 MAX UNITS dB dB - 76 - 76 dB dB dB dB dB dB MHz kHz U (Note 5) MIN 2.400 q TYP 2.420 10 0.01 0.01 2 MAX 2.440 45 UNITS V ppm/C LSB/V LSB/V LSB/mA (Note 5) MIN q q q TYP MAX 0.8 10 UNITS V V A pF V V V V V V V V 2.4 5 4.70 q 4.0 2.65 2.60 0.05 0.10 0.05 0.10 q 0.4 3 LTC1274/LTC1277 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL PARAMETER IOZ COZ ISOURCE ISINK High-Z Output Leakage D11 to D0/8 High-Z Output Capacitance D11 to D0/8 Output Source Current Output Sink Current CONDITIONS VOUT = 0V to VDD, CS High CS High (Note 10) VOUT = 0V VOUT = VDD q q POWER REQUIRE E TS SYMBOL PARAMETER VDD VLOGIC VSS IDD Positive Supply Voltage (Notes 11, 12) Logic Supply (Notes 11,12) Negative Supply Voltage (Note 11) Positive Supply Current ISS PDISS Negative Supply Current Power Dissipation TI I G CHARACTERISTICS SYMBOL fSAMPLE(MAX) tCONV tACQ t1 t2 t3 t4 t5 t6 t7 t8 t9 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time CS to RD Setup Time CS to CONVST Setup Time NAP to CONVST Wake-Up Time CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY Delay Between Conversions Wait Time RD After BUSY Data Access Time After RD t10 t11 t12 t13 t14 t15 Bus Relinquish Time RD Low Time CONVST High Time Aperture Delay of Sample-and-Hold SLEEP to REFRDY Wake-Up Time 10F Bypass at VREF Pin 4.7F Bypass at VREF Pin HBEN to High Byte Data Valid CL = 100pF (LTC1277 Only) q 4 UW U U (Note 5) MIN TYP MAX 10 15 - 10 10 UNITS A pF mA mA (Note 5) CONDITIONS Unipolar and Bipolar Mode Unipolar and Bipolar Mode (LTC1277) Bipolar Mode Only fSAMPLE = 100ksps NAP = 0V (LTC1277 Only) SLEEP = 0V fSAMPLE = 100ksps, Bipolar Mode Only SLEEP = 0V fSAMPLE = 100ksps NAP = 0V (LTC1277 Only) SLEEP = 0V (Unipolar/Bipolar) q q q q q q q q MIN 4.75 TYP 2.7 to 5.25 MAX 5.25 - 5.25 UNITS V V V mA A A A A mW mW W - 2.45 2 180 0.3 40 0.3 10 0.9 4 320 5 70 5 20 1.8 25/50 UW (Note 5) See Figures 13 to 17. MIN q q q CONDITIONS (Note 11) TYP 6 0.35 MAX 8 2 UNITS ksps s s ns ns 100 (Note 10) (Note 10) (LTC1277 Only) (Note 11) (Note 13) CL = 100pF CL = 100pF (Note 11) (Note 10) CL = 20pF (Note 10) q q 0 30 620 40 70 20 - 20 50 110 140 125 170 90 100 65 0.35 2 150 ns ns ns ns s ns ns ns ns ns ns ns ns ns q q q q q q CL = 100pF q 65 20 20 t9 40 35 4.2 3.3 35 60 CL = 100pF q (Note 10) (Notes 10, 13) q q ns ms ms 100 ns LTC1274/LTC1277 TI I G CHARACTERISTICS SYMBOL t16 t17 t18 PARAMETER HBEN to Low Byte Data Valid HBEN to RD Setup Time RD to HBEN Setup Time The q denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together and VLOGIC is tied to VDD in LTC1277 (unless otherwise noted). Note 3: When these pin voltages are taken below VSS (ground for unipolar mode) or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 60mA below VSS (ground for unipolar mode) or above VDD without latch-up. Note 4: When these pin voltages are taken below VSS (ground for unipolar mode), they will be clamped by internal diodes. This product can handle input currents greater than 60mA below VSS (ground for unipolar mode) without latch-up. These pins are not clamped to VDD. Note 5: VDD = 5V (VSS = - 5V for bipolar mode), VLOGIC = VDD (LTC1277), fSAMPLE = 100ksps, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for unipolar and bipolar modes. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity vs Output Code DIFFERENTIAL NONLINEARITY ERROR (LSB) 1.00 INTEGRAL NONLINEARITY ERROR (LSB) EFFECTIVE NUMBER OF BITS (ENOBs) fSAMPLE = 100kHz 0.50 0 -0.50 -1.00 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE LT1274/77 * TPC01 UW UW (Note 5) See Figures 13 to 17. MIN q q q CONDITIONS CL = 100pF (LTC1277 Only) (Note 10) (LTC1277 Only) (Note 10) (LTC1277 Only) TYP 45 MAX 100 UNITS ns ns ns 10 10 Note 8: For LTC1274, bipolar offset is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. For LTC1277, bipolar offset voltage is measured from - 0.5LSB when the output code flickers between 0111 1111 1111 and 1000 0000 0000. Note 9: The AC tests apply to bipolar mode only and the S/(N + D) is 71dB (typ) for unipolar mode at 100kHz input frequency. Note 10: Guaranteed by design, not subject to test. Note 11: Recommended operating conditions. Note 12: AIN must not exceed VDD or fall below VSS by more than 50mV to specified accuracy. Note 13: The falling CONVST edge starts a conversion. If CONVST returns high at a bit decision point during the conversion it can create small errors. For best performance ensure that CONVST returns high either within 400ns after conversion start (i.e., before the first bit decision) or after BUSY rises (i.e., after the last bit test). See timing diagrams Modes 1a and 1b (Figures 13, 14). Differential Nonlinearity vs Output Code 1.00 fSAMPLE = 100kHz 0.50 12 11 10 9 8 7 6 5 4 3 2 1 ENOBs and S/(N + D) vs Input Frequency 74 68 NYQUIST FREQUENCY 62 56 50 S/(N + D)(dB) 0 -0.50 fSAMPLE = 100kHz 100k INPUT FREQUENCY (Hz) 1M 2M -1.00 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE LT1274/77 * TPC02 0 10k LTC1274/77 * TPC03 5 LTC1274/LTC1277 TYPICAL PERFORMANCE CHARACTERISTICS S/(N + D) vs Input Frequency and Amplitude 80 80 VIN = 0dB 70 SIGNAL/(NOISE + DISTORTION)(dB) 70 60 50 40 30 20 10 0 10k SIGNAL-TO-NOISE RATIO (dB) DISTORTION (dB) VIN = - 20dB VIN = - 60dB fSAMPLE = 100kHz 100k INPUT FREQUENCY (Hz) 1M 2M Spurious-Free Dynamic Range vs Input Frequency 0 SPURIOUS-FREE DYNAMIC RANGE (dB) -10 -20 fSAMPLE = 100kHz -40 -50 -60 -70 -80 -90 AMPLITUDE (dB) -30 -100 10k 100k INPUT FREQUENCY (Hz) Intermodulation Distortion Plot 0 fa -20 fb fb - fa 2fb - fa 2fa - fb 2fb fa + fb 2fa 3fb 2fb + fa 2fa + fb 3fa -100 -120 0 10k 20k FREQUENCY (Hz) 30k 40k 50k LTC1274/77 * TPC09 ACQUISITION TIME (s) AMPLITUDE (dB) -40 -60 -80 6 UW LTC1274/77 * TPC04 Signal-to-Noise Ratio (Without Harmonics) vs Input Frequency 0 Distortion vs Input Frequency fSAMPLE = 100kHz -20 -40 -60 2ND HARMONIC -80 THD 3RD HARMONIC -100 60 50 40 30 20 10 0 10k fSAMPLE = 100kHz 100k INPUT FREQUENCY (Hz) 1M 2M -120 10k 100k INPUT FREQUENCY (Hz) 1M 2M LTC1274/77 * TPC05 LTC1274/77 * TPC06 Intermodulation Distortion Plot 0 -20 -40 -60 fb - fa -80 2fa 2fa - fb 2fb - fa 2fb fb - fa 3fa 2fa - fb fa + 2fb 3fb fSAMPLE = 100kHz fa = 9.54kHz fb = 9.79kHz -100 -120 1M 2M 0 10 20 FREQUENCY (kHz) 30 40 50 LTC1274/77 * TPC08 LTC1274/77 * TPC07 Acquistion Time vs Source Impedance 3.5 fSAMPLE = 100kHz fa = 96.948kHz fb = 97.681kHz TA = 25C 3.0 2.5 2.0 1.5 1.0 0.5 0 10 100 1k SOURCE RESISTANCE () 10k LTC1274/75 * TPC10 LTC1274/LTC1277 TYPICAL PERFORMANCE CHARACTERISTICS AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) Supply Current vs Temperature 3.0 fSAMPLE = 100kHz 2.5 2.0 1.5 1.0 0.5 0 -55 -25 -30 -40 -50 DGND (VRIPPLE = 0.1V) REFERENCE VOLTAGE (V) SUPPLY CURRENT (mA) 50 25 75 0 TEMPERATURE (C) Supply Current vs Supply Voltage 3.0 fSAMPLE = 100kHz 2.5 SUPPLY CURRENT (mA) SUPPLY CURRENT (A) WAKE-UP TIME (ms) 2.0 1.5 1.0 0.5 0 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 LTC1274/77 * TPC14 PI FU CTIO S LTC1274 AIN (Pin 1): Analog Input. 0V to 4.096V, unipolar (VSS = 0V) or 2.048V, bipolar (VSS = - 5V). VREF (Pin 2): 2.42V Reference Output. Bypass to AGND (10F tantalum in parallel with 0.1F ceramic). VREF can be overdriven positive with an external reference voltage. AGND (Pin 3): Analog Ground. D11 to D4 (Pins 4 to 11): Three-State Data Outputs. D11 is the Most Significant Bit. DGND (Pin 12): Digital Ground. D3 to D0 (Pins 13 to 16): Three-State Data Outputs. REFRDY (Pin 17): Reference Ready Signal. It goes high when the reference has settled after SLEEP indicating that the ADC is ready to sample. SLEEP (Pin 18): SLEEP Mode Input. Tie this pin to low to put the ADC in Sleep mode and save power (REFRDY will go low). The device will draw 1A in this mode. CONVST (Pin 19): Conversion Start Signal. This active low signal starts a conversion on its falling edge (to recognize CONVST, CS has to be low.) UW 100 LT1274/77 * TPC11 Power Supply Feedthrough vs Ripple Frequency 0 -10 -20 fSAMPLE = 100kHz 2.430 2.425 2.420 2.415 2.410 2.405 2.435 Reference Voltage vs Load Current -60 V (V SS RIPPLE = 10mV) -70 -80 -90 -100 1 10 100 RIPPLE FREQUENCY (kHz) 1000 AVDD (VRIPPLE = 1mV) 125 -6 -5 -3 -2 -1 -4 LOAD CURRENT (mA) 0 1 LTC1274/77 * TPC12 LT1274/77 * TPC13 Supply Current vs Sample Rate With Sleep and Nap Modes 10000 CREF = 4.7F WITHOUT SLEEP OR NAP 1000 NAP MODE 100 NAP = REFRDY (SLEEP MODE) 10 NAP = 5V (SLEEP MODE) 10 9 8 7 6 5 4 3 2 1 Wake-Up Time vs CREF (Sleep Mode) TA = 25C 1 0.1 0 1 10 100 1k 10k 100k 0 5 SAMPLE RATE (Hz) LTC1274/77 * TPC15 10 15 20 25 30 35 40 45 50 CREF (F) LTC1274/77 * TPC16 U U U 7 LTC1274/LTC1277 PI FU CTIO S RD (Pin 20): Read Input. This enables the output drivers when CS is low. CS (Pin 21): The Chip Select input must be low for the ADC to recognize CONVST and RD inputs. BUSY (Pin 21): The BUSY output shows the converter status. It is low when a conversion is in progress. The rising Busy edge can be used to latch the conversion result. VSS (Pin 23): Negative 5V Supply. Negative 5V will select bipolar operation. Bypass to AGND with 0.1F ceramic. Tie this pin to analog ground to select unipolar operation. VDD (Pin 24): Positive 5V Supply. Bypass to AGND (10F tantalum in parallel with 0.1F ceramic). D7 to D4* (Pins 8 to 11): Three-State Data Outputs. DGND (Pin 12): Digital Ground. D3/11 to D0/8* (Pins 13 to 16): Three-State Data Outputs. D11 is the Most Significant Bit. VLOGIC (Pin 17): 5V or 3V Digital Power Supply. This pin allows a 5V or 3V logic interface with the processor. All logic outputs (Data Bits, BUSY and REFRDY) will swing between 0V and VLOGIC. HBEN (Pin 18): High Byte Enable Input. The four Most Significant Bits will appear at Pins 13 to 16 when this pin is high. The LTC1277 uses straight binary for unipolar mode and offset binary for bipolar mode. CONVST (Pin 19): Conversion Start Signal. This active low signal starts a conversion on its falling edge (to recognize CONVST, CS has to be low). RD (Pin 20): Read Input. This enables the output drivers when CS is low. CS (Pin 21): The Chip Select input must be low for the ADC to recognize CONVST and RD inputs. BUSY (Pin 22): The BUSY output shows the converter status. It is low when a conversion is in progress. VSS (Pin 23): Negative 5V Supply. Negative 5V will select bipolar operation. Bypass to AGND with 0.1F ceramic. Tie this pin to analog ground to select unipolar operation. VDD (Pin 24): 5V Positive Supply. Bypass to AGND (10F tantalum in parallel with 0.1F ceramic). Table 1. LTC1277 Two-Byte Read Data Bus Status DATA OUTPUTS Low Byte High Byte D7 DB7 Low D6 DB6 Low D5 DB5 Low D4 DB4 Low D3/11 DB3 DB11 D2/10 DB2 DB10 D1/9 D0/8 DB1 DB9 DB0 DB8 LTC1277 AIN+ (Pin 1): Positive Analog Input. (AIN+ - AIN-) = 0V to 4.096V, unipolar (VSS = 0V) or 2.048V, bipolar (VSS = - 5V). AIN- (Pin 2): Negative Analog Input. This pin needs to be free of noise during conversion. For single-ended inputs tie AIN- to analog ground. VREF (Pin 3): 2.42V Reference Output. Bypass to AGND (10F tantalum in parallel with 0.1F ceramic). VREF can be overdriven positive with an external reference voltage. AGND (Pin 4): Analog Ground. REFRDY (Pin 5): Reference Ready Signal. It goes high when the reference has settled after SLEEP indicating that the ADC is ready to sample. SLEEP (Pin 6): SLEEP Mode Input. Tie this pin to low to put the ADC in Sleep mode and save power (REFRDY will go LOW). The device will draw 1A in this mode. NAP (Pin 7): NAP Mode Input. Pulling this pin low will shut down all currents in the ADC except the reference. In this mode the ADC draws 180A. Wake-up from Nap mode is about 620ns. *The LTC1277 bipolar mode is in offset binary. 8 U U U LTC1274/LTC1277 BLOCK DIAGRA S LTC1274 CSAMPLE AIN VREF 2.42V REF REFRDY AGND DGND SUCCESSIVE APPROXIMATION REGISTER INTERNAL CLOCK CONTROL LOGIC 12 OUTPUT LATCHES * * * D11 D0 12-BIT CAPACITIVE DAC COMPARATOR ZEROING SWITCHES VDD VSS (0V FOR UNIPOLAR MODE OR -5V FOR BIPOLAR MODE) AIN+ AIN- VREF 2.42V REF REFRDY AGND DGND TEST CIRCUITS Load Circuits for Access Timing 5V 3k DBN 3k DGND A) HIGH-Z TO VOH (t9) AND VOL TO VOH (t6) CL DBN CL DGND B) HIGH-Z TO VOL (t9) AND VOH TO VOL (t6) 1274/77 * TC01 W LTC1274 * BD SLEEP CONVST RD CS BUSY LTC1277 CSAMPLE VDD ZEROING SWITCHES VSS (0V FOR UNIPOLAR MODE OR -5V FOR BIPOLAR MODE) COMPARATOR 12-BIT CAPACITIVE DAC SUCCESSIVE APPROXIMATION REGISTER INTERNAL CLOCK CONTROL LOGIC 12 OUTPUT LATCHES * * * * * D7 D1/9 D0/8 LTC1277 * BD HBEN SLEEP NAP CONVST RD CS BUSY VLOGIC 3V OR 5V Load Circuits for Output Float Delay 5V 3k DBN 3k DGND A) VOH TO HIGH-Z 10pF DBN 10pF DGND B) VOL TO HIGH-Z 1274/77 * TC02 9 LTC1274/LTC1277 TI I G DIAGRA S CS to RD Setup Timing CS t1 RD LTC1274/77 * TD01 NAP to CONVST Wake-Up Timing (LTC1277) NAP t3 CONVST LTC1274/77 * TD03 APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1274/LTC1277 use a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADCs are complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and CONVST inputs. At the start of conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN (LTC1274) or AIN+ (LTC1277) input connects to the sample-and-hold capacitor during the acquire phase, and the comparator offset is nulled by the feedback switch. In this acquire phase, a minimum delay of 2s will provide enough time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. The input switch connects CSAMPLE to ground (LTC1274) or AIN- (LTC1277), injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the AIN (LTC1274) or AIN+ - AIN- (LTC1277) input charge. The SAR contents (a 12bit data word) which represent the AIN (LTC1274) or AIN+ - AIN- (LTC1277) are loaded into the 12-bit output latches. SAMPLE SAMPLE AIN HOLD CDAC DAC VDAC CSAMPLE SI 10 U W W U U UW CS to CONVST Setup Timing CS t2 CONVST LTC1274/77 * TD02 SLEEP to REFRDY Wake-Up Timing SLEEP t14 REFRDY LTC1274/77 * TD04 - COMPARATOR + S A R 12-BIT LATCH 1274 * F01 Figure 1. LTC1274 AIN Input DYNAMIC PERFORMANCE The LTC1274/LTC1277 have excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADCs' frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output LTC1274/LTC1277 APPLICATIONS INFORMATION using an FFT algorithm, the ADCs' spectral content can be examined for frequencies outside the fundamental. Figures 2a and 2b show typical LTC1274 FFT plots. Signal-to-Noise Ratio The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies above DC and below half the sampling frequency. Figure 2a shows a typical spectral content with a 100kHz sampling rate and a 48.85kHz input. The dynamic performance is excellent for input frequencies well beyond Nyquist as shown in Figure 2b and Figure 3. 0 -20 fSAMPLE = 100kHz fIN = 48.85kHz 12 74 68 NYQUIST FREQUENCY 62 56 50 EFFECTIVE NUMBER OF BITS (ENOBs) AMPLITUDE (dB) -40 -60 -80 -100 -120 0 10 20 30 40 INPUT FREQUENCY (kHz) 50 LTC1274/77 * F02a Figure 2a. LTC1274 Nonaveraged, 4096 Point FFT Plot with 50kHz Input Frequency 0 -20 fSAMPLE = 100kHz fIN = 97.68kHz AMPLITUDE (dB) -40 -60 -80 -100 -120 0 10 20 30 40 INPUT FREQUENCY (kHz) 50 LTC1274/77 * F02b Figure 2b. LTC1274 Nonaveraged, 4096 Point FFT Plot with 100kHz Input Frequency U W U U 11 10 9 8 7 6 5 4 3 2 1 0 10k fSAMPLE = 100kHz 100k INPUT FREQUENCY (Hz) 1M 2M S/(N + D)(dB) LTC1274/77 * F03 Figure 3. ENOBs and S/(N + D) vs Input Frequency Effective Number of Bits The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) - 1.76]/6.02 where N is the Effective Number of Bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 100kHz, the LTC1274/LTC1277 maintain very good ENOBs over 300kHz. Refer to Figure 3. Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20log V22 + V32 + V42 ... + VN2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. THD versus input fre- 11 LTC1274/LTC1277 APPLICATIONS INFORMATION quency is shown in Figure 4. The ADCs have good distortion performance up to the Nyquist frequency and beyond. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa - fb) while the 3rd order IMD terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The LTC1274/LTC1277 have been designed to optimize input bandwidth, allowing ADCs to undersample input signals with frequencies above the converter's Nyquist frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The analog input of the LTC1274/LTC1277 is easy to drive. It draws only one small current spike while charging the sample-and-hold capacitor at the end of conversion. During conversion the analog input draws only a small leakage current. The only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. Any op amp that settles in 2s to small current transients will allow maximum speed operation. If slower op amps are used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the ADC AIN input include the LT (R)1006, LT1007, LT1220, LT1223 and LT1224 op amps. IMD (fa fb) = 20log Amplitude at (fa fb) Amplitude at fa Figure 5 shows the IMD performance at a 97kHz input. Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. 0 fSAMPLE = 100kHz -20 -20 0 fa fb fb - fa DISTORTION (dB) -60 2ND HARMONIC -80 THD 3RD HARMONIC AMPLITUDE (dB) -40 -40 -60 -80 -100 -120 10k -100 -120 100k INPUT FREQUENCY (Hz) 1M 2M LTC1274/77 * F04 Figure 4. Distortion vs Input Frequency 12 U W U U fSAMPLE = 100kHz fa = 96.948kHz fb = 97.681kHz 2fb - fa 2fa - fb 2fb fa + fb 2fa 3fb 2fb + fa 2fa + fb 3fa 0 10k 20k 30k FREQUENCY (Hz) 40k 50k LTC1274/77 * F05 Figure 5. Intermodulation Distortion LTC1274/LTC1277 APPLICATI S I FOR ATIO LTC1277 AIN+/AIN- Input Settling The input capacitor for the LTC1277 is switched onto the AIN+ input during the sample phase. The voltage on the AIN+ input must settle completely within the sample period. At the end of the sample phase the input capacitor switches to the AIN- input and the conversion starts. During the conversion the AIN+ input voltage is effectively "held" by the sample-and-hold and will not affect the conversion result. It is critical that the AIN- input voltage be free of noise and settles completely during the conversion. Internal Reference The ADCs have an on-chip, temperature compensated, curvature corrected bandgap reference which is factory trimmed to 2.42V. It is internally connected to the DAC and is available at Pin 2 (LTC1274) or Pin 3 (LTC1277) to provide up to 1mA current to an external load. For minimum code transition noise the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10F tantalum in parallel with a 0.1F ceramic). The VREF pin can be driven with a DAC or other means to provide input span adjustment. The VREF pin must be driven to at least 2.45V to prevent conflict with the internal reference. The reference should be driven to no more than INPUT RANGE: 0.846VREF(OUT) IN BIPOLAR MODE 0 TO 1.69VREF(OUT) IN UNIPOLAR MODE + LT1006 VREF(OUT) 2.45V 3 10F LTC1274 AIN VREF AGND LTC1274/77 * F06 - Figure 6. Driving the VREF with the LT1006 Op Amp U 3V to keep the input span within the 5V supply in unipolar mode. In bipolar mode the reference should be driven to no more than 5V, the positive supply voltage of the chip. Figure 6 shows an LT1006 op amp driving the Reference pin. In unipolar mode, the reference can be driven up to 2.95V at which point it will provide a 0V to 5V input span. For the bipolar mode, the reference can be driven up to 5V at which point it will provide a 4.23V input span. Figure 7 shows a typical reference, the LT1019A-2.5 connected to the LTC1274. This will provide an improved drift (equal to the maximum 5ppm/C of the LT1019A-2.5) and a 2.115V (bipolar) or 4.231V (unipolar) full scale. BOARD LAYOUT AND BYPASSING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1274/LTC1277, a printed circuit board is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. High quality tantalum and ceramic bypass capacitors should be used at the VDD and VREF pins as shown in 5V W U UO INPUT RANGE: 2.115V (0.846 x VREF) IN BIPOLAR AND 0V TO 4.231V (1.69VREF(OUT)) IN UNIPOLAR MODE 5V 5V VIN VOUT LT1019A-2.5 GND 3 10F LTC1274 AIN VREF AGND LTC1274/77 * F07 Figure 7. Supplying a 2.5V Reference Voltage to the LTC1274 with the LT1019A-2.5 13 LTC1274/LTC1277 APPLICATI S I FOR ATIO Figure 8. For bipolar mode, a 0.1F ceramic provides adequate bypassing for the VSS pin. The capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. Input signal leads to AIN and signal return leads from AGND (Pin 3 for LTC1274, Pin 4 for LTC1277) should be kept as short as possible to minimize input noise coupling. In applications where this is not possible a shielded cable between source and ADC is recommended. Also, since any potential difference in grounds between the signal source and the ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible. A single point analog ground separate from the logic system ground should be established with an analog 1 AIN AGND ANALOG INPUT CIRCUITRY VREF 2 10F 0.1F + - 3 ANALOG GROUND PLANE Figure 8. Power Supply Grounding Practice 2.42V VREF OUTPUT 10F + LTC1274 ANALOG INPUT 1 (0V TO 4.095V) VDD AIN 2 VREF VSS 3 AGND BUSY 0.1F 4 D11 (MSB) CS 5 D10 RD 6 D9 CONVST 7 D8 SLEEP 8 D7 REFRDY 12-BIT 9 D6 D0 PARALLEL 10 BUS D5 D1 11 D4 D2 12 DGND D3 Figure 9. LTC1274 Typical Circuit 14 U ground plane at AGND or as close as possible to the ADC. DGND (Pin 12) and all other analog grounds should be connected to this single analog ground point. No other digital grounds should be connected to this analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a Wait state during conversion or by using three-state buffers to isolate the ADC data bus. Figure 9 is a typical application circuit for the LTC1274. LTC1274 AVDD DVDD DGND 24 10F 17 12 GROUND CONNECTION TO DIGITAL CIRCUITRY DIGITAL SYSTEM 0.1F LTC1274/77 * F08 W U UO 5V 24 23 22 21 20 19 18 17 16 15 14 13 10F P CONTROL LINES CONVERSION START INPUT SLEEP MODE INPUT REFERENCE READY SIGNAL + 0.1F LTC1274/77 * F09 LTC1274/LTC1277 APPLICATI S I FOR ATIO DIGITAL INTERFACE The ADCs are designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Figures 10a to 10c are the input/output characteristics of the ADCs. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB...FS - 1.5LSV). The output code is scaled such that 1.0LSB = FS/4096 = 4.096V/4096 = 1.0mV. Unipolar Offset and Full-Scale Error Adjustments In applications where absolute accuracy is important, then offset and full-scale errors can be adjusted to zero. Offset 111...111 111...110 111...101 OUTPUT CODE 1LSB = FS = 4.096V = 1mV 4096 4096 OUTPUT CODE 111...100 000...011 000...010 000...001 000...000 0V UNIPOLAR ZERO 1 LSB INPUT VOLTAGE (V) FS - 1LSB LTC1274/77 F10a Figure 10a. LTC1274/LTC1277 Unipolar Transfer Characteristics 111...111 111...110 BIPOLAR ZERO OUTPUT CODE 100...001 100...000 011...111 011...110 000...001 000...000 -FS/2 1LSB = FS = 4.096V = 1mV 4096 4096 -1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 - 1LSB LTC1274/77 * F10c Figure 10c. LTC1277 Bipolar Transfer Characteristics (Offset Binary) U error must be adjusted before full-scale error. Figure 11a shows the extra components required for full-scale error adjustment. If both offset and full-scale adjustments are needed, the circuit in Figure 11b can be used. For zero offset error, apply 0.50mV (i.e., 0.5LSB) at the input and adjust the offset trim until the LTC1274/LTC1277 output code flickers between 0000 0000 0000 and 0000 0000 0001. For zero full-scale error, apply an analog input of 4.0945V (i.e., FS - 1.5LSB or last code transition) at the input and adjust R5 until the ADC output code flickers between 1111 1111 1110 and 1111 1111 1111. Bipolar Offset and Full-Scale Error Adjustments Bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. Again, bipolar offset must be 011...111 011...110 BIPOLAR ZERO 000...001 000...000 111...111 111...110 100...001 100...000 -FS/2 1LSB = FS = 4.096V = 1mV 4096 4096 -1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 - 1LSB LTC1274/77 * F10b W U UO Figure 10b. LTC1274 Bipolar Transfer Characteristics (2's Complement) 15 LTC1274/LTC1277 APPLICATI S I FOR ATIO adjusted before full-scale error. Bipolar offset error adjustment is achieved by trimming the offset adjust while the input voltage is 0.5LSB below ground. This is done by applying an input voltage of - 0.50mV (- 0.5LSB) to the input in Figure 11c and adjusting the R8 until the ADC's output code flickers between 0000 0000 0000 and 1111 1111 1111 in LTC1274 or between 0111 1111 1111 and 1000 0000 0000 in LTC1277. For full-scale adjustment, an input voltage of 2.0465V (FS - 1.5LSBs) is applied to the input and R5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111 in LTC1274 or between 1111 1111 1110 and 1111 1111 1111 in LTC1277. Internal Clock The A/D converters have an internal clock that eliminates the need of synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of 6s. No external adjustments are required and with the maximum acquisition time of 2s throughput performance of 100ksps is assured. Timing and Control Conversion start and data read operations are controlled by three digital inputs in the LTC1274: CS, CONVST and RD. For the LTC1277 there are four digital inputs: CS, CONVST, RD and HBEN. Figure 12 shows the logic structure associated with these inputs for LTC1277. A falling edge on CONVST will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output and this is low while conversion is in progress. The High Byte Enable input (HBEN) in the LTC1277 is to multiplex the 12 bits of conversion data onto the lower D7 to D0/8 outputs. Figures 13 through 17 show several different modes of operation. In modes 1a and 1b (Figures 13 and 17) CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. 16 U R1 50 V1 W U UO + A1 - R2 10k R3 10k AIN (LTC1274) AIN+ (LTC1277) R4 100 LTC1274 LTC1277 AGND AIN- (LTC1277) LTC1274/77 F11a FULL-SCALE ADJUST ADDITIONAL PINS OMITTED FOR CLARITY 20LSB TRIM RANGE Figure 11a. Full-Scale Adjust Circuit ANALOG INPUT 0V TO 4.096V R1 10k R2 10k 10k + - R4 100k R5 4.3k FULL-SCALE ADJUST 5V R7 R8 100k 10k OFFSET ADJUST AIN (LTC1274) AIN+ (LTC1277) 5V R9 20 R3 100k LTC1274 LTC1277 AIN- (LTC1277) LTC1274/77 F11b R6 400 Figure 11b. LTC1274/LTC1277 Unipolar Offset and Full-Scale Adjust Circuit ANALOG INPUT R1 10k R2 10k + - R4 100k R5 4.3k FULL-SCALE ADJUST 5V R7 R8 100k 20k OFFSET ADJUST -5V AIN (LTC1274) AIN+ (LTC1277) LTC1274 LTC1277 R3 100k AIN- (LTC1277) LTC1274/77 F11c R6 200 Figure 11c. LTC1274/LTC1277 Bipolar Offset and Full-Scale Adjust Circuit LTC1274/LTC1277 APPLICATI S I FOR ATIO The narrow logic pulse on CONVST ensures that CONVST doesn't return high during the conversion (see Note 13 following the Timing Characteristics table). In Mode 2 (Figure 15) CS is tied low. The falling edge of CONVST signal again starts the conversion. Data outputs both are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared MPU databus. In slow memory and ROM modes (Figures 16 and 17) CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). RD CS D CONVST NAP SLEEP 1274/77 * F12 Figure 12. Internal Logic for Control Inputs CS, RD, CONVST, NAP and SLEEP (LTC1277) CS = RD = 0 HBEN (LTC1277) tCONV CONVST t4 (SAMPLE N) t5 BUSY t6 LTC1274 DATA DATA (N - 1) DB11 TO DB0 t15 LTC1277 DATA DATA (N - 1) DB7 TO DB0 DATA N DB7 TO DB0 Figure 13. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) U In slow memory mode the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a Wait state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high releasing the processor; the processor applies a logic high to RD (= CONVST) and reads the new conversion data. In ROM mode the processor applies a logic low to RD (= CONVST), starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion. ACTIVE HIGH ENABLE THREE-STATE OUTPUTS DB11....DB0 BUSY Q CONVERSION START (RISING EDGE TRIGGER) FLIP FLOP CLEAR t16 (SAMPLE N + 1) t7 DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0 DATA N DB11 TO DB8 DATA N DB7 TO DB0 DATA (N + 1) DB7 TO DB0 LTC1274/77 * F13 W U UO 17 LTC1274/LTC1277 APPLICATI S I FOR ATIO CS = RD = 0 HBEN (LTC1277) t12 CONVST t5 BUSY t6 LTC1274 DATA DATA (N - 1) DB11 TO DB0 t15 LTC1277 DATA DATA (N - 1) DB7 TO DB0 DATA (N - 1) DB11 TO DB8 DATA (N - 1) DB7 TO DB0 DATA N DB7 TO DB0 tCONV (SAMPLE N) t7 Figure 14. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) CS = 0 HBEN (LTC1277) tCONV t17 t4 CONVST t5 BUSY (SAMPLE N) t7 t8 RD t11 LTC1274 DATA LTC1277 DATA Figure 15. Mode 2. CONVST Starts a Conversion. Data is Read by RD 18 U t16 (SAMPLE N + 1) t5 DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0 DATA N DB11 TO DB8 DATA N DB7 TO DB0 DATA (N + 1) DB7 TO DB0 LTC1274/77 * F14 W U UO t12 (SAMPLE N + 1) t10 t9 DATA N DB11 TO DB0 t16 DATA N DB11 TO DB8 DATA N DB7 TO DB0 LTC1274/77 * F15 LTC1274/LTC1277 APPLICATI S I FOR ATIO CS = 0 HBEN (LTC1277) RD = CONVST t5 BUSY tCONV (SAMPLE N) t9 LTC1274 DATA DATA (N - 1) DB11 TO DB0 t6 DATA N DB11 TO DB0 DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0 LTC1277 DATA DATA (N - 1) DB7 TO DB0 DATA N DB7 TO DB0 Figure 16. Slow Memory Mode CS = 0 HBEN (LTC1277) t15 t18 RD = CONVST t5 BUSY t9 LTC1274 DATA DATA (N - 1) DB11 TO DB0 t10 DATA N DB11 TO DB0 (SAMPLE N) t7 tCONV (SAMPLE N + 1) LTC1277 DATA DATA (N - 1) DB7 TO DB0 DATA (N - 1) DB11 TO DB8 Figure 17. ROM Mode Timing Power Shutdown The LTC1274/LTC1277 provide shutdown features that will save power when the ADC is in inactive periods. Both ADCs have a Sleep mode. To power down the ADCs, SLEEP (Pin 18 in LTC1274 or Pin 6 in LTC1277) needs to be driver low. When in Sleep mode, the LTC1274/LTC1277 will not start a conversion even though the CONVST goes low. The parts draw 1A. After release from the Sleep mode, the ADCs need 3ms (4.7F bypass capacitor on VREF pin) to wake up and a REFRDY signal will go to high to indicate the ADC is ready to do conversions. The LTC1277 has an additional Nap mode. When NAP (Pin 7) is tied low, all the power is off except the internal reference which is still active and provides 2.42V output voltage to the other circuitry. In this mode the ADC draws 0.9mW instead of 10mW (for minimum power, the logic inputs must be within 600mV from the supply rails). The wake-up time from the power shutdown to active state is 620ns. The typical performance graph on the front page of this data sheet shows that the power will be reduced greatly by using the Sleep and Nap modes. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U t15 t7 t18 (SAMPLE N + 1) t10 DATA N DB11 TO DB8 DATA N DB11 TO DB0 DATA (N + 1) DB7 TO DB0 DATA (N + 1) DB11 TO DB8 LTC1274/77 * F16 W U UO DATA N DB7 TO DB0 DATA N DB11 TO DB8 LTC1274/77 * F17 19 LTC1274/LTC1277 APPLICATI S I FOR ATIO In the Sleep mode, the comparator of the ADC will start consuming power after the rising edge of SLEEP as shown 3ms (CREF = 4.7F) SLEEP REFRDY COMPARATOR STATUS ON OFF Figure 18a. Power Saved in Sleep Mode (NAP = HIGH) PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. SW Package 24-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.291 - 0.299** (7.391 - 7.595) 0.010 - 0.029 x 45 (0.254 - 0.737) 0.093 - 0.104 (2.362 - 2.642) 0.037 - 0.045 (0.940 - 1.143) 24 23 22 21 0 - 8 TYP 0.009 - 0.013 (0.229 - 0.330) 0.014 - 0.019 0.016 - 0.050 (0.356 - 0.482) (0.406 - 1.270) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 1 2 3 4 5 6 7 8 9 10 11 12 NOTE 1 0.050 (1.270) TYP RELATED PARTS PART NUMBER LTC1272 LTC1273/75/76 LTC1278 LTC1279 LTC1282 LTC1409 LTC1410 DESCRIPTION 12-Bit, 3s, 250kHz Sampling A/D Converter 12-Bit, 300ksps Sampling A/D Converters with Reference 12-Bit, 500ksps Sampling A/D Converter with Shutdown 12-Bit, 600ksps Sampling A/D Converter with Shutdown 12-Bit, 140ksps Sampling A/D Converter with Reference 12-Bit, 800ksps Sampling A/D Converter with Shutdown 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown COMMENTS Single 5V, Sampling 7572 Upgrade Complete with Clock, Reference 70dB SINAD at Nyquist, Low Power 70dB SINAD at Nyquist, Low Power 3V or 3V ADC with Reference, Clock Fast, Complete Low Power ADC, 80mV Fast, Complete Wideband ADC, 160mV LT/GP 1195 10K * PRINTED IN USA 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977 U in Figure 18a. If REFRDY is tied to NAP, the comparator will be powered up after REFRDY's rising edge. Hence more power will be saved as in Figure 18b. 3ms (CREF = 4.7F) SLEEP NAP = REFRDY ON LTC1274/77 * F18a W U U UO COMPARATOR STATUS ON OFF ON LTC1274/77 * F18b Figure 18b. Power Saved in Sleep Mode (NAP = REFRDY) 0.598 - 0.614* (15.190 - 15.600) 20 19 18 17 16 15 14 13 0.004 - 0.012 (0.102 - 0.305) NOTE 1 0.394 - 0.419 (10.007 - 10.643) (c) LINEAR TECHNOLOGY CORPORATION 1995 |
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