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ASAHI KASEI
[AK93C41A/51A]
AK93C41A / 51A
0.9V operation 1K / 2Kbit Serial CMOS EEPROM
Features ADVANCED CMOS EEPROM TECHNOLOGY LOW VCC OPERATION ... Vcc = 0.9V 3.6V AK93C41A * * 1024 bits, 64 x 16 organization AK93C51A * * 2048 bits, 128 x 16 organization SERIAL INTERFACE - Interfaces with popular microcontrollers and standard microprocessors LOW POWER CONSUMPTION - 10A Max. Standby (VCC=3.6V) Automatic address increment (READ) Automatic write cycle time-out with auto-ERASE Busy/Ready status signal Software controlled write protection Hardware write protect for lower block (AK93C51A only) IDEAL FOR LOW DENSITY DATA STORAGE - Low cost, space saving, 8-pin package
Preliminary
Block Diagram
DAM05E-01 -1-
1999/12
ASAHI KASEI
[AK93C41A/51A]
General Description The AK93C41A/51A is a 1024/2048-bit serial CMOS EEPROM divided into 64/128 registers of 16 bits each. The AK93C41A/51A has 4 instructions such as READ, WRITE, EWEN and EWDS. Those instructions control the AK93C41A/51A. The AK93C41A/51A can operate full function under wide operating voltage range from 0.9V to 3.6V. The charge up circuit is integrated for high voltage generation that is used for write operation. A serial interface of AK93C41A/51A, consisting of chip select (CS), serial clock (SK), data-in (DI) and dataout (DO), can easily be controlled by popular microcontrollers or standard microprocessors. AK93C41A/51A takes in the write data from data input pin (DI) to a register synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation, AK93C41A/51A takes out the read data from a register to data output pin (DO) synchronously with rising edge of SK. The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data output or Busy/Ready signal output. Software and Hardware controlled write protection When Vcc is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disabled. Before WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or Vcc is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions. The PROTECT pin is available only on the AK93C51A. When PROTECT pin is tied to GND, PROGRAM operations onto the lower 1Kbit ($00a$3F) will not be executed. When PROTECT pin is tied to VCC, normal operation is enabled. There is an internal pull-down on the PROTECT pin.
*
Busy/Ready status signal After a write instruction, the DO output serves as a Busy/Ready status indicator. After the falling edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs). DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.
*
Type of Products Model AK93C41AV AK93C51AV Memory size 1Kbits 2Kbits Temp.Range -10C70C -10C70C Vcc 0.9V3.6V 0.9V3.6V Package 8pin Plastic TSSOP 8pin Plastic TSSOP
DAM05E-01 -2-
1999/12
ASAHI KASEI Pin arrangement
[AK93C41A/51A]
(note) AK93C41A * * NC, AK93C51A * * PROTECT
Pin Name CS SK DI DO GND PROTECT
(AK93C51A only)
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Memory Protect PROTECT =L or NC : Protect enable PROTECT =H : Protect disable
Vcc NC
Power Supply Not Connected
DAM05E-01 -3-
1999/12
ASAHI KASEI
[AK93C41A/51A]
Functional Description The AK93C41A/51A has 4 instructions such as READ, WRITE, EWEN and EWDS. A valid instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the desired memory Address location. The CS pin must be brought low for a minimum of 250ns (Tcs) between each instruction when the instruction is continuously executed.
Instruction Start Bit READ WRITE EWEN EWDS WRAL 1 1 1 1 1
Op Code 10 01 00 00 00
Address A5-A0 A5-A0 11XXXX 00XXXX 01XXXX
Data D15-D0 D15-D0
Comments
Reads data stored in memory, at specified address. Writes register. Write enable must precede all programming modes. Disables all programming instructions.
D15-D0
Writes all registers.
table1. Instruction Set for the AK93C41A
Instruction Start Bit READ WRITE EWEN EWDS WRAL 1 1 1 1 1
Op Code 10 01 00 00 00
Address X A6-A0 X A6-A0 11XXXXXX 00XXXXXX 01XXXXXX
Data D15-D0 D15-D0
Comments
Reads data stored in memory, at specified address. Writes register. Write enable must precede all programming modes. Disables all programming instructions.
D15-D0
Writes all registers.
table2. Instruction Set for the AK93C51A (Note)
*
The WRAL instruction are used for factory function test only. User can't use the WRAL instruction. * The AK93C41A/51A perceives the start bit in the logic"1" and also "01".
DAM05E-01 -4-
1999/12
ASAHI KASEI
[AK93C41A/51A]
Write The write instruction is followed by 16 bits of data to be written into the specified address. The self-timed programming cycle is initiated on the rising edge of the SK clock as the last data bit (D0) is clocked in. The DO indicates the Busy/Ready status of the chip after the self-timed programming cycle is initiated. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction.
WRITE (AK93C41A)
WRITE (AK93C51A)
DAM05E-01 -5-
1999/12
ASAHI KASEI
[AK93C41A/51A]
Read The read instruction is the only instruction which outputs serial data on the DO pin. Following the Start bit, first Op code and address are decoded, then the data from the selected memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from the selected memory location. The output data changes are synchronized with the rising edges of the serial clock (SK). The data in the next address can be read sequentially by continuing to provide clock. The address automatically cycles to the next higher address after the 16bit data shifted out. AK93C41A * * When the highest address is reached ($3F), the address counter rolls over to address $00 allowing the read cycle to be continued indefinitely. * * When the highest address is reached ($7F), the address counter rolls over to AK93C51A address $00 allowing the read cycle to be continued indefinitely.
READ (AK93C41A)
READ (AK93C51A)
DAM05E-01 -6-
1999/12
ASAHI KASEI
[AK93C41A/51A]
EWEN / EWDS When Vcc is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disable. Before WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or Vcc is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions.
EWEN/EWDS (AK93C41A)
EWEN/EWDS (AK93C51A)
DAM05E-01 -7-
1999/12
ASAHI KASEI
[AK93C41A/51A]
Absolute Maximum Ratings
Parameter Power Supply All Input Voltages with Respect to Ground Ambient storage temperature
Symbol VCC VIO Tst
Min -0.6 -0.6 -65
Max +5.0 VCC+0.6 +150
Unit V V C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter Power Supply Ambient Operating Temperature
Symbol VCC Ta
Min 0.9 -10
Max 3.6 +70
Unit V C
DAM05E-01 -8-
1999/12
ASAHI KASEI
[AK93C41A/51A]
Electrical Characteristics (1) D.C. ELECTRICAL CHARACTERISTICS ( 0.9VVcc3.6V, -10CTa70C, unless otherwise specified )
Parameter Current Dissipation
Symbol ICC1
Condition VCC=3.6V, tSKP=4us, *1
Min.
Max. TBD TBD TBD TBD 10.0
Unit mA mA mA mA uA V V V
(WRITE) ICC2
VCC=0.9V, tSKP=10us, *1 VCC=3.6V, tSKP=4us, *1
Current Dissipation
ICC3
(READ,EWEN,EWDS) ICC4
VCC=0.9V, tSKP=10us, *1 VCC=3.6V *2 0.8 x VCC -0.1 IOH=-10A IOL=10A VCC=3.6V VIN=VCC/GND VCC=3.6V, CS=GND VOUT=VCC/GND VCC-0.4
Current Dissipation ICCSB (Standby) Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage VIH VIL VOH VOL
VCC+0.5 0.2 x VCC
0.2 `1.0 `1.0
V uA uA
Input Leakage ILI (CS,SK,DI pin) Output Leakage ILO (DO pin)
*1: VIN=VIH/VIL,DO=Open *2: VIN=VCC/GND,CS=GND,DO=Open
DAM05E-01 -9-
1999/12
ASAHI KASEI (2) A.C. ELECTRICAL CHARACTERISTICS
[AK93C41A/51A]
( 0.9VVcc3.6V, -10CTa70C, unless otherwise specified )
Parameter SK Cycle Time
Symbol tSKP1 tSKP2
Condition 1.8VVCC3.6V 0.9VVCC<1.8V 1.8VVCC3.6V 0.9VVCC<1.8V
Min. 4 10 2 5 TBD TBD TBD TBD
Max.
Unit us us ns us ns ns ns ns
SK Pulse Width
tSKW1 tSKW2
CS Setup Time CS Hold Time Data Setup Time Data Hold Time Output delay
tCSS tCSH tDIS tDIH tPD1 tPD2 1.8VVCC3.6V, *3 0.9VVCC<1.8V, *3 1.8VVCC3.6V 0.9VVCC<1.8V
TBD TBD 10 20 TBD
ns us ms ms ns
Selftimed Programming Time Min CS Low Time CS to Status Valid1 CS to Status Valid2 CS to Output High-Z
tE/W1 tE/W2 tCS tSV tSVV tOZ1 tOZ2
CL=100pF CL=100pF 1.8VVCC3.6V 0.9VVCC<1.8V
TBD TBD TBD TBD
ns ns ns ns
*3: CL=100pF
DAM05E-01 - 10 -
1999/12
ASAHI KASEI
[AK93C41A/51A]
Synchronous Data timing
The Start of Instruction
The End of Instruction
DAM05E-01 - 11 -
1999/12
ASAHI KASEI
[AK93C41A/51A]
Busy/Ready Signal Output
DAM05E-01 - 12 -
1999/12

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