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| DATA SHEET MOS INTEGRATED CIRCUIT PD75P048 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The PD75P048 is a One-Time PROM version of the PD75048. The PD75P048 is suitable for small-scale production or experimental production in system development. Detailed functions are described in the following user's manual. Read this manual when designing your system. PD75048 User's Manual: IEU-1278 FEATURES * The PD75048 compatible * * * * * * * * The PD75P048 for evaluation/pre-production, while the PD75048 for mass-production 8064 x 8 bits of one-time programmable ROM 512 x 4 bits of RAM 1024 x 4 bits of EEPROM (Data memory area) Ports 0 to 3 and 6 to 8 with software-selectable pull-up resistors Port 9 with software-selectable pull-down resistors 12 N-channel open drain input/output ports (ports 4, 5, and 10) Low-voltage operation possible (VDD = 2.7 to 6.0 V) ORDERING INFORMATION Part number Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP ( 14 mm) Quality grade Standard Standard PD75P048CW PD75P048GC-AB8 Caution Pull-up/pull-down resistor mask options are not available. Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. IC-3239 (O.D. No. IC-8720) Date Published August 1994 P Printed in Japan The mark 5 shows major revised points. (c) 1994 PD75P048 PIN CONFIGURATION (Top View) * 64-pin plastic shrink DIP SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PPO/P21 PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 RESET X1 X2 VPP XT1 XT2 VDD AVDD AVREF+ AVREF- AN7 AN6 AN5 AN4 AN3/P113 AN2/P112 AN1/P111 AN0/P110 AVSS TI0/P13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS P30/MD0 P31/MD1 P32/MD2 P33/MD3 P40 P41 P42 P43 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2 PD75P048CW * 64-pin plastic QFP P43 P42 P41 P40 MD3/P33 MD2/P32 MD1/P31 MD0/P30 VSS SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PPO/P21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2 TI0/P13 AVSS AN0/P110 AN1/P111 AN2/P112 AN3/P113 AN4 AN5 AN6 2 PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 RESET X1 X2 VPP XT1 XT2 VDD AVDD AVREF+ AVREF- AN7 PD75P048GC-AB8 PD75P048 PIN IDENTIFICATION P00-03 P10-13 P20-23 P30-33 P40-43 P50-53 P60-63 P70-73 P80-83 P90-93 P100-103 P110-113 KR0-7 SCK SI SO SB0, 1 RESET TI0 PTO0 BUZ PCL INT0,1,4 INT2 X1, 2 XT1, 2 MAR MAI MAZ MAT PPO AN0-7 AVREF+ AVREFAVDD AVSS VDD VSS VPP MD0-MD3 : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6 : Port7 : Port8 : Port9 : Port10 : Port11 : Key Return : Serial Clock : Serial Input : Serial Output : Serial Bus 0, 1 : Reset Input : Timer Input 0 : Programmable Timer Output 0 : Buzzer Clock : Programmable Clock : External Vectored Interrupt 0, 1, 4 : External Test Input 2 : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2 : Reference Integration Control : Integration Control : Autozero Control : External Comparate Timing Input : Programmable Pulse Output ... MFT timer mode : Analog Input 0-7 : Analog Reference (+) : Analog Reference (-) : Analog VDD : Analog VSS : Positive Power Supply : Ground : Programming Power Supply : Mode Selection MFT A/D mode 5 Remarks MFT: Multi-function timer 3 4 TI0/P13 PTO0/P20 SI/SB1/P03 SO/SB0/P02 SCK/P01 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0 - KR3/P60 - P63 KR4 - KR7/P70 - P73 BUZ/P23 AVDD AVREF+ AVREF- AVSS AN0 - AN3/P110 - P113 AN4 - AN7 MAR/P100 MAI/P101 MAZ/P102 MAT/P103 PPO/P21 BLOCK DIAGRAM BASIC INTERVAL TIMER INTBT TIMER/ COUNTER #0 INTT0 SERIAL INTERFACE INTCSI DATA MEMORY PROGRAM COUNTER CY ALU BANK BIT SEQ. BUFFER PORT 0 SP PORT 1 P00 - P03 P10 - P13 PORT 2 P20 - P23 PORT 3 P30/MD0 - P33/MD3 GENERAL REG. INTERRUPT CONTROL PROM PROGRAM MEMORY 8064 x 8 BITS WATCH TIMER INTW DECODE AND CONTROL PORT 4 P40 - P43 PORT 5 RAM 512 x 4 BITS PORT 6 P50 - P53 P60 - P63 PORT 7 EEPROM 1024 x 4 BITS A/D CONVERTER PORT 8 P70 - P73 P80 - P83 fx/2N CLOCK OUTPUT CONTROL CLOCK DIVIDER CLOCK GENERATOR SUB MAIN CPU CLOCK STAND BY CONTROL PORT 9 P90 - P93 PORT 10 P100 - P103 MULTIFUNCTION TIMER PORT 11 PCL/P22 XT1 XT2 X1 X2 P110 - P113 PD75P048 INTMFT VPP VDD VSS RESET PD75P048 CONTENTS 1. PIN FUNCTIONS ************************************************************************************************************************* 1.1 PORT PINS ****************************************************************************************************************************************** 1.2 NON-PORT PINS ********************************************************************************************************************************* 6 6 8 1.3 PIN INPUT/OUTPUT CIRCUITS ******************************************************************************************************** 10 2. DIFFERENCES BETWEEN THE PD75P048 AND THE PD75048 *************************************** 13 3. PROM (PROGRAM MEMORY) WRITE AND VERIFY ************************************************************* 14 3.1 PROM WRITE AND VERIFY OPERATION MODE ************************************************************************** 14 3.2 PROM WRITE PROCEDURE ************************************************************************************************************** 15 3.3 PROM READ PROCEDURE **************************************************************************************************************** 16 4. SCREENING OF ONE-TIME PROM MODEL *************************************************************************** 17 5. ELECTRICAL SPECIFICATIONS ************************************************************************************************** 18 6. PERFORMANCE CURVE (REFERENCE VALUE) ********************************************************************* 32 7. PACKAGE DRAWINGS *************************************************************************************************************** 34 8. RECOMMENDED SOLDERING CONDITIONS ************************************************************************* 36 APPENDIX A. DEVELOPMENT TOOLS ****************************************************************************************** 37 APPENDIX B. RELATED DOCUMENTS ****************************************************************************************** 38 5 5 5 5 5 5 5 PD75P048 1. 1.1 PIN FUNCTIONS PORT PINS (1/2) Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 Note 2 Note 2 Note 2 Note 2 Note 2 Input/ Output Input I/O I/O I/O Input Shared Pin INT4 SCK SO/SB0 SI/SB1 INT0 INT1 INT2 TI0 Function 4-bit input port (PORT0). For P01 to P03, pull-up resistors can be provided by software in units of 3 bits. 8-Bit I/O x When Reset Input I/O Circuit Type Note 1 B F -A F -B M -C With noise elimination function 4-bit input port (PORT1). Pull-up resistors can be provided by software in units of 4 bits. 4-bit I/O port (PORT2). Pull-up resistors can be provided by software in units of 4 bits. x Input B -C I/O PTO0 PPO PCL BUZ x Input E-B I/O MD0 MD1 MD2 MD3 Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits. x Input E-B P40 - P43 I/O - N-ch open-drain 4-bit I/O port (PORT4). Can withstand 10 V. Data input/output pins for the PROM write and verity (Four low-order bits). High impedance M-A P50 - P53 Note 2 I/O - N-ch open-drain 4-bit I/O port (PORT5). Can withstand 10 V. Data input/output pins for the PROM write and verify (Four high-order bits). High impedance M-A Note 1. The circle ( ) indicates the Schmitt trigger input. 2. Can directly drive LEDs. 6 PD75P048 1.1 PORT PINS (2/2) Pin Name P60 P61 P62 P63 P70 P71 P72 P73 P80 - P83 I/O I/O Input/ Output I/O Shared Pin KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 - 4-bit I/O port (PORT 8). A pull-up resistor can be provided by software in units of 4 bits. 4-bit I/O port (PORT 9). A pull-up resistor can be provided by software in units of 4 bits. N-ch open drain 4-bit I/O port (PORT 10). Can withstand 10 V in open-drain mode. x x Input E-B 4-bit I/O port (PORT 7). A pull-up resistor can be provided by software in units of 4 bits Input F -A Function Programmable 4-bit I/O port (PORT 6). Pull-up resistors can be provided by software in units of 4 bits. 8-Bit I/O When Reset Input I/O Circuit Type Note F -A P90 - P93 I/O - Input E-D P100 P101 P102 P103 P110 P111 P112 P113 I/O MAR MAI MAZ MAT High impedance M-A 5 Input AN0 AN1 AN2 AN3 4-bit input port (PORT 11). Input Y Note The circle ( ) indicates the Schmitt trigger input. 7 PD75P048 1.2 NON-PORT PINS (1/2) Pin Name TI0 Input/ Output Input Shared Pin P13 Function Input for receiving external event pulse signal for timer/event counter Timer/event counter output Clock output Output for arbitrary frequency output (for buzzer output or system clock trimming) Serial clock I/O Serial data output Serial bus I/O Serial data input Serial bus I/O Edge detection vectored interrupt input (either rising edge or falling edge detection) Edge detection vectored interrupt input (detection edge selectable) Edge detection testable input (rising edge detection) Parallel falling edge detection testable input Parallel falling edge detection testable input In MFT integrating A/D converter mode Reverse integration signal output Integration signal output When Reset Input I/O Circuit Type Note B -C PTO0 PCL BUZ I/O I/O I/O P20 P22 P23 Input Input Input E-B E-B E-B SCK SO/SB0 I/O I/O P01 P02 Input Input F -A F -B SI/SB1 I/O P03 Input M -C INT4 Input P00 Input B B -C INT0 INT1 INT2 Input P10 P11 Input Input P12 Input B -C KR0 - KR3 KR4 - KR7 MAR I/O I/O I/O P60 - P63 P70 - P73 P100 Input Input High impedance High impedance High impedance High impedance Input F -A F -A M-A MAI I/O P101 M-A MAZ I/O P102 Auto-zero signal output M-A MAT I/O P103 Comparator input M-A PPO I/O P21 In MFT timer mode Timer pulse output E-B AN0 - AN3 AN4 - AN7 AVREF+ Input P110 - P113 For A /D converter only - - 8-bit analog input - Y-A Y-A Input Reference voltage input (AVDD side) Reference voltage input (AVSS side) Positive power supply GND potential - Z-A AVREF- Input - - Z-A AVDD AVSS - - - - - - - - Note The circle ( ) indicates the Schmitt trigger input. Remark MFT: Multi-Function Timer 8 PD75P048 1.2 NON-PORT PINS (2/2) Pin Name X1, X2 Input/ Output Input Shared Pin - Function Crystal/ceramic resonator connection for main system clock generation. When external clock signal is used, it is applied to X1, and its reverse phase signal is applied to X2. Crystal connection for subsystem clock generation. When external clock signal is used, it is applied to XT1, and its reverse phase signal is applied to XT2. XT1 can be used as a 1-bit input (test). System reset input Operation mode selection pins during the PROM write/verify cycles. Normally connected to VDD directly; +12.5 V is applied as the programming voltage during the PROM write/verify cycles. Positive power supply GND potential When Reset - I/O Circuit Type Note 1 - XT1, XT2 Input - - - RESET MD0 - MD3 VPP Note 2 Input I/O - P30 - P33 - Input B E-B - - - - VDD VSS - - - - - - - - Note 1. The circle ( ) indicates the Schmitt trigger input. 2. The VPP should be connected to VDD directly in normal operation mode. If VPP and VDD pins are not connected, the PD75P048 does not operate correctly. 9 PD75P048 1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuit of each PD75P048 pin is shown below in a simplified manner. (1/3) Type A (For Type E-B) VDD Data P-ch IN N-ch Output disable N-ch OUT Type D (For Type E-B, F-A) VDD P-ch CMOS input buffer Type B Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) Type E-B VDD P.U.R. P.U.R. enable Data Type D Output disable P-ch IN IN/OUT Type A Schmitt trigger input with hysteresis P.U.R.: Pull-Up Resistor Type B-C Type E-D VDD Data P.U.R. P.U.R. enable Output disable Type D IN/OUT P-ch Type A IN P.D.R. enable N-ch P.D.R. P.U.R.: Pull-Up Resistor P.D.R.: Pull-Down Resistor 10 PD75P048 (2/3) Type F-A VDD P.U.R. P.U.R. enable Data Type D Output disable P-ch P.U.R. enable Type M-C VDD P.U.R. P-ch IN/OUT IN/OUT Data Output disable Type B N-ch P.U.R.: Pull-Up Resistor Type F-B Type Y P.U.R.: Pull-Up Resistor VDD P.U.R. P.U.R. enable Output disable (P) Data Output disable Output disable (N) N-ch Input enable VDD P-ch IN/OUT AVSS AVSS Reference voltage (from voltage tap of series resistor string) P-ch IN AVDD P-ch N-ch AVDD + Sampling C - P.U.R.: Pull-Up Resistor Type M-A IN/OUT Type Y-A IN instruction Data Output disable Input buffer N-ch (Can withstand + 10 V) AVDD IN AVDD P-ch N-ch Sampling C + - AVSS AVSS Middle-voltage input buffer (Can withstand + 10 V) P.U.R.: Pull-Up Resistor Reference voltage (from voltage tap of series resistor string) 11 PD75P048 (3/3) Type Z-A AVREF+ Reference voltage AVREF- 12 PD75P048 2. DIFFERENCES BETWEEN THE PD75P048 AND THE PD75048 The PD75P048 is a One-Time PROM version of the PD75048. The PD75P048 has the same CPU and internal hardwares. Table 2-1 shows the differences between the PD75P048 and the PD75048. Bear in mind the differences between these two products when debugging or developing on an experimental basis your application system by using the one-time PROM model, and then mass-producing the application system by using the mask ROM model. Details for the CPU functions and internal hardwares are available in PD75048 User's Manual (IEU-1278). Table 2-1 Differences between the PD75P048 and the PD75048 Items Program Memory PD75P048 One-time PROM PD75048 Mask ROM * 0000H to 1F7FH * 8064 x 8 bits Pull-up Resistors Ports 0 to 3 and 6 to 8 Ports 4, 5 and 10 Pull-Down Resistors XT1 Feedback Resistor Pin Connection 60 - 63 (SDIP) 5 - 8 (QFP) 16 (SDIP) 25 (QFP) Electrical Specification Port 9 Software-selectable N/A Mask-option Software-selectable On-chip P33/MD3 - P30/MD0 Mask-option P33 - P30 5 VPP IC Current dissipation differs. For details, refer to Data Sheet of each model. 5 5 Other Circuit scale and mask layout differ. Consequently, noise immunity and noise radiation differ. Note The noise immunity and noise radiation of the PROM and mask ROM models differ. To replace the PROM mode, which has been used for experimental production of your application system with the mask ROM model for mass production of the application system, be sure to perform thorough evaluation by using the CS model (not ES model) of the mask ROM model. 5 13 PD75P048 3. PROM (PROGRAM MEMORY) WRITE AND VERIFY The PD75P048 contains 8064 bytes of PROM. The following table shows the pin functions during the write and verify cycles. Note that it is not necessary to enter an address, because the address is updated by pulsing the X1 clock pins. Pin Name VPP X1, X2 Function Normally 2.7 to 6 V; 12.5 V is applied during write/verify After a write/verify write, the X1 and X2 clock pins are pulsed. The inverted signal of the X1 should be input to the X2. Note that these pins are also pulsed during a read. Operation mode selection pins. 8-bit data input/output pins for write and verify MD0 - MD3 (P30 - P33) P40 - P43 (lower 4 bits) P50 - P53 (higher 4 bits) VDD Supply voltage. Normally 2.7 to 6 V; 6 V is applied during write/verify Caution The PD75P048CW/GC do not have a UV erase window, thus the PROM contents cannot be erased with ultra-violet ray. 3.1 PROM WRITE AND VERIFY OPERATION MODE When 6 V and 12.5 V are applied to the VDD and VPP pins, respectively, the PROM is placed in the write/verify mode. The operation is selected by the MD0 to MD3 pins, as shown in the table. The other pins should be returned to VSS potential via pull-down resistors. Operation Mode Specification Operation Mode VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L x MD2 H H H H MD3 L H H H Clear program memory address to 0 Write mode Verify mode Program inhibit x: Don't care. 14 PD75P048 3.2 PROM WRITE PROCEDURE PROMs can be written at high speed using the following procedure: (see the following figure) (1) Pull unused pins to VSS through resistors. Set the X1 pin low. (2) Supply 5 volts to the VDD and VPP pins. (3) Wait for 10 s. (4) Select the zero clear program memory address mode. (5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins. (6) Select the program inhibit mode. (7) Write data in the 1 ms write mode. (8) Select the program inhibit mode. (9) Select the verify mode. If the data is correct, proceed to step (10). If not, repeat steps (7), (8) and (9). (10) Perform one additional write (duration of 1 ms x number of writes at (7) to (9)). (11) Select the program inhibit mode. (12) Apply four pulses to the X1 pin to increment the program memory address by one. (13) Repeat steps (7) to (12) until the end address is reached. (14) Select the zero clear program memory address mode. (15) Return the VDD and VPP pins back to + 5 volts. (16) Turn off the power. The following figure shows steps (2) to (12). X repetition Write Verify Additional write Address increment VPP VPP VDD VDD+1 VDD VDD X1 P40-P43 P50-P53 Input data Output data Input data MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33) 15 PD75P048 3.3 PROM READ PROCEDURE The PROM contents can be read in the verify mode by using the following procedure: (see the following figure) (1) Pull unused pins to VSS through resistors. Set the X1 pin low. (2) Supply 5 volts to the VDD and VPP pins. (3) Wait for 10 s. (4) Select the clear program memory address mode. (5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins. (6) Select the program inhibit mode. (7) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one address. (8) Select the program inhibit mode. (9) Select the clear program memory address mode. (10) Return the VDD and VPP pins back to + 5 volts. (11) Turn off the power. The following figure shows steps (2) to (9). VPP VPP VDD VDD+1 VDD VDD X1 P40-P43 P50-P53 Output data Output data MD0 (P30) MD1 (P31) "L" MD2 (P32) MD3 (P33) 16 PD75P048 4. SCREENING OF ONE-TIME PROM MODEL Because of their structure, the one-time PROM models (PD75P48CW and PD75P48GC-AB8) cannot be fully tested by NEC before shipment. It is therefore recommended that you implement screening to verify the PROM after necessary data have been written to it, and after the PROM has been stored at high temperature under the following conditions: Storage Temperature 125 C Storage Time 24 hours 5 17 PD75P048 5 5. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25C) Parameter Supply Voltage Input Voltage Symbol VDD VI1 VI2 Other than ports 4, 5, 10 Ports 4, 5, 10 w/pull-up resistor Open drain Output Voltage High-Level Output Current Low-Level Output Current VO IOH IOL Note Conditions Ratings -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +11 -0.3 to VDD+0.3 -10 -30 Peak rms Peak rms Peak rms Peak rms 30 15 20 5 170 120 30 20 -10 to +70 -65 to +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA C C 1 pin All pins Ports 0, 3, 4, 5 1 pin Other than ports 0, 3, 4, 5 1 pin Total of ports 0, 3 - 9, 11 Total of ports 0, 2, 10 Operating Temperature Storage Temperature Topt Tstg Note rms = Peak value x Duty Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. EEPROM RATINGS (Ta = -10 to +70C, VDD = 2.7 to 6.0 V) Parameter Write Times Data Retention Time Symbol -- -- Conditions Ratings 100,000 10 Unit times years CAPACITANCE (Ta = 25C, VDD = 0 V) Parameter Input Capacitance Output Capacitance Input/Output Symbol CI CO CIO f = 1 MHz Pins other than those measured are at 0 V 15 Conditions MIN. TYP. 15 MAX. pF 15 pF pF Unit 18 PD75P048 MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70C, VDD = 2.7 to 6.0 V) Recommended Constants Oscillator Ceramic Item Oscillation frequency(fX) Note 1 Conditions VDD = oscillation voltage range MIN. TYP. MAX. Unit X1 X2 2.0 5.0 Note 3 MHz C1 VDD C2 Oscillation stabilization time Note 2 After VDD come to MIN. value of oscillation voltage range 2.0 VDD = 4.5 to 6.0 V 4.19 5.0 4 ms Crystal X1 X2 Oscillation frequency (fX) Note 1 Oscillation stabilization time Note 2 Note 3 MHz 10 ms C1 VDD C2 30 X1 input frequency (fX) Note 1 ms External Clock X1 X2 2.0 5.0 Note 3 MHz PD74HCU04 X1 input high-, low-level widths (tXH, tXL) 100 250 ns Note 1. Only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2. Time required for oscillation to stabilize after VDD has reached the minimum volue of the oscillation voltage range or the STOP mode has been released. 3. When the oscillation frequency is 4.19 MHz < fx 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 s, falling short of the rated minimum value of 0.95 s. Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. * Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the ground pattern through which a high curent flows. * Do not extract signals from the oscillation circuit. 19 PD75P048 SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70C, VDD = 2.7 to 6.0 V) Recommended Constants XT1 XT2 R C3 VDD C4 Oscillator Crystal Item Oscillation frequency (fXT) Note 1 Conditions MIN. 32 TYP. 32.768 1.0 MAX. 35 2 10 Unit kHz s s Oscillation stabilization time Note 2 VDD = 4.5 to 6.0 V External Clock XT1 XT2 XT1 input frequency (fXT) Note 1 32 100 kHz XT1 input high-, low-level widths (tXTH, tXTL) 5 15 s Note 1. Indicates only the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2. Time required for oscillation to stabilize after VDD has reached the minimum value of the oscillation voltage range. Caution When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. * Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit. 20 PD75P048 DC CHARACTERISTICS (Ta = -10 to +70C, VDD = 2.7 to 6.0 V) Parameter High-Level Input Voltage Symbol VIH1 VIH2 VIH3 VIH4 Low-level Input Voltage VIL1 VIL2 VIL3 High-Level Output Voltage Low-Level Output Voltage VOH VOL Conditions Ports 2,3,8,9,11 Ports 0,1,6,7, RESET Ports 4,5,10 X1, X2, XT1, XT2 Ports 2-5, 8-11 Ports 0, 1, 6, 7, RESET X1, X2, XT1, XT2 VDD = 4.5 to 6.0V, IOH = -1 mA IOH = -100 A Ports 3,4,5 VDD = 4.5 to 6.0V, IOL = 15mA w/pull-up resistor Open-drain MIN. 0.7VDD 0.8VDD 0.7VDD 0.7VDD VDD-0.5 0 0 0 VDD-1.0 VDD-0.5 0.4 2.0 0.4 0.5 Open-drain pull-up resistor 1 k Other than below X1,X2,XT1 VI = 9V VI = 0V VO = VDD VO = 9V VO = 0V Ports 0,1,2,3,6,7,8 (except P00) VI = 0V Ports 4,5,10 VO = VDD-2.0 V Port 9 VIN = VDD VDD = 5.0V10% VDD = 3.0V10% VDD = 5.0V10% VDD = 3.0V10% VDD = 5.0V10% VDD = 3.0V10% 15 30 15 10 15 10 40 40 40 Ports 4,5,10 (open-drain) Other than below X1,X2,XT1 Other than below Ports 4,5,10 (open-drain) 0.2VDD 3 20 20 -3 -20 3 20 -3 80 300 70 60 70 60 TYP. MAX. VDD VDD VDD 10 VDD 0.3VDD 0.2VDD 0.4 Unit V V V V V V V V V V V V V V VDD = 4.5 to 6.0V, IOL = 1.6 mA IOL = 400 A SB0, 1 High-Level Input Leakage Current ILIH1 ILIH2 ILIH3 Low-Level Input Leakage Current High-Level Output Leakage Current Low-Level Output Leakage Current Internal Pull-Up Resistor ILIL1 ILIL2 ILOH1 ILOH2 ILOL RU1 RU2 Internal Pull-Down Resistor RD VI = VDD A A A A A A A A k k k k k k 21 PD75P048 Parameter Supply Current Note 1 Symbol IDD1 IDD2 4.19MHz crystal oscillator C1 = C2 = 22pF 32.768kHz Note 4 crystal oscillator XT1 = 0V STOP mode Conditions VDD = 5V10% Note 2 VDD = 3V10% HALT mode Note 3 MIN. TYP. 5.5 1.7 900 450 100 35 0.5 0.3 MAX. 17 5.1 2700 1400 300 110 20 10 5 Unit mA mA VDD = 5V10% VDD = 3V10% A A A A A A A A IDD3 IDD4 IDD5 Operation mode HALT mode VDD = 5V10% VDD = 3V10% VDD = 3V10% VDD = 3V10% Ta = 25C IDD6 32.768kHz oscillator STOP mode VDD = 3V10% Note 5 6 20 Note 1. Current flowing through internal pull-up resistor. Current flowing when EEPROM is accessed is not included. 2. When PD75048 operates in high-speed mode with processor clock control register (PCC) set to 0011. 3. When PD75048 operates in low-speed mode with PCC set to 0000. 4. When the system clock control register (SCC) is set to 1001, the oscillation of the main system clock is stopped, and the subsystem clock is used. 5. When STOP instruction is executed with SCC set to 0000. Note Supply current when EEPROM is accessed is shown in EEPROM Characteristics. 22 PD75P048 AC CHARACTERISTICS (Ta = -10 to +70C, VDD = 2.7 to 6.0 V) Parameter CPU Clock Cycle Time (Minimum Instruction Execution Time = 1 Machine Cycle) Note 1 TI0 Input Frequency TI0 Input High-, LowLevel Widths Interrupt Input High-, Low-Level Widths Symbol tCY Conditions w/main system clock w/subsystem clock fTI tTIH, tTIL tINTH, tINTL VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V INT0 INT1, 2, 4 KR0-7 RESET Low-Level Width tRSL VDD = 4.5 to 6.0V MIN. 0.95 3.8 114 0 0 0.48 1.8 Note 2 TYP. MAX. 32 32 Unit s s s MHz kHz 122 125 1 275 s s s s s s 10 10 10 Note 1. The CPU clock () cycle time is determined by the oscillation frequency of the connected oscillator, system clock control register (SCC), and processor clock control register (PCC). The figure on the right is cycle time tCY vs. supply voltage VDD characteristics at the main system clock. 2. 2tCY or 128/fX depending on the setCycle time tCY [s] 6 5 4 3 Operation quaranteed range 32 tCY vs VDD (with main system clock) ting of the interrupt mode register (IM0). 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] 23 PD75P048 SERIAL TRANSFER OPERATION Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY1 tKL1 tKH1 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 1600 3800 tKCY1/2-50 tKCY1/2-150 150 400 RL = 1k, CL = 100pF Note TYP. MAX. Unit ns ns ns ns ns ns SI Set-Up Time (vs. SCK ) tSIK1 SI Hold Time (vs. SCK ) tKSI1 SCK SO Output Delay Time tKSO1 VDD = 4.5 to 6.0V 250 1000 ns ns TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY2 tKL2 tKH2 tKSI2 tKSO2 RL = 1k, CL = 100 pF Note Conditions VDD = 4.5 to 6.0V VDD = 4.5 to 6.0V MIN. 800 3200 400 1600 100 400 TYP. MAX. Unit ns ns ns ns ns ns SI Set-Up Time (vs. SCK ) tSIK2 SI Hold Time (vs. SCK ) SCK SO Output Delay Time VDD = 4.5 to 6.0V 300 1000 ns ns Note RL and CL are load resistance and load capacitance of the SO output line. 24 PD75P048 SBI MODE (SCK: internal clock output (master)) Parameter SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0,1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width Symbol tKCY3 tKL3 tKH3 tSIK3 tKSI3 tKSO3 tKSB tSBK tSBL tSBH RL = 1k, CL = 100pF Note Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 1600 3800 tKCY3/2-50 tKCY3/2-150 150 tKCY3/2 TYP. MAX. Unit ns ns ns ns ns ns VDD = 4.5 to 6.0V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns ns SBI MODE (SCK: external clock input (slave)) Parameter SCK Cycle Time SCK Ligh-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0,1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width Symbol tKCY4 tKL4 tKH4 tSIK4 tKSI4 tKSO4 tKSB tSBK tSBL tSBH RL = 1k, CL = 100pF Note Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 800 3200 400 1600 100 tKCY4/2 TYP. MAX. Unit ns ns ns ns ns ns VDD = 4.5 to 6.0V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 ns ns ns ns ns ns Note RL and CL are load resistance and load capacitance of the SB0 and SB1 output lines. 25 PD75P048 A/D CONVERTER (Ta = -10 to +70C, VDD = 2.7 to 6.0V, AVSS = VSS = 0V) Parameter Resolution Absolute Accuracy Conversion Time Sampling Time Note 1 Symbol Conditions 2.5V AVREF VDD MIN. 8 TYP. 8 MAX. 8 1.5 168/fX 44/fX Unit bit LSB Note 2 tCONV tSAMP VIAN AVDD AVREF+ AVREFRAN AIREF 1 - LSB) 2 s s V V V V M mA Note 3 Analog Input Voltage Analog Supply Voltage Reference Input Voltage Reference Input Voltage Analog Input Impedance AVREF Current AVREF2.5 2.5V (AVref+) - (AVref-) 2.5V (AVref+) - (AVref-) 2.5 0 1000 0.25 AVREF+ VDD AVDD 1.0 2.0 Note 1. Absolute accuracy excluding quantization error ( MHz) 2. Time since execution of conversion start instruction until end of conversion (EOC = 1) (40.1 s: fX = 4.19 3. Time since execution of conversion start instruction until end of sampling (10.5 s: fX = 4.19 MHz) 26 PD75P048 AC TIMING TEST POINT (excluding X1 and XT1 inputs) 0.8 VDD Test points 0.2 VDD 0.2 VDD 0.8 VDD CLOCK TIMING 1/fX tXL tXH X1 input VDD -0.5V 0.4 V 1/fXT tXTL tXTH XT1 input VDD -0.5V 0.4 V TI0 TIMING 1/fTI tTIL tTIH TI0 27 PD75P048 SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE: tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 SI Input data tKS01 SO Output data TWO-LINE SERIAL I/O MODE: tKCY2 tKL2 tKH2 SCK tSIK2 tKSI2 SB0,1 tKSO2 28 PD75P048 SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER: tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4 tKSB tSBL tSBH tSBK tKSI3,4 SB0,1 tKS03,4 COMMAND SIGNAL TRANSFER: tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4 tKSB tSBK tKSI3,4 SB0,1 tKS03,4 INTERRUPT INPUT TIMING tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET INPUT TIMING tRSL RESET 29 PD75P048 EEPROM CHARACTERISTICS Parameter Supply current for EEPROM access Note 1 Symbol IDD7 Conditions 4.19MHz crystal oscillator VDD = 5V+10% C1 = C = 22pF VDD = 3V+10% Note 3 Note 2 MIN. TYP. 6.5 2 MAX. 20 6 Unit mA mA Note 1. Current flowing through the internal pull-up resistor is not included. 2. When the processor clock control register (PCC) is set to 0011 and the high-speed mode is used. 3. When PCC is set to 0000 and the low-speed mode is used. EEPROM WRITE TIME Select the write time of the EEPROM in accordance with the oscillation frequency of the main system clock as follows: Oscillation Frequency of Main System Clock (fX) fX = 2.0 to 5.0 MHz fX = 2.0 to 4.2 MHz fX = 2.0 MHz Setting of EEPROM Control Register EWTC1 0 0 1 EWTC0 0 1 0 Write time 212 x 18/fX (17.6 ms) 211 x 18/fX (8.8 ms) 210 x 18/fX Remarks ( ): fX = 4.19 MHz LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = -10 to +70C) Parameter Data Retention Supply Voltage Data Retention Supply Current Note 1 Release Signal Set Time Oscillation Stabilization Wait Time Note 2 Symbol VDDDR IDDDR tSREL tWAIT Released by RESET Released by interrupt request VDDDR = 2.0 V 0 217/fX Note 3 Conditions MIN. 2.0 TYP. MAX. 6.0 Unit V 0.1 10 A s ms ms Note 1. Does not include current flowing through internal pull-up resistor 2. The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3. Depends on the setting of the basic interval timer mode register (BTM) as follows: BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 WAIT time ( ): fX = 4.19 MHz 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.82 ms) 213/fX (approx. 1.95 ms) 30 PD75P048 DATA RETENTION TIMING (releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Data retention mode Operation mode VDD VDDDR STOP instruction execution RESET tSREL tWAIT DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt) HALT mode STOP mode Data retention mode Operation mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) tSREL tWAIT 31 PD75P048 5 6. PERFORMANCE CURVE (REFERENCE VALUE) IDD vs VDD (Crystal oscillation) 10 (T a = 25 C) High-speed mode PCC = 0011 5.0 Medium-speed mode PCC = 0010 Low-speed mode PCC = 0000 1.0 Main system clock HALT mode 0.5 Subsystem clock operation mode + Main system lock stopped Supply current IDD [mA] Main system clock stopped + Subsystem clock HALT mode 0.1 0.05 Main system clock STOP mode + Subsystem clock oscillation 0.01 X1 X2 Crystal oscillator XT1 XT2 0.005 Crystal oscillator 32.768 kHz 4.19 MHz 330 k 22 pF 22 pF 22 pF 22 pF VDD VDD 0.001 0 1 2 3 4 5 6 7 Supply voltage VDD [V] Note Does not include current flowing through EEPROM. 32 PD75P048 IDD vs VDD (Crystal oscillation) 10 (T a = 25 C) 5.0 High-speed mode PCC = 0011 Medium-speed mode PCC = 0010 Low-speed mode PCC = 0000 1.0 Main system clock HALT mode 0.5 Subsystem clock operation mode + Main system clock stopped Supply current IDD [mA] Subsystem clock HALT mode + Main system clock stopped 0.1 0.05 Main system clock STOP mode + Subsystem clock oscillation 0.01 X1 X2 Crystal oscillator 2.0 MHz XT1 XT2 330 k 0.005 Crystal oscillator 32.768 kHz 22 pF 22 pF 22 pF 22 pF VDD VDD 0.001 0 1 2 3 4 5 6 7 Supply voltage VDD [V] Note Does not include current flowing through EEPROM. 33 PD75P048 7. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 A 32 K L J I F D G H N M C B M R NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N R MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15 INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1 34 PD75P048 64 PIN PLASTIC QFP ( 14) A B 48 49 33 32 detail of lead end C D S 64 1 17 16 F G H IM J K P N L P64GC-80-AB8-2 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.15 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.006 0.100 0.004 0.004 0.112 MAX. NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. M 55 Q 35 PD75P048 5 8. RECOMMENDED SOLDERING CONDITIONS It is recommended that PD75P048 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-1207). For other soldering methods and conditions, consult NEC. Table 8-1 Soldering Conditions of Surface-Mount Type PD75P048GC-AB8: 64-pin plastic QFP ( Soldering Method Infrared Reflow 14 mm) Soldering Conditions Symbol for Recommended Condition IR35-00-2 Package peak temperature: 235C, time: 30 seconds max. (210C min.), number of times: 2 max. VPS VP15-00-2 Pin Partial Heating -- Caution Do not use two or more soldering methods in combination (except the pin partial heating method). Table 8-2 Soldering Conditions of Through-Hole Type PD75P048CW: 64-pin plastic shrink DIP (750 mil) Soldering Method Wave soldering (lead parts only) Pin Partial Heating Soldering Conditions Soldering bath temperature: 260C max., time: 10 seconds max., Pin temperature: 260oC max., time: 10 seconds max. Caution The wave soldering must be performed at the lead part only. Note that the soldering must not be directly contacted to the board. 36 PD75P048 APPENDIX A. DEVELOPMENT TOOLS The following development tools are readily available to support development of systems using PD75P048: Hardware IE-75000-R Note 1 IE-75001-R IE-75000-R-EM Note 2 EP-75028CW-R EP-75028GC-R EV-9200GC-64 PG-1500 PA-75P036CW Emulation board for IE-75000-R and IE-75001-R Common emulation probe commonly used with PD75028CW Emulation probe commonly used with PD75028GC, provided with EV-9200GC-64, 64-pin conversion socket PROM programmer PROM programmer adapter commonly used with PD75P036. It is connected to PG-1500. PA-75P036GC PROM programmer adapter commonly used with PD75P036GC. It is connected to PG-1500. Software IE Control Program PG-1500 Controller RA75X Relocatable Assembler Host machine PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A Note 3) IBM PC/ATTM (Refer to OS for IBM PC.) In-circuit emulator for 75X series 5 Note 1. Maintenance product 2. Not provided with IE-75001-R. 3. Ver. 5.00/5.00A has a task swap function, but this function cannot be used with this software. Remarks For development tools from other companies, refer to 75X Series Selection Guide (IF-1027). OS for IBM PC As OS for IBM PC, the followings are supported. OS PC DOSTM MS-DOS Version Ver. 5.02 to Ver. 6.1 Ver. 3.30 to Ver. 5.00A 5.0/V IBM DOSTM Note 2 Note 2 Note 1 J5.02/V Note 1. Version later than 5.0 have a task swap function, but this function cannot be used with this software. 2. This supports English mode only. 37 PD75P048 5 APPENDIX B. RELATED DOCUMENTS Documents related to device Document User's manual Instruction list 75X series selection guide Document No. IEU-1278 -- IF-1027 Documents related to development tools Doument Hardware IE-75000-R/IE-75001-R user's manual IE-75000-R-EM user's manual EP-750028CW-R user's manual EP-75028GC-R user's manual PG-1500 user's manual Software RA75X assembler package user's manual Operation Language PG-1500 controller user's manual Document No. EEU-1416 EEU-1294 EEU-1314 EEU-1306 EEU-1335 EEU-1346 EEU-1343 EEU1291 Other related documents Document Package manual Semiconductor device - mounting maual NEC semiconductor device quality grade NEC semiconductor device reliabiliy quality control Static electricity discharge (ESD) test Semiconductor device quality guarantee guide Product guide related to microcomputer - other manufacturers Document No. IEI-1213 IEI-1207 IEI-1209 -- -- MEI-1202 -- Note The documents listed above are subject to change without notice. Be sure to use the latest document for designing. 38 PD75P048 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 39 PD75P048 [MEMO] NEC is manufacturing and selling the products under microcomputer (with on-chip EEPROM) patent license with the BULL CP8. This product should not be used for IC cards (SMART CARD). No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT and PC DOS are trademarks of IBM Corporation. |
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